Support plate, preparation method of support plate and electronic equipment

Abstract

The embodiment of the invention provides a carrier plate, a preparation method of the carrier plate and electronic equipment, and relates to the technical field of chip packaging, the carrier plate comprises at least one rewiring sub-layer, the rewiring sub-layer comprises a first conductive layer, a first insulating layer and a second insulating layer, and the first conductive layer comprises a plurality of first conductive wires; the first insulating layer covers part of the side wall of the first conductive wire, the first insulating layer comprises a first surface and a second surface which are oppositely arranged in the thickness direction of the first conductive wire, and the second surface of the first insulating layer is provided with a plurality of concave-convex structures; the second insulating layer is located on the second surface of the first insulating layer, the second insulating layer covers part of the surface of the first conductive wire, and the second insulating layer is in contact with the second surface of the first insulating layer. According to the invention, bubbles are not easy to generate between the first insulating layer and the second insulating layer and the first conductive wire.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and more specifically, to a carrier board, a method for preparing the carrier board, and an electronic device. Background Technology

[0002] A chip, also known as a microcircuit, microchip, or integrated circuit, is actually a general term for semiconductor electronic components. Chips can be classified in many ways; based on their signal processing capabilities, they can be divided into analog chips and digital chips. To protect the chip, it needs to be packaged, forming a chip package structure.

[0003] However, there are still some problems with the chip packaging structure in related technologies that need to be solved. Summary of the Invention

[0004] To overcome the technical problems mentioned in the above background, embodiments of this application provide a carrier board, the carrier board including at least one redistribution sublayer, the redistribution sublayer including: A first conductive layer, the first conductive layer including a plurality of first conductive traces; A first insulating layer covers a portion of the sidewall of the first conductive trace. Along the thickness direction of the first conductive trace, the first insulating layer includes a first surface and a second surface disposed opposite to each other. The second surface of the first insulating layer has a plurality of uneven structures. A second insulating layer is located on the second surface of the first insulating layer, the second insulating layer covers a portion of the surface of the first conductive trace, and the second insulating layer is in contact with the second surface of the first insulating layer.

[0005] In some possible implementations, the thickness of the first insulating layer is less than the thickness of the second insulating layer; Preferably, the ratio of the thickness of the first insulating layer to the thickness of the first conductive trace is greater than or equal to 0.25 and less than or equal to 0.5. Preferably, the ratio of the thickness of the second insulating layer to the thickness of the first conductive trace is greater than or equal to 0.7 and less than or equal to 1.05. Preferably, the thickness of the first conductive trace is greater than or equal to 10 μm and less than or equal to 20 μm; Preferably, the thickness of the first insulating layer is greater than or equal to 2.5 μm and less than or equal to 10 μm; Preferably, the thickness of the second insulating layer is greater than or equal to 7 μm and less than or equal to 21 μm.

[0006] In some possible implementations, the distance from the side of the second insulating layer away from the first surface to the first surface is greater than the distance from the side of the first conductive trace away from the first surface to the first surface. Preferably, the second insulating layer has a plurality of first grooves on the side away from the first insulating layer, and the first grooves expose the side of the corresponding first conductive trace away from the first surface; Preferably, the first surface exposes the side of the first conductive trace away from the second insulating layer; Preferably, the first surface is flush with the side of the first conductive trace away from the second insulating layer; Preferably, the orthographic projection of the first insulating layer onto the plane of the first surface coincides with the orthographic projection of the second insulating layer onto the plane of the first surface.

[0007] In some possible implementations, the first insulating layer contacts the sidewall of the first conductive trace; Preferably, the second insulating layer is in contact with the sidewall of the first conductive trace; Preferably, the surface of the uneven structure is wavy; Preferably, the material of the first insulating layer includes polyimide; Preferably, the material of the second insulating layer includes polyimide.

[0008] In some possible implementations, the redistribution sublayer is multi-layered, with the multiple redistribution sublayers stacked sequentially along the thickness direction from the substrate, and the first conductive traces in the multiple redistribution sublayers being electrically connected sequentially.

[0009] In some possible implementations, this application also provides a method for preparing a carrier plate, the method comprising: Provide a substrate; A first conductive layer is formed on the substrate, the first conductive layer including a plurality of first conductive traces; A first insulating layer is formed on the substrate. Along the thickness direction of the substrate, the first insulating layer includes a first surface and a second surface disposed opposite to each other. The thickness of the first insulating layer is less than the thickness of the first conductive trace. A second insulating layer is formed on the second surface, the second insulating layer covering a portion of the surface of the first conductive trace, and the dynamic viscosity of the first insulating layer is less than that of the second insulating layer.

[0010] In some possible implementations, the step of forming the first insulating layer on the substrate includes: When the minimum spacing between two adjacent first conductive traces is greater than 0 and less than or equal to 5 μm, a first insulating layer with a dynamic viscosity greater than or equal to 5 cp and less than or equal to 500 cp is formed on the substrate. When the minimum spacing between two adjacent first conductive traces is greater than 5 μm, a first insulating layer with a dynamic viscosity greater than or equal to 50 cp and less than or equal to 1000 cp is formed on the substrate. Preferably, the step of forming a second insulating layer on the second surface includes: A second insulating layer with a dynamic viscosity greater than or equal to 3000 cp is formed on the second surface.

[0011] In some possible implementations, the step of forming a second insulating layer on the second surface includes: A second insulating material layer is formed on the second surface; A second insulating layer comprising a plurality of first grooves is formed on the side of the second insulating material layer away from the first insulating layer, the first grooves exposing the side of the first conductive trace away from the first surface.

[0012] In some possible implementations, after the step of forming the second insulating layer on the second surface, the method further includes: A second conductive layer is formed on the side of the second insulating layer away from the first insulating layer. The second conductive layer includes a plurality of second conductive traces, and the second conductive traces are electrically connected to the first conductive traces. A third insulating layer is formed on the side of the second insulating layer away from the first insulating layer, and the thickness of the third insulating layer is less than the thickness of the second conductive trace along the direction from the first surface to the second surface. A fourth insulating layer is formed on the side of the third insulating layer away from the first insulating layer. The fourth insulating layer covers a portion of the second conductive trace. The side of the fourth insulating layer away from the first insulating layer has a second groove that exposes the second conductive trace. The dynamic viscosity of the third insulating layer is less than that of the fourth insulating layer. Preferably, after the step of forming the fourth insulating layer on the side of the third insulating layer away from the first insulating layer, the method further includes: Remove the substrate.

[0013] In some possible implementations, this application also provides an electronic device comprising the carrier plate described in this application, or comprising a carrier plate prepared by the method for preparing the carrier plate described in this application.

[0014] Compared with the prior art, this application has the following beneficial effects: This application provides a carrier board, a method for preparing the carrier board, and an electronic device. By setting the insulating layer of the redistribution sublayer as a first insulating layer and a second insulating layer stacked together, and the dynamic viscosity of the newly formed first insulating layer is less than that of the newly formed second insulating layer, that is, the second surface of the first insulating layer has multiple concave and convex structures that are recessed into the first surface, it is less likely that bubbles will be generated between the first and second insulating layers and the first conductive trace, thereby improving the reliability of the electronic device corresponding to the carrier board. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic cross-sectional view of the redistribution sublayer provided in an embodiment of this application; Figure 2 This is a schematic cross-sectional view of the carrier plate provided in an embodiment of this application; Figure 3 A cross-sectional schematic diagram of an electronic device provided in an embodiment of this application; Figure 4 A schematic flowchart illustrating a method for preparing a carrier plate according to an embodiment of this application; Figure 5 This is a cross-sectional schematic diagram of a first conductive layer formed on a substrate, provided as an embodiment of this application. Figure 6 This is a cross-sectional schematic diagram of a first insulating layer formed on a substrate, provided as an embodiment of this application. Figure 7 A cross-sectional schematic diagram of a second insulating material layer formed on a second surface provided in an embodiment of this application; Figure 8 A cross-sectional schematic diagram of a second insulating layer including a plurality of first grooves is provided for an embodiment of this application; Figure 9 A cross-sectional schematic diagram showing the formation of a second conductive layer on the side of the second insulating layer away from the first insulating layer, provided as an embodiment of this application; Figure 10 A cross-sectional schematic diagram showing the formation of a third insulating layer on the side of the second insulating layer away from the first insulating layer, provided for an embodiment of this application; Figure 11 A cross-sectional schematic diagram of a fourth insulating layer formed on the side of the third insulating layer away from the first insulating layer, provided as an embodiment of this application; Figure 12 This is a schematic cross-sectional view of a substrate-removed carrier plate provided in an embodiment of this application.

[0017] Reference numerals: 1. First insulating layer; 11. First surface; 12. Second surface; 13. Undulated structure; 2. Second insulating layer; 21. First groove; 3. First conductive trace; 4. Carrier board; 5. Substrate; 6. Solder ball; 7. Chip; 8. Substrate; 9. Second insulating material layer; 10. Second conductive trace; 14. Third insulating layer; 15. Fourth insulating layer; 151. Second groove; 16. Redirecting sublayer. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0021] Furthermore, when using terms such as "above," "above," "below," "below," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by gaps or other elements. In addition, the terms "first," "second," and "third," etc., are only used for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0022] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0023] The chip packaging structure in the related technology includes a carrier board, which includes at least one layer of conductive traces and an insulating layer. The conductive traces are located inside the insulating layer, and the insulating layer plays a role in protecting, filling and supporting the conductive traces.

[0024] As the number of chip I / Os increases, the demand for higher interconnect density and smaller interconnect width and spacing becomes more stringent. This leads to the problem of air bubbles forming between the insulating layer and the conductive traces, reducing the filling effect of the insulating layer on the conductive traces. This is not conducive to setting up fine circuitry in the chip package structure and ultimately affects the reliability of the chip package structure.

[0025] To address the aforementioned technical problems, the following innovative technical solutions are designed. The specific implementation schemes of this application will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the existing solutions are the result of practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in this embodiment below should be considered contributions made to this application during the invention process, and should not be construed as technical content known to those skilled in the art.

[0026] Please see Figure 1 This embodiment provides a carrier board, which includes at least one redistribution sublayer 16, the redistribution sublayer 16 including a first conductive layer, a first insulating layer 1 and a second insulating layer 2.

[0027] The first conductive layer includes multiple first conductive traces 3.

[0028] The first insulating layer 1 covers part of the sidewall of the first conductive trace 3. Along the thickness direction Z of the first conductive trace 3, the first insulating layer 1 includes a first surface 11 and a second surface 12 disposed opposite to each other. The second surface 12 of the first insulating layer 1 has a plurality of concave and convex structures 13.

[0029] The second insulating layer 2 is located on the second surface 12 of the first insulating layer 1. The second insulating layer 2 covers part of the surface of the first conductive trace 3, and the second insulating layer 2 is in contact with the second surface 12 of the first insulating layer 1.

[0030] by Figure 1 From a certain perspective, the first surface 11 can be the bottom surface of the first insulating layer 1, and the second surface 12 can be the top surface of the first insulating layer 1.

[0031] Along the direction Z from the first surface 11 to the second surface 12, the first conductive trace 3 includes a first surface, a second surface, and a sidewall disposed opposite to each other, with the sidewall connecting the first surface and the second surface.

[0032] Since the first insulating layer 1 covers part of the sidewall of the first conductive trace 3, the thickness D1 of the first insulating layer 1 is less than the thickness D3 of the first conductive trace 3 along the direction Z from the first surface 11 to the second surface 12, that is, the first insulating layer 1 does not completely cover the first conductive trace 3.

[0033] The second insulating layer 2 then covers the remaining sidewall of the first conductive trace 3, but the second insulating layer 2 does not cover the side of the first conductive trace 3 away from the first surface 11, so that the second insulating layer 2 will not affect the electrical connection between the first conductive trace 3 and other conductive traces.

[0034] The dynamic viscosity of the newly formed first insulating layer 1 is less than that of the newly formed second insulating layer 2. Since the dynamic viscosity of the newly formed first insulating layer 1 is relatively small, the second surface 12 of the first insulating layer 1 has a plurality of concave and convex structures 13 that are recessed into the first surface 11. After the second insulating layer 2 is formed, the second insulating layer 2 will come into contact with the concave and convex structures 13.

[0035] Meanwhile, since the dynamic viscosity of the newly formed first insulating layer 1 is relatively small, the first insulating layer 1 can more easily make close contact with the sidewall of the first conductive trace 3, making it less likely for air bubbles to form between the first insulating layer 1 and the first conductive trace 3.

[0036] In addition, in the related technology, the insulating layer at the redistribution sublayer 16 is only one layer, which makes the height-depth-width ratio of the insulating layer at the first conductive trace 3 large, thus making it easy for air bubbles to be generated between the insulating layer and the first conductive trace 3.

[0037] In this embodiment, the insulating layer at the redistribution sublayer 16 is configured as a first insulating layer 1 and a second insulating layer 2 stacked together, i.e., coated with insulating layers at least twice. This allows the aspect ratio of a single insulating layer at the first conductive trace 3 to be smaller, thus reducing the aspect ratio of the first insulating layer 1 and the second insulating layer 2 at the first conductive trace 3. This further ensures tighter contact between the first insulating layer 1 and the second insulating layer 2 and the sidewall of the first conductive trace 3, making it less prone to air bubbles forming between them. This improves the filling effect of the first insulating layer 1 and the second insulating layer 2 on the first conductive trace 3, which is more conducive to setting up fine circuitry in electronic devices and ultimately improves the reliability of the electronic device corresponding to the carrier board 4. The electronic device here can be, for example, a chip package structure.

[0038] Since the dynamic viscosity of the newly formed second insulating layer 2 is greater than that of the newly formed first insulating layer 1, it is not easy for an uneven structure to be generated on the side of the second insulating layer 2 away from the first insulating layer 1. That is, in order to prevent air bubbles from being generated between the second insulating layer 2 and the first conductive trace 3, the side of the second insulating layer 2 away from the first insulating layer 1 can be made smoother, which is more conducive to the subsequent fabrication of fine circuits.

[0039] Based on the above design, this embodiment sets the insulating layer of the redistribution sublayer 16 as a first insulating layer 1 and a second insulating layer 2 stacked together, and the dynamic viscosity of the newly formed first insulating layer 1 is less than that of the newly formed second insulating layer 2. That is, the second surface 12 of the first insulating layer 1 has a plurality of concave and convex structures 13 recessed toward the first surface 11, which makes it less likely for bubbles to be generated between the first insulating layer 1 and the second insulating layer 2 and the first conductive trace 3, thereby improving the reliability of the electronic device corresponding to the carrier board 4.

[0040] In some possible implementations, please refer again. Figure 1 Along the direction Z from the first surface 11 to the second surface 12, the thickness D1 of the first insulating layer 1 is less than the thickness D2 of the second insulating layer 2.

[0041] In related technologies, the bubbles generated between the insulating layer and the first conductive trace 3 mainly appear on the first side of the insulating layer and the first conductive trace 3 near the first surface 11, i.e. Figure 1 The lower part of the first conductive trace 3 as seen from the viewpoint.

[0042] Therefore, in this embodiment, the thickness D1 of the first insulating layer 1 is set to be less than the thickness D2 of the second insulating layer 2, which makes it less likely for bubbles to form between the first insulating layer 1 and the first conductive trace 3. In other words, the position where bubbles are more likely to form between the insulating layer and the first conductive trace 3 in related technologies is less likely to form bubbles in this embodiment.

[0043] Optionally, the ratio of the thickness D1 of the first insulating layer 1 to the thickness D3 of the first conductive trace 3 is greater than or equal to 0.25 and less than or equal to 0.5.

[0044] For example, the ratio of thickness D1 to thickness D3 can be 0.25, 0.3, 0.35, 0.4, 0.45 or 0.5, etc. Setting the ratio of thickness D1 to thickness D3 reasonably can make it less likely for bubbles to form between the first insulating layer 1 and the first conductive trace 3.

[0045] Optionally, the ratio of the thickness D2 of the second insulating layer 2 to the thickness D3 of the first conductive trace 3 is greater than or equal to 0.7 and less than or equal to 1.05.

[0046] For example, the ratio of thickness D2 to thickness D3 can be 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1 or 1.05, etc. Setting the ratio of thickness D1 to thickness D3 appropriately can make it less likely for bubbles to form between the second insulating layer 2 and the first conductive trace 3.

[0047] Optionally, the thickness D1 of the first insulating layer 1 is greater than or equal to 2.5 μm and less than or equal to 10 μm.

[0048] The thickness D3 of the first conductive trace 3 is usually greater than or equal to 10 μm and less than or equal to 20 μm. Therefore, the thickness D1 of the first insulating layer 1 is greater than or equal to 2.5 μm and less than or equal to 10 μm. For example, the thickness D1 can be 2.5 μm, 3 μm, 5 μm, 7 μm, 9 μm or 10 μm, etc.

[0049] Optionally, the thickness D2 of the second insulating layer 2 is greater than or equal to 7 μm and less than or equal to 21 μm.

[0050] For example, the thickness D2 can be 7μm, 10μm, 12μm, 15μm, 18μm, 20μm or 21μm, etc.

[0051] Optionally, the distance D4 from the side of the second insulating layer 2 away from the first surface 11 to the first surface 11 is greater than the distance D3 from the side of the first conductive trace 3 away from the first surface 11 to the first surface 11. In this way, the filling effect of the second insulating layer 2 on the first conductive trace 3 can be improved.

[0052] Optionally, the difference between the distance D4 from the side of the second insulating layer 2 away from the first surface 11 to the first surface 11 and the distance D3 from the side of the first conductive trace 3 away from the first surface 11 to the first surface 11 is greater than or equal to 2μm and less than or equal to 6μm. For example, it can be 2μm, 3μm, 4μm, 5μm or 6μm, etc.

[0053] In some possible implementations, please refer again. Figure 1 The distance D4 from the side of the second insulating layer 2 away from the first surface 11 to the first surface 11 is greater than the distance D3 from the side of the first conductive trace 3 away from the first surface 11 to the first surface 11.

[0054] Optionally, the second insulating layer 2 has a plurality of first grooves 21 on the side away from the first insulating layer 1, and the first grooves 21 expose the corresponding first conductive traces 3 on the side away from the first surface 11.

[0055] When the first conductive traces 3 are connected in a direction parallel to the first insulating layer 1, it is not necessary to expose the side of the first conductive trace 3 away from the first surface 11 through the first groove 21. When the side of the first conductive trace 3 away from the first surface 11 needs to be electrically connected to conductive traces other than the redistribution sublayer 16, the corresponding first conductive trace 3 needs to be exposed through the first groove 21. This makes it easier for the side of the first conductive trace 3 away from the first surface 11 to be electrically connected to other conductive traces. For example, it makes it easier for the first conductive trace 3 to be electrically connected to the conductive traces of the substrate 5 in the electronic device, or it makes it easier for the first conductive trace 3 to be electrically connected to the pins of the chip 7 in the electronic device.

[0056] Optionally, the first surface 11 exposes the side of the first conductive trace 3 away from the second insulating layer 2. This makes it easier for the side of the first conductive trace 3 near the first surface 11 to be electrically connected to other conductive traces, such as making it easier for the first conductive trace 3 to be electrically connected to the conductive traces of the substrate 5 in the electronic device, or making it easier for the first conductive trace 3 to be electrically connected to the solder balls 6 in the electronic device.

[0057] Optionally, the first surface 11 is flush with the side of the first conductive trace 3 away from the second insulating layer 2. This allows the carrier board 4 to be electrically connected to the rest of the electronic device.

[0058] Optionally, the orthographic projection of the first insulating layer 1 onto the plane containing the first surface 11 coincides with the orthographic projection of the second insulating layer 2 onto the plane containing the first surface 11. That is, the sidewalls of the first insulating layer 1 and the second insulating layer 2 are aligned with each other, which can further improve the reliability of the carrier plate 4.

[0059] In some possible implementations, please refer again. Figure 1 The first insulating layer 1 is in contact with the sidewall of the first conductive trace 3. That is, the first insulating layer 1 is in close contact with the sidewall of the first conductive trace 3, so that air bubbles are less likely to form between the first insulating layer 1 and the first conductive trace 3.

[0060] Optionally, the second insulating layer 2 is in contact with the sidewall of the first conductive trace 3. That is, the second insulating layer 2 is in close contact with the sidewall of the first conductive trace 3, so that air bubbles are less likely to form between the second insulating layer 2 and the first conductive trace 3.

[0061] Optionally, the surface of the uneven structure 13 is wavy. Since the dynamic viscosity of the first insulating layer 1 is relatively small compared to that of the second insulating layer 2, a wavy uneven structure 13 will naturally form on the first insulating layer 1 when the first insulating layer 1 is coated.

[0062] Optionally, the material of the first insulating layer 1 includes polyimide, and the material of the second insulating layer 2 includes polyimide.

[0063] The main materials of the first insulating layer 1 and the second insulating layer 2 can both be polyimide. By adding different solvents, the dynamic viscosity of the first insulating layer 1 can be made to be less than that of the second insulating layer 2.

[0064] For some possible implementations, please refer to Figure 2 The redistribution sublayer 16 is multi-layered, and the multi-layer redistribution sublayer 16 is stacked sequentially along the thickness direction Z from the carrier board 4. The first conductive traces 3 in the multi-layer redistribution sublayer 16 are electrically connected sequentially.

[0065] The carrier board 4 can be designed to include multiple redistribution sublayers 16, as needed, with the first conductive traces 3 interconnected between each redistribution sublayer 16. For example... Figure 2 The carrier board 4 shown includes two redistribution sublayers 16. This improves the overall reliability of the carrier board 4, thereby further enhancing the reliability of the electronic device corresponding to the carrier board 4.

[0066] For some possible implementations, please refer to Figure 2 and Figure 3 This application also provides an electronic device, which includes the carrier plate 4 described in this application, or includes the carrier plate 4 prepared by the method for preparing the carrier plate described in this application.

[0067] The electronic device can be a chip package structure. The electronic device also includes a substrate 5, a chip 7 and solder balls 6. The substrate 5 has conductive traces. The carrier 4 in this application can be located between the substrate 5 and the solder balls 6. The carrier 4 is electrically connected to the conductive traces and solder balls 6 in the substrate 5.

[0068] The carrier 4 in this application may also be located between the substrate 5 and the chip 7. The carrier 4 is electrically connected to the conductive traces in the substrate 5 and the pins of the chip 7.

[0069] In this embodiment, since the electronic device includes the carrier board 4 of this application, the first insulating layer 1 and the second insulating layer 2 in the carrier board 4 of the electronic device are in close contact with the sidewall of the first conductive trace 3, making it less likely for air bubbles to form between the first insulating layer 1 and the second insulating layer 2 and the first conductive trace 3. This can improve the filling effect of the first insulating layer 1 and the second insulating layer 2 on the first conductive trace 3, which is more conducive to setting up the fine circuit of the electronic device and ultimately improves the reliability of the electronic device.

[0070] For some possible implementations, please refer to Figure 4 This application also provides a method for preparing a carrier plate, the method comprising: S10: Provide a substrate 8.

[0071] Please see again Figure 3 When the formed carrier plate 4 is located between the substrate 5 and the solder ball 6, the substrate 8 can be the substrate. When the formed carrier plate 4 is located between the substrate 5 and the chip 7, the substrate 8 can be the substrate 5.

[0072] S11: A first conductive layer is formed on the substrate 8, the first conductive layer including a plurality of first conductive traces 3.

[0073] Please see Figure 5 A first conductive layer is formed on substrate 8.

[0074] S12: A first insulating layer 1 is formed on the substrate 8 along the thickness direction Z of the first conductive trace 3. The first insulating layer 1 includes a first surface 11 and a second surface 12 disposed opposite to each other. The thickness D1 of the first insulating layer 1 is less than the thickness D3 of the first conductive trace 3.

[0075] Please see Figure 6 A first insulating layer 1 is formed on the substrate 8. The dynamic viscosity of the first insulating layer 1 is relatively small. Therefore, after the first insulating layer 1 is formed, a wavy uneven structure 13 will be formed on the first insulating layer 1.

[0076] S13: A second insulating layer 2 is formed on the second surface 12. The second insulating layer 2 covers part of the surface of the first conductive trace 3. The dynamic viscosity of the first insulating layer 1 is less than that of the second insulating layer 2.

[0077] Please see Figure 7 and Figure 8 A second insulating layer 2 is formed on the second surface 12. The dynamic viscosity of the second insulating layer 2 is greater than that of the first insulating layer 1. Therefore, the side of the second insulating layer 2 away from the first surface 11 is not prone to producing uneven structure 13 and is a flat surface.

[0078] The dynamic viscosity of the first insulating layer 1 in the carrier plate 4 formed by the above method is less than that of the second insulating layer 2. Multiple concave-convex structures 13 that are recessed toward the first surface 11 can be formed on the second surface 12 of the first insulating layer 1. After the second insulating layer 2 is formed, the second insulating layer 2 will come into contact with the concave-convex structures 13.

[0079] Meanwhile, the dynamic viscosity of the first insulating layer 1 is relatively low. Therefore, the first insulating layer 1 can more easily make close contact with the sidewall of the first conductive trace 3, making it less likely for air bubbles to form between the first insulating layer 1 and the first conductive trace 3.

[0080] Furthermore, by applying the first insulating layer 1 and the second insulating layer 2 twice, the aspect ratio of the single insulating layer at the first conductive trace 3 can be reduced, which can improve the problem of the difficulty of thick coating process. That is, the aspect ratio of the first insulating layer 1 and the second insulating layer 2 at the first conductive trace 3 can be reduced, which can further make the first insulating layer 1 and the second insulating layer 2 in close contact with the sidewall of the first conductive trace 3, making it less likely for air bubbles to form between the first insulating layer 1 and the second insulating layer 2 and the first conductive trace 3. This can improve the filling effect of the first insulating layer 1 and the second insulating layer 2 on the first conductive trace 3, which is more conducive to setting up the fine circuit of electronic equipment, and ultimately improves the reliability of the electronic equipment corresponding to the carrier board 4.

[0081] Since the dynamic viscosity of the second insulating layer 2 is greater than that of the first insulating layer 1, it is not easy for uneven structures to be generated on the side of the second insulating layer 2 away from the first insulating layer 1. That is, in order to make it less likely for air bubbles to be generated between the second insulating layer 2 and the first conductive trace 3, the side of the second insulating layer 2 away from the first insulating layer 1 can be made smoother, which is more conducive to the subsequent fabrication of fine circuits.

[0082] In some possible implementations, the step of forming the first insulating layer 1 on the substrate 8 includes: When the minimum spacing W between two adjacent first conductive traces 3 is greater than 0 and less than or equal to 5 μm, a first insulating layer 1 with a dynamic viscosity greater than or equal to 5 cp and less than or equal to 500 cp is formed on the substrate 8.

[0083] Please see again Figure 7 For example, when the minimum pitch W is 1μm, 2μm, 3μm, 4μm, or 5μm, a first insulating layer 1 with a dynamic viscosity of 5cp, 50cp, 100cp, 200cp, 300cp, 400cp, 450cp, or 500cp can be formed on the substrate 8. This makes it less likely for bubbles to form between the first insulating layer 1 and the first conductive trace 3.

[0084] When the minimum spacing W between two adjacent first conductive traces 3 is greater than 5 μm, a first insulating layer 1 with a dynamic viscosity greater than or equal to 50 cp and less than or equal to 1000 cp is formed on the substrate 8.

[0085] For example, when the minimum pitch W is 6μm, 7μm, 9μm, 11μm, or 12μm, a first insulating layer 1 with a dynamic viscosity of 50cp, 100cp, 200cp, 500cp, 700cp, 900cp, or 1000cp can be formed on the substrate 8. This makes it less likely for bubbles to form between the first insulating layer 1 and the first conductive trace 3.

[0086] Optionally, the step of forming the second insulating layer 2 on the second surface 12 includes: A second insulating layer 2 with a dynamic viscosity greater than or equal to 3000 cp is formed on the second surface 12.

[0087] For example, a second insulating layer 2 with a dynamic viscosity of 3000 cp, 3200 cp, 3500 cp, or 4000 cp can be formed on the second surface 12. In this way, it is less likely for air bubbles to form between the second insulating layer 2 and the first conductive trace 3, and the side of the second insulating layer 2 away from the first surface 11 is flatter.

[0088] In some possible implementations, the step of forming the second insulating layer 2 on the second surface 12 includes: Please see again Figure 7 A second insulating material layer 9 is formed on the second surface 12.

[0089] Please see again Figure 8 A second insulating layer 2 comprising a plurality of first grooves 21 is formed on the side of the second insulating material layer 9 away from the first insulating layer 1. The first grooves 21 expose the side of the first conductive trace 3 away from the first surface 11.

[0090] In this way, it is easier for the side of the first conductive trace 3 away from the first surface 11 to be electrically connected to the other conductive traces. For example, it is easier for the first conductive trace 3 to be electrically connected to the conductive traces of the substrate 5 in the electronic device, or it is easier for the first conductive trace 3 to be electrically connected to the pins of the chip 7 in the electronic device.

[0091] In some possible implementations, after the step of forming the second insulating layer 2 on the second surface 12, the method further includes: Please see Figure 9 A second conductive layer is formed on the side of the second insulating layer 2 away from the first insulating layer 1. The second conductive layer includes a plurality of second conductive traces 10, which are electrically connected to the first conductive traces 3.

[0092] Please see Figure 10 A third insulating layer 14 is formed on the side of the second insulating layer 2 away from the first insulating layer 1, along the direction Z from the first surface 11 to the second surface 12, and the thickness of the third insulating layer 14 is less than the thickness of the second conductive trace 10.

[0093] The dynamic viscosity of the third insulating layer 14 is the same as that of the first insulating layer 1. The dynamic viscosity of the third insulating layer 14 is relatively small. Therefore, after the third insulating layer 14 is formed, a wavy uneven structure 13 will be formed on the third insulating layer 14.

[0094] Please see Figure 11 A fourth insulating layer 15 is formed on the side of the third insulating layer 14 away from the first insulating layer 1. The fourth insulating layer 15 covers a portion of the second conductive trace 10. The side of the fourth insulating layer 15 away from the first insulating layer 1 has a second groove 151 exposing the second conductive trace 10. The dynamic viscosity of the third insulating layer 14 is less than that of the fourth insulating layer 15.

[0095] The dynamic viscosity of the fourth insulating layer 15 is the same as that of the second insulating layer 2. The dynamic viscosity of the fourth insulating layer 15 is greater than that of the third insulating layer 14. Therefore, the side of the fourth insulating layer 15 that is far from the first surface 11 is not prone to producing uneven structure 13 and is a flat surface.

[0096] The dynamic viscosity of the third insulating layer 14 in the carrier plate 4 formed by the above method is less than that of the fourth insulating layer 15. Multiple uneven structures 13 can be formed on the third insulating layer 14. After the fourth insulating layer 15 is formed, the fourth insulating layer 15 will come into contact with the uneven structures 13 on the third insulating layer 14.

[0097] Meanwhile, the third insulating layer 14 has a relatively low dynamic viscosity, so the third insulating layer 14 can more easily make close contact with the sidewall of the second conductive trace 10, making it less likely for air bubbles to form between the third insulating layer 14 and the second conductive trace 10.

[0098] Furthermore, by applying the third insulating layer 14 and the fourth insulating layer 15 twice, the aspect ratio of the single insulating layer at the second conductive trace 10 can be reduced. This reduces the aspect ratio of the third insulating layer 14 and the fourth insulating layer 15 at the second conductive trace 10, further ensuring close contact between the third insulating layer 14 and the fourth insulating layer 15 and the sidewall of the second conductive trace 10. This makes it less likely for air bubbles to form between the third insulating layer 14 and the fourth insulating layer 15 and the second conductive trace 10, thereby improving the filling effect of the third insulating layer 14 and the fourth insulating layer 15 on the second conductive trace 10. This is more conducive to setting up fine circuits in electronic devices and ultimately improves the reliability of the electronic devices corresponding to the carrier board 4.

[0099] The above method can also be used to form another redistribution sublayer 16 on the side of the fourth insulating layer 15 away from the first insulating layer 1. This embodiment only illustrates that the formed carrier board 4 includes two redistribution sublayers 16.

[0100] Optionally, the first insulating layer 1, the second insulating layer 2, the third insulating layer 14 and the fourth insulating layer 15 can be cured, for example by baking.

[0101] Optionally, after the step of forming the fourth insulating layer 15 on the side of the third insulating layer 14 away from the first insulating layer 1, the method further includes: Please see Figure 12 Remove substrate 8.

[0102] Please see again Figure 3 When the formed carrier plate 4 is located between the substrate 5 and the solder ball 6, the substrate 8 needs to be removed.

[0103] When the carrier plate 4 is located between the substrate 5 and the chip 7, the substrate 8 can be the substrate 5, and in this case, it is not necessary to remove the substrate 8.

[0104] Figure 12 The final carrier plate 4 and Figure 2 The carrier plate 4 is the same.

[0105] In summary, the above method can form multiple redistribution sublayers 16, and the insulating layer and conductive traces in each redistribution sublayer 16 are less likely to generate air bubbles, which is more conducive to setting up fine circuits for electronic devices and ultimately improving the reliability of the electronic devices corresponding to the carrier board 4.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A carrier plate, characterized by The carrier plate comprises at least one rewiring sub-layer, which comprises: a first conductive layer comprising a plurality of first conductive traces; a first insulating layer covering part of the sidewalls of the first conductive traces, along the thickness direction of the first conductive traces, the first insulating layer comprises oppositely arranged first and second surfaces, and the second surface of the first insulating layer has a plurality of concave-convex structures; a second insulating layer on the second surface of the first insulating layer, covering part of the surface of the first conductive traces, and the second insulating layer and the second surface of the first insulating layer are in contact with each other.

2. The carrier of claim 1, wherein The thickness of the first insulating layer is less than the thickness of the second insulating layer; Preferably, the ratio of the thickness of the first insulating layer to the thickness of the first conductive traces is greater than or equal to 0.25 and less than or equal to 0.5; Preferably, the ratio of the thickness of the second insulating layer to the thickness of the first conductive traces is greater than or equal to 0.7 and less than or equal to 1.05; Preferably, the thickness of the first conductive traces is greater than or equal to 10 μm and less than or equal to 20 μm; Preferably, the thickness of the first insulating layer is greater than or equal to 2.5 μm and less than or equal to 10 μm; Preferably, the thickness of the second insulating layer is greater than or equal to 7 μm and less than or equal to 21 μm.

3. The carrier of claim 1, wherein The distance from the side of the second insulating layer away from the first surface to the first surface is greater than the distance from the side of the first conductive traces away from the first surface to the first surface; Preferably, the side of the second insulating layer away from the first insulating layer has a plurality of first grooves, and the first grooves expose the side of the corresponding first conductive traces away from the first surface; Preferably, the first surface exposes the side of the first conductive traces away from the second insulating layer; Preferably, the first surface is flush with the side of the first conductive traces away from the second insulating layer; Preferably, the orthographic projection of the first insulating layer on the plane where the first surface is located coincides with the orthographic projection of the second insulating layer on the plane where the first surface is located.

4. The carrier of claim 1, wherein The first insulating layer is in contact with the sidewall of the first conductive traces; Preferably, the second insulating layer is in contact with the sidewall of the first conductive traces; Preferably, the surface of the concave-convex structure is wavy; Preferably, the material of the first insulating layer comprises polyimide; Preferably, the material of the second insulating layer comprises polyimide.

5. The carrier plate according to any one of claims 1 to 4, characterized in that The rewiring sub-layer is multi-layered, the multi-layered rewiring sub-layers are sequentially stacked along the thickness direction of the substrate, and the first conductive traces in the multi-layered rewiring sub-layers are sequentially electrically connected.

6. A method of producing a carrier plate, characterized by, The method comprises: providing a substrate; forming a first conductive layer on the substrate, the first conductive layer comprising a plurality of first conductive traces; forming a first insulating layer on the substrate, along the thickness direction of the substrate, the first insulating layer comprising oppositely arranged first and second surfaces, and the thickness of the first insulating layer being less than the thickness of the first conductive traces; forming a second insulating layer on the second surface, the second insulating layer covering part of the surfaces of the first conductive traces, the first insulating layer having a dynamic viscosity less than that of the second insulating layer.

7. The method of claim 6, wherein the carrier plate is prepared by The step of forming the first insulating layer on the substrate comprises: when the minimum distance between two adjacent first conductive traces is greater than 0 and less than or equal to 5 μm, forming a first insulating layer on the substrate, the first insulating layer having a dynamic viscosity greater than or equal to 5 cp and less than or equal to 500 cp; when the minimum distance between two adjacent first conductive traces is greater than 5 μm, forming a first insulating layer on the substrate, the first insulating layer having a dynamic viscosity greater than or equal to 50 cp and less than or equal to 1000 cp; Preferably, the step of forming the second insulating layer on the second surface comprises: forming a second insulating layer on the second surface, the second insulating layer having a dynamic viscosity greater than or equal to 3000 cp.

8. The method of claim 6, wherein the carrier plate is prepared by, The step of forming the second insulating layer on the second surface comprises: forming a second insulating material layer on the second surface; forming a second insulating layer on the second surface, the second insulating layer having a dynamic viscosity greater than or equal to 3000 cp.

9. The method of claim 6-8, wherein, The step of forming the second insulating layer on the second surface comprises: forming a second insulating material layer on the second surface; forming a second insulating layer on the second surface, the second insulating layer having a dynamic viscosity greater than or equal to 3000 cp. The step of forming the second insulating layer on the second surface comprises: forming a second conductive layer on the side of the second insulating layer away from the first insulating layer, the second conductive layer comprising a plurality of second conductive traces, the second conductive traces being electrically connected to the first conductive traces; forming a third insulating layer on the side of the second insulating layer away from the first insulating layer, the third insulating layer having a thickness less than that of the second conductive traces in the direction from the first surface to the second surface; 10. An electronic device, comprising: forming a fourth insulating layer on the side of the third insulating layer away from the first insulating layer, the fourth insulating layer covering part of the second conductive traces, the side of the fourth insulating layer away from the first insulating layer having second recesses exposing the second conductive traces, the third insulating layer having a dynamic viscosity less than that of the fourth insulating layer; Preferably, after the step of forming the fourth insulating layer on the side of the third insulating layer away from the first insulating layer, the method further comprises: removing the substrate. The electronic device comprises the carrier plate of any one of claims 1-5, or the carrier plate prepared by the method of any one of claims 6-9.

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