I2C interface and working method thereof

Abstract

The invention discloses an I2C interface and a working method thereof.The I2C interface is integrated on a chip and used for achieving signal transmission between the I2C interface and an external interface of the chip, and the I2C interface specifically comprises a register module, a core processing module and an open-drain output module; the working method of the I2C interface comprises the following steps: the open-drain output module obtains an open-drain enable signal in the register module, receives an output control signal output by the core processing module, performs operator operation on the open-drain enable signal and the output control signal to obtain an open-drain output control signal, and outputs the open-drain output control signal to a PAD in a chip, therefore, the PAD outputs an open-drain signal to the outside of the chip. By adopting the scheme, the push-pull output type PAD can be used by the I2C interface, and even if the PAD does not have an open-drain output function, a signal completely conforming to an I2C communication protocol can be output, so that normal communication with other interfaces is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to an I2C interface and a working method thereof, and belongs to the technical field of computers. BACKGROUND

[0002] The I2C bus (English name: Inter Integrated Circuit) is a simple, bidirectional two-wire synchronous serial bus developed by Philips Company, which connects different nodes to the same bus system through the clock line SCL and the data line SDA to realize effective communication between devices connected to the bus. Among them, the I2C bus requires that the clock line SCL and the data line SDA both comply with the open drain output rule, which ensures normal communication between nodes and is the key to eliminating the risk of level conflict between nodes, supporting multi-master arbitration, realizing voltage adaptation and reducing communication power consumption. Therefore, the open drain output function is the most important thing for the implementation of the I2C interface.

[0003] In the traditional implementation scheme of the I2C interface, the I2C bus outputs a push-pull output control signal to the chip PAD (English name: Peripheral Access Device, Chinese name: pin pad), and in order to comply with the open drain output rule, it needs to completely rely on the open drain output function of the PAD technology to convert the push-pull output control signal into an open drain signal that complies with the I2C protocol specification, and then realize normal communication with other interfaces.

[0004] However, in this traditional implementation, if the target chip does not provide such a dedicated open drain PAD in the PAD library, or the PAD cannot use the open drain function due to other reasons, the standard I2C communication function cannot be realized. Secondly, when the chip needs to be designed and migrated across different semiconductor process nodes or different foundries, the original open drain PAD may not be directly compatible, and the design team needs to find, verify or customize a new PAD, thereby increasing the design cycle and cost of the chip. SUMMARY

[0005] In order to solve the above technical problems, the present application provides an I2C interface and a working method thereof.

[0006] To this end, according to a first aspect of the present application, an I2C interface is provided, which is integrated in a chip and is used to realize signal transmission between the chip and an external interface, characterized in that the I2C interface specifically comprises: a register module, a core processing module, and an open drain output module. The register module is connected with the open drain output module and is used to output an open drain enable signal to the open drain output module. The core processing module is connected with the open-drain output module, and is configured to output an output control signal to the open-drain output module. The open-drain output module is connected with the register module and the core processing module, and is configured to receive an open-drain enable signal output by the register module and an output control signal output by the core processing module, and output an open-drain output control signal according to the open-drain enable signal and the output control signal, the open-drain output control signal being a signal conforming to the I2C communication protocol. The open-drain output module is further configured to output the open-drain output control signal to a PAD in the chip, so that the PAD outputs an open-drain signal to the outside of the chip.

[0007] According to a second aspect of the present application, a working method of an I2C interface is provided, and the method comprises: In step S1, the open-drain output module acquires an open-drain enable signal in the register module, and receives an output control signal output by the core processing module. In step S2, the open-drain output module performs operation on the open-drain enable signal and the output control signal to obtain an open-drain output control signal, the open-drain output control signal comprising an open-drain output data signal and an open-drain output enable signal conforming to the I2C communication protocol. In step S3, the open-drain output module outputs the open-drain output control signal to a PAD in the chip, so that the PAD outputs an open-drain signal conforming to the I2C communication protocol to the outside of the chip.

[0008] According to a third aspect of the present application, a chip is provided, and the chip comprises the I2C interface described above, and the chip communicates with an interface or a device outside the chip through the I2C interface.

[0009] In the technical solution provided by the present application, the open-drain output function is moved from the PAD to the open-drain output module inside the I2C interface, so that the open-drain output control signal output by the open-drain output module can control the open-drain output of the outside of the chip, thereby getting rid of the dependence on the open-drain function of the PAD. By using the present solution, the I2C interface can use the push-pull output type PAD, that is, in the case that the PAD does not have the open-drain output function, the output signal can also completely conform to the I2C communication protocol, thereby realizing the normal communication between the I2C interface and other interfaces. Meanwhile, the I2C interface provided by the present application can also be compatible with the PAD with the open-drain function, thereby greatly improving the autonomy, flexibility and portability of the chip design. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the present application, the following will briefly introduce the prior art or the embodiments of the present application with reference to the drawings. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0011] Figure 1 is a schematic diagram of an I2C working structure; Figure 2 is a schematic diagram of an I2C interface working structure in a conventional manner; Figure 3 is a schematic diagram of I2C interface output signal change in a conventional manner; Figure 4 is a schematic diagram of an I2C interface structure provided by an embodiment of the present application; Figure 5 is a schematic diagram of a first open-drain output sub-module structure in an I2C interface provided by an embodiment of the present application; Figure 6 is a schematic diagram of a second open-drain output sub-module structure in an I2C interface provided by an embodiment of the present application; Figure 7 is a schematic diagram of I2C interface output signal change in the present application provided by an embodiment of the present application; Figure 8 is a schematic diagram of an I2C interface working flow provided by an embodiment of the present application; Figure 9 is an I2C interface output truth table provided by an embodiment of the present application. DETAILED DESCRIPTION

[0012] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the drawings.

[0013] The following description refers to the accompanying drawings. Unless otherwise indicated, like numbers in the different figures indicate the same or similar elements. The following example embodiments described are not meant to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0014] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the drawings. Embodiment One

[0015] Before describing the I2C interface provided by the present application, first, the related background information of the embodiments of the present application will be described.

[0016] As Figure 1As shown, the I2C bus connects different nodes to the same bus system through the clock line SCL and the data line SDA, and uses a unique timing control method, address addressing mechanism and open drain output rule to realize effective communication between multiple master and slave nodes. Since the I2C bus requires that the clock line SCL and the data line SDA both comply with the open drain output rule, both lines need to be externally connected to a pull-up resistor to ensure the voltage stability of the high level on the line.

[0017] Figure 2 A working structure schematic diagram of the I2C interface in the traditional design method is shown, wherein the chip PAD is located on the silicon substrate inside the chip and is a physical interface for connecting the chip inside and the external device, which cannot be directly seen by the user. The PAD is connected to the pin (PIN) after packaging through a metal wire, and the PAD pin is divided into an input pin and an output pin, which are respectively used for receiving external signals and outputting signals to the outside, and play a role in signal transmission. The I2C interface outputs control signals in a push-pull mode to the chip PAD through the clock line SCL and the data line SDA, and generally needs to rely on the open drain output function of the PAD process to convert the push-pull output control signal into an open drain output signal, so as to normally communicate with other interfaces.

[0018] Figure 3 A schematic diagram of the change of the output signal of the I2C interface in the traditional design method is shown. The signal output by the chip using the I2C interface in the traditional design method needs to comply with the I2C communication protocol, that is, it needs to comply with the I2C bus open drain output rule, and generally needs to use a PAD with an open drain function. The PAD with an open drain function processes the signal received from the I2C interface to obtain an open drain signal output by the chip to other interfaces. When the I2C interface push-pull output is high, the signal outputs a high impedance state, and when the push-pull output is low, the signal outputs a low level. If the PAD itself does not have an open drain output function, the signal output by the PAD does not comply with the I2C communication protocol, thereby causing the I2C interface to be unable to normally communicate with other interfaces. As can be seen, in the traditional I2C interface chip, the use of the I2C interface in the chip needs to completely rely on the open drain function of the PAD.

[0019] Based on this, the embodiments of the present application provide an I2C interface and a working method thereof. The I2C interface provided by the present application can not rely on the open drain function of the PAD, thereby reducing the cost of the chip and expanding the application scenario of the I2C interface.

[0020] The I2C interface and the working method thereof provided by the present application will be described in detail below.

[0021] As Figure 4As shown, the embodiment of the present application provides an I2C interface integrated in a chip for realizing signal transmission between the chip and an external interface, which comprises a register module, a core processing module and an open-drain output module. The register module is connected with the open-drain output module and is configured to output an open-drain enable signal to the open-drain output module. The core processing module is connected with the open-drain output module and is configured to output an output control signal to the open-drain output module. The open-drain output module is connected with the register module and the core processing module, configured to receive the open-drain enable signal output by the register module and the output control signal output by the core processing module, and output an open-drain output control signal according to the open-drain enable signal and the output control signal, wherein the open-drain output control signal is a signal complying with the I2C communication protocol rules. The open-drain output module is further configured to output the open-drain output control signal to a PAD in the chip, so that the PAD outputs an open-drain signal to the outside of the chip. Specifically, the open-drain output module comprises a first open-drain output submodule and a second open-drain output submodule, which are respectively connected with the register module and the core processing module, configured to receive the open-drain enable signal output by the register module and the output control signal output by the core processing module, and output an open-drain output control signal according to the open-drain enable signal and the output control signal, and output the open-drain output control signal to the PAD in the chip. Further, the first open-drain output submodule is connected with a clock line open-drain enable signal line in the register module, a clock line output enable signal line and a clock line output data signal line in the core processing module, configured to receive the clock line open-drain enable signal output by the register module, receive the clock line output enable signal in the output control signal output by the core processing module, and receive the clock line output data signal in the output control signal output by the core processing module. The second open-drain output submodule is connected with a data line open-drain enable signal line in the register module, a data line output enable signal line and a data line output data signal line in the core processing module, configured to receive the data line open-drain enable signal output by the register module, receive the data line output enable signal in the output control signal output by the core processing module, and receive the data line output data signal in the output control signal output by the core processing module. In the embodiment, the chip further comprises a first PAD and a second PAD, the first open-drain output sub-module is connected with the first PAD of the chip, and is configured to output a clock line open-drain output enable signal and a clock line open-drain output data signal to the first PAD of the chip according to a clock line open-drain enable signal, a clock line output enable signal and a clock line output data signal, so that the first PAD outputs a clock line open-drain signal conforming to an I2C communication protocol to outside of the chip; and the second open-drain output sub-module is connected with the second PAD, and is configured to output a data line open-drain output enable signal and a data line open-drain output data signal to the second PAD of the chip according to a data line open-drain enable signal, a data line output enable signal and a data line output data signal, so that the second PAD outputs a data line open-drain signal conforming to the I2C communication protocol to outside of the chip. Specifically, the first PAD and the second PAD respectively output the clock line open-drain signal and the data line open-drain signal to outside of the chip. An implementable manner is shown in FIG. 1, which comprises a chip and a peripheral device. Figure 5 Specifically, the first open-drain output sub-module comprises a first AND gate, a first NOT gate, a second AND gate, a second NOT gate and a third AND gate. The first AND gate is connected with the first NOT gate, the register module and the core processing module, and is configured to operate the clock line open-drain enable signal output by the register module and the clock line output enable signal and the clock line output data signal in the output control signal output by the core processing module to obtain a first result, and output the first result to the first NOT gate. The first NOT gate is connected with the first AND gate and the second AND gate, and is configured to operate the first result output by the first AND gate to obtain a second result, and output the second result to the second AND gate. The second AND gate is connected with the first NOT gate and the core processing module, and is configured to operate the clock line output enable signal in the output control signal output by the core processing module and the second result to obtain the clock line open-drain output enable signal. The second NOT gate is connected with the register module and the third AND gate, and is configured to operate the clock line open-drain enable signal output by the register module to obtain a third result, and output the third result to the third AND gate. The third AND gate is connected with the core processing module and the second NOT gate, and is configured to operate the clock line output data signal in the output control signal output by the core processing module and the third result to obtain the clock line open-drain output data signal. An implementable manner is shown in FIG. 1, which comprises a chip and a peripheral device. Figure 6 Specifically, the second open-drain output sub-module comprises a fourth AND gate, a third NOT gate, a fifth AND gate, a fourth NOT gate and a sixth AND gate. The fourth AND gate is connected with the third NOT gate, the register module and the core processing module, and is used for operating the data line open drain enable signal output by the register module, the data line output enable signal and the data line output data signal in the output control signal output by the core processing module, obtaining a fourth result, and outputting the fourth result to the third NOT gate; The third NOT gate is connected with the fourth AND gate and the fifth AND gate, and is used for operating the fourth result output by the fourth AND gate to obtain a fifth result, and outputting the fifth result to the fifth AND gate; The fifth AND gate is connected with the third NOT gate and the core processing module, and is used for operating the data line output enable signal in the output control signal output by the core processing module and the fifth result to obtain the data line open drain output enable signal; The fourth NOT gate is connected with the register module and the sixth AND gate, and is used for operating the data line open drain enable signal output by the register module to obtain a sixth result, and outputting the sixth result to the sixth AND gate; The sixth AND gate is connected with the core processing module and the fourth NOT gate, and is used for operating the data line output data signal in the output control signal output by the core processing module and the sixth result to obtain the data line open drain output data signal.

[0022] The I2C interface provided by the above scheme can completely comply with the I2C communication protocol in the case of using the push-pull output type PAD, that is, the PAD does not have the open drain output function, so as to realize normal communication with other interfaces.

[0023] As Figure 7As shown, it is a schematic diagram of signal change of I2C interface output signal to chip PAD in the application, I2C open drain enables to open, the core processing module outputs data as in the prior art, there is high and low level change, the core processing module output enable outputs high level, the open drain output module receives the output control signal of the core processing module, and the output enable signal becomes high level only when the output data signal of the output control signal is low level, and remains low level when the output data is high level, which is a typical open drain output signal mode, under the control of the open drain output module, the signal to the PAD internal is in high impedance state when the I2C interface open drain enable is low, and is in low level when the output enable is high, at this time, the signal has met the rule of I2C bus open drain output, and there is no need to require the PAD function, and the signal after passing through the PAD is an open drain signal output to the chip outside; At this time, the I2C interface does not need to depend on whether the PAD has the open drain function, and the PAD with or without the open drain function can output the open drain signal meeting the I2C communication protocol; Compared with the I2C interface in the traditional mode, the I2C interface provided in the application scheme has higher compatibility, and can output the signal meeting the I2C communication protocol completely in the case that the PAD has or does not have the open drain output function, so that the normal communication of the I2C interface and other interfaces is realized.

[0024] Further, in the I2C interface provided by the embodiment, when the PAD has the open drain function, the I2C open drain enable is closed, and the open drain signal meeting the I2C communication protocol is also output through the PAD. Embodiment two

[0025] The embodiment two of the application provides an I2C interface working method, and the method flow can be executed by an electronic device or by one or more chips in the electronic device.

[0026] As shown in the figure, Figure 8 The I2C interface working method comprises the following steps: Step 101, the open drain output module obtains the open drain enable signal in the register module and receives the output control signal output by the core processing module; In the embodiment, the open drain enable signal comprises a clock line open drain enable signal and a data line open drain enable signal; In an implementable mode, the open drain enable signal in the register module is specifically the configuration of the open drain enable connection line in the register module, and the configuration is 1, indicating that the open drain enable signal is 1, and the open drain function is enabled, and the configuration is 0, indicating that the open drain enable signal is 0, and the open drain function is not enabled; In the embodiment, the output control signal comprises an output enable signal and an output data signal; In the embodiment, the output control signals output by the core processing module include clock line output enable signals, clock line output data signals, data line output enable signals and data line output data signals respectively. The hardware gate structure of the open-drain output module for processing the received clock line output control signals (clock line output enable signals and clock line output data signals) and data line output control signals (data line output enable signals and data line output data signals) output by the core processing module is the same. Therefore, the signals output by the core processing module are collectively referred to as output control signals, and the signals output by the open-drain output module are collectively referred to as open-drain output control signals in the embodiment. In the embodiment, when the PAD in the chip has an open-drain function, the open-drain enable signal in the register module can also be configured as 0, indicating that the open-drain function of the I2C interface is not enabled. At this time, the output of the open-drain signal outside the chip is realized by the PAD. In step 102, the open-drain output module performs operation on the open-drain enable signal and the output control signal to obtain open-drain output control signals. The open-drain output control signals include open-drain output data signals and open-drain output enable signals conforming to the I2C communication protocol. In the embodiment, the operator operation specifically includes AND operation and NOT operation. In an implementable manner, step 102 specifically includes: the open-drain output module performs AND operation on the open-drain enable signal, the output enable signal in the output control signal and the output data signal in the output control signal to obtain a first result, performs NOT operation on the first result to obtain a second result, performs AND operation on the second result and the output enable signal in the output control signal to obtain the open-drain output module output enable signal, performs NOT operation on the open-drain enable signal to obtain a third result, and performs AND operation on the third result and the output data signal in the output control signal to obtain the open-drain output module output data signal. For example, the open-drain enable signal is 1, the output data signal in the output control signal is 0, and the output enable signal in the output control signal is 1. The open-drain output module performs operator operation to obtain the open-drain output module output enable signal as 1 and the open-drain output module output data signal as 0. In step 103, the open-drain output module outputs the open-drain output control signal to the PAD in the chip, so that the PAD outputs the open-drain signal conforming to the I2C communication protocol outside the chip. In the embodiment, as Figure 9The truth table of the I2C interface output signal is shown, wherein the I2C interface open drain function is enabled, the I2C interface open drain enable is 1, the I2C interface open drain function is not enabled, the I2C interface open drain enable is 0; the PAD has the open drain function, the PAD open drain enable is 1, the PAD does not have the open drain function, the PAD open drain enable is 0; the core processing module output data is high, the core processing module output data is 1, the core processing module output data is low, the core processing module output data is 0; the core processing module output enable is high, the core processing module output enable is 1, the core processing module output enable is low, the core processing module output enable is 0; the open drain output module output data is high, the open drain output module output data is 1, the open drain output module output data is low, the open drain output module output data is 0; the open drain output module output enable is high, the open drain output module output enable is 1, the open drain output module output enable is low, the open drain output module output enable is 0.

[0027] In the embodiment, if the I2C open drain function is enabled, the PAD can output the open drain signal to the outside of the chip regardless of whether the PAD has the open drain function, and if the I2C does not enable the open drain function and the PAD has the open drain function, the open drain output to the outside of the chip is realized by the PAD.

[0028] The above-mentioned serial numbers of the embodiments of the application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0029] The embodiment of the application further provides a chip, which comprises the I2C interface of the embodiment one, and the chip communicates with the external interface or device through the I2C interface.

[0030] In the embodiment, the PAD connected with the I2C interface in the chip can be the PAD with the open drain function or the PAD without the open drain function.

[0031] In the present application, the terms "first", "second" and the like are used only for descriptive purposes, and cannot be construed as indicating or implying relative importance or sequence; the term "multiple" refers to two or more, unless otherwise explicitly limited. The term "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects. The terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, "connecting" can be fixed connection, or detachable connection, or integral connection; "connected" can be directly connected, or indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0032] In the description of the present application, it should be understood that the orientation or position relationship indicated by the terms "upper", "lower" and the like is based on the orientation or position relationship shown in the drawings, and is only for the purpose of facilitating the description of the present application and simplifying the description, and does not indicate or imply that the device or unit referred to must have a particular direction, be constructed and operated in a particular orientation, therefore, it cannot be understood as a limitation on the present application.

[0033] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. An I2C interface integrated in a chip for realizing signal transmission between the chip and an interface outside the chip, characterized in that, The I2C interface comprises a register module, a core processing module and an open drain output module; The register module is connected with the open drain output module and is configured to output an open drain enable signal to the open drain output module; The core processing module is connected with the open drain output module and is configured to output an output control signal to the open drain output module; The open drain output module is connected with the register module and the core processing module and is configured to receive the open drain enable signal output by the register module and the output control signal output by the core processing module, output an open drain output control signal according to the open drain enable signal and the output control signal, and output the open drain output control signal to a PAD in a chip so that the PAD outputs an open drain signal to outside of the chip. The open drain output module comprises a first open drain output submodule and a second open drain output submodule; 2. The I2C interface according to claim 1, characterized in that, The first open drain output submodule and the second open drain output submodule are respectively connected with the register module and the core processing module, configured to receive the open drain enable signal output by the register module and the output control signal output by the core processing module, output an open drain output control signal according to the open drain enable signal and the output control signal, and output the open drain output control signal to a PAD in a chip. The first open drain output submodule is connected with a clock line open drain enable signal line in the register module and is configured to read the clock line open drain enable signal output by the register module; 3. The I2C interface of claim 2, wherein, The first open drain output submodule is connected with a clock line output enable signal line in the core processing module and is configured to receive a clock line output enable signal in the output control signal output by the core processing module; The first open drain output submodule is further connected with a clock line output data signal line in the core processing module and is configured to receive a clock line output data signal in the output control signal output by the core processing module. The first open drain output submodule is connected with a first PAD of the chip and is configured to output a clock line open drain output enable signal and a clock line open drain output data signal to the first PAD of the chip according to the clock line open drain enable signal, the clock line output enable signal and the clock line output data signal, so that the first PAD outputs a clock line open drain signal conforming to an I2C communication protocol to outside of the chip.

4. The I2C interface of claim 3, wherein, The first open drain output submodule specifically comprises a first AND gate, a first NOT gate, a second AND gate, a second NOT gate and a third AND gate; 5. The I2C interface of claim 3, wherein, The first AND gate is connected with the first NOT gate, the register module and the core processing module and is configured to perform operation on the clock line open drain enable signal output by the register module, the clock line output enable signal and the clock line output data signal in the output control signal output by the core processing module, obtain a first result, and output the first result to the first NOT gate; ​ The first NOT gate is connected with the first AND gate and the second AND gate, and is configured to perform operation on a first result output by the first AND gate to obtain a second result, and output the second result to the second AND gate; The second AND gate is connected with the first NOT gate and the core processing module, and is configured to perform operation on the second result and a clock line output enable signal in an output control signal output by the core processing module to obtain a clock line open drain output enable signal; The second NOT gate is connected with the register module and the third AND gate, and is configured to perform operation on a clock line open drain enable signal output by the register module to obtain a third result, and output the third result to the third AND gate; The third AND gate is connected with the core processing module and the second NOT gate, and is configured to perform operation on the third result and a clock line output data signal in the output control signal output by the core processing module to obtain a clock line open drain output data signal.

6. The I2C interface of claim 2, wherein, The second open drain output sub-module is connected with a data line open drain enable signal line in the register module, and is configured to receive the data line open drain enable signal output by the register module; The second open drain output sub-module is connected with a data line output enable signal line in the core processing module, and is configured to receive the data line output enable signal in the output control signal output by the core processing module; The second open drain output sub-module is further connected with a data line output data signal line in the core processing module, and is configured to receive the data line output data signal in the output control signal output by the core processing module.

7. The I2C interface according to claim 6, characterized in that, The second open drain output sub-module is connected with a second PAD of the chip, and is configured to output a data line open drain output enable signal and a data line open drain output data signal to the second PAD of the chip according to the data line open drain enable signal, the data line output enable signal and the data line output data signal, so that the second PAD outputs a data line open drain signal conforming to an I2C communication protocol to outside of the chip.

8. The I2C interface of claim 6, wherein, The second open drain output sub-module specifically includes a fourth AND gate, a third NOT gate, a fifth AND gate, a fourth NOT gate and a sixth AND gate; The fourth AND gate is connected with the third NOT gate, the register module and the core processing module, and is configured to perform AND gate operation on the data line open drain enable signal output by the register module, the data line output enable signal in the output control signal output by the core processing module and the data line output data signal to obtain a fourth result, and output the fourth result to the third NOT gate; The third NOT gate is connected with the fourth AND gate and the fifth AND gate, and is configured to perform operation on the fourth result output by the fourth AND gate to obtain a fifth result, and output the fifth result to the fifth AND gate; The fifth AND gate is connected with the third NOT gate and the core processing module, and is configured to perform operation on the fifth result and the data line output enable signal in the output control signal output by the core processing module to obtain a data line open drain output enable signal. The fourth NOT gate is connected with the register module and the sixth AND gate, and is configured to perform operation on a data line open drain enable signal output by the register module to obtain a sixth result, and output the sixth result to the sixth AND gate; The sixth AND gate is connected with the core processing module and the fourth NOT gate, and is configured to perform operation on a data line output data signal in an output control signal output by the core processing module and the sixth result to obtain a data line open drain output data signal.

9. A method of operating an I2C interface according to any one of claims 1-8, characterized by, The method comprises: In step S1, the open drain output module acquires an open drain enable signal in the register module, and receives an output control signal output by the core processing module; In step S2, the open drain output module performs operation on the open drain enable signal and the output control signal to obtain an open drain output control signal, and the open drain output control signal comprises an open drain output data signal and an open drain output enable signal conforming to an I2C communication protocol; In step S3, the open drain output module outputs the open drain output control signal to a PAD in a chip, so that the PAD outputs an open drain signal conforming to the I2C communication protocol to outside of the chip.

10. A chip, characterized by The chip comprises the I2C interface in any one of claims 1-8, and the chip communicates with an interface or a device outside of the chip through the I2C interface.

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