FPGA carrier board and COMe module cooperative start method and related equipment

Abstract

The application provides a FPGA carrier board and COMe module cooperative starting method and related equipment, the method comprises the following steps: continuously monitoring the reset state signal of the COMe module through the FPGA chip on the carrier board; determining the current starting type of the carrier board according to the level characteristics of the reset state signal; if the starting type is cold starting, executing the preset standard cold starting sequence; if the starting type is soft restart, keeping all power supply enables and performing special reset on the network switching chip on the carrier board; after the carrier board completes starting, actively delaying for a preset time length and then sending the power supply ready signal to the COMe module to trigger the COMe module to start. The technical scheme of the application identifies the starting type by monitoring the state signal of the COMe module, performs differential control respectively for the cold starting and soft restart scenes, cooperates with the COMe module delay starting, and solves the problem that the COMe modular system starting is prone to abnormality and the reliability is insufficient.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of embedded computer systems, and in particular to a method for cooperative startup of an FPGA carrier board and a COMe module and related equipment. BACKGROUND

[0002] COM Express (COMe) modular embedded system is a system commonly used in network communication devices (such as high-end switches, data centers) and industrial control computers, etc., and mainly composed of a standardized core computing module (COMe module) and a carrier board carrying specific functions, and the carrier board usually integrates FPGA chips, network switch chips and other devices, which need strict power-on sequence and reset control to ensure normal startup of the system. The traditional COMe modular embedded system is basically based on a special power management IC (PMIC) or a simple logic circuit for startup management, and the traditional scheme has the following significant shortcomings:

[0003] Switch chip recognition exception: when the system is soft restarted (without power) by software instructions, the traditional power sequence controller cannot effectively reset the switch chip and other devices on the carrier board. Because the power rail remains stable, the traditional scheme does not re-execute the power-on sequence, causing the switch chip to be in a "dead" state, resulting in a probability that the system cannot recognize the switch chip after soft restart, and must be completely powered off (cold start) to recover, which seriously affects the maintainability and reliability of the system.

[0004] Startup timing competition risk: the COMe module starts up quickly, and if it starts PCIe enumeration and other operations too early, the FPGA and switch chip on the carrier board have not completed initialization, which will cause enumeration failure and system startup exception, and the traditional scheme lacks an effective mechanism to coordinate the startup rhythm between the COMe module and the carrier board devices.

[0005] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0006] The present application provides a method for cooperative startup of an FPGA carrier board and a COMe module and related equipment, and the main purpose of the present application is to solve the technical problems mentioned in the background of the prior art.

[0007] The first aspect of the present application provides a method for cooperative startup of an FPGA carrier board and a COMe module, comprising:

[0008] continuously monitoring the reset state signal of the COMe module by the FPGA chip on the carrier board;

[0009] determining the current startup type of the carrier board according to the level characteristics of the reset state signal;

[0010] if the start type is a cold start, a preset standard cold start sequence is executed;

[0011] if the start type is a soft restart, all power supplies are kept enabled and a special reset is performed on the network switch chip on the carrier board;

[0012] after the carrier board completes the start, a power supply ready signal is actively sent to the COMe module after a preset time delay, triggering the COMe module to start.

[0013] In an optional implementation of the first aspect of the present application, the determination of the current start type of the carrier board according to the level feature of the reset state signal comprises:

[0014] if the reset state signal is initially high and does not jump, it is determined that the current start type of the carrier board is the cold start;

[0015] if the reset state signal is initially high, jumps to low and then returns to high, it is determined that the current start type of the carrier board is the soft restart.

[0016] In an optional implementation of the first aspect of the present application, if the start type is a cold start, a preset standard cold start sequence is executed, which comprises:

[0017] if the start type is a cold start, each power supply rail on the carrier board is sequentially powered on in a predetermined order;

[0018] after all the power supply rails are stabilized, the reset signal of the network switch chip on the carrier board is released.

[0019] In an optional implementation of the first aspect of the present application, if the start type is a cold start, each power supply rail on the carrier board is sequentially powered on in a predetermined order, which comprises:

[0020] the power supply rails with different specifications on the carrier board are sequentially powered on in descending order of voltage, then the enable clock signal on the carrier board is powered on, and finally the core power supply of the network switch chip is powered on.

[0021] In an optional implementation of the first aspect of the present application, if the start type is a soft restart, all power supplies are kept enabled and a special reset is performed on the network switch chip on the carrier board, which comprises:

[0022] If the start type is a soft restart, a power-on operation on each power rail on the carrier board is skipped, and a special reset operation is directly performed on the network switch chip on the carrier board, the special reset operation including generating a complete cycle of reset pulse signals to force the network switch chip to reinitialize.

[0023] In an optional implementation of the first aspect of the present application, the actively delaying for a preset time length before sending the power supply ready signal to the COMe module after the carrier board completes the start to trigger the COMe module to start includes:

[0024] After the carrier board completes the start, delaying for a preset time length to keep the power supply signal of the COMe module at a low level;

[0025] After the preset time length, sending the power supply ready signal to the COMe module to pull up the power supply signal of the COMe module to a high level.

[0026] In an optional implementation of the first aspect of the present application, the cooperative start method is implemented through a programmable state machine built in the FPGA chip, and the logic of the programmable state machine is configured through a hardware description language.

[0027] The second aspect of the present application provides a cooperative start device of an FPGA carrier board and a COMe module, the cooperative start device of the FPGA carrier board and the COMe module including:

[0028] A signal monitoring module is configured to continuously monitor a reset state signal of a COMe module through an FPGA chip on a carrier board.

[0029] A start type determination module is configured to determine a current start type of the carrier board according to a level feature of the reset state signal.

[0030] A cold start module is configured to perform a preset standard cold start sequence if the start type is a cold start.

[0031] A soft restart module is configured to keep all power supply enables and perform a special reset on a network switch chip on the carrier board if the start type is a soft restart.

[0032] A COMe delay start module is configured to actively delay for a preset time length before sending a power supply ready signal to the COMe module after the carrier board completes the start to trigger the COMe module to start.

[0033] The third aspect of the present application provides a network communication device, the network communication device including a memory and at least one processor, the memory having instructions stored therein, and the memory and the at least one processor being interconnected through a circuit.

[0034] The at least one processor invokes the instructions in the memory to cause the network communication device to perform the method for cooperative startup of the FPGA carrier board and the COMe module according to any one of the first aspect of the application.

[0035] The fourth aspect of the application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method for cooperative startup of the FPGA carrier board and the COMe module according to any one of the first aspect of the application.

[0036] Beneficial effects: The application provides a method for cooperative startup of the FPGA carrier board and the COMe module and related equipment, which comprises continuously monitoring a reset state signal of the COMe module through an FPGA chip on the carrier board; determining a current startup type of the carrier board according to a level feature of the reset state signal; if the startup type is cold startup, executing a preset standard cold startup sequence; if the startup type is soft restart, keeping all power supply enables and performing special reset on a network switching chip on the carrier board; after the carrier board completes startup, actively delaying for a preset time length and then sending a power supply ready signal to the COMe module to trigger the COMe module to perform startup. The technical scheme of the application identifies the startup type by monitoring the state signal of the COMe module, respectively performs differential control for cold startup and soft restart scenarios, cooperates with the COMe module to delay startup, and solves the problem that the COMe modular system startup is prone to abnormality and has insufficient reliability. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 An embodiment schematic diagram of main steps of the method for cooperative startup of the FPGA carrier board and the COMe module;

[0038] Figure 2 A logic schematic diagram of the method for cooperative startup of the FPGA carrier board and the COMe module;

[0039] Figure 3 An embodiment schematic diagram of the device for cooperative startup of the FPGA carrier board and the COMe module;

[0040] Figure 4 An embodiment schematic diagram of the network communication device. DETAILED DESCRIPTION

[0041] The terms "first", "second", "third", "fourth" and the like in the description and in the claims of the present application, and above-described drawings, if any, are used to distinguish between similar objects and are not necessarily used to describe a particular sequential or chronological order. It is to be understood that the use of the terms so-termed "first", "second", "third", "fourth" and the like, if any, in the description and in the claims of the present application is simply intended to differentiate between similar objects and is not necessarily intended to denote a particular sequential or chronological order. It is to be understood that the data so used can be interchanged, where appropriate, so that the embodiments described herein can be carried out in sequences other than those illustrated or described herein. Furthermore, use of the terms "comprising" or "having" and any variations thereof in the claims is intended to cover a non-exclusive inclusion, such that a process, method, system, product or apparatus that comprises a list of steps or units not only comprises those listed steps or units but can include other steps or units not expressly listed or inherent to such process, method, product or apparatus.

[0042] For the sake of understanding, the specific flow of the embodiments of the present application is described below, please refer to Figure 1 The first aspect of the present application provides a cooperative starting method of FPGA carrier board and COMe module, the cooperative starting method can be realized by the programmable state machine built-in in the FPGA chip, the logic of the programmable state machine is configured by hardware description language, and the cooperative starting method comprises the following steps.

[0043] S100, continuously monitoring the reset state signal of the COMe module by the FPGA chip on the carrier board; in the present application, the embedded system composed of the FPGA carrier board and the COMe module can include a core computing module (i.e. COMe module) complying with the PICMG COM Express standard and a carrier board with specific functions on the hardware architecture, at least one FPGA (field programmable gate array) chip and one high-performance network switch chip are integrated on the carrier board, the FPGA chip serves as the control core of the carrier board, and is responsible for power timing management, reset logic control and cooperative interaction with the COMe module.

[0044] In step S100, after the system is powered on or receives a restart instruction, the FPGA chip on the carrier board will start working immediately, the state machine module built-in in the FPGA chip starts to continuously monitor the COMe reset state signal led out from the COMe module, and the FPGA chip will determine the current starting type of the carrier board according to the level state and change characteristics of the COMe reset state signal.

[0045] S200, determining the current starting type of the carrier board according to the level characteristics of the reset state signal; for example, step S200 can specifically include: if the reset state signal is initially high and does not jump, it is determined that the current starting type of the carrier board is the cold start; if the reset state signal is initially high, jumps to low and then returns to high, it is determined that the current starting type of the carrier board is the soft restart.

[0046] In the present application, the specific principle of cold start discrimination is that when the entire system is powered on from a completely powered-off state (i.e. cold start), the reset state signal of the COMe module will be stable at a high level after initial power-on, and if the FPGA chip monitors this initial high level state, it can be determined that the current is a cold start scenario.

[0047] The specific principle of soft restart discrimination is that when the system is in normal operation, a soft restart (power-on restart) is triggered by the operating system or software instructions, the COMe module will perform a reset process, which will cause the COMe reset state signal pin to generate a pulse jump from high to low and then back to high. If the FPGA chip captures this pulse signal, it can be determined that the current is a soft restart scenario.

[0048] S300, if the start type is a cold start, a preset standard cold start sequence is executed; in the present application, the FPGA chip enters a cold start state and starts to execute a complete power-on timing control. The FPGA chip will enable each power rail on the board in a strict sequence that is pre-set and meets the requirements of all device manuals, for example, first turn on the 12V main power, then turn on the 5V, 3.3V, 1.8V, 1.0V auxiliary power, and then enable the clock and core power of the switching chip. After all the power rails are stable, the FPGA chip will release the reset signal to the switching chip to complete the power-on initialization, and thus the board itself completes the initialization process of the cold start.

[0049] That is, in an optional embodiment of step S300 of the present application, if the start type is a cold start, a preset standard cold start sequence is executed, which includes sequentially powering on each power rail on the board in a predetermined order (for example, first powering on the power rails with different voltage specifications on the board in order of decreasing voltage, then powering on the clock signal on the board, and finally powering on the core power of the network switching chip); after all the power rails are stable, the reset signal of the network switching chip on the board is released.

[0050] S400, if the start type is a soft restart, keeping all power supply enabled and performing a special reset on the network switch chip on the carrier board; in the present application, when the FPGA chip determines to perform a soft restart, since the main power supply and other power supply rails of the system are always stable, the above-mentioned complex power-on timing control step is completely skipped. At this time, the core task of the FPGA chip is to solve the "dead" state of the switch chip that may be caused by not powering off, and the FPGA performs a targeted reset operation. Specifically, the FPGA chip controls the GPIO interface connected to the reset pin (PP_RESETN) of the switch chip, so that the interface level experiences a level change process of "pulling low → keeping for a certain period of time → pulling high again", and this forced reset pulse can ensure that the switch chip is reliably reinitialized and restored to an identifiable initial state, which fundamentally solves the problem of loss of the switch chip after soft restart.

[0051] That is, in an optional embodiment of step S400 of the present application, if the start type is a soft restart, keeping all power supply enabled and performing a special reset on the network switch chip on the carrier board comprises: if the start type is a soft restart, skipping the power-on operation on each power supply rail on the carrier board and directly performing a special reset operation on the network switch chip on the carrier board, the special reset operation comprising generating a complete period of reset pulse signal to force the network switch chip to reinitialize.

[0052] S500, after the carrier board completes the start, actively delaying for a preset time length and then sending a power supply ready signal to the COMe module to trigger the COMe module to start. In the present application, after the carrier board completes the start, the FPGA chip and the switch chip and other devices on the carrier board still need a certain time to complete their respective internal initialization (such as FPGA chip configuration loading, switch chip self-checking, etc.), so the FPGA chip will not immediately notify the COMe module to start after completing the boot carrier board start task.

[0053] In the present application, after confirming that all key devices on the carrier board have started, the state machine in the FPGA chip will enter a delay state, and the preset delay time length can be set to 100 milliseconds to 500 milliseconds, and the specific value can be adjusted according to the internal initialization time of the devices on the carrier board. The purpose of delaying the start of the COMe module is to give the devices on the carrier board sufficient preparation time, to ensure that the network switch chip as a PCIe device is 100% ready before the COMe module starts to perform PCIe bus device enumeration, so as to correctly respond to the enumeration request, thereby avoiding the timing competition risk caused by the mismatch of start speed. After the delay time ends, the FPGA chip sends a power supply ready signal to the COMe module to pull up the power supply level of the COMe module.

[0054] That is, in an optional embodiment of step S500 of the application, after the completion of the startup of the carrier board, the step of actively delaying for a preset time length and then sending the power supply ready signal to the COMe module to trigger the startup of the COMe module comprises: after the completion of the startup of the carrier board, delaying for a preset time length to keep the power supply signal of the COMe module at a low level; and after the preset time length, sending the power supply ready signal to the COMe module to make the power supply signal of the COMe module pull high to a high level.

[0055] In order to better understand the technical solutions of the application, the main working process of the FPGA carrier board and COMe module cooperative startup method can be summarized as follows: Figure 2

[0056] Initial state and monitoring: the system is powered on or receives a restart instruction. The serialized power module in the FPGA starts to work and continuously monitors the COMe reset state signal from the COMe module. The signal reflects the reset state of the COMe module.

[0057] Path determination and selection: cold startup path: if the COMe reset state signal is initially high, the FPGA determines that it is a cold startup, and then enters the standard cold startup sequence. The sequence strictly follows the predetermined order (such as 12V first, then 5V, 3.3V, 1.8V, and then enables the clock and core power supply) to turn on all power supply rails, and finally releases the exchange chip reset. Soft startup path: if the FPGA detects that the COMe reset state signal has a jump from high to low and then recovers to high, it is determined to be a soft restart. At this time, since the power supply rail is always stable, the FPGA skips the complete power-on sequence and directly enters the soft restart dedicated sequence. The core operation of the sequence is to re-trigger the reset signal (PP_RESETN) of the exchange chip to make it go through a complete "pull low-then pull high" reset cycle, forcing the exchange chip to reinitialize.

[0058] Cooperative startup control: regardless of which path is taken, after completing its own initialization, the FPGA does not immediately notify the COMe module to start. For example, in the delay power supply step in the startup logic Figure 2 of the FPGA, the FPGA delays the pull-up of the COMe board power supply ready signal. This signal is a "carrier board ready" signal sent to the COMe module. By actively delaying, the FPGA ensures that all devices on the carrier board (especially the exchange chip) are 100% ready before the COMe module starts to start and PCIe enumeration, perfectly avoiding the risk of timing competition.

[0059] System ready: after the FPGA pulls up the COMe power supply ready signal, the COMe module starts to start normally, and the system enters the working state.​

[0060] In general, the FPGA carrier board and COMe module cooperative start method of the present application can bring the following beneficial effects:

[0061] Completely solve the soft restart reliability problem: through intelligent identification of soft restart events and execution of targeted switching chip reset operation, the systematic failure caused by soft restart leading to device identification failure is eradicated, greatly improving the reliability and maintainability of the system.

[0062] Seamless cooperative start: using the delay control mechanism of the COMe power supply ready signal, the system instability factors caused by start timing competition are eliminated.

[0063] High integration and flexibility: using FPGA as the unified control core, the power timing, reset logic, state monitoring and other functions are integrated in a single chip, simplifying the hardware design and reducing the cost. The control logic can be flexibly adjusted through programming, with strong adaptability.

[0064] Compatibility and reliability: the scheme completely follows the industrial standard (PICMG COMe specification), and at the same time, the innovative logic design makes up for the shortcomings of the standard protocol in complex application scenarios.

[0065] Referring to Figure 3 , the second aspect of the present application provides a FPGA carrier board and COMe module cooperative start device, which comprises:

[0066] A signal monitoring module 10 is used to continuously monitor the reset state signal of the COMe module through the FPGA chip on the carrier board.

[0067] A start type determination module 20 is used to determine the current start type of the carrier board according to the level characteristics of the reset state signal.

[0068] A cold start module 30 is used to execute the preset standard cold start sequence if the start type is cold start.

[0069] A soft restart module 40 is used to keep all power enables and perform special reset on the network switching chip on the carrier board if the start type is soft restart.

[0070] A COMe delay start module 50 is used to actively delay for a preset time after the carrier board completes the start, and then send a power supply ready signal to the COMe module to trigger the COMe module to start.

[0071] In an optional embodiment of the second aspect of the present application, the start type determination module comprises:

[0072] a cold start determination unit configured to determine that the current start type of the board is the cold start if the reset status signal is initially high and does not jump;

[0073] a soft restart determination unit configured to determine that the current start type of the board is the soft restart if the reset status signal is initially high, jumps to low and then returns to high.

[0074] In an optional implementation of the second aspect of the present application, the cold start determination unit comprises:

[0075] a power-on management subunit configured to sequentially power on each power rail on the board in a predetermined order if the start type is the cold start;

[0076] a reset signal release subunit configured to release the reset signal of the network switch chip on the board after all the power rails are stable.

[0077] In an optional implementation of the second aspect of the present application, the sequentially powering on each power rail on the board in a predetermined order comprises:

[0078] firstly, sequentially powering on the power rails with different voltage specifications on the board in descending order of voltage, then powering on the enable clock signal on the board, and finally powering on the core power supply of the network switch chip.

[0079] In an optional implementation of the second aspect of the present application, the soft restart module comprises:

[0080] a switch chip special reset unit configured to, if the start type is the soft restart, skip the power-on operation of each power rail on the board, and directly perform a special reset operation on the network switch chip on the board, the special reset operation comprising generating a complete cycle of reset pulse signals to force the network switch chip to reinitialize.

[0081] In an optional implementation of the second aspect of the present application, the COMe delay start module comprises:

[0082] a level holding unit configured to, after the board completes the start, delay for a preset time period to keep the power supply signal of the COMe module low;

[0083] a level pull-up unit configured to, after the preset time period, send the power supply ready signal to the COMe module to pull up the power supply signal of the COMe module to high.

[0084] In an alternative implementation of the second aspect of the present application, the cooperative starting method is implemented by a programmable state machine built in the FPGA chip, and the logic of the programmable state machine is configured by a hardware description language.

[0085] Figure 4 Fig. 1 is a schematic diagram of a network communication device according to an embodiment of the present application. The network communication device can have a great difference in configuration or performance, and can include one or more central processing units (CPUs) 60 (e.g., one or more processors) and a memory 70, and one or more storage media 80 (e.g., one or more mass storage devices) storing application programs or data. The memory and the storage media can be temporary storage or persistent storage. The programs stored in the storage media can include one or more, and each program can include a series of instruction operations in the network communication device. Further, the processor can be configured to communicate with the storage media and execute the series of instruction operations in the storage media on the network communication device.

[0086] The network communication device can further include one or more power supplies 90, one or more wired or wireless network interfaces 100, one or more input / output interfaces 110, and / or one or more operating systems, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art can understand that the network communication device can include more or fewer components than those shown in the figure, or some components can be combined, or different components can be arranged. Figure 4 The network communication device structure shown does not constitute a limitation on the network communication device, and can include more or fewer components than those shown in the figure, or some components can be combined, or different components can be arranged.

[0087] The present application also provides a computer readable storage medium, which can be a non-volatile computer readable storage medium or a volatile computer readable storage medium, and the computer readable storage medium stores instructions, which, when executed on a computer, cause the computer to perform the steps of the cooperative starting method of the FPGA carrier board and the COMe module.

[0088] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system or system, unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0089] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or the entire or part of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0090] The above description and the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for co-booting of an FPGA carrier board with a COMe module, characterized in that, The method comprises the following steps: continuously monitoring the reset state signal of the COMe module through the FPGA chip on the carrier board; determining the current startup type of the carrier board according to the level characteristics of the reset state signal; if the reset state signal is initially high and does not jump, it is determined that the current startup type of the carrier board is cold startup; if the reset state signal is initially high and jumps to low and then returns to high, it is determined that the current startup type of the carrier board is soft restart; if the startup type is cold startup, the power rails with different specifications on the carrier board are powered on in order from high to low voltage, then the enable clock signal on the carrier board is powered on, and finally the core power supply of the network switching chip is powered on; after all the power rails are stable, the reset signal of the network switching chip on the carrier board is released; if the startup type is soft restart, the power-on operation of each power rail on the carrier board is skipped, and a special reset operation is directly performed on the network switching chip on the carrier board, the special reset operation including generating a complete cycle of reset pulse signal to force the network switching chip to reinitialize; after the carrier board completes startup, the power supply signal of the COMe module is kept low for a preset time period; after the preset time period, a power supply ready signal is sent to the COMe module to pull the power supply signal of the COMe module high to high level; The cooperative startup method is realized by a programmable state machine built in the FPGA chip, and the logic of the programmable state machine is configured by a hardware description language.

2. A co-booting apparatus of an FPGA carrier board and a COMe module, characterized in that, The cooperative startup device of the FPGA carrier board and the COMe module comprises: a signal monitoring module for continuously monitoring the reset state signal of the COMe module through the FPGA chip on the carrier board; a startup type determination module for determining the current startup type of the carrier board according to the level characteristics of the reset state signal; if the reset state signal is initially high and does not jump, it is determined that the current startup type of the carrier board is cold startup; if the reset state signal is initially high and jumps to low and then returns to high, it is determined that the current startup type of the carrier board is soft restart; a cold startup module for, if the startup type is cold startup, powering on the power rails with different specifications on the carrier board in order from high to low voltage, then powering on the enable clock signal on the carrier board, and finally powering on the core power supply of the network switching chip; after all the power rails are stable, the reset signal of the network switching chip on the carrier board is released; a soft restart module for, if the startup type is soft restart, skipping the power-on operation of each power rail on the carrier board and directly performing a special reset operation on the network switching chip on the carrier board; the special reset operation includes generating a complete cycle of reset pulse signal to force the network switching chip to reinitialize. The COMe delay starting module is used for delaying a preset time length to keep the power supply signal of the COMe module as low level after the carrier board completes starting; and sending a power supply ready signal to the COMe module after the preset time length to pull up the power supply signal of the COMe module as high level.

3. A network communication device, comprising: The network communication device comprises a memory and at least one processor, the memory has instructions stored therein, and the memory and the at least one processor are interconnected by a line; The at least one processor invokes the instructions in the memory, so that the network communication device executes the FPGA carrier board and COMe module cooperative starting method as claimed in claim 1.

4. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by a processor to implement the FPGA carrier board and COMe module cooperative starting method as claimed in claim 1.

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