A semiconductor device and a method for manufacturing a semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and relate to the technical field of semiconductor. The semiconductor device comprises a substrate; a channel layer arranged on one side of the substrate; a barrier layer arranged on a side of the channel layer away from the substrate; an electrode layer arranged on a side of the barrier layer away from the substrate, the electrode layer comprising a control electrode, a first electrode and a second electrode; at least one adjustment layer arranged on a side of the barrier layer away from the substrate; at least one conductive layer arranged on a side of the adjustment layer away from the substrate, the conductive layer being electrically connected to the control electrode; in a thickness direction of the semiconductor device, a projection of the electrode layer and a projection of the adjustment layer are staggered; and a doping type of the adjustment layer is different from a doping type of the barrier layer. The technical solution provided by the embodiments improves the depletion capability at a position with a higher electric field, and improves the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0002] With the development of semiconductor technology, the requirements for semiconductor devices are becoming increasingly stringent. Existing semiconductor devices suffer from high electric fields and dynamic on-resistance drift. Current methods for improving semiconductor devices to address these issues have limited adjustability. The high electric fields in existing semiconductor devices negatively impact their performance. Summary of the Invention

[0003] This invention provides a semiconductor device and a method for manufacturing a semiconductor device to solve the problem of high electric field in existing semiconductor devices, which affects the performance of the semiconductor device.

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution:

[0005] This invention provides a semiconductor device, comprising:

[0006] Substrate;

[0007] A channel layer disposed on one side of the substrate;

[0008] A barrier layer disposed on the side of the channel layer away from the substrate;

[0009] An electrode layer is disposed on the side of the barrier layer away from the substrate, and the electrode layer includes a control electrode, a first electrode, and a second electrode;

[0010] At least one conditioning layer disposed on the side of the barrier layer away from the substrate;

[0011] At least one conductive layer is disposed on the side of the adjustment layer away from the substrate, and the conductive layer is electrically connected to the control electrode;

[0012] Along the thickness direction of the semiconductor device, the projection of the electrode layer is offset from the projection of the adjustment layer; the doping type of the adjustment layer is different from the doping type of the barrier layer.

[0013] Optionally, when the semiconductor device includes at least two adjustment layers, the conductive layer and the adjustment layer are respectively disposed in a one-to-one correspondence;

[0014] Each of the conductive layers is electrically connected to the control electrode, the regulating layer is conductive along the direction of the conductive layer toward the barrier layer, and the regulating layer is cut off along the direction of the barrier layer toward the regulating layer.

[0015] Optionally, along a direction perpendicular to the thickness of the semiconductor device, the adjustment layer is disposed between the first electrode and the control electrode of the semiconductor device, close to the control electrode; and / or,

[0016] Along a direction perpendicular to the thickness of the semiconductor device, the adjustment layer is disposed between the second electrode and the control electrode of the semiconductor device, close to the control electrode.

[0017] Optionally, the adjustment layer and the control electrode are spaced apart by a first preset distance;

[0018] The adjustment layer is disposed at a position where the electric field strength of the semiconductor device is greater than the average electric field strength of the semiconductor device.

[0019] Optionally, the thickness of the adjustment layer is greater than or equal to 0 and less than or equal to 50 nm; and / or,

[0020] The material of the conditioning layer includes a p-type doped material; and / or,

[0021] The material of the conditioning layer includes diamond, p-GaN, p-NiO, p-ZnO, or... .

[0022] Optionally, the semiconductor device further includes:

[0023] A connecting layer is disposed between the adjustment layer and the conductive layer;

[0024] The interconnect layer comprises a P-type degenerate semiconductor material.

[0025] Optionally, the thickness of the connecting layer is greater than 0 and less than or equal to 5 nm; and / or,

[0026] The material of the bonding layer includes: P-Si or GaAs; and / or,

[0027] The electron affinity of the connecting layer is greater than 3.07 eV.

[0028] Optionally, the conductive layer includes an ohmic metal layer; and / or,

[0029] The electron affinity of the connecting layer is greater than or equal to 5.8 eV.

[0030] Secondly, this embodiment provides a method for fabricating a semiconductor device, comprising:

[0031] Provide substrate;

[0032] A trench layer is formed on one side of the substrate;

[0033] A barrier layer is formed on the side of the channel layer away from the substrate;

[0034] An electrode layer is formed on the side of the barrier layer away from the substrate, the electrode layer including a control electrode, a first electrode, and a second electrode;

[0035] An adjustment layer is formed on the side of the barrier layer away from the substrate; wherein, along the thickness direction of the semiconductor device, the projection of the electrode layer is offset from the projection of the adjustment layer; the doping type of the adjustment layer is different from the doping type of the barrier layer;

[0036] A conductive layer is formed on the side of the adjustment layer away from the substrate, and the conductive layer is connected to the control electrode of the electrode layer.

[0037] Optionally, before forming a conductive layer on the side of the adjustment layer away from the substrate, and before connecting the conductive layer to the control electrode of the electrode layer, the method further includes:

[0038] A connection layer is formed on the side of the adjustment layer away from the substrate, the connection layer comprising a P-type degenerate semiconductor material;

[0039] A conductive layer is formed on the side of the adjustment layer away from the substrate, and the conductive layer is connected to the control electrode of the electrode layer, including:

[0040] A conductive layer is formed on the side of the connection layer away from the adjustment layer, and the conductive layer is electrically connected to the control electrode of the electrode layer, so as to electrically connect the adjustment layer to the control electrode.

[0041] The semiconductor device provided in this embodiment of the invention comprises an electrode layer including a control electrode, a first electrode, and a second electrode; at least one regulating layer disposed on the side of the barrier layer away from the substrate; and at least one conductive layer disposed on the side of the regulating layer away from the substrate, the conductive layer being electrically connected to the control electrode. Along the thickness direction of the semiconductor device, the projections of the electrode layer and the regulating layer are offset. The doping type of the regulating layer is different from that of the barrier layer. This configuration allows the regulating layer to be disposed at a location with a higher electric field near the control electrode, and the conductive layer to be disposed on the side of the regulating layer away from the substrate. The conductive layer is electrically connected to the control electrode, thereby connecting the regulating layer to the control electrode. Because the doping type of the regulating layer is different from that of the barrier layer, the regulating layer and the barrier layer form a unidirectional conductive path from the conductive layer to the regulating layer and from the regulating layer to the barrier layer. Since the barrier layer is N-type doped and the regulating layer is P-type doped, the regulating layer provides holes. When the control electrode is turned off, the holes provided by the regulating layer diffuse, depleting electrons at locations with higher electric fields, thereby improving the breakdown voltage of the semiconductor device. When the control electrode is turned on, the hole injection efficiency of the regulating layer is improved due to the electric field. The regulating layer's ability to consume hot electrons is enhanced, and its ability to deplete hot electrons at higher positions of the electric field is strengthened. This effectively alleviates the dynamic on-resistance drift, current collapse, and threshold voltage shift of semiconductor devices, and improves the withstand voltage and stability of semiconductor devices. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of the present invention and these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0045] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0046] Figure 4 This is a flowchart of a method for fabricating a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] Based on the above-mentioned technical problems, this embodiment proposes the following solutions:

[0050] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. See also... Figure 1 This invention provides a semiconductor device comprising: a substrate 1; a channel layer 3 disposed on one side of the substrate 1; a barrier layer 4 disposed on the side of the channel layer 3 away from the substrate 1; an electrode layer disposed on the side of the barrier layer 4 away from the substrate 1, the electrode layer including a control electrode 5, a first electrode 6, and a second electrode 8; at least one adjustment layer 2 disposed on the side of the barrier layer 4 away from the substrate 1; at least one conductive layer 7 disposed on the side of the adjustment layer 2 away from the substrate 1, the conductive layer 7 being electrically connected to the control electrode 5; along the thickness direction Z of the semiconductor device, the projection of the electrode layer is offset from the projection of the adjustment layer 2; the doping type of the adjustment layer 2 is different from the doping type of the barrier layer 4.

[0051] Specifically, substrate 1 may include a Si substrate, a SiC substrate, or a sapphire substrate, etc. Barrier layer 4 may include a nitride semiconductor layer. Channel layer 3 is used for electron transport. Channel layer 3 includes ions of metals such as Al and Ga. Electrode layers may include gate, source, and drain electrodes. Cap layer 5 includes an electrode layer formed by ions of p-type nitride semiconductor and metals such as titanium and tungsten, such as a gate layer.

[0052] A two-dimensional electron gas (2DEG) is generated at the interface between channel layer 3 and barrier layer 4. The 2DEG passes through channel layer 3, forming a current. Conductive layer 7 can be an electrode layer formed by ions of metals such as titanium, copper, or gold, for example, a source or drain.

[0053] By placing the adjustment layer 2 on the side of the barrier layer 4 away from the substrate 1, and since the doping type of the adjustment layer 2 is different from that of the barrier layer 4, the conductive layer 7 on the side of the adjustment layer 2 away from the substrate 1 is electrically connected to the adjustment layer 2. The conductive layer 7 is electrically connected to the control electrode 5, so that when an external power supply transmits an electrical signal to the control electrode 5, the electrical signal can be transmitted to the barrier layer 4 through the conductive layer 7 and the adjustment layer 2. Since the doping type of the adjustment layer 2 is different from that of the barrier layer 4, the electrical signal is unidirectionally conducted from the electrode layer to the adjustment layer 2 and the barrier layer 4. In this embodiment, the adjustment layer 2 placed on the side of the barrier layer 4 away from the substrate 1 does not block the two-dimensional electron gas 2DEG at the interface between the barrier layer 4 and the channel layer 3 located below the adjustment layer 2, thus ensuring the conductivity and stability of the semiconductor device.

[0054] During the operation of the semiconductor device, some hot electrons escape to the side of the barrier layer 4 away from the substrate 1. By setting the adjustment layer 2, which has a larger bandgap, the electron depletion capability of the adjustment layer 2 is stronger. This allows electrons at higher electric field positions in the semiconductor device to be effectively consumed, thereby reducing the electric field strength near the control electrode 5 of the semiconductor device.

[0055] Both barrier layer 4 and channel layer 3 are N-type doped. The adjustment layer 2 has a different doping type than barrier layer 4; it is P-type doped. When the control electrode 5 is off, the P-type doped material in adjustment layer 2 provides hole diffusion, which can deplete electrons escaping from higher electric field positions, thereby improving the drain-to-source breakdown voltage (BVD) and gate bias (RB) capability of the semiconductor device. When the gate is on, due to the electric field, the hole injection efficiency is improved, the ability of adjustment layer 2 to deplete hot electrons is enhanced, and its ability to deplete hot electrons from higher electric field positions in the semiconductor device becomes stronger. Therefore, it can alleviate the dynamic on-resistance drift (Ron shift), current collapse, and threshold voltage drift of the semiconductor device.

[0056] The semiconductor device provided in this embodiment comprises an electrode layer including a control electrode 5, a first electrode 6, and a second electrode 8; at least one adjustment layer 2 disposed on the side of the barrier layer 4 away from the substrate 1; and at least one conductive layer 7 disposed on the side of the adjustment layer 2 away from the substrate 1, the conductive layer 7 being electrically connected to the control electrode 5; along the thickness direction Z of the semiconductor device, the projections of the electrode layers and the adjustment layer 2 are offset; the doping type of the adjustment layer 2 is different from that of the barrier layer 4. This configuration allows the adjustment layer 2 to be disposed at a location with a higher electric field near the control electrode 5, and the conductive layer 7 to be disposed on the side of the adjustment layer 2 away from the substrate 1. The conductive layer 7 is electrically connected to the control electrode 5, thereby connecting the adjustment layer 2 to the control electrode 5. Because the doping type of the adjustment layer 2 is different from that of the barrier layer 4, the adjustment layer 2 and the barrier layer 4 form a unidirectional conductive path from the conductive layer 7 to the adjustment layer 2 and from the adjustment layer 2 to the barrier layer 4. Since the barrier layer 4 is N-type doped and the adjustment layer 2 is P-type doped. The regulating layer 2 provides holes. When the control electrode 5 is turned off, the holes provided by the regulating layer 2 diffuse, which can deplete electrons at higher positions in the electric field, thereby improving the breakdown voltage capability of the semiconductor device. When the control electrode 5 is turned on, due to the effect of the electric field, the hole injection efficiency of the regulating layer 2 is improved, the ability of the regulating layer 2 to consume hot electrons is enhanced, and the ability to deplete hot electrons at higher positions in the electric field becomes stronger. This effectively alleviates the dynamic on-resistance drift, current collapse, and threshold voltage shift of the semiconductor device, thereby improving the breakdown voltage capability and stability of the semiconductor device.

[0057] It should be noted that in some embodiments, the control electrode 5 can be the gate, the first electrode 6 can be the source, and the second electrode 8 can be the gate; no limitations are imposed here.

[0058] It should be noted that the control electrode 5 may include a cap layer and a gate metal layer disposed on the side of the cap layer away from the substrate. The cap layer may include P-GaN. The cap layer is used to block direct contact between the gate metal and the 2DEG of the channel layer, reducing interface defects and trapped states, thereby reducing gate leakage current. The doped cap layer, such as P-GaN, can optimize the surface electric field distribution and reduce current collapse. The cap layer is also used to positively adjust the threshold voltage by changing the doping distribution of the barrier layer, while increasing transconductance and saturation current to control the threshold voltage. The cap layer can reduce the damage to the interface of the barrier layer 4 caused by the etching process and maintain the mobility and carrier concentration of the 2DEG. In the non-operating state, the cap layer of the control electrode 5 blocks the 2DEG at the interface between the barrier layer 4 and the channel layer 3 below the control electrode 5, thereby forming a normally-off (enhancement-mode) semiconductor device.

[0059] The differences between the adjustment layer 2 and the cap layer of the control electrode 5 provided in this embodiment include, but are not limited to, the fact that the adjustment layer 2 does not block the two-dimensional electron gas 2DEG at the interface between the barrier layer 4 and the channel layer 3 below it. The thickness of the adjustment layer 2 is less than the thickness of the cap layer of the control electrode 5, and the bandgap width of the adjustment layer 2 is greater than the bandgap width of the cap layer of the control electrode 5.

[0060] Optional, Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. See also... Figure 2 When the semiconductor device includes at least two adjustment layers 2, the conductive layer 7 is disposed in a one-to-one correspondence with the adjustment layer 2; each of the conductive layers 7 is electrically connected to the control electrode 5, the adjustment layer 2 is conductive along the conductive layer 7 toward the barrier layer 4, and the adjustment layer 2 is cut off along the barrier layer 4 toward the adjustment layer 2.

[0061] Specifically, when a semiconductor device includes at least two regulating layers 2, the conductive layers 7 are configured in a one-to-one correspondence with the regulating layers 2, facilitating the connection of each regulating layer 2 to the control electrode 5 through its corresponding conductive layer 7. The regulating layers 2 are configured to be conductive along the conductive layer 7 towards the barrier layer 4, and also to be cut off along the barrier layer 4 towards the regulating layer 2. This allows the hole diffusion provided by the regulating layers 2 to deplete electrons at higher positions in the electric field when the control electrode 5 is turned off, thereby improving the breakdown voltage capability of the semiconductor device and preventing short circuits. When the control electrode 5 is turned on, due to the effect of the electric field, the hole injection efficiency of the regulating layers 2 is improved, and the ability of the regulating layers 2 to consume hot electrons is enhanced, particularly at higher positions in the electric field. This effectively mitigates the dynamic on-resistance drift, current collapse, and threshold voltage shift of the semiconductor device, further improving its breakdown voltage capability and stability.

[0062] Optionally, based on the above embodiments, see also... Figure 2 Along the thickness direction X perpendicular to the semiconductor device, the adjustment layer 2 is disposed between the first electrode 6 and the control electrode 5 of the semiconductor device, close to the control electrode 5; and / or, along the thickness direction X perpendicular to the semiconductor device, the adjustment layer 2 is disposed between the second electrode 8 and the control electrode 5 of the semiconductor device, close to the control electrode 5.

[0063] Specifically, the electric field is high near the control electrode 5 or at locations with interface defects in the semiconductor device. By providing a regulating layer 2, holes are provided to deplete electrons near the control electrode 5 or at locations with high electric fields, thereby improving the depletion capability of the semiconductor device at locations with high electric fields, and thus improving the breakdown voltage and reliability of the semiconductor device.

[0064] Optionally, based on the above embodiments, see also... Figure 2 The adjustment layer 2 and the control electrode 5 are spaced apart by a first preset distance; the adjustment layer 2 is disposed at a position where the electric field strength of the semiconductor device is greater than the average electric field strength of the semiconductor device.

[0065] Specifically, a first preset distance is set between the regulating layer 2 and the control electrode 5 to maintain a certain creepage distance between them. This first preset distance can be reasonably set according to the type of semiconductor device, and its specific range is not limited. By placing the regulating layer 2 at a location where the electric field strength of the semiconductor device is greater than its average electric field strength, electrons at locations with higher electric field strength are depleted through holes in the regulating layer 2, improving the electron depletion capability at these locations and further enhancing the semiconductor device's withstand voltage.

[0066] Optionally, based on the above embodiments, see also... Figure 2 The thickness of the adjustment layer 2 is greater than 0 and less than or equal to 50 nm; and / or, the material of the adjustment layer 2 includes a p-type doped material; and / or, the material of the adjustment layer 2 includes diamond, p-GaN, p-NiO, p-ZnO, or... .

[0067] Specifically, if the thickness of the regulating layer 2 is too thick, it can easily block the two-dimensional electron gas (2DEG) at the interface between the barrier layer 4 and the channel layer 3, affecting the conductivity of the semiconductor device. If the thickness of the regulating layer 2 is too thin, it will reduce the ability of the regulating layer 2 to deplete electrons at higher positions in the electric field, affecting the breakdown voltage. By setting the thickness of the regulating layer 2 to be greater than 0 and less than or equal to 50 nm, preferably less than or equal to 10 nm, the thickness of the regulating layer 2 can be reasonably selected according to the design requirements of the breakdown voltage of the semiconductor device. On the one hand, this setting ensures that the regulating layer 2 does not block the two-dimensional electron gas (2DEG) at the interface between the barrier layer 4 and the channel layer 3, thus guaranteeing the conductivity and stability of the semiconductor device. On the other hand, this setting allows the regulating layer 2 to provide sufficient holes to deplete electrons at higher positions in the electric field, thereby improving the breakdown voltage of the semiconductor device.

[0068] The material of the conditioning layer 2 includes p-type doped materials, such as diamond, p-GaN, p-NiO, p-ZnO, or... Materials with a large bandgap and P-type doping are used to provide holes, thereby improving the breakdown voltage of the semiconductor device when the gate 5 is turned off and the hot electron dissipation capability of the semiconductor device when the gate 5 is turned on. This reduces the dynamic on-resistance drift of the semiconductor device and improves the stability of the semiconductor device.

[0069] Optional, Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention. See also... Figure 3 The semiconductor device further includes: a connection layer 9 disposed between the adjustment layer 2 and the conductive layer 7; the connection layer 9 comprises a P-type degenerate semiconductor material.

[0070] Specifically, P-type degenerate semiconductor materials refer to P-type semiconductors formed by high-concentration doping with group III elements (such as boron and aluminum). Their Fermi level may enter the valence band, causing the carrier statistical distribution to follow a Fermi-Dirac distribution rather than a Boltzmann distribution. These materials exhibit significant quantum effects under low-temperature or high-doping conditions. The probability of holes occupying valence band states is limited by the Pauli exclusion principle, and their conductivity characteristics are close to those of metals.

[0071] Since the adjustment layer 2 is a p-type doped material, its Fermi level is very close to the valence band, resulting in a large work function. A connecting layer 9, comprising a p-type degenerate semiconductor material, is provided. Because the p-type degenerate semiconductor material has a high electron affinity, it facilitates the fabrication of the connecting layer 9 first on the side of the adjustment layer 2 away from the substrate 1, allowing for the fabrication of the conductive layer 7 on the side of the connecting layer 9 away from the adjustment layer 2, thus enabling the fabrication of the ohmic contact metal.

[0072] Since the connecting layer 9 is a p-type degenerate semiconductor material, in its degenerate state, due to its extremely high doping concentration, the Fermi level shifts upward, making it easier for electrons to transition from the conduction band to the valence band, resulting in conductivity approaching that of a metal. By setting the connecting layer 9, it is convenient to effectively connect the p-type doped material of the adjustment layer 2 to the conductive layer 7. Because the material of the connecting layer 9 has a high electron affinity, it facilitates improving the ohmic contact capability between the conductive layer 7 and the connecting layer 9. This design makes the fabrication of the conductive layer 7 easier and allows for a wider range of material selection for the conductive layer 7. By setting the connecting layer 9, the fabrication of the ohmic contact conductive layer 7 is easier, eliminating the need for high-temperature annealing, thus better avoiding the performance degradation of the control electrode 5 caused by high-temperature annealing, and improving the performance stability of the semiconductor device.

[0073] Optionally, based on the above embodiments, see also... Figure 3 The thickness of the connecting layer 9 is greater than or equal to 0 and less than or equal to 5 nm; and / or the material of the connecting layer 9 includes P-Si or GaAs; and / or the electron affinity of the connecting layer 9 is greater than 3.07 eV.

[0074] Specifically, since excessive thickness of the connecting layer 9 can affect the regulation capability of the regulating layer 2, the thickness of the connecting layer 9 is set to be greater than or equal to 0 and less than or equal to 5 nm. Preferably, the thickness of the connecting layer 9 can be set between 1 nm and 2 nm. This setting maintains the electron depletion capability of the regulating layer 2 for the semiconductor device and improves its ability to consume hot electrons, while avoiding the regulation capability of the regulating layer 2 being affected by excessive thickness of the connecting layer 9. Setting the electron affinity of the connecting layer 9 to be greater than 3.07 eV can effectively reduce the difficulty of ohmic contact fabrication.

[0075] Optionally, based on the above embodiments, see also... Figure 3 The conductive layer 7 includes an ohmic metal layer; and / or the electron affinity of the connecting layer 9 is greater than or equal to 5.8 eV.

[0076] Specifically, this design facilitates the fabrication of ohmic contacts by incorporating the interconnect layer 9, reducing the difficulty of ohmic contact preparation and avoiding the use of a metal with a high diffusion coefficient as the conductive layer 7, thus improving the stability of the semiconductor device. This design also avoids the need for high-temperature annealing during the fabrication of the conductive layer 7, preventing degradation of the control electrode 5's polarity. Furthermore, this design avoids the TiN puncture islands generated during annealing of the conductive layer 7, reducing dislocations and defects in the semiconductor device and further enhancing its stability.

[0077] Conductive layer 7 includes an ohmic metal layer, as exemplified, see [link to example]. Figure 3 The conductive layer 7 may include a first ohmic metal layer, a second ohmic metal layer, and a third ohmic metal layer disposed on the side of the interconnecting layer 9 away from the substrate 1. For example, the first ohmic metal layer may include TiN. The second ohmic metal layer may include Cu. The third ohmic metal layer may include TiN. In some embodiments, the conductive layer 7 may include Au; in other embodiments, the conductive layer 7 may not include Au, without any limitation herein.

[0078] Setting the electron affinity of the connecting layer 9 to be greater than or equal to 5.8 eV can significantly reduce the difficulty of preparing ohmic contacts.

[0079] Based on the same inventive concept, this embodiment provides a method for fabricating a semiconductor device. Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Based on the above embodiments, and in conjunction with... Figures 1 to 4 The method for fabricating a semiconductor device provided in this embodiment includes:

[0080] S101, Provide substrate 1.

[0081] S102, A trench layer 3 is formed on one side of the substrate 1.

[0082] S103, A barrier layer 4 is formed on the side of the channel layer 3 away from the substrate 1.

[0083] S104. An electrode layer is formed on the side of the barrier layer 4 away from the substrate 1. The electrode layer includes a control electrode 5, a first electrode 6, and a second electrode 8.

[0084] S105, An adjustment layer 2 is formed on the side of the barrier layer 4 away from the substrate 1; wherein, along the thickness direction Z of the semiconductor device, the projection of the electrode layer is offset from the projection of the adjustment layer 2; the doping type of the adjustment layer 2 is different from the doping type of the barrier layer 4.

[0085] S106. A conductive layer 7 is formed on the side of the adjustment layer 2 away from the substrate 1, and the conductive layer 7 is connected to the control electrode 5 of the electrode layer.

[0086] The semiconductor device fabrication method provided in this embodiment includes forming an adjustment layer 2 on the side of the barrier layer 4 away from the substrate 1; wherein, along the thickness direction Z of the semiconductor device, the projection of the electrode layer is offset from the projection of the adjustment layer 2; the doping type of the adjustment layer 2 is different from that of the barrier layer 4. A conductive layer 7 is formed on the side of the adjustment layer 2 away from the substrate 1, and the conductive layer 7 is connected to the control electrode 5 of the electrode layer. The semiconductor device fabricated by the semiconductor device fabrication method provided in this embodiment has an adjustment layer 2 at a position with a higher electric field near the control electrode 5, and a conductive layer 7 is formed on the side of the adjustment layer 2 away from the substrate 1. The conductive layer 7 is electrically connected to the control electrode 5, thereby making the adjustment layer 2 electrically connected to the control electrode 5. Because the doping type of the adjustment layer 2 is different from that of the barrier layer 4, the adjustment layer 2 and the barrier layer 4 form a unidirectional conductive path from the conductive layer 7 to the adjustment layer 2 and from the adjustment layer 2 to the barrier layer 4. Since the barrier layer 4 is N-type doped and the adjustment layer 2 is P-type doped. The regulating layer 2 provides holes. When the control electrode 5 is turned off, the holes provided by the regulating layer 2 diffuse, which can deplete electrons at higher positions in the electric field, thereby improving the breakdown voltage capability of the semiconductor device without blocking the 2DEG below the regulating layer 2, thus improving the stability of the semiconductor device. When the control electrode 5 is turned on, due to the effect of the electric field, the hole injection efficiency of the regulating layer 2 is improved, the ability of the regulating layer 2 to consume hot electrons is enhanced, and the ability to deplete hot electrons at higher positions in the electric field becomes stronger. This effectively alleviates the dynamic on-resistance drift, current collapse, and threshold voltage shift of the semiconductor device, improving the breakdown voltage capability and stability of the semiconductor device.

[0087] Optionally, based on the above embodiment, before step S106, which involves forming a conductive layer 7 on the side of the adjustment layer 2 away from the substrate 1 and connecting the conductive layer 7 to the control electrode 5 of the electrode layer, the method further includes:

[0088] A connection layer 9 is formed on the side of the adjustment layer 2 away from the substrate 1, and the connection layer 9 comprises a P-type degenerate semiconductor material.

[0089] Step S106: Forming a conductive layer 7 on the side of the adjustment layer 2 away from the substrate 1, and connecting the conductive layer 7 to the control electrode 5 of the electrode layer may include:

[0090] A conductive layer 7 is formed on the side of the connecting layer 9 away from the adjusting layer 2, and the conductive layer 7 is electrically connected to the control electrode 5 of the electrode layer, so as to electrically connect the adjusting layer 2 to the control electrode 5.

[0091] The semiconductor device fabrication method provided in this embodiment further includes forming a connection layer 9 on the side of the adjustment layer 2 away from the substrate 1, the connection layer 9 comprising a p-type degenerate semiconductor material. A conductive layer 7 is formed on the side of the connection layer 9 away from the adjustment layer 2, and the conductive layer 7 is electrically connected to the control electrode 5 of the electrode layer to electrically connect the adjustment layer 2 to the control electrode 5. The semiconductor device fabricated by the semiconductor device fabrication method provided in this embodiment has a connection layer 9 disposed between the adjustment layer 2 and the conductive layer 7. Since the adjustment layer 2 is a p-type doped material, the Fermi level of the adjustment layer 2 is very close to the valence band position, so the work function of the adjustment layer 2 becomes very large. By setting the connection layer 9, which comprises a p-type degenerate semiconductor material, and since the p-type degenerate semiconductor material is selected as a material with a high electron affinity, it is convenient to prepare the connection layer 9 first when preparing the conductive layer 7 on the side of the adjustment layer 2 away from the substrate 1, and to facilitate the preparation of the conductive layer 7 on the side of the connection layer 9 away from the adjustment layer 2 for the preparation of the ohmic contact metal.

[0092] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A channel layer disposed on one side of the substrate; A barrier layer disposed on the side of the channel layer away from the substrate; An electrode layer is disposed on the side of the barrier layer away from the substrate, and the electrode layer includes a control electrode, a first electrode, and a second electrode; At least one conditioning layer disposed on the side of the barrier layer away from the substrate; At least one conductive layer is disposed on the side of the adjustment layer away from the substrate, and the conductive layer is electrically connected to the control electrode; Along the thickness direction of the semiconductor device, the projection of the electrode layer is offset from the projection of the adjustment layer; the doping type of the adjustment layer is different from the doping type of the barrier layer.

2. The semiconductor device according to claim 1, characterized in that, When the semiconductor device includes at least two adjustment layers, the conductive layer and the adjustment layer are respectively disposed in a one-to-one correspondence; Each of the conductive layers is electrically connected to the control electrode, the regulating layer is conductive along the direction of the conductive layer toward the barrier layer, and the regulating layer is cut off along the direction of the barrier layer toward the regulating layer.

3. The semiconductor device according to claim 2, characterized in that, Along a direction perpendicular to the thickness of the semiconductor device, the adjustment layer is disposed between the first electrode and the control electrode of the semiconductor device, close to the control electrode; And / or, Along a direction perpendicular to the thickness of the semiconductor device, the adjustment layer is disposed between the second electrode and the control electrode of the semiconductor device, close to the control electrode.

4. The semiconductor device according to claim 3, characterized in that, The adjustment layer and the control electrode are spaced apart by a first preset distance; The adjustment layer is disposed at a position where the electric field strength of the semiconductor device is greater than the average electric field strength of the semiconductor device.

5. The semiconductor device according to claim 1, characterized in that, The thickness of the adjustment layer is greater than 0 and less than or equal to 50 nm; and / or, The material of the conditioning layer includes a p-type doped material; and / or, The material of the conditioning layer includes diamond, p-GaN, p-NiO, p-ZnO, or... .

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The semiconductor device further includes: A connecting layer is disposed between the adjustment layer and the conductive layer; The interconnect layer comprises a P-type degenerate semiconductor material.

7. The semiconductor device according to claim 6, characterized in that, The thickness of the connecting layer is greater than or equal to 0 and less than or equal to 5 nm; and / or, The material of the bonding layer includes: P-Si or GaAs; and / or, The electron affinity of the connecting layer is greater than 3.07 eV.

8. The semiconductor device according to claim 6, characterized in that, The conductive layer includes an ohmic metal layer; and / or, The electron affinity of the connecting layer is greater than or equal to 5.8 eV.

9. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A trench layer is formed on one side of the substrate; A barrier layer is formed on the side of the channel layer away from the substrate; An electrode layer is formed on the side of the barrier layer away from the substrate, the electrode layer including a control electrode, a first electrode, and a second electrode; An adjustment layer is formed on the side of the barrier layer away from the substrate; wherein, along the thickness direction of the semiconductor device, the projection of the electrode layer is offset from the projection of the adjustment layer; the doping type of the adjustment layer is different from the doping type of the barrier layer; A conductive layer is formed on the side of the adjustment layer away from the substrate, and the conductive layer is connected to the control electrode of the electrode layer.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, Before forming a conductive layer on the side of the adjustment layer away from the substrate, and connecting the conductive layer to the control electrode of the electrode layer, the method further includes: A connection layer is formed on the side of the adjustment layer away from the substrate, the connection layer comprising a P-type degenerate semiconductor material; A conductive layer is formed on the side of the adjustment layer away from the substrate, and the conductive layer is connected to the control electrode of the electrode layer, including: A conductive layer is formed on the side of the connection layer away from the adjustment layer, and the conductive layer is electrically connected to the control electrode of the electrode layer, so as to electrically connect the adjustment layer to the control electrode.

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