Method for manufacturing a semiconductor device and semiconductor device

Abstract

This application discloses a method for manufacturing a semiconductor device and a semiconductor device. The method includes: forming a gate structure on the front side of a wafer; sequentially depositing a self-aligned oxide material layer and a self-aligned polysilicon material layer on the wafer and the gate structure; performing a wet etching process to pattern the self-aligned polysilicon material layer to form a self-aligned polysilicon layer; performing a dry etching process to pattern the self-aligned oxide material layer to form a self-aligned oxide layer; and performing a metal silicide process on the self-aligned polysilicon layer, the exposed wafer, and the upper surface of the gate structure to form a metal silicide layer. This application improves the uniformity and integrity of the formed metal silicide layer, thereby improving device yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0002] In existing semiconductor processes, to form a metal silicide layer, a self-aligned oxide (SAB) layer and a self-aligned polysilicon (SA-poly) layer are typically deposited after the spacer of the gate structure is formed. These layers protect the gate structure and control the formation area of ​​the metal silicide layer in subsequent processes. The SA-poly and SA-oxide layers are usually formed using a one-step or two-step dry etching process. However, insufficient etch window in a one-step dry etching process can lead to oxide residue, while a two-step dry etching process can result in polymer residue on the wafer surface, causing defects that hinder the normal formation of the subsequent metal silicide layer and reduce device yield. Summary of the Invention

[0003] In view of the above problems, the purpose of this application is to provide a method for manufacturing a semiconductor device and a semiconductor device, which aims to improve the uniformity and integrity of the formed metal silicide layer, thereby improving the device yield.

[0004] According to a first aspect of the embodiments of this application, a method for manufacturing a semiconductor device is provided, comprising:

[0005] A gate structure is formed on the front side of the wafer;

[0006] A self-aligned oxide material layer and a self-aligned polysilicon material layer are sequentially deposited on the wafer and the gate structure;

[0007] The self-aligned polysilicon material layer is patterned by performing a wet etching process to form a self-aligned polysilicon layer;

[0008] The self-aligned oxide material layer is patterned using a dry etching process to form a self-aligned oxide layer;

[0009] A metal silicide process is performed on the self-aligned polysilicon layer, the exposed wafer, and the upper surface of the gate structure to form a metal silicide layer.

[0010] Optionally, the gate structure includes a gate oxide layer and a polysilicon gate stacked sequentially, and the sidewalls of the polysilicon gate are provided with sidewalls, the sidewalls including a silicon oxide layer and a silicon nitride layer stacked sequentially.

[0011] Optionally, after depositing a self-aligned oxide material layer and a self-aligned polysilicon material layer sequentially on the wafer and the gate structure, a multilayer film structure is deposited on the back side of the wafer. The multilayer film structure includes a gate oxide material layer, a polysilicon material layer, a silicon oxide material layer, a silicon nitride material layer, and a self-aligned polysilicon material layer stacked sequentially.

[0012] Optionally, the wet etching process for patterning the self-aligned polysilicon material layer to form a self-aligned polysilicon layer includes:

[0013] A wet etching process is performed to pattern the self-aligned polysilicon material layer on the wafer and the gate structure to form the self-aligned polysilicon layer. The orthographic projection of the opening of the self-aligned polysilicon layer overlaps with the orthographic projection of the source region, drain region and part of the gate structure of the semiconductor device.

[0014] Optionally, the step of performing a wet etching process to pattern the self-aligned polysilicon material layer to form a self-aligned polysilicon layer further includes:

[0015] The wet etching process is performed to remove the self-aligned polysilicon material layer deposited on the back side of the wafer.

[0016] Optionally, the step of performing a wet etching process to pattern the self-aligned polysilicon material layer to form a self-aligned polysilicon layer further includes:

[0017] During the wet etching process, residual polymer on the surface of the semiconductor device is removed.

[0018] Optionally, the orthographic projection of the opening of the self-aligned oxide layer overlaps with the orthographic projection of the source region, drain region, and part of the gate structure of the semiconductor device.

[0019] Optionally, during the processing after the formation of the self-aligned polysilicon layer, the thickness of the silicon nitride material layer deposited on the back side of the wafer is reduced.

[0020] Optionally, the silicon nitride material layer deposited on the back side of the wafer is thinned to a thickness of up to 100 Å.

[0021] According to a second aspect of the embodiments of this application, a semiconductor device is provided, manufactured according to the manufacturing method described above.

[0022] The unexpected technical effect of this application is:

[0023] A gate structure is formed on the front side of the wafer. A self-aligned oxide material layer and a self-aligned polysilicon material layer are sequentially deposited on the wafer and the gate structure. A wet etching process is performed to pattern the self-aligned polysilicon material layer to form a self-aligned polysilicon layer. A dry etching process is performed to pattern the self-aligned oxide material layer to form a self-aligned oxide layer. A metal silicide process is then performed on the self-aligned polysilicon layer, the exposed wafer, and the upper surface of the gate structure to form a metal silicide layer. By using a two-step etching process of wet etching and dry etching to etch the self-aligned polysilicon material layer and the self-aligned oxide material layer step by step, the oxide remain caused by insufficient etching window in a one-step dry etching process is eliminated. The defects caused by residual polymer on the wafer surface in the two-step dry etching process are also eliminated. This improves the uniformity and integrity of the formed metal silicide layer, reduces contact resistance, and improves the conductivity of the device.

[0024] Furthermore, a wet etching process is performed to pattern the self-aligned polysilicon material layer on the wafer and gate structure to form a self-aligned polysilicon layer. The orthographic projection of the opening of the self-aligned polysilicon layer overlaps with the orthographic projection of the source region, drain region, and part of the gate structure of the semiconductor device. At the same time, the self-aligned polysilicon material layer deposited on the back of the wafer is removed by the same wet etching process, which effectively eliminates the machine track marks caused by the side reactions of the self-aligned polysilicon material layer deposited on the back of the wafer in the traditional process, and significantly improves the surface quality of the back of the wafer and the reliability of subsequent packaging and testing.

[0025] Furthermore, during the wet etching process of the self-aligned polysilicon layer deposited on the front side of the wafer, the self-aligned polysilicon layer deposited on the back side of the wafer is simultaneously removed, exposing the silicon nitride layer as the new outermost layer. In subsequent processes following the formation of the self-aligned polysilicon layer on the front side of the wafer (e.g., silicide, contact (CT), back-end-of-line (BEOL) processes), wet etching is performed, reducing the thickness of the silicon nitride layer deposited on the back side of the wafer. This allows for adjustment of the stress balance between the front and back wafer layers, significantly improving the problem of excessively high compressive stress in the silicon nitride layer deposited on the back side of the wafer. Ultimately, this effectively alleviates the phenomenon of lower gate oxide breakdown voltage in semiconductor devices located at the wafer edge during gate oxide breakdown voltage testing. Attached Figure Description

[0026] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0027] Figure 1A The diagram shows a multilayer film structure deposited on the back side of a wafer in a related technology.

[0028] Figure 1B The diagram shows the oxide residue in the self-aligned oxide layer after etching process in related technologies.

[0029] Figure 1C The diagram shows an imprint formed on the back of a wafer in relation to the machine track in a related technology.

[0030] Figure 1D The figure shown is a schematic diagram of the gate oxide breakdown voltage test curve of a semiconductor device in the related technology;

[0031] Figure 2 The diagram shown is a schematic flowchart of an exemplary semiconductor device manufacturing method according to an embodiment of this application.

[0032] Figures 3A to 3G The diagram shows cross-sectional views of different stages of an exemplary semiconductor device manufacturing method according to an embodiment of this application.

[0033] Figure reference numerals: 110 - wafer; 120 - gate oxide layer; 130 - polysilicon layer; 140 - silicon oxide layer; 150 - silicon nitride layer; 160 - first self-aligned polysilicon layer; 170 - first self-aligned oxide layer; 320 - gate structure; 321a - gate oxide layer; 322a - polysilicon gate; 323a - silicon oxide layer; 324a - silicon nitride layer; 330 - second self-aligned oxide layer; 330a - self-aligned oxide layer; 340 - self-aligned polysilicon layer; 340a - second self-aligned polysilicon layer; 340b - third self-aligned polysilicon layer; 350 - photoresist; 360 - metal silicide layer. Detailed Implementation

[0034] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0035] This application may be presented in various forms, some of which will be described below.

[0036] In existing semiconductor processes, to form a metal silicide layer, a self-aligned oxide (SAB) layer and a self-aligned polysilicon (SA-poly) layer are typically deposited after the sidewalls of the gate structure are formed. This protects the gate structure and controls the formation area of ​​the metal silicide layer in subsequent processes. However, this conventional process also simultaneously deposits a self-aligned polysilicon material layer on the back side of the wafer, resulting in deposition on the back side of the wafer. Figure 1A The multilayer film structure shown. Figure 1A As shown, a multilayer film structure consisting of a gate oxide layer 120, a polysilicon layer 130, a silicon oxide layer 140, a silicon nitride layer 150, and a first self-aligned polysilicon layer 160 is formed on the back side of wafer 110. Furthermore, a one-step dry etching process is typically used to form the self-aligned polysilicon layer and the self-aligned oxide layer on the front side of the wafer. Due to the small etch window, areas with small spacing between the self-aligned polysilicon layers deposited on the sidewalls of adjacent gate structures (i.e., the poly-to-poly spacing) are prone to defects such as… Figure 1B The oxide remainder in the first self-aligned oxide layer 170, as shown, hinders the normal formation of the subsequent metal silicide layer, leading to increased contact resistance (CT resistance) and affecting device yield. If a two-step dry etching process is attempted to form the self-aligned polysilicon layer and the self-aligned oxide layer on the front side of the wafer in stages, polymer residue will remain on the wafer surface after the first step of etching to form the self-aligned polysilicon layer. This will worsen the defect situation during the second step of etching to form the self-aligned oxide layer, further affecting device yield.

[0037] like Figure 1A As shown, since the outermost layer on the back side of wafer 110 is a first self-aligned polysilicon material layer 160, this layer is prone to oxidation or other side reactions in subsequent high-temperature or wet processes, thereby forming on the back side of wafer 110 related to the machine track (e.g.) Figure 1C The imprints shown affect the reliability of subsequent packaging tests. In addition, the silicon nitride material layer 150 grown on the back side of wafer 110 causes stress imbalance between the front and back film layers of wafer 110, which ultimately results in a lower gate oxide breakdown voltage for semiconductor devices located at the wafer edge during gate oxide breakdown voltage testing. Figure 1D The diagram shows a schematic of the gate oxide breakdown voltage test curve for a semiconductor device in related technologies. The horizontal axis represents the tested gate oxide breakdown voltage Vbd of the semiconductor device, and the vertical axis represents the probability distribution of the tested breakdown voltage. Figure 1D As shown, in related technologies, semiconductor devices with low gate oxide breakdown voltage Vbd are all located at the wafer edge.

[0038] Based on this, this application provides a method for manufacturing a semiconductor device and a semiconductor device, thereby eliminating oxide residues caused by insufficient etching windows in a one-step dry etching process, eliminating defects caused by polymer residues on the wafer surface in a two-step dry etching process, avoiding track marks caused by residual self-aligned polysilicon material layers on the back side of the wafer, alleviating the phenomenon of low gate oxide breakdown voltage of semiconductor devices located at the wafer edge during gate oxide breakdown voltage testing, thereby improving the uniformity and integrity of the formed metal silicide layer and improving device yield.

[0039] Figure 2 The diagram shown is a schematic flowchart of an exemplary semiconductor device manufacturing method according to an embodiment of this application. Figures 3A to 3G The diagram shows cross-sectional views of different stages in an exemplary semiconductor device manufacturing method according to an embodiment of this application. The following is in conjunction with... Figures 3A to 3G Detailed description Figure 2 The method for manufacturing the semiconductor device is shown. (For example...) Figure 2 As shown, the manufacturing method includes:

[0040] In step S210, a gate structure is formed on the front side of the wafer.

[0041] In some embodiments, such as Figure 3A As shown, a gate structure 320 is formed on the front side of wafer 110. The gate structure 320 includes a gate oxide layer 321a and a polysilicon gate 322a stacked sequentially. The gate oxide layer 321a is located between the polysilicon gate 322a and wafer 110. Sidewalls are also provided on the sidewalls of the polysilicon gate 322a, and the sidewalls include a silicon oxide layer 323a and a silicon nitride layer 324a stacked sequentially. The fabrication process of the gate structure 320 can be performed using any suitable method well known to those skilled in the art. For example, the gate oxide layer 321a can be first deposited on the surface of wafer 110 using thermal oxidation or chemical vapor deposition. Then, a polysilicon layer is deposited using low-pressure chemical vapor deposition (LPCVD) and the polysilicon gate 322a is formed by photolithography-dry etching. Next, the silicon oxide layer 323a and the silicon nitride layer 324a are deposited sequentially, and the sidewalls are formed by anisotropic dry etching. The source and drain regions can be formed by ion implantation and annealing before or after the formation of the gate structure 320. The type of implanted ions is set according to the device type (NMOS or PMOS) and process node requirements.

[0042] like Figure 3AAs shown, after the gate structure 320 is formed on the front side of wafer 110, a gate oxide layer 120, a polysilicon layer 130, a silicon oxide layer 140, and a silicon nitride layer 150 are sequentially stacked on the back side of wafer 110. The gate oxide layer 120, polysilicon layer 130, silicon oxide layer 140, and silicon nitride layer 150 deposited on the back side of wafer 110 are all deposited simultaneously during the formation of the gate structure 320 on the front side of wafer 110. Therefore, the thickness, composition, and stress characteristics of these four film structures deposited on the back side of wafer 110 are consistent with the corresponding film layers deposited on the front side of wafer 110.

[0043] In step S220, a self-aligned oxide material layer and a self-aligned polysilicon material layer are sequentially deposited on the wafer and the gate structure.

[0044] In some embodiments, such as Figure 3B As shown, a self-aligned oxide material layer 330a is deposited on the front side of wafer 110 and the upper surface of gate structure 320 using a chemical vapor deposition process. The self-aligned oxide material layer 330a is deposited only on the front side of wafer 110, while the back side of the wafer remains... Figure 3A The four-layer membrane structure shown remains unchanged.

[0045] In some embodiments, such as Figure 3C As shown, a second self-aligned polysilicon layer 340a is deposited on the front side of wafer 110 and above the self-aligned oxide layer 330a deposited on the upper surface of the gate structure 320 using a furnace tube silicon growth process. Furthermore, since the furnace tube reaction chamber is batch-loaded and the wafers 110 are arranged in a vertical insertion manner, the reactive gases simultaneously reach both the front and back sides. Therefore, during the deposition of the second self-aligned polysilicon layer 340a on the front side of wafer 110, a third self-aligned polysilicon layer 340b is simultaneously deposited below the silicon nitride layer 150 deposited on the back side of wafer 110. The second self-aligned polysilicon layer 340a deposited on the front side of wafer 110 and the third self-aligned polysilicon layer 340b deposited on the back side of wafer 110 are completed within the same process cycle and have the same grain size, doping concentration, and stress state. After the self-aligned polysilicon layer deposition process is completed, a multilayer film structure is deposited on the back side of wafer 110. The multilayer film structure includes a gate oxide material layer 120, a polycrystalline silicon material layer 130, a silicon oxide material layer 140, a silicon nitride material layer 150, and a newly generated third self-aligned polycrystalline silicon material layer 340b, which are stacked sequentially.

[0046] In step S230, a wet etching process is performed to pattern the self-aligned polysilicon material layer to form a self-aligned polysilicon layer.

[0047] In some embodiments, such as Figure 3DAs shown, photoresist 350 is spin-coated over the second self-aligned polysilicon material layer 340a deposited on the front side of wafer 110, and an opening pattern is formed by exposure and development. The orthogonal projection of this opening pattern overlaps with the orthogonal projection of the source region, drain region, and part of the gate structure 320 of the semiconductor device in the wafer. Subsequently, as... Figure 3E As shown, using photoresist 350 as a mask, a wet etching process is performed on the second self-aligned polysilicon material layer 340a deposited on the front side of wafer 110. This selectively removes the second self-aligned polysilicon material layer 340a not covered by photoresist on the front side of wafer 110, thereby forming a patterned self-aligned polysilicon layer 340. The orthogonal projection of the opening of the self-aligned polysilicon layer 340 overlaps with the orthogonal projection of the source region, drain region, and part of the gate structure of the semiconductor device. In one example, the thickness of the self-aligned polysilicon layer is 300 Å. Simultaneously, since the back side of wafer 110 is also exposed to the etching solution, the third self-aligned polysilicon material layer 340b is removed synchronously in the same etching step, exposing the silicon nitride material layer 150 as the new outermost layer. This effectively eliminates the machine track marks formed by side reactions of the self-aligned polysilicon material layer deposited on the back side of the wafer in conventional processes, significantly improving the surface quality of the back side of the wafer and the reliability of subsequent packaging and testing. In some embodiments, after etching is completed, residual etching solution and photoresist 350 are removed by rinsing with deionized water and purging with nitrogen, and both the front and back surfaces of wafer 110 are restored to a clean surface, preparing for subsequent processes such as metal silicide formation and contact hole processing.

[0048] In some embodiments, during the front-end process, fluorine- or carbon-containing polymer byproducts may remain on the sidewalls of the gate structure 320 and the exposed surfaces of the source / drain regions. These polymers typically exist in the form of a thin film of a certain thickness. If not removed in time, they will introduce interface contamination during the subsequent metal silicide formation stage, leading to increased contact resistance or leakage current. It is understood that this application integrates the surface polymer removal step of the semiconductor device into the wet etching process of step S230, using the etching solution to chemically dissolve and mechanically peel off the polymer while removing the third self-aligned polysilicon material layer 340b. The surface polymer residue of the semiconductor device is effectively removed, ensuring that both the front and back sides of wafer 110 meet the cleanliness standards required for subsequent metal silicide processes.

[0049] In step S240, a dry etching process is performed to pattern the self-aligned oxide material layer to form a self-aligned oxide layer.

[0050] In some embodiments, such as Figure 3FAs shown, using photoresist 350 as a mask, a dry etching process is performed on the self-aligned oxide material layer 330a deposited on the front side of wafer 110. Anisotropic etching is performed on the areas of the self-aligned oxide material layer 330a not covered by photoresist, thereby selectively patterning the self-aligned oxide material layer 330a into a second self-aligned oxide layer 330. In one example, the thickness of the second self-aligned oxide layer is 1200 Å. The orthographic projection of the opening of the second self-aligned oxide layer 330 overlaps with the orthographic projection of the source region, drain region, and part of the gate structure of the semiconductor device. After the dry etching process is completed, the photoresist 350 is removed.

[0051] Understandably, by employing a two-step etching process of wet etching and dry etching to etch the self-aligned polysilicon material layer and the self-aligned oxide material layer in stages, the oxide remain caused by insufficient etching window in the one-step dry etching process is eliminated. It also eliminates the defects caused by residual polymer on the wafer surface in the two-step dry etching process, thereby improving the uniformity and integrity of the formed metal silicide layer, reducing contact resistance and improving the conductivity of the device.

[0052] In step S250, a metal silicide process is performed on the self-aligned polysilicon layer, the exposed wafer, and the upper surface of the gate structure to form a metal silicide layer.

[0053] In some embodiments, such as Figure 3G As shown, a metal silicide process is performed on the self-aligned polysilicon layer 340, the exposed wafer 110, and the upper surface of the gate structure 320 to form a metal silicide layer 360. The metal silicide formed by metallizing the self-aligned polysilicon layer 340 and the metal silicide formed by metallizing part of the upper surface of the gate structure 320 together serve as the gate of the semiconductor device. The metal silicide formed by metallizing the self-aligned polysilicon layer 340 serves as a supplementary gate, which can increase the conductive channel between the source and drain of the active region, thereby increasing the high voltage withstand capability of the semiconductor device.

[0054] In some embodiments, since the wet etching process in step S230 simultaneously removes the third self-aligned polysilicon material layer 340b deposited on the back side of wafer 110, the silicon nitride material layer 150 originally located below the third self-aligned polysilicon material layer 340b is directly exposed and becomes the outermost layer on the back side of wafer 110. In subsequent processes after the formation of the self-aligned polysilicon layer 340 on the front side of wafer 110 (e.g., silicide process, contact (CT) process, back-end-of-line (BEOL) process), wet etching processes are performed, reducing the thickness of the silicon nitride material layer 150 deposited on the back side of wafer 110. Figure 3G As shown, the silicon nitride material layer 150 deposited on the back side of wafer 110 is thinned to a thickness h of 100 Å. In one example, as... Figure 3A As shown, the thickness of the silicon nitride material layer 150 deposited on the back side of wafer 110 is 950 Å. (As...) Figure 3G As shown, the thickness of the thinned silicon nitride material layer 150 deposited on the back side of wafer 110 is 850 Å.

[0055] Understandably, the thickness of the silicon nitride material layer 150 deposited on the back side of wafer 110 is reduced. This can adjust the stress balance between the front and back film layers of wafer 110, significantly improve the problem of excessive compressive stress in the back silicon nitride material layer 150, and ultimately effectively alleviate the phenomenon of low gate oxide breakdown voltage of semiconductor devices located at the edge of the wafer during gate oxide breakdown voltage testing.

[0056] Finally, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The embodiments described above, as per the implementation of this application, do not exhaustively describe all details, nor do they limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: A gate structure is formed on the front side of the wafer; A self-aligned oxide material layer and a self-aligned polysilicon material layer are sequentially deposited on the wafer and the gate structure. During the process of forming the gate structure and the sidewalls of the gate structure on the front side of the wafer, and during the process of sequentially depositing the self-aligned oxide material layer and the self-aligned polysilicon material layer on the wafer and the gate structure, a multilayer film structure is simultaneously deposited on the back side of the wafer. The multilayer film structure includes a gate oxide material layer, a polysilicon material layer, a silicon oxide material layer, a silicon nitride material layer, and a self-aligned polysilicon material layer stacked sequentially. Performing a wet etching process to pattern the self-aligned polysilicon material layer to form a self-aligned polysilicon layer includes: performing the wet etching process to remove the self-aligned polysilicon material layer deposited on the back side of the wafer. The self-aligned oxide material layer is patterned using a dry etching process to form a self-aligned oxide layer; Metal silicide processes are performed on the self-aligned polysilicon layer, the exposed wafer, and the upper surface of the gate structure to form a metal silicide layer. During the processing following the formation of the self-aligned polysilicon layer, the thickness of the silicon nitride material layer deposited on the back side of the wafer is reduced.

2. The manufacturing method according to claim 1, wherein, The gate structure includes a gate oxide layer and a polysilicon gate layer stacked sequentially. The sidewalls of the polysilicon gate are provided with sidewalls, which include a silicon oxide layer and a silicon nitride layer stacked sequentially.

3. The manufacturing method according to claim 1, wherein, The process of performing a wet etching process to pattern the self-aligned polysilicon material layer to form a self-aligned polysilicon layer includes: A wet etching process is performed to pattern the self-aligned polysilicon material layer on the wafer and the gate structure to form the self-aligned polysilicon layer. The orthographic projection of the opening of the self-aligned polysilicon layer overlaps with the orthographic projection of the source region, drain region and part of the gate structure of the semiconductor device.

4. The manufacturing method according to claim 3, wherein, The step of performing a wet etching process to pattern the self-aligned polysilicon material layer to form a self-aligned polysilicon layer further includes: During the wet etching process, residual polymer on the surface of the semiconductor device is removed.

5. The manufacturing method according to claim 4, wherein, The orthographic projection of the opening of the self-aligned oxide layer overlaps with the orthographic projection of the source region, drain region, and part of the gate structure of the semiconductor device.

6. The manufacturing method according to claim 5, wherein, The silicon nitride material layer deposited on the back side of the wafer is thinned to a thickness of 100 Å.

7. A semiconductor device manufactured according to the manufacturing method according to any one of claims 1 to 6.

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