Semiconductor module

Abstract

The invention discloses a semiconductor module. The semiconductor module comprises a substrate; the inverter chip comprises a first high-side inverter chip and a second high-side inverter chip which are oppositely arranged in a first direction; and the first jumper area is located between the first high-side inverter chip and the second high-side inverter chip in the first direction, and only the first jumper area is arranged in an area jointly defined by the first edge connecting line, the second edge connecting line, the third edge connecting line and the fourth edge connecting line. Therefore, the effective area, used for arranging the first high-side inverter chip and the second high-side inverter chip, on the first substrate part can be increased, so that the inverter chip with a relatively large specification can be arranged in the semiconductor module, and the through-current capability of the semiconductor module is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor module. Background Technology

[0002] With the development of semiconductor chip technology and packaging technology, high-power semiconductor modules are being used more and more widely. A power integrated module (PIM) is a product that integrates a three-phase frequency converter circuit, a diode bridge circuit, and a braking circuit into a single module, enabling a compact design of the main circuit.

[0003] In related technologies, the structural design within the PIM is not reasonable enough, and the space for arranging internal components is limited. This makes it impossible to arrange larger chips in the PIM, which in turn limits the current carrying capacity of the PIM. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of the present invention is to provide a semiconductor module that can accommodate a larger-sized inverter chip.

[0005] A semiconductor module according to an embodiment of the present invention has a first direction and a second direction, and a high side and a low side disposed opposite to each other in the second direction. The semiconductor module includes: a housing; a substrate disposed within the housing, the substrate having a first substrate portion and a second substrate portion arranged sequentially at intervals along the first direction, the first substrate portion having a first high-side inverter chip upper region and a first low-side inverter chip upper region arranged at intervals along the second direction, wherein the first high-side inverter chip upper region is closer to the high side than the first low-side inverter chip upper region, and the second substrate portion having a second high-side inverter chip upper region, a third low-side inverter chip upper region, and a third low-side inverter chip upper region arranged sequentially at intervals along the second direction. The upper region of the second low-side inverter chip is located closer to the high side than the upper region of the second low-side inverter chip; multiple inverter chips, each of which is a single chip, each of which has a control electrode pad, a first load electrode pad, and a second load electrode pad, the multiple inverter chips including a first high-side inverter chip, a second high-side inverter chip, a third high-side inverter chip, a first low-side inverter chip, a second low-side inverter chip, and a third low-side inverter chip, the first high-side inverter chip and the second high-side inverter chip are located on the upper region of the first high-side inverter chip and are spaced apart along the first direction, the first high-side inverter chip is located on the upper region of the second high-side inverter chip in a first direction. The third high-side inverter chip is disposed on the upper core area of ​​the second high-side inverter chip, and the first low-side inverter chip is disposed on the upper core area of ​​the first low-side inverter chip. The second low-side inverter chip is disposed on the upper core area of ​​the second low-side inverter chip, and the third low-side inverter chip is disposed on the upper core area of ​​the third low-side inverter chip. The first high-side inverter chip and the second high-side inverter chip are disposed closer to the high side along the second direction on the upper core area of ​​the first high-side inverter chip. The upper core area of ​​the first high-side inverter chip has an avoidance notch, and a first jumper area extending along the second direction is provided in the avoidance notch. The first jumper area is spaced apart from the upper core area of ​​the first high-side inverter chip. At least a portion of the first jumper area is located between the first high-side inverter chip and the second high-side inverter chip in a first direction. The edge of the first high-side inverter chip adjacent to the second high-side inverter chip in a first direction is defined as the first edge. The edge of the second high-side inverter chip adjacent to the first high-side inverter chip in a first direction is defined as the second edge. The edge of the first high-side inverter chip adjacent to the low side in a second direction is defined as the third edge. The edge of the first high-side inverter chip adjacent to the high side in a second direction is defined as the fourth edge. The edge of the second high-side inverter chip adjacent to the low side in a second direction is defined as the fifth edge. The edge of the second high-side inverter chip adjacent to the high side in a second direction is defined as the sixth edge.The edge closer to the lower side between the third and fifth edges is designated as the low-side edge, and the edge closer to the higher side between the fourth and sixth edges is designated as the high-side edge. The area enclosed by the extensions of the first edge, the second edge, the high-side edge, and the low-side edge is designated as the interval region. The portion of the interval region corresponding to the clearance notch is only provided with the first jumper area. A conductive element connects the second load electrode pad of the first high-side inverter chip to the first jumper area. The control electrode pad of the first high-side inverter chip is located closer to the high side along the second direction on the first high-side inverter chip. The control electrode pad of the first high-side inverter chip is electrically connected to an external terminal.

[0006] Therefore, by providing only the first jumper area in the interval area corresponding to the avoidance gap, the effective area on the first substrate for setting the first high-side inverter chip and the second high-side inverter chip can be increased, thereby allowing a larger inverter chip to be set in the semiconductor module to improve the current carrying capacity of the semiconductor module.

[0007] In some examples of the present invention, a second jumper area is further provided on the first substrate portion. The second jumper area is disposed in the clearance notch. The edge of the first high-side inverter chip that is closer to the high side in the second direction is defined as the high side edge. The second jumper area is disposed at intervals on the side of the high side edge facing the high side in the second direction. The second jumper area is located on the side of the first jumper area away from the second substrate portion in the first direction. A conductive element is connected between the control electrode pad of the first high-side inverter chip and the second jumper area. A conductive element is connected between the second jumper area and the external terminal.

[0008] In some examples of the present invention, the first high-side inverter chip and the second high-side inverter chip are arranged opposite each other in a first direction, and the projections of the first high-side inverter chip and the second high-side inverter chip in the first direction completely overlap.

[0009] In some examples of the present invention, the portion of the first jumper area located between the first high-side inverter chip and the second high-side inverter chip has a dimension L1 in the first direction, and L1 satisfies the relationship: 1.7mm≤L1≤3.2mm.

[0010] In some examples of the present invention, the dimension of the first substrate portion in the second direction is A; the distance between the first high-side inverter chip and the edge of the first substrate portion facing the high side is B, and A and B satisfy the relationship: 0.086A≤B≤0.117A; the distance between the second high-side inverter chip and the edge of the first substrate portion facing the high side is C, and A and C satisfy the relationship: 0.086A≤C≤0.117A.

[0011] In some examples of the present invention, the control electrode pad of the first high-side inverter chip is disposed on the side of the first high-side inverter chip that is further away from the second substrate portion along the first direction.

[0012] In some examples of the present invention, the first high-side inverter chip has a control electrode channel, the second load electrode pad of the first high-side inverter chip includes two sub-load electrode pads, the control electrode channel is disposed between the two sub-load electrode pads, and the control electrode channel of the first high-side inverter chip extends along the first direction.

[0013] In some examples of the present invention, the first jumper area is located in the middle of the upper core area of ​​the first high-side inverter chip in the first direction.

[0014] In some examples of the present invention, a third jumper area is further provided on the first substrate portion. The third jumper area is connected to one end of the first jumper area adjacent to the upper core area of ​​the first low-side inverter chip. The third jumper area extends from the first jumper area in a first direction toward a direction away from the second substrate portion. A conductive element is connected between the third jumper area and the upper core area of ​​the first low-side inverter chip.

[0015] In some examples of the present invention, the first low-side inverter chip is disposed on the upper core area of ​​the first low-side inverter chip more closely adjacent to the second substrate portion along the first direction, and a conductive element is connected between the side of the upper core area of ​​the first low-side inverter chip away from the second substrate portion in the first direction and the third jumper area.

[0016] In some examples of the present invention, a fourth jumper region is further provided on the first substrate portion, the fourth jumper region being connected to the end of the first jumper region away from the upper core area of ​​the first low-side inverter chip, and the fourth jumper region extending from the first jumper region toward the second substrate portion in a first direction.

[0017] In some examples of the present invention, the third high-side inverter chip is located in the middle of the second substrate portion in the first direction.

[0018] In some examples of the present invention, the control electrode pad of the third high-side inverter chip is disposed more adjacent to the high side on the third high-side inverter chip along the second direction; the control electrode pad of the third high-side inverter chip is disposed more adjacent to the first substrate portion on the third high-side inverter chip along the first direction.

[0019] In some examples of the present invention, the third high-side inverter chip has a control electrode channel, the second load electrode pad of the third high-side inverter chip includes two sub-load electrode pads, the control electrode channel is disposed between the two sub-load electrode pads, and the control electrode channel of the third high-side inverter chip extends along the first direction.

[0020] In some examples of the present invention, a fifth jumper area is further provided on the second substrate portion. The fifth jumper area is located on the side of the upper core area of ​​the second high-side inverter chip away from the first substrate portion in the first direction. A conductive element is connected between the control electrode pad of the third high-side inverter chip and the fifth jumper area.

[0021] In some examples of the present invention, the third low-side inverter chip is located in the middle of the second substrate portion in the first direction.

[0022] In some examples of the present invention, the control electrode pad of the third low-side inverter chip is disposed on the third low-side inverter chip more closely adjacent to the low side along the second direction; the control electrode pad of the third low-side inverter chip is disposed on the third low-side inverter chip more closely adjacent to the side of the third low-side inverter chip away from the first substrate portion along the first direction.

[0023] In some examples of the present invention, the third low-side inverter chip has a control electrode channel, the second load electrode pad of the third low-side inverter chip includes two sub-load electrode pads, the control electrode channel is disposed between the two sub-load electrode pads, and the control electrode channel of the third low-side inverter chip extends along the first direction.

[0024] In some examples of the present invention, the second low-side inverter chip is disposed on the second substrate portion more closely adjacent to the first substrate portion along the first direction.

[0025] In some examples of the present invention, the control electrode pad of the second low-side inverter chip is disposed on the second low-side inverter chip more closely adjacent to the low side along the second direction; the control electrode pad of the second low-side inverter chip is disposed on the second low-side inverter chip more closely adjacent to the side of the second low-side inverter chip away from the first substrate portion along the first direction.

[0026] In some examples of the present invention, the second low-side inverter chip has a control electrode channel, the second load electrode pad of the second low-side inverter chip includes two sub-load electrode pads, the control electrode channel is disposed between the two sub-load electrode pads, and the control electrode channel of the second low-side inverter chip extends along the first direction.

[0027] In some embodiments of the present invention, the substrate includes a first sub-substrate and a second sub-substrate arranged sequentially at intervals along the first direction, wherein the first substrate is disposed on the first sub-substrate and the second substrate is disposed on the second sub-substrate.

[0028] In some examples of the present invention, the substrate further has a third substrate portion, which is disposed on the side of the first substrate portion away from the second substrate portion in a first direction, and the third substrate portion is provided with a brake unit upper core area and a rectifier unit upper core area.

[0029] In some examples of the present invention, the substrate includes a third sub-substrate, which is spaced apart from the first sub-substrate on a side away from the second sub-substrate in a first direction, and the third substrate portion is disposed on the third sub-substrate.

[0030] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0032] Figure 1 It is a schematic diagram based on a semiconductor module in the prior art;

[0033] Figure 2 This is a schematic diagram of a semiconductor module according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of a semiconductor module from another perspective according to an embodiment of the present invention;

[0035] Figure 4 for Figure 3 Cross-sectional view in the GG direction;

[0036] Figure 5 This is a schematic diagram of a semiconductor module according to an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of a semiconductor module according to an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of the dimensions of a semiconductor module according to an embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram of the first substrate portion according to an embodiment of the present invention;

[0040] Figure 9 This is a schematic diagram showing the dimensions of the first substrate portion according to an embodiment of the present invention;

[0041] Figure 10 This is a schematic diagram of the second substrate portion according to an embodiment of the present invention;

[0042] Figure 11 This is a schematic diagram showing the dimensions of the second substrate portion according to an embodiment of the present invention;

[0043] Figure 12 This is a schematic diagram of the third substrate portion according to an embodiment of the present invention;

[0044] Figure 13 This is a schematic diagram showing the dimensions of the third substrate portion according to an embodiment of the present invention;

[0045] Figure 14 This is a schematic diagram of an inverter chip according to an embodiment of the present invention.

[0046] Figure label:

[0047] 100. Semiconductor module; 10001. High-side; 10002. Low-side;

[0048] 1. Housing; 101. External terminal; 1011. First terminal; 1012. Second terminal; 1013. Third terminal; 1014. Fourth terminal; 1015. Fifth terminal; 1016. Sixth terminal; 1017. Seventh terminal; 1018. Eighth terminal; 1019. Ninth terminal; 10110. Tenth terminal; 10111. Eleventh terminal; 10112. Twelfth terminal; 10113. Thirteenth terminal; 10114. Fourteenth terminal; 10115. Fifteenth terminal; 10116. Sixteenth terminal; 10117. Seventeenth terminal; 10118. Eighteenth terminal; 10119. Nineteenth terminal; 10120. Twentieth terminal; 10121. Twenty-first terminal; 10122. Twenty-second terminal; 10123. Twenty-third terminal; 102. Silicone gel; 103. Side wall portion; 104. Top wall portion;

[0049] 2. Substrate; 201. First sub-substrate; 2011. Third substrate section; 202. Second sub-substrate; 2021. First substrate section; 203. Third sub-substrate; 2031. Second substrate section;

[0050] 3. Brake chip upper core area; 301, brake chip; 3011, brake diode; 3012, brake transistor;

[0051] 4. Rectifier chip upper chip area; 401, rectifier chip; 4011, first rectifier diode; 4012, second rectifier diode;

[0052] 5. First high-side inverter chip upper chip area; 501. Avoidance gap;

[0053] 6. First low-side inverter chip upper area; 7. Second high-side inverter chip upper area; 8. Second low-side inverter chip upper area; 9. Third low-side inverter chip upper area;

[0054] 10. Inverter chip; 1001. Second load electrode pad; 10011. Sub-load electrode pad; 1002. Control electrode pad;

[0055] 11. First high-side inverter chip; 1101. First edge; 1102. Third edge; 1103. Fourth edge; 12. Second high-side inverter chip; 1201. Second edge; 1202. Fifth edge; 1203. Sixth edge; 1206. Spacing region; 13. Third high-side inverter chip; 14. First low-side inverter chip; 15. Second low-side inverter chip; 16. Third low-side inverter chip;

[0056] 17. First jumper area;

[0057] 18. Second jumper area; 19. Control electrode flow channel; 20. Third jumper area; 21. Fourth jumper area; 22. Fifth jumper area; 23. Conductive component;

[0058] 24. Fast recovery diode; 25. Insulated gate bipolar transistor. Detailed Implementation

[0059] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0060] The following is for reference. Figures 1-14 A semiconductor module 100 according to an embodiment of the present invention is described, the semiconductor module 100 including but not limited to PIM (Power Integrated Module).

[0061] Combination Figures 2-6 As shown, the semiconductor module 100 according to the present invention has a first direction and a second direction, and a high side 10001 and a low side 10002 disposed opposite to each other in the second direction, and may mainly include: a housing 1, a substrate 2 and a plurality of inverter chips 10.

[0062] The substrate 2 is disposed inside the housing 1. The substrate 2 has a first substrate portion 2021 and a second substrate portion 2031 arranged sequentially at intervals along a first direction. Multiple elements can be disposed on the first substrate portion 2021 and the second substrate portion 2031 respectively to form the basic structure of the semiconductor module 100.

[0063] The first substrate portion 2021 has a first high-side inverter chip upper region 5 and a first low-side inverter chip upper region 6 arranged at intervals along the second direction. The first high-side inverter chip upper region 5 is closer to the high side 10001 of the semiconductor module 100 than the first low-side inverter chip upper region 6, which facilitates the arrangement of high-voltage power chips on the high side 10001 of the first substrate portion 2021. The second substrate portion 2031 has a second high-side inverter chip upper region 7, a third low-side inverter chip upper region 9, and a second low-side inverter chip upper region 8 arranged at intervals along the second direction. The second high-side inverter chip upper region 7 is closer to the high side 10001 of the semiconductor module 100 than the second low-side inverter chip upper region 8, which facilitates the arrangement of high-voltage power chips on the high side 10001 of the second substrate portion 2031. It should be noted that the first direction and the second direction are approximately perpendicular to each other, or the first direction and the second direction are perpendicular to each other.

[0064] In embodiments of the present invention, the first high-side inverter chip upper region 5, the second high-side inverter chip upper region 7, the first low-side inverter chip upper region 6, the second low-side inverter chip upper region 8, and the third low-side inverter chip upper region 9 can all be used to arrange power chips in the semiconductor module 100.

[0065] The semiconductor module 100 includes multiple inverter chips 10, each being a single chip. Each inverter chip 10 has a control electrode pad 1002, a first load electrode pad, and a second load electrode pad 1001. By applying a driving voltage to the control electrode pad 1002 and the second load electrode pad 1001, the connection and disconnection between the first load electrode pad and the second load electrode pad 1001 are controlled. For example, the inverter chip 10 is a reverse-conducting insulated-gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor, etc.

[0066] When the inverter chip 10 is a reverse-conducting insulated-gate bipolar transistor, the first load electrode pad is the collector pad, the second load electrode pad 1001 is the emitter pad, and the control electrode pad 1002 is the gate pad.

[0067] When the inverter chip 10 is a metal-oxide-semiconductor field-effect transistor, the first load electrode pad is the drain pad, the second load electrode pad 1001 is the source pad, and the control electrode pad 1002 is the gate pad.

[0068] In existing technologies, combined with Figure 1 As shown, each inverter chip 10 in the semiconductor module 100 includes an insulated-gate bipolar transistor 25 and a fast recovery diode 24. For example, when arranging the inverter chip 10 on the substrate 2, at least one insulated-gate bipolar transistor 25 and one fast recovery diode 24 need to be arranged, so the number of chips in the prior art semiconductor module 100 is relatively large.

[0069] In the embodiments of this application, the inverter chip 10 can integrate the insulated gate bipolar transistor 25 and the fast recovery diode 24 on a single chip. This reduces the number of chips in the semiconductor module 100 of this application. By integrating chip functions, the number of conductive components 23 can be reduced, thereby not only improving manufacturing efficiency but also reducing inductance, thus improving the performance of the semiconductor module 100.

[0070] It should be noted that in some embodiments of the present invention, the conductive element 23 may be an electrical connecting wire or an electrical connecting piece, etc.

[0071] The multiple inverter chips 10 include a first high-side inverter chip 11, a second high-side inverter chip 12, a third high-side inverter chip 13, a first low-side inverter chip 14, a second low-side inverter chip 15, and a third low-side inverter chip 16.

[0072] Furthermore, the first high-side inverter chip 11 and the second high-side inverter chip 12 are disposed on the upper core region 5 of the first high-side inverter chip and are spaced apart along the first direction. In the embodiment of the present invention, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged in the first direction of the upper core region 5 of the first high-side inverter chip, mainly occupying the arrangement size of the upper core region 5 of the first high-side inverter chip in the first direction. The spaced arrangement of the first high-side inverter chip 11 and the second high-side inverter chip 12 not only ensures that the first high-side inverter chip 11 and the second high-side inverter chip 12 are independent of each other, but also facilitates the heat dissipation of the first high-side inverter chip 11 and the second high-side inverter chip 12. It can prevent the first high-side inverter chip 11 and the second high-side inverter chip 12 from accumulating heat due to being too close together. This can prevent the first high-side inverter chip 11 and the second high-side inverter chip 12 from overheating and failing, which is beneficial to ensuring the reliability of the first high-side inverter chip 11 and the second high-side inverter chip 12.

[0073] In addition, the first high-side inverter chip 11 is further away from the second substrate portion 2031 in the first direction than the second high-side inverter chip 12. This facilitates the arrangement of the first high-side inverter chip 11 and the second high-side inverter chip 12 on the first substrate portion 2021 and facilitates the connection of the first high-side inverter chip 11 and the second high-side inverter chip 12 with other structures in the semiconductor module 100.

[0074] The third high-side inverter chip 13 is located on the upper core area 7 of the second high-side inverter chip, which can keep the third high-side inverter chip 13 away from the first high-side inverter chip 11 and the second high-side inverter chip 12, so as to prevent the three inverter chips 10 from being too close to each other and causing thermal failure of the device or the substrate 2.

[0075] The first low-side inverter chip 14 is disposed on the upper core area 6 of the first low-side inverter chip, the second low-side inverter chip 15 is disposed on the upper core area 8 of the second low-side inverter chip, and the third low-side inverter chip 16 is disposed on the upper core area 9 of the third low-side inverter chip. Therefore, the first high-side inverter chip 11, the second high-side inverter chip 12, the third high-side inverter chip 13, the third low-side inverter chip 16, the second low-side inverter chip 15, and the third low-side inverter chip 16 in the semiconductor module 100 can all be arranged separately to form the basic structure of the semiconductor module 100, ensuring the normal operation of the semiconductor module 100.

[0076] In some embodiments of the present invention, combined with Figures 2-6 As shown, the first high-side inverter chip 11 and the second high-side inverter chip 12 are disposed on the upper core area 5 of the first high-side inverter chip, closer to the high-side 10001 along the second direction. The upper core area 5 of the first high-side inverter chip is provided with a clearance notch 501, and a first jumper area 17 extending along the second direction is provided in the clearance notch 501. The first jumper area 17 is spaced apart from the upper core area 5 of the first high-side inverter chip, and at least a portion of the first jumper area 17 is located between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction. The edge of the first high-side inverter chip 11 adjacent to the second high-side inverter chip 12 in the first direction is defined as... The first edge 1101, the edge of the second high-side inverter chip 12 adjacent to the first high-side inverter chip 11 in the first direction is set as the second edge 1201, the edge of the first high-side inverter chip 11 adjacent to the low side 10002 in the second direction is set as the third edge 1102, the edge of the first high-side inverter chip 11 adjacent to the high side 10001 in the second direction is set as the fourth edge 1103, the edge of the second high-side inverter chip 12 adjacent to the low side 10002 in the second direction is set as the fifth edge 1202, and the edge of the second high-side inverter chip 12 adjacent to the high side 10001 in the second direction is set as the sixth edge 1203.

[0077] The lower edge is defined as the one closer to the lower side 10002 between the third edge 1102 and the fifth edge 1202. The higher edge is defined as the one closer to the higher side 10001 between the fourth edge 1103 and the sixth edge 1203. The area enclosed by the extension lines of the first edge 1101, the second edge 1201, the higher edge, and the lower edge is defined as the interval area 1206. The portion of the interval area 1206 corresponding to the clearance notch 501 is only provided with the first jumper area 17. The second load electrode pad 1001 of the first high-side inverter chip 11 is connected to the first jumper area 17 by a conductive element 23. The control electrode pad 1002 of the first high-side inverter chip 11 is provided on the first high-side inverter chip 11 along the second direction closer to the higher side 10001. The control electrode pad 1002 of the first high-side inverter chip 11 is electrically connected to the external terminal 101.

[0078] In existing technologies, combined with Figure 1As shown, the first high-side inverter chip 11 and the second high-side inverter chip 12 are each composed of at least one insulated-gate bipolar transistor (IGBT) 25 and one fast recovery diode 24. When the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged on the first substrate portion 2021, the fast recovery diode 24 and the IGBT 25 constituting the first high-side inverter chip 11 are spaced apart in the second direction, and the fast recovery diode 24 constituting the first high-side inverter chip 11 is closer to the high side 10001, and the IGBT 25 is closer to the low side 10002. The first jumper region 17, which connects to the second load electrode pad 1001 of the insulated-gate bipolar transistor 25, is located between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction. To ensure a stable connection between the second load electrode pad 1001 of the insulated-gate bipolar transistor 25 constituting the first high-side inverter chip 11 and the first jumper region 17, the control electrode flow channel 19 between the two sub-load electrode pads 10011 of the second load electrode pad 1001 constituting the first high-side inverter chip 11 needs to extend in the first direction. In this case, the structure... The control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is located on the side of the insulated gate bipolar transistor 25 that is closer to the low side 10002 in the second direction, and the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 is located on the side of the insulated gate bipolar transistor 25 that is closer to the second substrate portion 2031 in the first direction. At this time, in order to avoid the conductive member 23 between the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11 and the external terminal 101 being too long, the prior art needs to set a first The second jumper region 18 is electrically connected to the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11. Due to the positional limitation of the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11, the second jumper region 18 can only be located between the first high-side inverter chip 11 and the second high-side inverter chip 12. This ensures a stable connection between the second jumper region 18 and the conductive element 23 between the second jumper region 18 and the control electrode pad 1002 of the insulated gate bipolar transistor 25 constituting the first high-side inverter chip 11, and prevents intersection with other conductive elements 23.

[0079] The existing technology, by setting the gap 501 between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction, results in a larger size in order to accommodate the first jumper area 17 and the second jumper area 18. In other words, in the existing technology, the portion of the first high-side inverter chip 11 and the second high-side inverter chip 12 located in the upper core area 5 of the first high-side inverter chip has a smaller size in the first direction. Both the first high-side inverter chip 11 and the second high-side inverter chip 12 are composed of at least one insulated gate bipolar transistor 25 and one fast recovery diode 24. When the insulated gate bipolar transistor 25 and the fast recovery diode 24 are spaced apart in the second direction, the chip placement area requirement can be met. However, when the first high-side inverter chip 11 and the second high-side inverter chip 12 are single chips and have a large volume, the layout of the first substrate portion 2021 in the existing technology cannot meet the placement area requirements of the first high-side inverter chip 11 and the second high-side inverter chip 12.

[0080] In an embodiment of the present invention, a conductive element 23 is connected between the second load electrode pad 1001 of the first high-side inverter chip 11 and the first jumper area 17. The control electrode pad 1002 of the first high-side inverter chip 11 is disposed on the first high-side inverter chip 11 closer to the high side 10001 along the second direction. The control electrode pad 1002 of the first high-side inverter chip 11 is electrically connected to the external terminal 101. It should be noted that the control electrode pad 1002 of the first high-side inverter chip 11 and the external terminal 101 can be directly electrically connected; or a jumper pad can be provided so that the control electrode pad 1002 of the first high-side inverter chip 11 and the jumper pad are electrically connected through a conductive element, and then the jumper pad is electrically connected to the external terminal through a conductive element.

[0081] When the control electrode pad 1002 of the first high-side inverter chip 11 can be directly electrically connected to the external terminal 101, since both the first high-side inverter chip 11 and the second high-side inverter chip 12 are single chips, and the control electrode pad 1002 of the first high-side inverter chip 11 is disposed closer to the high side 10001 along the second direction on the first high-side inverter chip 11, the electrical connection path between the control electrode pad 1002 of the first high-side inverter chip 11 and the external terminal 101 can be shorter.

[0082] Further, the edge of the first high-side inverter chip 11 adjacent to the second high-side inverter chip 12 in the first direction is defined as the first edge 1101; the edge of the second high-side inverter chip 12 adjacent to the first high-side inverter chip 11 in the first direction is defined as the second edge 1201; the edge of the first high-side inverter chip 11 adjacent to the low side 10002 in the second direction is defined as the third edge 1102; the edge of the first high-side inverter chip 11 adjacent to the high side 10001 in the second direction is defined as the fourth edge 1103; and the edge of the second high-side inverter chip 12 adjacent to the low side 10002 in the second direction is defined as the fifth edge 1202. The edge of the second high-side inverter chip 12 adjacent to the high side 10001 in the second direction is designated as the sixth edge 1203. The edge closer to the low side 10002 between the third edge 1102 and the fifth edge 1202 is designated as the low side edge. The edge closer to the high side 10001 between the fourth edge 1103 and the sixth edge 1203 is designated as the high side edge. The area enclosed by the extension lines of the first edge 1101, the second edge 1201, the high side edge, and the low side edge is designated as the interval region 1206. The portion of the interval region 1206 corresponding to the clearance gap 501 is only provided with the first jumper area 17.

[0083] With this configuration, the portion of the clearance notch 501 between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction will only contain the first jumper area 17 for the second load electrode pad 1001 of the first high-side inverter chip 11 to be jumpered. There will be no other jumper areas between the clearance notch 501 and the second high-side inverter chip 11 in the first direction. This allows the portion of the clearance notch 501 between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction to be used only to accommodate the first jumper area 17. This makes the size of the portion of the clearance notch 501 between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction smaller, thereby making the area of ​​the first substrate portion 2021 corresponding to both sides of the clearance notch 501 in the first direction larger, which can increase the effective area of ​​the first high-side inverter chip 11 and the second high-side inverter chip 12.

[0084] Combination Figures 2-6As shown, a second jumper area 18 is also provided on the first substrate portion 2021. It should be noted that the second jumper area 18 is the jumper pad mentioned above. The second jumper area 18 is provided in the clearance notch 501. The second jumper area 18 is spaced apart on the side of the fourth edge 1103 facing the high side 10001 in the second direction. The second jumper area 18 is located on the side of the first jumper area 17 away from the second substrate portion 2031 in the first direction. A conductive element 23 is connected between the control electrode pad 1002 of the first high-side inverter chip 11 and the second jumper area 18. A conductive element 23 is connected between the second jumper area 18 and the external terminal 101.

[0085] By setting the second jumper area 18, a conductive element 23 is connected between the control electrode pad 1002 of the first high-side inverter chip 11 and the second jumper area 18, and a conductive element 23 is also connected between the second jumper area 18 and the external terminal 101. This allows the conductive element 23 between the control electrode pad 1002 of the first high-side inverter chip 11 and the second jumper area 18 to be shorter, and the conductive element 23 connecting the second jumper area 18 and the external terminal 101 to be shorter as well. This prevents the use of a longer conductive element 23 when the control electrode pad 1002 of the first high-side inverter chip 11 is electrically connected to the external terminal 101, thereby improving the switching stability of the control electrode pad 1002 of the first high-side inverter chip 11. In addition, the setting of the second jumper area 18 does not occupy the space of the avoidance notch 501 corresponding to the portion between the first high-side inverter chip 11 and the second high-side inverter chip 12, thus increasing the effective area on the first substrate for setting the first high-side inverter chip and the second high-side inverter chip.

[0086] In an embodiment of the present invention, the fourth terminal 1014 corresponds to the first substrate portion 2021 and is disposed on the side of the first substrate portion 2021 near the high side 10001. The fourth terminal 1014 is disposed in the first direction on the side closer to the second high-side inverter chip 12 than the second jumper area 18, thus ensuring that the second jumper area 18 is disposed between the control electrode pad 1002 of the first high-side inverter chip 11 and the fourth terminal 1014.

[0087] This configuration allows the second jumper area 18 to be positioned closer to the first high-side inverter chip 11, shortening the distance between the second jumper area 18 and the control electrode pad 1002 on the first high-side inverter chip 11. This helps to shorten the length of the conductive element 23 between the control electrode pad 1002 on the first high-side inverter chip 11 and the second jumper area 18, as well as the length of the conductive element 23 between the second jumper area 18 and the fourth terminal 1014. This prevents the excessive length of the conductive element 23 from affecting the switching speed and stability of the first high-side inverter chip 11. On the other hand, it reduces the structural gap between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction, thereby increasing the effective area on the core region 5 of the first high-side inverter chip where the inverter chip 10 can be arranged.

[0088] Combination Figures 2-7 As shown, the first high-side inverter chip 11 and the second high-side inverter chip 12 are arranged opposite each other in the first direction, and the projections of the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction overlap each other. This arrangement not only facilitates the arrangement of the first high-side inverter chip 11 and the second high-side inverter chip 12, but also allows the first high-side inverter chip 11 and the second high-side inverter chip 12 to be far away from the first low-side inverter chip 14, which can improve the heat dissipation performance of the semiconductor device 100.

[0089] Combination Figures 5-7 As shown, the portion of the first jumper area 17 located between the first high-side inverter chip 11 and the second high-side inverter chip 12 has a dimension of L1 in the first direction, and L1 satisfies the relationship: 1.7mm≤L1≤3.2mm.

[0090] In some embodiments of this application, the portion of the first jumper region 17 located between the first high-side inverter chip 11 and the second high-side inverter chip 12 has a dimension of L1 in the first direction, where L1 ≤ 3.2 mm.

[0091] The portion of the first jumper area 17 located between the first high-side inverter chip 11 and the second high-side inverter chip 12 cannot be too large in the first direction. An excessively large size would cause the first jumper area 17 to occupy too much space in the first direction of the first substrate portion 2021, hindering the placement of larger inverter chips 10. To increase the effective area on the upper core region 5 of the first high-side inverter chip that can accommodate the inverter chip 10, the dimension L1 of the portion of the first jumper area 17 located between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction is set to not exceed 3.2 mm. For example, L1 can be 3.2 mm, 3.1 mm, 3.0 mm, 2.9 mm, and 2.8 mm, etc. A suitable and specific parameter should be selected during the specific design process.

[0092] In some embodiments of this application, the portion of the first jumper region 17 located between the first high-side inverter chip 11 and the second high-side inverter chip 12 has a dimension of L1 in the first direction, where L1 ≥ 1.7 mm.

[0093] The portion of the first jumper area 17 located between the first high-side inverter chip 11 and the second high-side inverter chip 12 must not be too small in the first direction; otherwise, proper wiring will be impossible in the first jumper area 17. To ensure proper wiring in the first jumper area 17, the dimension L1 of the portion of the first jumper area 17 located between the first high-side inverter chip 11 and the second high-side inverter chip 12 in the first direction must be no less than 1.7 mm. For example, L1 can be 1.7 mm, 1.8 mm, 1.9 mm, or 2.0 mm, etc. A suitable and specific parameter should be selected during the design process.

[0094] By setting L1 between 1.7mm and 3.2mm, not only can the effective area for setting the first high-side inverter chip 11 and the second high-side inverter chip 12 on the upper core area 5 of the first high-side inverter chip be large, but it can also ensure that the first jumper area 17 can be wired normally. A reasonable balance can be achieved between the normal arrangement of chips and the normal wire bonding of the first jumper area 17, thus ensuring the performance of the semiconductor module 100.

[0095] Combination Figures 5-7 As shown, the first substrate portion 2021 has a dimension of A in the second direction, and the distance between the edge of the first high-side inverter chip 11 facing the high side 10001 and the edge of the first substrate portion 2021 facing the high side 10001 is B. A and B satisfy the relationship: 0.086A≤B≤0.117A.

[0096] In some specific embodiments of this application, the B / A ratio does not exceed 0.117. For example, the B / A ratio can be 0.117, 0.116, or 0.115. If the B / A ratio is too large, the first high-side inverter chip 11 will be positioned further away from the high-side 10001 on the first substrate portion 2021. This will not only make the distance between the control electrode pad 1002 on the first high-side inverter chip 11 and the external terminal 101 and the second jumper area 18 too large, resulting in the conductive element 23 between the control electrode pad 1002 and the external terminal 101 being too long, or the conductive element 23 between the control electrode pad 1002 and the second jumper area 18 being too long, affecting the switching stability of the first high-side inverter chip 11, but also make the distance between the first high-side inverter chip 11 and the first low-side inverter chip 14 too close, which is not conducive to the heat dissipation of the first high-side inverter chip 11. To ensure the heat dissipation of the first high-side inverter chip 11 and the stability of the switching of the control electrode pad 1002 on the first high-side inverter chip 11, as well as to ensure the reliability of the semiconductor module 100, a suitable and specific parameter is selected during the design process.

[0097] In some specific embodiments of this application, the B / A ratio is not less than 0.086. For example, the B / A ratio can be 0.086, 0.087, or 0.088. It should be noted that if the B / A ratio is too small, the distance between the edge of the first high-side inverter chip 11 and the edge of the first substrate 2021 facing the high side 10001 will be too close. There will be no space on the first substrate 2021 to set the second jumper area 18. This will result in the conductive part 23 that directly connects the control electrode pad 1002 of the first high-side inverter chip 11 to the external terminal 101 being too long, and the switching stability of the control electrode pad 1002 of the first high-side inverter chip 11 will be poor. In order to ensure the switching stability of the control electrode pad 1002 on the first high-side inverter chip 11 and to ensure the reliability of the semiconductor module 100, a suitable specific parameter should be selected in the specific design.

[0098] Combination Figures 5-7 As shown, the first substrate 2021 has a dimension of A in the second direction, and the distance between the edge of the second high-side inverter chip 12 facing the high side 10001 and the edge of the first substrate 2021 facing the high side 10001 is C. A and C satisfy the relationship: 0.086A≤C≤0.117A.

[0099] In some specific embodiments of this application, C / A does not exceed 0.117. For example, C / A can be 0.117, 0.116, or 0.115. If C / A is too large, the second high-side inverter chip 12 will be arranged further away from the high side 10001 in the second direction of the first substrate portion 2021. This will not only make the length of the conductive part 23 between the control electrode pad 1002 on the second high-side inverter chip 12 and the external terminal 101 too large, affecting the switching stability of the second high-side inverter chip 12, but also make the distance between the second high-side inverter chip 12 and the first low-side inverter chip 14 too close, which is not conducive to the heat dissipation of the second high-side inverter chip 12. In order to ensure the heat dissipation of the second high-side inverter chip 12 and the switching stability of the control electrode pad 1002 on the second high-side inverter chip 12, as well as to ensure the reliability of the semiconductor module 100, a suitable specific parameter is selected in the specific design.

[0100] In some specific embodiments of this application, the C / A ratio is not less than 0.086. For example, the sixth parameter value can be 0.086, 0.087, or 0.088. If the C / A ratio is too small, the distance between the second high-side inverter chip 12 and the edge of the first substrate 2021 facing the high side 10001 will be too close, and there will be no space on the first substrate 2021 to provide the fourth jumper area 21. This will result in the length of the conductive element 23 between the first jumper area 17 and the external terminal 101 being too large, affecting the working stability of the second load electrode pad 1001 of the first high-side inverter chip 11.

[0101] Combination Figures 5-6 As shown, the control electrode pad 1002 of the first high-side inverter chip 11 is disposed on the side of the first high-side inverter chip 11 that is closer to the second substrate portion 2031 along the first direction.

[0102] It should be noted that in the embodiments of the present invention, all inverter chips 10 are chips with the same structure. This facilitates installation and prevents incorrect chip placement, ensuring chip consistency. Furthermore, during installation, the positions of the control electrode pad 1002, the first load electrode pad, and the second load electrode pad 1001 on the substrate 2 can be adjusted by rotating the inverter chip 10. Specifically, the control electrode pad 1002 on the first high-side inverter chip 11 is located on the side of the first high-side inverter chip 11 that is further away from the first high-side inverter chip 11 along the first direction and closer to the second substrate portion 2031. This can further shorten the length of the conductive element 23 between the control electrode pad 1002 on the first high-side inverter chip 11 and the second jumper area 18, or further shorten the length of the conductive element 23 between the control electrode pad 1002 on the first high-side inverter chip 11 and the external terminal 101, while ensuring chip consistency.

[0103] Combination Figure 1 , Figure 5 , Figure 6 and Figure 7 As shown, compared to the prior art, in the embodiment of the present invention, after rotating the first high-side inverter chip 11 by a certain angle, the control electrode pad 1002 on the first high-side inverter chip 11 can be disposed closer to the side of the first high-side inverter chip 11 away from the second substrate portion 2031 along the first direction. Thus, after adjusting the position of the second jumper area 18, the control electrode pad 1002 on the first high-side inverter chip 11 can be disposed closer to the second jumper area 18.

[0104] It is understood that, in the embodiments of the present invention, the second jumper area 18 is located between the control electrode pad 1002 on the first high-side inverter chip 11 and the fourth terminal 1014 on the housing 1. This can shorten the distance between the control electrode pad 1002, the second jumper area 18 and the fourth terminal 1014, thereby not only shortening the length of the conductive element 23 and preventing the conductive element 23 from becoming too long and deforming, but also reducing the temperature at both ends of the conductive element 23 through the heat dissipation of the second jumper area 18, so as to improve its current carrying capacity.

[0105] Combination Figure 6 , Figure 8 and Figure 14As shown, the first high-side inverter chip 11 has a control electrode channel 19, and the second load electrode pad 1001 of the first high-side inverter chip 11 includes two sub-load electrode pads 10011. The control electrode channel 19 is disposed between the two sub-load electrode pads 10011 and extends along a first direction.

[0106] Specifically, the first high-side inverter chip 11 can be a reverse-conducting insulated-gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor. The first high-side inverter chip 11 has a control electrode channel 19 extending along a first direction. In both the reverse-conducting insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor, the bonding wires on the second load electrode pad 1001 need to be parallel to the control electrode channel 19.

[0107] In this embodiment of the invention, the second load electrode pad 1001 on the first high-side inverter chip 11 includes two sub-load electrode pads 10011, and the two sub-load electrode pads 10011 form a control electrode flow channel 19 to ensure the structural reliability of the first high-side inverter chip 11.

[0108] Combination Figure 6 and Figure 8 As shown, the first jumper area 17 is located in the middle of the upper core area 5 of the first high-side inverter chip in the first direction. This can increase the setting area of ​​the first high-side inverter chip 11 and the second high-side inverter chip 12 on the upper core area 5 of the first high-side inverter chip, making the setting area of ​​the first high-side inverter chip 11 and the second high-side inverter chip 12 on the upper core area 5 more balanced and reasonable. This can prevent one of the first high-side inverter chip 11 and the second high-side inverter chip 12 from having a larger setting area and the other smaller, which would cause one of the first high-side inverter chip 11 and the second high-side inverter chip 12 to be unable to be properly set on the first substrate 2021. This can further optimize the structural layout of the first substrate 2021.

[0109] Combination Figure 6 and Figure 8 As shown, a third jumper area 20 is also provided on the first substrate portion 2021. The third jumper area 20 is connected to one end of the first jumper area 17 adjacent to the upper core area 6 of the first low-side inverter chip. The third jumper area 20 extends from the first jumper area 17 in a first direction toward a direction away from the second substrate portion 2031. A conductive element 23 is connected between the third jumper area 20 and the upper core area 6 of the first low-side inverter chip.

[0110] Specifically, the third jumper area 20 is connected to the first jumper area 17, enabling electrical connection between them. The third jumper area 20 is located at the end of the first jumper area 17 adjacent to the upper core area 6 of the first low-side inverter chip. This allows the third jumper area 20 to be positioned close to the upper core area 6 of the first low-side inverter chip, facilitating wire bonding between the third jumper area 20 and the structure on the upper core area 6 of the first low-side inverter chip.

[0111] The third jumper area 20 extends in the first direction, which increases the area of ​​the third jumper area 20 and facilitates wire bonding on the third jumper area 20. In addition, the extension direction of the third jumper area 20 extends from the first jumper area 17 in a direction away from the second substrate portion 2031. This shortens the distance between the third jumper area 20 and the upper core area 6 of the first low-side inverter chip. A conductive element 23 connects the third jumper area 20 and the upper core area 6 of the first low-side inverter chip. This arrangement helps to shorten the length of the conductive element 23 between the upper core area 6 of the first low-side inverter chip and the third jumper area 20, and can avoid deformation of the conductive element 23 due to excessive length, so as to ensure the structural reliability of the conductive element 23.

[0112] Combination Figure 2 As shown, the first low-side inverter chip 14 is disposed on the upper core area 6 of the first low-side inverter chip, which is closer to the second substrate portion 2031 along the first direction. A conductive element 23 is connected between the side of the upper core area 6 of the first low-side inverter chip that is away from the second substrate portion 2031 in the first direction and the third jumper area 20.

[0113] Specifically, the bonding positions of the first low-side inverter chip 14 and the upper core area 6 of the first low-side inverter chip are respectively spaced apart in the first direction of the upper core area 6 of the first low-side inverter chip. This can prevent the bonding positions of the conductive element 23 on the upper core area 6 of the first low-side inverter chip from encroaching on the arrangement position of the first low-side inverter chip 14 in the second direction of the upper core area 6 of the first low-side inverter chip. This is beneficial to increase the effective area of ​​the first low-side inverter chip 14 on the first substrate portion 2021, and to arrange a larger size first low-side inverter chip 14 in the first substrate portion 2021, thereby improving the current carrying capacity of the semiconductor module 100 of the present invention.

[0114] Furthermore, this also allows for minimizing the length of the conductive element 23 between the control electrode pad 1002 of the first low-side inverter chip 14 and the external terminal 101, while ensuring the structural consistency of multiple inverter chips 10. This further improves the switching stability of the control electrode pad 1002 of the first low-side inverter chip 14.

[0115] Combination Figure 6As shown, a fourth jumper area 21 is also provided on the first substrate portion 2021. The fourth jumper area 21 is connected to the end of the first jumper area 17 that is away from the upper core area 6 of the first low-side inverter chip, so that the fourth jumper area 21 can be electrically connected to the first jumper area 17. The fourth jumper area 21 extends from the first jumper area 17 in a first direction toward the second substrate portion 2031. This not only increases the area of ​​the fourth jumper area 21 and facilitates wire bonding on the fourth jumper area 21, but also allows the fourth jumper area 21 to avoid the arrangement of the second jumper area 18.

[0116] In embodiments of the present invention, combined with Figure 5 and Figure 6 As shown, the fifth terminal 1015 is located on the side of the fourth jumper area 21 facing the second substrate portion 2031 in the first direction, and a conductive element 23 is connected between the fifth terminal 1015 and the fourth jumper area 21. This arrangement allows the fifth terminal 1015 to avoid the fourth terminal 1014 while ensuring a reliable connection between the conductive element 23 and the fourth jumper area 21. This facilitates shortening the conductive element 23 between the control electrode pad 1002 on the first high-side inverter chip 11 and the second jumper area 18, and also facilitates shortening the conductive element 23 between the second jumper area 18 and the fourth terminal 1014.

[0117] According to an embodiment of the present invention, in combination Figure 9 As shown, the first high-side inverter chip upper chip area 5 includes dimensions L2, L3, L4, L5, and L6, where L2 is 20.8 mm, L3 is 22.4 mm, L5 is 7.7 mm, and L6 is 2.1 mm. The second jumper area 18 includes dimensions L7 and L8, where L7 is 2.2 mm and L8 is 1.6 mm. The fourth jumper area 21 includes dimensions L9 and L12, where L9 is [missing value] and L12 is 1.6 mm. The third jumper area 20 includes dimensions L10 and L11, where L10 is 6.34 mm and L11 is 2.1 mm. The first low-side inverter chip upper chip area 6 includes dimensions L13 and L14, where L13 is 17.4 mm and L14 is 8.4 mm.

[0118] Combination Figure 5 , Figure 6 and Figure 10As shown, the third high-side inverter chip 13 is located in the middle of the second substrate portion 2031 in the first direction. This arrangement makes the distances between the two sides of the third high-side inverter chip 13 in the first direction and the two sides of the second substrate portion 2031 in the first direction similar. This arrangement allows the heat from both sides of the third high-side inverter chip 13 in the first direction to be transferred to the edge of the second substrate portion 2031 simultaneously. This ensures that the heat dissipation efficiency of both sides of the third high-side inverter chip 13 in the first direction is the same, thereby guaranteeing the heat dissipation effect of both sides of the third high-side inverter chip 13 in the first direction. This solves the problem of heat accumulation caused by low heat dissipation efficiency on one side of the third high-side inverter chip 13 in the first direction, and thus helps to improve the heat dissipation performance of the third high-side inverter chip 13.

[0119] Combination Figure 5 , Figure 6 and Figure 10 As shown, the control electrode pad 1002 of the third high-side inverter chip 13 is disposed on the third high-side inverter chip 13 closer to the high side 10001 along the second direction; the control electrode pad 1002 of the third high-side inverter chip 13 is disposed on the third high-side inverter chip 13 closer to the first substrate portion 2021 along the first direction.

[0120] Specifically, the third high-side inverter chip 13 is a high-side power chip in the semiconductor module 100. Its control electrode pad 1002 is disposed close to the high side 10001 of the semiconductor module 100 in the second direction and adjacent to the first substrate portion 2021 in the first direction. A conductive element 23 is provided between the eighth terminal 1018 on the housing 1 and the control electrode pad 1002 of the third high-side inverter chip 13. The eighth terminal 1018 is located on the side of the third high-side inverter chip 13 away from the first substrate portion 2021 in the first direction. This can prevent the conductive element 23 between the control electrode pad 1002 and the eighth terminal 1018 on the third high-side inverter chip 13 from becoming too long and deformed, and can ensure the reliability of the conductive element 23 between the control electrode pad 1002 and the eighth terminal 1018 on the third high-side inverter chip 13.

[0121] Combination Figure 5 , Figure 6 , Figure 10 and Figure 14 As shown, the third high-side inverter chip 13 has a control electrode channel 19. The second load electrode pad 1001 of the third high-side inverter chip 13 includes two sub-load electrode pads 10011. The control electrode channel 19 is disposed between the two sub-load electrode pads 10011. The control electrode channel 19 of the third high-side inverter chip 13 extends along a first direction.

[0122] Specifically, the third high-side inverter chip 13 can be a reverse-conducting insulated-gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor, etc. The third high-side inverter chip 13 is provided with a control electrode channel 19, which extends in a first direction. In the reverse-conducting insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor, the bonding wires on the second load electrode pad 1001 need to be parallel to the control electrode channel 19.

[0123] In this embodiment of the invention, the second load electrode pad 1001 on the third high-side inverter chip 13 includes two sub-load electrode pads 10011, and the two sub-load electrode pads 10011 form a control electrode flow channel 19 to ensure the structural reliability of the third high-side inverter chip 13.

[0124] Combination Figure 5 , Figure 6 and Figure 10 As shown, a fifth jumper area 22 is also provided on the second substrate portion 2031. The fifth jumper area 22 is located in the first direction on the side of the upper core area 7 of the second high-side inverter chip away from the first substrate portion 2021. In this way, the fifth jumper area 22 can be provided between the third high-side inverter chip 13 and the eighth terminal 1018. A conductive element 23 is connected between the control electrode pad 1002 of the third high-side inverter chip 13 and the fifth jumper area 22.

[0125] Specifically, when the third high-side inverter chip 13 is wired to the eighth terminal 1018, a conductive element 23 is provided between the third high-side inverter chip 13 and the fifth jumper area 22, and a conductive element 23 is provided between the fifth jumper area 22 and the eighth terminal 1018. In this way, on the one hand, the third high-side inverter chip 13 and the eighth terminal 1018 can be connected, and on the other hand, by setting the fifth jumper area 22, the length of the conductive element 23 between the third high-side inverter chip 13 and the eighth terminal 1018 can be shortened. This can reduce the heat generation of the conductive element 23, thereby lowering the temperature at both ends of the conductive element 23 and improving the reliability of the semiconductor module 100.

[0126] Combination Figure 5 , Figure 6 and Figure 10As shown, the third low-side inverter chip 16 is located in the middle of the second substrate portion 2031 in the first direction. This arrangement makes the distances between the two sides of the third low-side inverter chip 16 in the first direction and the two sides of the second substrate portion 2031 in the first direction similar. This arrangement allows the heat from both sides of the third low-side inverter chip 16 in the first direction to be transferred to the edge of the second substrate portion 2031 simultaneously. This ensures that the heat dissipation efficiency of both sides of the third low-side inverter chip 16 in the first direction is the same, thereby guaranteeing the heat dissipation effect of both sides of the third low-side inverter chip 16 in the first direction. This solves the problem of heat accumulation caused by low heat dissipation efficiency on one side of the third low-side inverter chip 16 in the first direction, and thus helps to improve the heat dissipation performance of the third low-side inverter chip 16.

[0127] Furthermore, the second load electrode pad 1001 on the third low-side inverter chip 16 needs to be connected to the jumper area on the first substrate 2021 via a conductive element 23, and the control electrode pad 1002 on the third low-side inverter chip 16 needs to be connected to the jumper area on the portion of the second substrate 2031 away from the third low-side inverter chip 16 in the first direction via a conductive element 23. By positioning the third low-side inverter chip 16 in the middle of the second substrate 2031 in the first direction, the second load electrode on the third low-side inverter chip 16 can be connected to the jumper area in the first direction away from the third low-side inverter chip 16 via a conductive element 23. The conductive element 23 between the pad 1001 and the jumper area on the first substrate 2021 is not too long. This also ensures that the conductive element 23 between the control electrode pad 1002 on the third low-side inverter chip 16 and the jumper area on the portion of the second substrate 2031 away from the third low-side inverter chip 16 in the first direction is not too long. This prevents one of the two conductive elements 23 from being too long and affecting the performance of the third low-side inverter chip 16. This allows the lengths of the two conductive elements 23 to be reasonably balanced, thereby improving the performance of the third low-side inverter chip 16.

[0128] Combination Figure 5 , Figure 6 and Figure 10 As shown, the control electrode pad 1002 of the third low-side inverter chip 16 is disposed on the third low-side inverter chip 16 closer to the low side 10002 along the second direction; the control electrode pad 1002 of the third low-side inverter chip 16 is disposed on the side of the third low-side inverter chip 16 away from the first substrate portion 2021 along the first direction.

[0129] Specifically, the third low-side inverter chip 16 is a low-side power chip in the semiconductor module 100. Its control electrode pad 1002 is disposed close to the low side 10002 of the semiconductor module 100 in the second direction, and is disposed adjacent to the side of the third low-side inverter chip 16 away from the first substrate portion 2021 in the first direction. A conductive element 23 is provided between the twelfth terminal 10112 on the housing 1 and the control electrode pad 1002 of the third low-side inverter chip 16, and the twelfth terminal 10112 is located closer to the low side 10002 in the second direction of the semiconductor module 100. This allows the control electrode pad 1002 on the third low-side inverter chip 16 to be disposed close to the twelfth terminal 10112, which can prevent the conductive element 23 between the control electrode pad 1002 and the twelfth terminal 10112 on the third low-side inverter chip 16 from being too long and deformed, and can ensure the reliability of the conductive element 23 between the control electrode pad 1002 and the twelfth terminal 10112 on the third low-side inverter chip 16.

[0130] Combination Figure 5 , Figure 6 , Figure 10 and Figure 14 As shown, the third low-side inverter chip 16 has a control electrode channel 19. The second load electrode pad 1001 of the third low-side inverter chip 16 includes two sub-load electrode pads 10011. The control electrode channel 19 is disposed between the two sub-load electrode pads 10011. The control electrode channel 19 of the third low-side inverter chip 16 extends along a first direction.

[0131] Specifically, the third low-side inverter chip 16 can be a reverse-conducting insulated-gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor, etc. The third low-side inverter chip 16 has a control electrode channel 19 extending in a first direction. In the reverse-conducting insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor, the bonding wires on the second load electrode pad 1001 need to be parallel to the control electrode channel 19.

[0132] In this embodiment of the invention, the second load electrode pad 1001 on the third low-side inverter chip 16 includes two sub-load electrode pads 10011, and the two sub-load electrode pads 10011 form a control electrode flow channel 19 to ensure the structural reliability of the third low-side inverter chip 16.

[0133] In an embodiment of the present invention, a conductive element 23 is provided between the fourteenth terminal 10114 corresponding to the first substrate portion 2021 and the second load electrode pad 1001 on the third low-side inverter chip 16.

[0134] Combination Figures 2-7As shown, the second low-side inverter chip 15 is disposed on the second substrate portion 2031 closer to the first substrate portion 2021 along the first direction.

[0135] Specifically, this arrangement allows the second low-side inverter chip 15 and the third low-side inverter chip 16 to be staggered in the first direction. This configuration serves two purposes: firstly, it prevents the second low-side inverter chip 15 and the third low-side inverter chip 16 from being too close, which could lead to heat concentration in the semiconductor module 100 and reduce its reliability; secondly, since a conductive element 21 connects the second load electrode pad 1001 on the second low-side inverter chip 15 to the jumper area of ​​the first substrate portion 2021, placing the second low-side inverter chip 15 closer to the first substrate portion 2021 along the first direction allows the second low-side inverter chip... The conductive element between the second load electrode pad 1001 on the second low-side inverter chip 15 and the jumper area of ​​the first substrate portion 2021 is shorter, thereby reducing the internal inductance to suppress surge voltage between the first load electrode pad and the second load electrode pad 1001 on the second low-side inverter chip 15, and further improving the stability of the conductive element between the second load electrode pad 1001 on the second low-side inverter chip 15 and the jumper area of ​​the first substrate portion 2021, thereby improving the performance of the second load electrode pad 1001 on the second low-side inverter chip 15.

[0136] It should be noted that the jumper area on the first substrate 2021 that is electrically connected to the second load electrode pad 1001 on the second low-side inverter chip 15 needs to be electrically connected to an external terminal.

[0137] Combination Figure 5 , Figure 6 and Figure 10 As shown, the control electrode pad 1002 of the second low-side inverter chip 15 is disposed on the second low-side inverter chip 15 more closely adjacent to the low side 10002 along the second direction; the control electrode pad 1002 of the second low-side inverter chip 15 is disposed on the side of the second low-side inverter chip 15 away from the first substrate portion 2021 along the first direction.

[0138] Specifically, the second low-side inverter chip 15 is a low-side power chip in the semiconductor module 100. Its control electrode pad 1002 is disposed close to the low side 10002 of the semiconductor module 100 in the second direction, and is disposed adjacent to the side of the second low-side inverter chip 15 away from the first substrate portion 2021 in the first direction. A conductive element 23 is provided between the thirteenth terminal 10113 on the housing 1 and the control electrode pad 1002 of the second low-side inverter chip 15. The thirteenth terminal 10113 is disposed in a position closer to the low side 10002 in the second direction of the semiconductor module 100. This allows the control electrode pad 1002 on the second low-side inverter chip 15 to be disposed close to the thirteenth terminal 10113, which can prevent the conductive element 23 between the control electrode pad 1002 and the thirteenth terminal 10113 on the second low-side inverter chip 15 from being too long and deformed, and can ensure the reliability of the conductive element 23 between the control electrode pad 1002 and the thirteenth terminal 10113 on the second low-side inverter chip 15.

[0139] Combination Figure 5 , Figure 6 , Figure 10 and Figure 14 As shown, the second low-side inverter chip 15 has a control electrode channel 19, and the second load electrode pad 1001 of the second low-side inverter chip 15 includes two sub-load electrode pads 10011. The control electrode channel 19 is disposed between the two sub-load electrode pads 10011 and extends along a first direction.

[0140] Specifically, the second low-side inverter chip 15 can be a reverse-conducting insulated-gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor, etc. The second low-side inverter chip 15 has a control electrode channel 19 extending in a first direction. In the reverse-conducting insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor, the bonding wires on the second load electrode pad 1001 need to be parallel to the control electrode channel 19.

[0141] In this embodiment of the invention, the second load electrode pad 1001 on the second low-side inverter chip 15 includes two sub-load electrode pads 10011, and the two sub-load electrode pads 10011 form a control electrode flow channel 19 to ensure the structural reliability of the second low-side inverter chip 15.

[0142] According to an embodiment of the present invention, in combination Figure 11As shown, the second high-side inverter chip upper region 7 includes dimensions L15 and L16, where L15 is 11.9 mm and L16 is 9.44 mm. The third low-side inverter chip upper region 9 includes dimensions L17 and L18, where L17 is 14.4 mm and L18 is 8.66 mm. The second low-side inverter chip upper region 8 includes dimensions L19 and L20, where L19 is 13 mm and L20 is 8.5 mm. The fifth jumper region 22 includes dimensions L21 and L22, where L21 is 4.3 mm and L22 is 1.41 mm.

[0143] Combination Figure 5 , Figure 6 and Figure 12 As shown, the substrate 2 also has a third substrate portion 2011, which is disposed on the side of the first substrate portion 2021 away from the second substrate portion 2031 in a first direction. The third substrate portion 2011 is provided with a brake chip upper core area 3 and a rectifier chip upper core area 4.

[0144] Specifically, the third substrate 2011 is provided with a brake chip upper core region 3 and a rectifier chip upper core region 4. The brake chip upper core region 3 and the rectifier chip upper core region 4 are spaced apart from each other in a second direction. The brake chip upper core region 3 is provided with a brake chip 301, which includes a brake diode 3011 and a brake transistor 3012. The rectifier chip upper core region 4 is provided with a rectifier chip 401, which includes a first rectifier diode 4011 and a second rectifier diode 4012.

[0145] According to an embodiment of the present invention, in combination Figure 13 As shown, the upper core area 4 of the rectifier chip includes dimensions L23, L24, L25, L26, L27, L28, and L46, where L23 is 6.2mm, L24 is 6.2mm, L25 is 6.5mm, L26 is 12.6mm, L27 is 10.4mm, L28 is 11.8mm, and L46 is 20.2mm. The upper core area 3 of the brake chip includes dimensions L29 and L30, where L29 is 22.4mm and L30 is 6.1mm.

[0146] In embodiments of the present invention, combined with Figure 5 and Figure 6 As shown, the housing 1 has multiple regularly arranged external terminals 101 around its perimeter. The brake chip 301, rectifier chip 401 and inverter chip 10 are respectively connected to the corresponding external terminals 101. The external terminals 101 extend outward from the housing 1 in at least a portion.

[0147] Multiple external terminals 101 are defined as the first terminal 1011, the second terminal 1012, the third terminal 1013, the fourth terminal 1014, the fifth terminal 1015, the sixth terminal 1016, the seventh terminal 1017, the eighth terminal 1018, the ninth terminal 1019, the tenth terminal 10110, the eleventh terminal 10111, the twelfth terminal 10112, the thirteenth terminal 10113, the fourteenth terminal 10114, the fifteenth terminal 10115, the sixteenth terminal 10116, the seventeenth terminal 10117, the eighteenth terminal 10118, the nineteenth terminal 10119, the twentieth terminal 10120, the twenty-first terminal 10121, the twenty-second terminal 10122, and the twenty-third terminal 10123.

[0148] Among them, the first terminal 1011, the second terminal 1012, the third terminal 1013, the fourth terminal 1014, the fifth terminal 1015, the sixth terminal 1016, and the seventh terminal 1017 are located on one side of the housing 1 in the second direction and are arranged at intervals in the first direction. The eighth terminal 1018, the ninth terminal 1019, the tenth terminal 10110, and the eleventh terminal 10111 are located on one side of the housing 1 in the first direction and are arranged at intervals in the second direction. The twelfth terminal 10112, the thirteenth terminal 10113, the fourteenth terminal 10114, the fifteenth terminal 10115, the sixteenth terminal 10116, the seventeenth terminal 10117, the eighteenth terminal 10118, and the nineteenth terminal 10119 are located on the other side of the housing 1 in the second direction and are arranged at intervals in the first direction. The twentieth terminal 10120, the twenty-first terminal 10121, the twenty-second terminal 10122, and the twenty-third terminal 10123 are located on the other side of the housing 1 in the first direction and are arranged at intervals in the second direction.

[0149] Furthermore, the first terminal 1011, the second terminal 1012, the eighteenth terminal 10118, and the nineteenth terminal 10119 correspond to the third substrate portion 2011 in the second direction, the third terminal 1013, the fourth terminal 1014, the fifth terminal 1015, the fourteenth terminal 10114, the fifteenth terminal 10115, the sixteenth terminal 10116, and the seventeenth terminal 10117 correspond to the first substrate portion 2021 in the second direction, and the sixth terminal 1016, the seventh terminal 1017, the twelfth terminal 10112, and the thirteenth terminal 10113 correspond to the second substrate portion 2031 in the second direction.

[0150] In this way, the basic structure of the semiconductor module 100 can be formed, integrating the braking circuit, rectifier circuit and inverter circuit, simplifying the circuit layout and the construction of the heat dissipation system.

[0151] Combination Figure 4As shown, the housing 1 is obtained by molding encapsulation. The molding encapsulation can be formed by transfer molding, for example, using a thermoplastic material or a chemically cured material. The molding material can be epoxy resin. The housing 1 can be a plastic shell. The third substrate 2011, the first substrate 2021, the second substrate 2031, the brake chip 301, the rectifier chip 401, the inverter chip 10, and at least a portion of the external terminals 101 are all disposed within the housing 1. The housing 1 can also be filled with silicone gel 102. In this way, the housing 1 and the silicone gel 102 can provide physical and electrical protection for the third substrate 2011, the first substrate 2021, the second substrate 2031, the brake chip 301, the rectifier chip 401, the inverter chip 10, and at least a portion of the external terminals 101 to prevent structural damage caused by external environmental impact and ensure the normal operation of the semiconductor module 100.

[0152] Combination Figure 4 As shown, the substrate 2 includes a third sub-substrate 203, a first sub-substrate 201, and a second sub-substrate 202 arranged sequentially at intervals along a first direction. The first substrate portion 2021 is disposed on the first sub-substrate 201, the second substrate portion 2031 is disposed on the second sub-substrate 202, and the third substrate portion 2011 is disposed on the third sub-substrate 203.

[0153] Specifically, in the embodiments of the present invention, the substrate 2 is composed of a first sub-substrate 201, a second sub-substrate 202, and a third sub-substrate 203. The first sub-substrate 201 can provide a stable and reliable mounting position for the first substrate portion 2021 to ensure the positional reliability of the first high-side inverter chip 11, the second high-side inverter chip 12, and the first low-side inverter chip 14 on the first substrate portion 2021. The second sub-substrate 202 can provide a stable and reliable mounting position for the second substrate portion 2031 to ensure the positional reliability of the second low-side inverter chip 15, the third low-side inverter chip 16, and the third high-side inverter chip 13 on the second substrate portion 2031. The third sub-substrate 203 can provide a stable and reliable mounting position for the third substrate portion 2011 to ensure the positional reliability of the brake chip 301 and the rectifier chip 401 on the third substrate portion 2011.

[0154] In embodiments of the present invention, the semiconductor module 100 includes a housing 1 and a substrate 2. The substrate 2 includes a dielectric insulating layer and two metal oxide layers attached to the dielectric insulating layer, with the dielectric insulating layer located between the two metal oxide layers. The constituent materials of the metal oxide layers include, but are not limited to, at least one of copper, copper alloys, aluminum, and aluminum alloys. Alternatively, the constituent materials of the metal oxide layers may be any other metal or alloy that remains in a solid state during operation of the semiconductor module 100. The substrate 2 includes, but is not limited to, a ceramic substrate, the constituent materials of which include, but are not limited to, at least one of alumina, aluminum nitride, zirconium oxide, silicon nitride, boron nitride, and any other dielectric ceramic material. The constituent materials of the dielectric insulating layer include, but are not limited to, at least one of Al2O3, AlN, SiC, BeO, or Si3N4.

[0155] For example, substrate 2 can be any one of, for example, a direct copper bonding substrate, a direct aluminum bonding substrate, and an active metal brazing substrate. Furthermore, substrate 2 can also be an insulating metal substrate. The insulating metal substrate generally includes a dielectric insulating layer, for example, the constituent materials of the dielectric insulating layer include, but are not limited to, at least one of epoxy resin and polyimide. For example, the material of the dielectric insulating layer may be filled with ceramic particles, the constituent materials of which include, but are not limited to, at least one of Si2O, Al2O3, AlN, and BN. The diameter of the ceramic particles is between 1 μm and 50 μm.

[0156] Alternatively, substrate 2 can also be a conventional printed circuit board with a non-ceramic dielectric insulating layer. For example, the constituent materials of the non-ceramic dielectric insulating layer include, but are not limited to, cured resin.

[0157] According to some embodiments of the present invention, the substrate 2 is a single plate, and three third substrate portions 2011, first substrate portions 2021 and second substrate portions 2031 are formed on the substrate 2 in a first direction and are spaced apart in sequence.

[0158] In another embodiment of the present invention, the substrate 2 is formed as three separate plates, namely a third sub-substrate 203, a first sub-substrate 201, and a second sub-substrate 202, which are arranged sequentially at intervals in a first direction. The first substrate portion 2021 is disposed on the first sub-substrate 201, the second substrate portion 2031 is disposed on the second sub-substrate 202, and the third substrate portion 2011 is disposed on the third sub-substrate 203.

[0159] In one embodiment of the present invention, the semiconductor module 100 may further include a heat sink, which is thermally connected to the substrate 2, for example, the substrate 2 is soldered to the heat sink. The third substrate portion 2011, the first substrate portion 2021, and the second substrate portion 2031 of the substrate 2 are disposed on the side of the substrate 2 away from the heat sink.

[0160] In another embodiment of the invention, the bottom of the housing 1 is open, and a heat sink is formed on the side of the substrate 2 facing the bottom of the housing 1, with the heat sink at least partially protruding from the open side of the bottom of the housing 1.

[0161] In embodiments of the present invention, the constituent materials of the silicone gel 102 include, but are not limited to, silicone gel and rigid molding compound. The silicone gel 102 may at least partially fill the interior of the housing 1 to cover the components and electrical connections on the substrate 2. The housing 1 itself includes a sidewall portion 103 and a top wall portion 104, and the external terminal 101 is partially embedded in the housing and covered by the silicone gel 102. Further, the external terminal 101 may be configured to at least partially extend from the sidewall portion 103 of the housing 1 and not be covered by the silicone gel 102, or extend from the top wall portion 104 of the housing 1 and not be covered by the silicone gel 102. The silicone gel 102 is configured to protect the components and conductive elements 23 inside the semiconductor module 100, particularly to prevent the components and electrical connections inside the housing 1 from environmental influences and mechanical damage.

[0162] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "circumferential," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0163] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0164] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor module, characterized in that, The semiconductor module (100) has a first direction and a second direction, and a high side (10001) and a low side (10002) disposed opposite to each other in the second direction. The semiconductor module (100) includes: Shell (1); A substrate (2) is disposed within the housing (1). The substrate (2) has a first substrate portion (2021) and a second substrate portion (2031) arranged sequentially at intervals along the first direction. The first substrate portion (2021) has a first high-side inverter chip upper core region (5) and a first low-side inverter chip upper core region (6) arranged at intervals along the second direction. The first high-side inverter chip upper core region (5) is closer to the high side (10001) than the first low-side inverter chip upper core region (6). The second substrate portion (2031) has a second high-side inverter chip upper core region (7), a third low-side inverter chip upper core region (9), and a second low-side inverter chip upper core region (8) arranged sequentially at intervals along the second direction. The second high-side inverter chip upper core region (7) is closer to the high side (10001) than the second low-side inverter chip upper core region (8). Multiple inverter chips (10), each inverter chip (10) is a single chip, each inverter chip (10) is provided with a control electrode pad (1002), a first load electrode pad and a second load electrode pad (1001), the multiple inverter chips (10) include a first high-side inverter chip (11), a second high-side inverter chip (12), a third high-side inverter chip (13), a first low-side inverter chip (14), a second low-side inverter chip (15) and a third low-side inverter chip (16), the first high-side inverter chip (11) and the second high-side inverter chip (12) are disposed on the first high-side inverter chip (16). The first high-side inverter chip (11) is further away from the second substrate portion (2031) in the first direction than the second high-side inverter chip (12). The third high-side inverter chip (13) is disposed in the second high-side inverter chip upper core area (7). The first low-side inverter chip (14) is disposed in the first low-side inverter chip upper core area (6). The second low-side inverter chip (15) is disposed in the second low-side inverter chip upper core area (8). The third low-side inverter chip (16) is disposed in the third low-side inverter chip upper core area (9). The first high-side inverter chip (11) and the second high-side inverter chip (12) are disposed on the upper core area (5) of the first high-side inverter chip, closer to the high side (10001) along the second direction. The upper core area (5) of the first high-side inverter chip is provided with a clearance notch (501). A first jumper area (17) extending along the second direction is provided in the clearance notch (501). The first jumper area (17) is spaced apart from the upper core area (5) of the first high-side inverter chip. At least a portion of the first jumper area (17) is located between the first high-side inverter chip (11) and the second high-side inverter chip (12) in the first direction. The first high-side inverter chip (11) is positioned closer to the second high-side inverter chip (12) in the first direction. The edge of the second high-side inverter chip (12) is the first edge (1101). The edge of the second high-side inverter chip (12) adjacent to the first high-side inverter chip (11) in the first direction is the second edge (1201). The edge of the first high-side inverter chip (11) adjacent to the low side (10002) in the second direction is the third edge (1102). The edge of the first high-side inverter chip (11) adjacent to the high side (10001) in the second direction is the fourth edge (1103). The edge of the second high-side inverter chip (12) adjacent to the low side (10002) in the second direction is the fifth edge (1202). The edge of the second high-side inverter chip (12) adjacent to the high side (10001) in the second direction is the sixth edge (1203). The one of the third edge (1102) and the fifth edge (1202) that is closer to the low side (10002) is designated as the low side edge, and the one of the fourth edge (1103) and the sixth edge (1203) that is closer to the high side (10001) is designated as the high side edge. The area enclosed by the extension lines of the first edge (1101), the second edge (1201), the high side edge, and the low side edge is designated as the interval area (1206). The portion of the interval area (1206) corresponding to the clearance gap (501) is only provided with the first jumper area (17). A conductive element (23) is connected between the second load electrode pad (1001) of the first high-side inverter chip (11) and the first jumper area (17). The control electrode pad (1002) of the first high-side inverter chip (11) is disposed on the first high-side inverter chip (11) along the second direction, which is closer to the high side (10001). The control electrode pad (1002) of the first high-side inverter chip (11) is electrically connected to the external terminal (101).

2. The semiconductor module according to claim 1, characterized in that, The first substrate portion (2021) is further provided with a second jumper area (18), which is disposed in the clearance notch (501). The second jumper area (18) is spaced apart from the fourth edge (1103) on the side facing the high side (10001) in the second direction. The second jumper area (18) is located on the side of the first jumper area (17) away from the second substrate portion (2031) in the first direction. A conductive element (23) is connected between the control electrode pad (1002) of the first high-side inverter chip (11) and the second jumper area (18). A conductive element (23) is connected between the second jumper area (18) and the external terminal (101).

3. The semiconductor module according to claim 1, characterized in that, The first high-side inverter chip (11) and the second high-side inverter chip (12) are arranged opposite to each other in the first direction, and the projections of the first high-side inverter chip (11) and the second high-side inverter chip (12) in the first direction overlap each other.

4. The semiconductor module according to claim 1, characterized in that, The portion of the first jumper area (17) located between the first high-side inverter chip (11) and the second high-side inverter chip (12) has a dimension of L1 in the first direction, and L1 satisfies the relationship: 1.7mm≤L1≤3.2mm.

5. The semiconductor module according to claim 1, characterized in that, The dimension of the first substrate portion (2021) in the second direction is A; The distance between the first high-side inverter chip (11) and the edge of the first substrate portion (2021) facing the high side (10001) is B, and A and B satisfy the relationship: 0.086A≤B≤0.117A; The distance between the second high-side inverter chip (12) and the edge of the first substrate (2021) facing the high side (10001) is C, and A and C satisfy the relationship: 0.086A≤C≤0.117A.

6. The semiconductor module according to claim 1, characterized in that, The control electrode pad (1002) of the first high-side inverter chip (11) is disposed on the side of the first high-side inverter chip (11) that is further away from the second substrate portion (2031) along the first direction.

7. The semiconductor module according to claim 6, characterized in that, The first high-side inverter chip (11) has a control electrode channel (19), and the second load electrode pad (1001) of the first high-side inverter chip (11) includes two sub-load electrode pads (1001). The control electrode channel (19) is disposed between the two sub-load electrode pads (10011), and the control electrode channel (19) of the first high-side inverter chip (11) extends along the first direction.

8. The semiconductor module according to claim 1, characterized in that, The first jumper area (17) is located in the middle of the upper core area (5) of the first high-side inverter chip in the first direction.

9. The semiconductor module according to claim 8, characterized in that, The first substrate portion (2021) is further provided with a third jumper area (20), the third jumper area (20) is connected to one end of the first jumper area (17) adjacent to the upper core area (6) of the first low-side inverter chip, the third jumper area (20) extends from the first jumper area (17) in a first direction toward a direction away from the second substrate portion (2031), and a conductive element (23) is connected between the third jumper area (20) and the upper core area (6) of the first low-side inverter chip.

10. The semiconductor module according to claim 9, characterized in that, The first low-side inverter chip (14) is disposed on the upper core area (6) of the first low-side inverter chip, which is closer to the second substrate portion (2031) along the first direction. A conductive element (23) is connected between the upper core area (6) of the first low-side inverter chip and the third jumper area (20) on the side away from the second substrate portion (2031) in the first direction.

11. The semiconductor module according to claim 8, characterized in that, The first substrate portion (2021) is further provided with a fourth jumper area (21), which is connected to the end of the first jumper area (17) away from the upper core area (6) of the first low-side inverter chip, and the fourth jumper area (21) extends from the first jumper area (17) in a first direction toward the second substrate portion (2031).

12. The semiconductor module according to claim 1, characterized in that, The third high-side inverter chip (13) is located in the middle of the second substrate portion (2031) in the first direction.

13. The semiconductor module according to claim 12, characterized in that, The control electrode pad (1002) of the third high-side inverter chip (13) is disposed on the third high-side inverter chip (13) more closely adjacent to the high side (10001) along the second direction; The control electrode pad (1002) of the third high-side inverter chip (13) is disposed on the third high-side inverter chip (13) closer to the first substrate portion (2021) along the first direction.

14. The semiconductor module according to claim 13, characterized in that, The third high-side inverter chip (13) has a control electrode channel (19). The second load electrode pad (1001) of the third high-side inverter chip (13) includes two sub-load electrode pads (1001). The control electrode channel (19) is disposed between the two sub-load electrode pads (1001). The control electrode channel (19) of the third high-side inverter chip (13) extends along the first direction.

15. The semiconductor module according to claim 13, characterized in that, The second substrate (2031) is further provided with a fifth jumper area (22), which is located on the side of the second high-side inverter chip core area (7) away from the first substrate (2021) in the first direction. A conductive element (23) is connected between the control electrode pad (1002) of the third high-side inverter chip (13) and the fifth jumper area (22).

16. The semiconductor module according to claim 1, characterized in that, The third low-side inverter chip (16) is located in the middle of the second substrate portion (2031) in the first direction.

17. The semiconductor module according to claim 16, characterized in that, The control electrode pad (1002) of the third low-side inverter chip (16) is disposed on the third low-side inverter chip (16) more closely adjacent to the low side (10002) along the second direction; The control electrode pad (1002) of the third low-side inverter chip (16) is disposed on the third low-side inverter chip (16) along the first direction, on the side of the third low-side inverter chip (16) that is further away from the first substrate portion (2021).

18. The semiconductor module according to claim 17, characterized in that, The third low-side inverter chip (16) has a control electrode channel (19), and the second load electrode pad (1001) of the third low-side inverter chip (16) includes two sub-load electrode pads (1001). The control electrode channel (19) is disposed between the two sub-load electrode pads (1001), and the control electrode channel (19) of the third low-side inverter chip (16) extends along the first direction.

19. The semiconductor module according to claim 1, characterized in that, The second low-side inverter chip (15) is disposed on the second substrate portion (2031) more closely adjacent to the first substrate portion (2021) along the first direction.

20. The semiconductor module according to claim 19, characterized in that, The control electrode pad (1002) of the second low-side inverter chip (15) is disposed on the second low-side inverter chip (15) more closely adjacent to the low side (10002) along the second direction; The control electrode pad (1002) of the second low-side inverter chip (15) is disposed on the side of the second low-side inverter chip (15) that is further away from the first substrate portion (2021) along the first direction.

21. The semiconductor module according to claim 17, characterized in that, The second low-side inverter chip (15) has a control electrode channel (19), and the second load electrode pad (1001) of the second low-side inverter chip (15) includes two sub-load electrode pads (1001). The control electrode channel (19) is disposed between the two sub-load electrode pads (1001), and the control electrode channel (19) of the second low-side inverter chip (15) extends along the first direction.

22. The semiconductor module according to claim 1, characterized in that, The substrate (2) includes a first sub-substrate (201) and a second sub-substrate (202) arranged sequentially at intervals along the first direction, with the first substrate portion (2021) disposed on the first sub-substrate (201) and the second substrate portion (2031) disposed on the second sub-substrate (202).

23. The semiconductor module according to claim 22, characterized in that, The substrate (2) also has a third substrate portion (2011), which is disposed on the side of the first substrate portion (2021) away from the second substrate portion (2031) in a first direction. The third substrate portion (2011) is provided with a brake unit upper core area and a rectifier unit upper core area.

24. The semiconductor module according to claim 23, characterized in that, The substrate (2) includes a third sub-substrate (203), which is disposed at a distance from the first sub-substrate (201) on the side away from the second sub-substrate (202) in a first direction, and the third substrate portion (2011) is disposed on the third sub-substrate (203).

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