Data read-write control method and data read-write controller

Abstract

The application discloses a data read-write control method and a data read-write controller. The method comprises the following steps: receiving a configuration command issued by a user, wherein the configuration command comprises a format requirement of a target memory; updating configuration information currently stored by the data read-write controller according to the configuration command; generating a command frame meeting the format requirement of the target memory according to the updated configuration information, so that the data read-write controller performs a corresponding data read-write operation according to the command frame. According to the technical scheme, the configuration information is updated according to the configuration command issued by the user, and the command frame meeting the format requirement of the target memory is generated, so that the flexible adaptation to the target memory with different format requirements is realized without modifying the core control logic of the data read-write controller.

Description

Data read / write control method and data read / write controller Technical Field

[0001] This application belongs to the field of integrated circuit design, specifically relating to a data read / write control method and a data read / write controller. Background Technology

[0002] In the field of integrated circuit design, the data read / write controller is a key component for enabling data interaction between the processor and external memory. However, in today's increasingly complex application environments, an electronic system may need to adapt to various memories from different manufacturers. These memories often differ in their supported command sets and command frame structures (such as address field length and data unit sequence). In this situation, traditional read / write controllers are prone to the following drawbacks:

[0003] First, it adopts a fixed hardware logic design. The configuration information such as the command frame format and operation type used to communicate with the memory is fixed in the design stage. It is impossible to dynamically adjust its internal configuration after operation, which means that a controller design can usually only serve a specific model or a specific manufacturer of memory.

[0004] Secondly, if the memory is to be replaced, the hardware logic of the controller must be redesigned, which increases development costs, prolongs the product launch cycle, and hinders the reuse of hardware design modules. Summary of the Invention

[0005] The purpose of this application is to provide a data read / write control method and a data read / write controller to improve the flexibility of the data read / write controller.

[0006] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part by practice of this application.

[0007] According to one aspect of the embodiments of this application, a data read / write control method is provided, comprising:

[0008] Receive configuration commands issued by the user, the configuration commands including the format requirements of the target memory;

[0009] Update the configuration information currently stored in the data read / write controller according to the configuration command;

[0010] Based on the updated configuration information, a command frame conforming to the format requirements of the target memory is generated, so that the data read / write controller can perform the corresponding data read / write operation according to the command frame.

[0011] According to one aspect of the embodiments of this application, a data read / write control method is provided, comprising:

[0012] Receive the operation command issued by the user, and decode the operation command to obtain the corresponding address field;

[0013] The command type of the operation command is determined based on the address field; the command type includes the configuration command and the data access command.

[0014] According to one aspect of the embodiments of this application, a data read / write control method is provided, comprising:

[0015] The configuration command is parsed to identify the object to be updated; the object to be updated includes one of the command field register, frame format register, or state machine register.

[0016] The configuration information of the object to be updated is updated according to the configuration command.

[0017] According to one aspect of the embodiments of this application, a data read / write control method is provided, comprising:

[0018] If the updated object is a command field register, then the command opcode carried by the configuration command is written into the corresponding command field register; wherein, the command opcode is used to indicate the type of operation that the data read / write controller needs to perform;

[0019] If the object to be updated is a frame format register, then the command frame format in the frame format register is updated according to the structure parameters carried by the configuration command; wherein, the structure parameters are used to indicate the structure of the command frame;

[0020] If the object to be updated is a state machine register, then the configuration information in the state machine register is updated according to the control parameters carried by the configuration command; the control parameters are used to indicate the state transition rules of the state machine in the state machine register.

[0021] According to one aspect of the embodiments of this application, a data read / write control method is provided, comprising:

[0022] In response to the data access command issued by the user, the operation state is determined according to the state transition rules in the state machine register; the operation state is used to indicate the stage or state in which the data read / write operation is performed.

[0023] Generate a corresponding command frame based on the operation status.

[0024] According to one aspect of the embodiments of this application, a data read / write control method is provided, comprising:

[0025] Based on the command field register and frame format register corresponding to the operation state, obtain the command opcode and command frame format respectively;

[0026] Based on the command opcode and the command frame format, assemble the command frame corresponding to the operation state.

[0027] According to one aspect of the embodiments of this application, a data read / write control method is provided, comprising:

[0028] Based on the configuration information in the state machine register, selectively skip one or more states in the operation states; and / or

[0029] When the state machine is in a specific state, the format of the command frame generated in that specific state is refreshed according to the command opcode stored in the command field register.

[0030] According to one aspect of the embodiments of this application, a data read / write control method is provided, comprising:

[0031] When performing an erase operation, the state machine controls the write enable state and sends an enable command before entering the erase command sending state.

[0032] After sending the enable command, the state machine is controlled to perform one of the following operations: directly jump from the write enable state to the erase command sending state; or jump from the write enable state to the state read state, and after confirming that the write enable was successful, jump to the erase command sending state.

[0033] According to one aspect of the embodiments of this application, a data read / write control method is provided, comprising:

[0034] When a write operation is performed, the state machine controls the write enable state and sends an enable command before entering the write command sending state.

[0035] After sending the enable command, control the state machine to perform one of the following operations: directly jump from the write enable state to the write command sending state; jump from the write enable state to the state read state, and after confirming that the write enable is successful, jump to the write command sending state again.

[0036] According to one aspect of the embodiments of this application, a data read / write controller is provided, comprising:

[0037] The user-side serial port is used to receive operation commands issued by the user.

[0038] The read / write control module is connected to the user-side transceiver serial port. The read / write control module is used to decode the operation command to distinguish between configuration commands and data access commands, and to update the configuration information currently stored in the data read / write controller according to the configuration command, so as to generate a command frame that conforms to the target memory format requirements according to the updated configuration information.

[0039] The data forwarding serial port is connected to the read / write control module and is used to interact with the external memory based on the command frame.

[0040] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device comprising:

[0041] Processor; and

[0042] A memory is provided for storing executable instructions of a processor; wherein the processor executes the executable instructions to cause the electronic device to perform the data read / write control method in any embodiment of this application.

[0043] According to one aspect of the embodiments of this application, a computer-readable medium is provided having a computer program stored thereon, which, when executed by a processor, implements the data read / write control method in any embodiment of this application.

[0044] The technical solution provided in this application provides a data read / write control method and a data read / write controller. The method includes: receiving a configuration command issued by a user, the configuration command including the format requirements of a target memory; updating the configuration information currently stored in the data read / write controller according to the configuration command; and generating a command frame conforming to the format requirements of the target memory according to the updated configuration information, so that the data read / write controller performs corresponding data read / write operations according to the command frame. This technical solution updates the configuration information according to the configuration command issued by the user and generates a command frame conforming to the format requirements of the target memory, thereby achieving flexible adaptation to target memories with different format requirements without modifying the core control logic of the data read / write controller.

[0045] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0047] Figure 1 schematically illustrates a data read / write controller structure provided in one embodiment of this application.

[0048] Figure 2 schematically illustrates a flowchart of a data read / write control method provided in one embodiment of this application.

[0049] Figure 3A schematically illustrates an address field table provided in one embodiment of this application.

[0050] Figure 3B schematically illustrates a controller logic architecture diagram provided in one embodiment of this application.

[0051] Figure 4A schematically illustrates an address byte diagram provided in one embodiment of this application.

[0052] Figure 4B schematically illustrates a classification diagram of read commands provided in one embodiment of this application.

[0053] Figure 4C schematically illustrates a frame format diagram provided in one embodiment of this application.

[0054] Figure 4D schematically illustrates a frame format diagram provided in one embodiment of this application.

[0055] Figure 5A schematically illustrates an operation flowchart provided in one embodiment of this application.

[0056] Figure 5B schematically illustrates a flowchart provided in one embodiment of this application.

[0057] Figure 6 schematically illustrates a flowchart of a data read / write control method provided in one embodiment of this application.

[0058] Figure 7 schematically illustrates the computer system architecture block diagram used to implement the technical solution of this application. Detailed Implementation

[0059] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0060] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0061] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0062] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0063] Figure 1 schematically illustrates the structure of a data read / write controller according to an embodiment of this application. As shown in Figure 1, the data read / write controller includes a user-side transceiver serial port, a data forwarding serial port, and a read / write control module.

[0064] The user-side serial port connects to the external user on one end and to the internal read / write control module on the other. It receives all operation commands issued by the user and transmits them to the read / write control module. Simultaneously, it receives the operation results (such as read data and status feedback) returned by the read / write control module and forwards them to the user.

[0065] The data forwarding serial port connects to an external memory on one end and to an internal read / write control module on the other. It receives command frames generated by the read / write control module to adapt to the target memory and sends them to the external memory. Simultaneously, it receives data or status returned from the external memory and sends it back to the read / write control module.

[0066] The read / write control module, as the core processing unit of the data read / write controller, establishes bidirectional connections with both the user-side transceiver serial port and the data forwarding serial port. It includes a command field register, a frame format register, and a state machine register. The command field register stores the opcode for at least one of the read, write, erase, and enable commands; the frame format register stores the structure parameters of the command frame, which define the structure of the command frame; and the state machine register stores the state transition rules of the state machine.

[0067] For example, the read / write control module can be used to receive operation commands from the user-side serial port, and perform address decoding on the operation commands to distinguish between configuration commands and data access commands; update the configuration information of at least one of the command field register, frame format register, and state machine register according to the configuration command; and generate a command frame that conforms to the target memory format requirements according to the updated configuration information.

[0068] The read / write control module is also used to receive external memory data or status transmitted back from the data forwarding serial port, process it, and then feed it back to the user through the user-side transceiver serial port.

[0069] In this embodiment, the data read / write controller independently handles command and data interactions between the user and the controller, and between the controller and external memory, through the user-side transceiver serial port and the data forwarding serial port, respectively. Simultaneously, the read / write control module serves as a centralized scheduling unit, with a built-in configurable register group dynamically adjusting command fields, frame formats, and state machine transition rules. Software-defined configuration logic replaces traditional hardware hard-coding, decoupling user operations from memory adaptation logic. This ensures the independent reliability of user interaction and memory data forwarding while allowing the same hardware architecture to be compatible with memories from different manufacturers. This solves the pain point of traditional controllers requiring hardware redevelopment when replacing memory, significantly reducing development and maintenance costs and substantially improving the controller's functional robustness and multi-scenario adaptability.

[0070] The data read / write control method provided in this application will be described in detail below with reference to specific embodiments. Figure 2 schematically shows a flowchart of a data read / write control method provided in one embodiment of this application. As shown in Figure 2, the data read / write control method provided in this embodiment includes steps 210 to 230, as follows:

[0071] Step 210: Receive configuration commands issued by the user.

[0072] Specifically, a configuration command is an instruction issued by the user to the data read / write controller to update the configuration information in the controller to adapt to the command format and timing requirements of the target external memory. This configuration command includes the format requirements of the target memory.

[0073] In one embodiment of this application, before receiving the configuration command issued by the user, an operation command issued by the user can be received, and the operation command can be address decoded to obtain the corresponding address field; the command type of the operation command can be determined based on the address field.

[0074] Specifically, an operation command is a set of instructions issued by the user to the data read / write controller to trigger the controller to execute a specific action. Address decoding refers to the parsing process performed by the data read / write controller on the received operation commands, specifically including extracting address-related information carried in the operation command to parse the logical operation corresponding to the address field. The address field is an information segment contained in the operation command that identifies the command's attributes.

[0075] Command types include configuration commands and data access commands. Data access commands are instructions issued by the user to the data read / write controller to trigger data interaction (such as reading data, writing data, erasing data, etc.) between the controller and external memory.

[0076] Figure 3A schematically illustrates an address field table provided in an embodiment of this application. As shown in Figure 3A, specific address fields can be preset for the data read / write controller and its associated modules. Specifically, the access module corresponding to the address field range of 0x1000_0000-0x1000_FFFF is the data read / write controller, and the command type is "configuration command," which can be used to configure the command fields, frame format, and state machine in the controller. The access module corresponding to the address field range of 0x2000_0000-0x2000_FFFF is register module 1, and the access module corresponding to the address field range of 0x3000_0000-0x3000_FFFF is register module 2. The command type is data access command, which is used to perform data read / write operations on the internal firmware content of the chip (such as register module 1 and register module 2).

[0077] For example, when a user sends an operation command through the user-side serial port, the address decoding unit in the read / write control module is activated and performs the following steps: parses the target address field from the received operation command data packet; compares the extracted address with a preset address range; if the address falls within the range of 0x1000_0000 to 0x1000_FFFF, the operation command is determined to be a configuration command; if the address falls within the range of 0x2000_0000 to 0x2000_FFFF or 0x3000_0000 to 0x3000_FFFF, the operation command is determined to be a data access command.

[0078] Figure 3B schematically illustrates a controller logic architecture diagram provided in one embodiment of this application. As shown in Figure 3B, the upper "Data Read / Write Controller Configuration Register Area" is a dedicated area for storing configuration parameters (such as opcodes and frame formats) corresponding to operations such as read commands, write commands, and erase commands. It is directly associated with various specific data access commands on the right through logical connections. The lower "Firmware Content" is the underlying firmware or logic code pre-installed in the controller, which carries the association and scheduling logic between the configuration register area and these operation commands.

[0079] For example, when a user issues a configuration command, the firmware receives and parses the command, writing the configuration parameters into the "Data Read / Write Controller Configuration Register Area" for storage. When a user issues a data access command, the firmware first identifies the command type, then reads the corresponding configuration parameters from the "Data Read / Write Controller Configuration Register Area," assembles a command frame adapted to the external memory, and finally executes the data access operation. In this way, the two areas successfully support the storage of configuration command parameters and the adapted execution of data access commands, respectively.

[0080] Step 220: Update the configuration information currently stored in the data read / write controller according to the configuration command.

[0081] Specifically, the configuration information is a set of parameters stored in the configuration register area of ​​the data read / write controller, which may include command opcodes, command frame structure parameters, state machine transition rules, etc., corresponding to read, write, and erase operations.

[0082] Step 230: Generate a command frame that conforms to the format requirements of the target memory based on the updated configuration information, so that the read / write controller can perform the corresponding data read / write operation according to the command frame.

[0083] Specifically, the target memory refers to the external storage device with which the user expects the data read / write controller to interact with data. Memory devices from different manufacturers may have different data interaction format requirements, specifically in key aspects such as the command opcodes corresponding to core operations (e.g., the encoded values ​​of read, write, erase, and write enable commands), command frame structure (e.g., the number of bytes in the address field, whether an operation end flag is required, and the order and number of command fields), and state transition rules related to read / write timing (e.g., whether the status needs to be confirmed before executing subsequent commands after write enable). Existing data read / write controllers mostly use fixed logic designs with hardware coding, which cannot be compatible with these differentiated format requirements. This necessitates redeveloping the controller's core logic when changing memory manufacturers. Therefore, this application provides the aforementioned data read / write control method to solve this technical problem.

[0084] The command frame here refers to an instruction structure that conforms to the target memory format requirements and is assembled based on the updated configuration information. It contains operation instructions and corresponding parameters and serves as the instruction carrier for data interaction between the data read / write controller and the target memory. Data read / write operations are data interaction behaviors such as reading and writing data carried out by the data read / write controller and the target memory based on the command frame. In other words, this operation refers to the specific read / write action corresponding to the data access command.

[0085] In the technical solution provided in this application embodiment, a configuration command issued by the user is first received, which includes the format requirements of the target memory. Then, the configuration information currently stored in the data read / write controller is updated according to the configuration command. Next, a command frame conforming to the target memory format requirements is generated based on the updated configuration information, so that the data read / write controller performs the corresponding data read / write operation according to the command frame. In this way, the configuration information can be updated according to the configuration command issued by the user, and a command frame conforming to the target memory format requirements can be generated, thereby achieving flexible adaptation to target memories with different format requirements without modifying the core control logic of the data read / write controller.

[0086] In one embodiment of this application, the configuration command can be parsed to identify the object to be updated; and the configuration information of the object to be updated can be updated according to the configuration command.

[0087] Specifically, the updated objects can be command field registers, frame format registers, and state machine registers. The command field register is a hardware-level storage unit built into the read / write control module of the data read / write controller. It is specifically used to store the command opcodes corresponding to core operations such as read, write, erase, and write enable, providing basic instruction data support for assembling command frames adapted to the target memory during subsequent data access command execution. The frame format register stores the structural parameters of the command frame (such as the number of bytes in the address field, whether it includes an operation end flag, and the order of command fields), and defines the assembly rules of the command frame to adapt to the frame format requirements of different manufacturers' memories. The state machine register stores the state transition rules of the state machine (such as whether to skip specific operation states, and the jump logic after write enable), providing the control basis for the state transitions when the state machine performs data read / write operations, and adapting to the read / write timing requirements of different memories.

[0088] For example, the read / write control module can first predefine the mapping relationship between key identifiers (such as register IDs and configuration type identifiers) and update objects, clearly defining "the command field register, frame format register, and state machine register corresponding to a specific register ID or identifier." Simultaneously, it associates the configuration parameter types corresponding to each update object, such as the command opcode corresponding to the command field register and the structure parameters corresponding to the frame format register. Subsequently, it receives the configuration command confirmed by address decoding, parses the command content fields in the command frame, and extracts the register ID or configuration type identifier. The extracted identifier is matched against the predefined mapping relationship. If the matching result is a command opcode configuration type identifier, the update object is determined to be a command field register; if it is a structure parameter type identifier, the update object is determined to be a frame format register; and if it is a state transition rule type identifier, the update object is determined to be a state machine register.

[0089] In one embodiment of this application, if the object to be updated is a command field register, the command opcode carried by the configuration command is written into the corresponding command field register; wherein, the command opcode is used to indicate the type of operation that the read / write controller needs to perform.

[0090] Specifically, the command opcode is coded information carried in the configuration command to uniquely identify a specific operation type. It can be used to instruct the data read / write controller to perform operations such as read, write, and erase. Operation types can include actions related to data interaction or status configuration with external memory, such as reading data, writing data, erasing data, and write enabling.

[0091] For example, the command content field of the configuration command can be parsed first to extract the operation type identifier (such as the distinguishing identifier for read, write, erase, and write enable operations) and the corresponding command opcode value (such as a vendor-specific read byte command code 0x04, write enable command code 0x06, etc.). Then, based on the predefined "correspondence between operation type identifiers and command field registers," such as read operation identifiers corresponding to read command field registers and erase operation identifiers corresponding to erase command field registers, the specific command field register that needs to be updated is precisely located. Finally, through the register enable logic inside the controller, the extracted command opcode value is written to the target register and data latching is completed, ensuring that the command opcode is stored effectively.

[0092] For example, the default read byte command opcode is 0x02. If it's necessary to adapt to memory vendor A's command opcode 0x04, the value of the corresponding sub-address in the read byte command register is updated to 0x04 via a configuration command. If it's subsequently changed to memory vendor B's command opcode 0x05, the value of the same register is updated to 0x05 via another configuration command. Similarly, the opcodes for write, erase, and enable commands can all be dynamically configured in this way, which will not be elaborated further here.

[0093] In another embodiment of this application, if the object to be updated is a frame format register, the command frame format in the frame format register is updated according to the structure parameters carried by the configuration command; wherein, the structure parameters are used to indicate the structural composition of the command frame.

[0094] Specifically, structural parameters are a set of parameters carried in the command content field of the configuration command, used to clarify the specific structure of the command frame. They may include information such as the number of bytes in the address field, the order of the command fields, whether an operation end flag needs to be added, and the number of bytes between the data field and the command field.

[0095] The command frame format is a set of rules stored in the frame format register that are used to standardize the structure of the command frame. Specifically, it covers the arrangement order, field length, required attributes, and spacing rules of the various functional fields (opcode field, address field, data field, flag field, etc.) within the command frame.

[0096] For example, structural parameters can be extracted first from the command content field of the configuration command. Then, based on the predefined correspondence between "structural parameter type and internal storage unit of the frame format register" (e.g., the address field byte number corresponds to the first 1-2 bits of the register, and the field order corresponds to the third-to-fifth bits), the specific storage area in the frame format register that needs to be updated is located. Next, through the write control logic inside the data read / write controller, the extracted structural parameters are formatted and verified according to the bit width requirements of the corresponding storage area to ensure that the parameters conform to the register storage specifications. Finally, the verified structural parameters are written one by one to the target storage area of ​​the frame format register and data latching is completed, thereby updating the command frame format rules. At this point, the updated command frame format will be directly used as the assembly standard for subsequent data access command execution, ensuring that the generated command frame strictly matches the frame structure requirements of the target memory and guaranteeing the compatibility of data interaction.

[0097] Figure 4A schematically illustrates an address byte diagram provided in an embodiment of this application. As shown in Figure 4A, when the configuration command determines that the update object is the frame format register, the "address field byte count" structure parameter carried by the configuration command can be extracted. This parameter can match the address length requirements of the target vendor's memory, for example, vendor A requires 2 bytes of address to read bytes and 3 bytes of address to read pages. Then it is written into the corresponding storage unit in the frame format register, for example, configuring the address field byte count to be 2 for the "read byte" operation.

[0098] When a read operation is executed, the read / write controller first reads the pre-configured address field byte count from the frame format register. Then, it selects the corresponding number of valid bytes from the multi-byte sequence of the target address as the address field of the command frame: if configured as a 4-byte address, the first byte sequence is selected; if configured as 3 bytes, the second byte sequence is selected; if configured as 2 bytes, the third byte sequence is selected; and if configured as 1 byte, the fourth byte sequence is selected. Finally, the data read / write controller assembles the address portion of the command frame according to this rule to ensure that the address field length strictly matches the requirements of the target memory.

[0099] Figure 4B schematically illustrates a read command classification diagram provided in one embodiment of this application. As shown in Figure 4B, after a read operation command is issued, a decision-making process of "selecting which read command to execute" will be initiated to determine the specific read operation type, such as reading bytes, reading pages, or reading the entire chip. Then, the read / write controller assembles the command frame by reading the pre-configured structural parameters in the frame format register according to the selected read command.

[0100] As shown in Figure 4C, if "Read Byte" is selected, the "Read Byte Command Frame Structure Parameter" in the frame format register is called, and "Read Byte Command (opcode from command field register) + Read Byte Command Address (valid address selected according to the number of address bytes) + Read Byte Command Data" are concatenated in sequence to form the command frame.

[0101] If "Read Page" is selected, the "Read Page Command Frame Structure Parameters" in the frame format register are called, and "Read Page Command + Read Page Command Address + Read Page Command Data + End of Read Page Data" is concatenated as the command frame.

[0102] If "Read Whole Chip" is selected, the "Read Whole Chip Command Frame Structure Parameters" in the frame format register will be called, and "Read Whole Chip Command + Read Whole Chip Command Address + Read Whole Chip Command Data + End of Read Whole Chip Data" will be concatenated as the command frame.

[0103] For example, as shown in Figure 4D, the operation of determining the end of reading page data for a read page command is also a configurable command option, which the user can select based on whether the current memory manufacturer supports it. For instance, for a read entire chip command, the user can choose not to load the read command address and not to perform the read page data end check.

[0104] In another embodiment of this application, if the object to be updated is a state machine register, the configuration information in the state machine register is updated according to the control parameters carried by the configuration command; the control parameters are used to indicate the state transition rules of the state machine in the state machine register.

[0105] Specifically, the state machine is a built-in timing logic unit in the read / write control module, used to manage the state transitions during data read / write operations, such as idle state → command sending state → data transmission state → completion state. The state transitions of the state machine strictly follow the state jump rules stored in the state machine register to ensure that data read / write operations are executed in the order required by the target memory.

[0106] State transition rules can include triggering conditions for switching between various operation states, such as the data transmission state triggering condition for "command sent successfully and no error signal", the operation completion state triggering condition for "data transmission byte count met", the error rollback state triggering condition for "error feedback detected", and the data transmission byte count threshold. State transition rules can also include target state mapping relationships, such as transitioning from the current state to the specified next state when a certain triggering condition is met, as well as exception handling logic, such as the rollback state when an error is triggered and the state transition path corresponding to the retry mechanism.

[0107] For example, control parameters can be extracted first from the command content field of the configuration command. Then, based on the predefined correspondence between "control parameter types and internal storage units of the state machine register" (e.g., jump trigger conditions correspond to bits 1-4 of the register, target state identifiers to bits 5-8, and exception rollback logic to bits 9-12), the specific storage area in the state machine register that needs to be updated is located. Next, the write control logic inside the data read / write controller performs format conversion on each extracted control parameter, such as converting the logic instruction into binary code recognizable by the register, and performs validity checks, such as verifying whether the trigger condition conforms to the state machine's state range and whether the target state is a valid state value, to ensure that the parameters meet the register storage specifications and state machine operation requirements. Finally, the verified control parameters are written one by one to the target storage area of ​​the state machine register and data latching is completed, realizing the update of the configuration information in the state machine register. Thus, the state transition rules corresponding to the updated configuration information will serve as the core basis for the timing flow of data read and write operations managed by the state machine. This will ensure that the state machine completes the entire process of state switching from idle, command sending, data transmission to operation completion in an orderly manner according to the read and write timing requirements of the target memory, thus guaranteeing the timing compatibility of data interaction.

[0108] In one embodiment of this application, in response to a data access command issued by a user, an operation state is determined according to the state transition rules in the state machine register; and a corresponding command frame is generated according to the operation state.

[0109] Specifically, the operation state refers to the specific working stage of the built-in state machine of the data read / write controller during the execution of data read / write operations. It is the basic unit of state machine timing transition and includes idle state, command sending state, data transmission state, operation completion state, and abnormal rollback state.

[0110] For example, before performing data read / write operations, the state machine needs to load the updated configuration information (including state transition rules and judgment conditions for each operation state) from the state machine register. Then, during execution, it monitors the execution nodes and feedback signals of the data read / write operations in real time, such as whether the command has been sent, whether the target memory has returned a data response, whether an abnormal error signal has been detected, and whether the number of bytes transmitted has reached a preset threshold. Next, the monitored real-time information is matched against the preset trigger conditions for each operation state in the state transition rules. If the matching result satisfies all the trigger conditions for a certain operation state, the state machine determines that the current operation is in that operation state and records the current operation state information through the state flag bit in the state machine register. Simultaneously, this operation state is fed back to the read / write control module, providing a state basis for the execution of subsequent operations (such as continuing data transmission, terminating the operation, or triggering exception handling), ensuring that the judgment of the operation state is accurately synchronized with the timing requirements of the target memory and the progress of the operation execution.

[0111] In one embodiment of this application, the process of generating a command frame may involve first obtaining the command opcode and command frame format according to the command field register and frame format register corresponding to the operation state, respectively; and then assembling the command frame corresponding to the operation state based on the command opcode and command frame format.

[0112] For example, after the state machine determines that it is currently in a certain operation state (such as the command sending state corresponding to reading bytes), it first locates the dedicated storage unit in the command field register that matches the operation state based on the association between the operation state and the read command type. Then, it reads the corresponding command opcode adapted to the target vendor, which is written through the configuration command, and the command frame format rules corresponding to the operation state, which are pre-configured in the read frame format register. For example, the field arrangement order and length requirements of "1 byte opcode + 2 bytes address + data segment" for reading bytes. Next, it assembles the command frame according to the frame format rules: first, the command opcode is used as the first field of the frame; then, address bytes of the frame format-limited length are selected from the target address sequence and concatenated after it; if the frame format has requirements, the corresponding data segment can also be added; finally, the flag fields specified in the frame format (such as the end bit) are added to complete the assembly of the command frame corresponding to the current operation state, ensuring that the frame strictly matches the command format requirements of the target memory.

[0113] In one embodiment of this application, one or more states in the operation state can be selectively skipped based on the configuration information in the state machine register.

[0114] For example, before performing data read / write operations, the state machine needs to load the configuration information updated by the configuration command in the state machine register, explicitly including predefined "state skip trigger conditions," such as "skip the data verification preparation state when reading a whole chip" and "skip the address secondary verification state when reading consecutive pages." Then, during execution, the current operation type (e.g., reading bytes, reading pages, and reading a whole chip), the target memory's feedback signals, and operation progress information are synchronized in real time. When in a certain operation state (e.g., "command sent complete"), the real-time information is matched with the corresponding "state skip trigger condition" in the state machine register. If the match is successful, the state machine triggers the skip logic, directly jumping from the current operation state to the skipped target state, without executing the corresponding logic of the skipped state. For example, if the current operation is reading a whole chip, and the trigger condition is "skip the data verification preparation state when reading a whole chip"; if the current operation state is "command sent complete," then the "data verification preparation state" is skipped, and the operation jumps directly from the "command sent complete" state to the "data transmission" state.

[0115] In this way, the timing simplification requirements of different manufacturers' memories can be flexibly adapted through the configuration information of the state machine registers. For example, some manufacturers do not require certain intermediate states in order to ensure operation execution efficiency and compatibility.

[0116] In another embodiment of this application, when the state machine is in a specific state, the format of the command frame generated in that specific state can be updated according to the command opcode stored in the command field register.

[0117] Specifically, a specific state is a particular operational state that is designated by the state machine register configuration information during the data read / write operation and requires the execution of special logic (such as updating the command frame format).

[0118] For example, when the state machine performs data read / write operations, if it determines that it has entered a preset specific state, the data read / write controller first reads the pre-configured command opcode from the corresponding storage unit of the command field register associated with the current operation type. Then, based on the predefined mapping relationship between the command opcode and the command frame format adjustment rules, it determines the format update requirements corresponding to the current opcode. For example, opcode 0x13 requires adding a 1-byte page length field to the command frame, and opcode 0x25 requires adjusting the data field length to 512 bytes. Finally, the format of the command frame initially generated in the specific state is optimized according to these update requirements, such as adding fields, adjusting field lengths, or changing their order. In this way, the final generated command frame format not only matches the operation type corresponding to the command opcode but also strictly conforms to the target memory manufacturer's specifications.

[0119] In one embodiment of this application, when an erase operation is performed, the control state machine first enters the write enable state and sends an enable command before entering the erase command sending state; after sending the enable command, the control state machine jumps directly from the write enable state to the erase command sending state.

[0120] Specifically, the erase operation is an operation in which the data read / write controller clears data from a specified area of ​​the target memory based on pre-configured information in the command field register, frame format register, and state machine register. The write enable state is a dedicated operation state of the state machine when performing the erase operation, used to send an enable command to the target memory to activate the erase operation. The enable command is an instruction adapted to the target memory manufacturer's specifications, used to trigger the memory to enter the erase-enabled state. It is generated by assembling the corresponding opcode pre-stored in the command field register and the frame structure configured in the frame format register, and its transmission is a necessary prerequisite step for performing the erase operation.

[0121] Figure 5A schematically illustrates a flowchart of an erase operation provided in an embodiment of this application. As shown in Figure 5A, the flowcharts for byte erase, block / page erase, full chip erase, and write operations are illustrated. The byte erase operation corresponds to write enable command - read / write enable state - byte erase command - byte erase command address - read status signal. The block / page erase operation corresponds to write enable command - read / write enable state - block or page erase command - block or page erase command address - read status signal. The full chip erase operation corresponds to write enable command - read / write enable state - full chip erase command - read status signal. The write operation corresponds to write enable command - read / write enable state - write operation command - write operation command address - write operation command data.

[0122] For example, the requirement that the target memory needs to be in a pre-write enable state for erasure can be converted into register configuration through configuration commands. That is, write the write enable command opcode to the command field register, configure the module connection rules of "write enable command → read / write enable state → erase command" to the frame format register, and define the jump logic of "write enable state → erase command sending state" in the state machine register.

[0123] When an erase operation is performed (any of the byte erase, block / page erase, or whole chip erase operations shown in Figure 5A), the state machine receives the erase command and first jumps to the write enable state. The controller reads the write enable opcode from the command field register, triggers the "write enable command" module according to the frame format rules, and sends the enable command. After the signal fed back by the target memory matches the readiness requirements of the "read / write enable state" module, the state machine jumps directly from the write enable state to the command sending state of the corresponding erase operation (i.e., the execution state corresponding to the "byte erase command" and "whole chip erase command" modules in Figure 5A) according to the jump rules pre-configured in the register, completing the pre-preparation and state transition for the erase command sending, and adapting to the pre-enablement specification of the target memory erase operation.

[0124] In another embodiment of this application, when an erase operation is performed, the control state machine first enters the write enable state and sends an enable command before entering the erase command sending state; after sending the enable command, the control state machine jumps from the write enable state to the state read state, and after confirming that the write enable is successful, it jumps to the erase command sending state.

[0125] Specifically, the state read state is the operational state between the write enable state and the erase command sending state when the state machine performs an erase operation. Its core function is to read the signal fed back by the target memory to verify the execution result of the write enable command. It is a verification work stage to confirm whether the write enable was successful.

[0126] For example, the requirement that the target memory "requires a write enable state before erasure and verification of the enable result" can be converted into register configuration through configuration commands. That is, write the write enable command opcode to the command field register, configure the rule of "write enable command → write enable state → state read state → erase command" to the frame format register, and define the jump logic of "write enable state → state read state (trigger condition is enable command sent complete) → erase command sent state (trigger condition is write enable successful)" in the state machine register.

[0127] When an erase operation is performed, the state machine, upon receiving the erase command, first jumps to the write enable state. The controller reads the write enable opcode from the command field register, triggering the "write enable command" module in the diagram to send the enable command. After sending, the state machine jumps to the state read state according to the rules, i.e., "read state signal" in Figure 5A, reading the feedback signal from the target memory; after verifying the signal to confirm successful write enable, the state machine then jumps to the command sending state for the corresponding erase operation (i.e., the execution state corresponding to each erase command module in Figure 5A), completing the pre-verification and state transition for the erase command sending, to adapt to the target memory's requirement to verify the write enable result.

[0128] In one embodiment of this application, when a write operation is performed, the control state machine first enters the write enable state and sends an enable command before entering the write command sending state; after sending the enable command, the control state machine directly jumps from the write enable state to the write command sending state.

[0129] Specifically, a write operation refers to the process of writing data to a specified area of ​​the target memory. The write command sending state is a dedicated operation state of the state machine when performing a write operation, used to trigger the data read / write controller to send the write command assembled by register configuration.

[0130] For example, the requirement that "write operations require a pre-write enable state and no intermediate verification" of the target memory can be converted into register configuration through configuration commands. That is, write the exclusive opcode of the write enable command to the command field register, configure the module connection rules of "write enable command → write enable state → write command send state" to the frame format register, and define the direct jump logic of "write enable state (trigger condition is write operation instruction received) → write command send state (trigger condition is enable command sent completed)" in the state machine register.

[0131] When a write operation is performed, after the state machine receives the write operation instruction, it first jumps to the write enable state. The controller reads the pre-stored write enable opcode in the command field register, assembles and sends the enable command according to the frame format rules. After the enable command is sent, the state machine jumps directly from the write enable state to the write command sending state according to the pre-configured rules of the state machine register. Then the controller reads the write command opcode in the command field register, assembles the write command frame in combination with the configuration of the frame format register, and sends it down. In this way, the specification of pre-enabling write operation of target memory and supporting direct jump is adapted, and the instruction flow of the write operation is completed.

[0132] In another embodiment of this application, when a write operation is performed, the control state machine first enters the write enable state and sends an enable command before entering the write command sending state; after sending the enable command, the control state machine jumps from the write enable state to the state read state, and after confirming that the write enable is successful, it jumps to the write command sending state.

[0133] Specifically, the state read state is a verification operation state between the write enable state and the write command send state when the state machine performs a write operation. Its core function is to read the signal fed back by the target memory to verify the execution result of the write enable command, and to provide a basis for judging whether to jump to the write command send state later.

[0134] For example, the requirement that "write operations require a write enable state beforehand and the enable result needs to be verified" of the target memory is first converted into register configuration through configuration commands. That is, the dedicated opcode of the write enable command is written to the command field register, the module connection rules of "write enable command → write enable state → state read state → write command send state" are configured to the frame format register, and the jump logic of "write enable state (trigger condition is write operation instruction received) → state read state (trigger condition is enable command sent successfully)" is defined in the state machine register.

[0135] When a write operation is performed, the state machine receives the write operation instruction and first jumps to the write enable state. The controller reads the pre-stored write enable opcode in the command field register, assembles it according to the frame format rules, and sends the enable command. After the enable command is sent, the state machine jumps to the state read state according to the pre-configured rules and reads the feedback signal from the target memory. After verifying the signal to confirm that the write enable is successful, the state machine jumps to the write command send state. The controller then reads the write command opcode in the command field register, assembles the write command frame according to the configuration of the frame format register, and sends it down. In this way, it adapts to the specification that the target memory needs to verify the write enable result, and completes the instruction flow and pre-verification of the write operation.

[0136] In one embodiment of this application, during the reading, writing, and operation command framing process, the user can adjust register parameters by configuring commands based on the actual specifications of the target memory to add, delete, or modify commands.

[0137] Figure 5B schematically illustrates a flowchart provided in an embodiment of this application. As shown in Figure 5B, for the first process (A→B→C→D→E), after receiving the operation instruction, the state machine sequentially enters the state corresponding to each module according to the pre-configured rules: first, it executes the instruction corresponding to A, and after completion, it jumps to the state corresponding to B (such as the write enable state) to execute the corresponding instruction (such as the write enable command), then sequentially jumps to the states corresponding to C and D to execute the operation instructions, and finally enters the state corresponding to E (such as the state read state) to read the target memory feedback signal and complete the operation.

[0138] For the second process (A→C→E), users can modify the module combination rules of the frame format register through configuration commands, remove the configuration items corresponding to B and D, and directly jump from the state corresponding to A to the state corresponding to C to execute instructions, and then jump to the state corresponding to E to read feedback, adapting to the specifications of the target memory that do not require the B and D stages.

[0139] For the third process (C→D→E), users can modify the module combination rules of the frame format register through configuration commands, remove the configuration items corresponding to A and C, directly enter the state corresponding to C to execute instructions, and jump to the states corresponding to D and E in sequence to complete the operation, adapting to the requirement that the target memory has no preceding A and B stages.

[0140] For the fourth process (B→C→D→E), users can modify the configuration of the pre-processor module of the frame format register to allow the state machine to first enter the state corresponding to B to execute the pre-processor instruction, and then jump to the states corresponding to C, D, and E in sequence to complete the operation, thus adapting to the specifications of the target memory that require the pre-processor B stage.

[0141] In addition, if a verification command module needs to be added for a certain operation in a real-world scenario (such as adding a new F module), the user can add the configuration item corresponding to F in the frame format register and associate it with the command opcode in the command field register to extend the command chain to "A→B→C→D→E→F" to achieve the addition and adaptation of commands.

[0142] Figure 6 schematically illustrates a flowchart of a data read / write control method according to an embodiment of this application. As shown in Figure 6, the data read / write control method of this application includes the following steps:

[0143] Step 601: Receive operation commands issued by the user. The data read / write controller receives read, write, erase, and other operation commands initiated by the user for the target memory.

[0144] Step 602: Obtain configuration commands and data access commands through address decoding. Decode the address segments in the operation commands to parse instructions pointing to the register configuration address space into configuration commands, used to adjust register parameters; parse instructions pointing to memory data or operation address space into data access commands, used to perform read, write, or erase operations.

[0145] Step 603: Confirm the update object based on the configuration command. Parse the opcode field in the configuration command to determine that the object to be updated is one or more of the command field register, frame format register, and state machine register.

[0146] Step 604: Update the configuration information of the object to be updated according to the configuration command. If the object to be updated is a command field register, write the command opcode carried by the configuration command into the corresponding command field register; if the object to be updated is a frame format register, update the command frame format in the frame format register according to the structure parameters carried by the configuration command; if the object to be updated is a state machine register, update the configuration information (i.e., state transition rules) in the state machine register according to the control parameters carried by the configuration command.

[0147] Step 605: In response to the data access command, determine the operation state according to the state transition rules in the state machine register. Identify the operation type of the data access command (such as a write operation), and determine the initial operation state (such as a write enable state, and its trigger condition is "receiving a data access command for a write operation") according to the pre-configured state transition rules in the state machine register.

[0148] Step 606: Generate the corresponding command frame according to the operation status. For example, when in the write-enabled state, read the write-enabled opcode in the command field register, combine it with the structure parameters corresponding to the write-enabled state in the frame format register, and assemble a command frame containing "write-enabled command + read / write-enabled state identifier"; if switching to the write command sending state, read the write opcode and address field, and reassemble the corresponding command frame.

[0149] Step 607: Execute the corresponding data read / write operation according to the command frame. Send the assembled command frame to the target memory, and at the same time, the state machine switches to the next operation state according to the signal fed back by the memory and the state transition rules; when the state read state is executed, read the operation result signal of the memory to confirm that the read / write / erase operation is completed, and end the current data access process.

[0150] This technical solution parses operation commands into configuration commands and data access commands. Based on the configuration commands, it flexibly updates the core parameters of the command field register, frame format register, and state machine register. Then, the state machine dynamically determines the operation state according to the pre-configured jump rules and generates command frames adapted to the target memory specifications. This not only enables flexible addition, deletion, modification, and configuration of command frames for read, write, and erase operations, effectively adapting to the differentiated pre-requirements, command formats, and timing rules of different manufacturers' memories, but also ensures the accuracy and stability of command execution through address decoding, state transition verification, and other processes. This significantly reduces the adaptation development cost across memory scenarios and improves the universality, compatibility, and reliability of data read and write operations.

[0151] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0152] Figure 7 schematically shows a computer system architecture block diagram for implementing the technical solution of this application.

[0153] It should be noted that the computer system 700 shown in Figure 7 is only an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0154] As shown in Figure 7, the computer system 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 702 or programs loaded from storage section 707 into random access memory (RAM). The RAM 703 also stores various programs and data required for system operation. The CPU 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output interface 705 (I / O interface) is also connected to the bus 704.

[0155] The following components are connected to the input / output interface 705: an input section 707 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a local area network card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the input / output interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0156] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0157] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0158] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0159] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the method according to the embodiments of this application.

[0160] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0161] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A data read / write control method, characterized in that, include: Receive operation commands issued by the user and decode the operation commands to obtain the corresponding address field; The command type of the operation command is determined based on the address field; If the command type is a data access command, then data read / write operations are performed according to the data access command; if the command type is a configuration command, then the configuration information currently stored in the data read / write controller is updated according to the configuration command; the configuration command includes the format requirements of the target memory; wherein, if the update object is a state machine register, then the configuration information in the state machine register is updated according to the control parameters carried by the configuration command; the control parameters are used to indicate the state transition rules of the state machine in the state machine register; a command frame conforming to the format requirements of the target memory is generated according to the updated configuration information, so that the data read / write controller performs the corresponding data read / write operation according to the command frame.

2. The data read / write control method according to claim 1, characterized in that, The step of updating the configuration information currently stored in the data read / write controller according to the configuration command includes: parsing the configuration command to identify the object to be updated; the object to be updated includes one of a command field register, a frame format register, or a state machine register; and updating the configuration information of the object to be updated according to the configuration command.

3. The data read / write control method according to claim 2, characterized in that, The step of updating the configuration information of the update object according to the configuration command includes: if the update object is a command field register, then writing the command opcode carried by the configuration command into the corresponding command field register; wherein, the command opcode is used to indicate the type of operation that the data read / write controller needs to perform; if the update object is a frame format register, then updating the command frame format in the frame format register according to the structure parameters carried by the configuration command; wherein, the structure parameters are used to indicate the structure of the command frame.

4. The data read / write control method according to claim 3, characterized in that, The step of generating a command frame conforming to the format requirements of the target memory based on the updated configuration information includes: responding to the data access command issued by the user, determining the operation state according to the state transition rules in the state machine register; the operation state is used to indicate the stage or state during the execution of data read / write operations; and generating a corresponding command frame based on the operation state.

5. The data read / write control method according to claim 4, characterized in that, The step of generating a corresponding command frame based on the operation state includes: obtaining the command opcode and command frame format based on the command field register and frame format register corresponding to the operation state, respectively; and assembling the command frame corresponding to the operation state based on the command opcode and the command frame format.

6. The data read / write control method according to claim 4, characterized in that, The method further includes: selectively skipping one or more states in the operation states according to the configuration information in the state machine register; and / or refreshing the format of the command frame generated in the specific state according to the command opcode stored in the command field register when the state machine is in a specific state.

7. The data read / write control method according to claim 4, characterized in that, The state transition rules include: when performing an erase operation, the state machine is controlled to enter the write enable state and send an enable command before entering the erase command sending state; after sending the enable command, the state machine is controlled to perform one of the following operations: directly jump from the write enable state to the erase command sending state; or jump from the write enable state to the state read state, and after confirming that the write enable is successful, jump to the erase command sending state.

8. The data read / write control method according to claim 4, characterized in that, The state transition rules also include: when performing a write operation, the state machine is controlled to enter the write enable state and send an enable command before entering the write command sending state; after sending the enable command, the state machine is controlled to perform one of the following operations: directly jump from the write enable state to the write command sending state; or jump from the write enable state to the state read state, and after confirming that the write enable is successful, jump to the write command sending state.

9. A data read / write controller, characterized in that, include: The user-side serial port is used to receive operation commands issued by the user. A read / write control module, connected to the user-side transceiver serial port, is used to decode the operation commands to distinguish between configuration commands and data access commands. If the command type is a data access command, data read / write operations are performed according to the data access command. If the command type is a configuration command, the configuration information currently stored in the data read / write controller is updated according to the configuration command. The configuration command includes the format requirements of the target memory. If the update object is a state machine register, the configuration information in the state machine register is updated according to the control parameters carried by the configuration command. The control parameters are used to indicate the state transition rules of the state machine in the state machine register. A command frame conforming to the format requirements of the target memory is generated based on the updated configuration information. The data forwarding serial port is connected to the read / write control module and is used to execute corresponding data read / write operations based on the command frame.

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