Accelerating devices, systems, and methods

Abstract

The application discloses an acceleration device, system and method, especially relates to the field of accelerating calculation, and includes a control state register module configured to store the read address, write address, read data length, write data length and read operation mask of each calculation subunit; a packet filtering module configured to identify the write access request of a host to a target storage area, analyze the payload of the write access request, and update the control state register module according to the analysis result; a direct memory access module configured to read input data according to the read address and read data length, and write output data back to a non-target storage area according to the write address and write data length after calculation is completed; and a state machine module configured to send an interrupt signal to the host through a calculation express interconnection input and output protocol to inform the host to read the output data from the non-target storage area. Therefore, the problem of high data transmission delay in the prior art can be solved, and the technical effect of reducing data transmission delay is achieved.

Description

Technical Field

[0001] This application relates to the field of accelerated computing technology, and in particular to an acceleration device, system and method. Background Technology

[0002] In related asymmetric encryption and decryption computation schemes, software implementation of a central processing unit (CPU) is usually relied upon, or hardware acceleration is provided by smart network cards based on the Peripheral Component Interconnect Express (PCIe) protocol. Whether it is a traditional acceleration device based on the PCIe protocol or an acceleration device based on the Compute Express Link (CXL) protocol, when the host configures, starts and manages the acceleration device for asymmetric encryption and decryption, it usually needs to perform control operations through the PCIe or Compute Express Link I / O (CXL.io) protocol. The host and the device cannot directly access each other's memory, but need to move data, which leads to high data transmission latency. Summary of the Invention

[0003] This application provides an acceleration device, system, and method to at least solve the problem of high data transmission latency in related technologies.

[0004] The first aspect of this application provides an acceleration device that is connected to a host via a computational fast interconnect, including a control status register module, a packet filtering module, a direct memory access module, an asymmetric encryption / decryption module, and a state machine module. The asymmetric encryption / decryption module includes multiple parallel asymmetric encryption / decryption computation subunits.

[0005] The control status register module is configured to store the read address, write address, read data length, write data length, and read operation mask for each asymmetric encryption / decryption computation subunit;

[0006] The packet filtering module is configured to identify write access requests from the host to the target storage area in the device memory via the Fast Interconnect Memory Protocol, and to parse the payload of the write access request in order to update the control status register module based on the parsing result in the payload. The address range of the target storage area is configured by the host via the Fast Interconnect Input / Output Protocol.

[0007] The direct memory access module is configured to read input data from a non-target memory area in the device memory according to the read address and read data length in the control status register module, and write the output data back to the non-target memory area in the device memory according to the write address and write data length after the calculation is completed.

[0008] The state machine module is configured to send an interrupt signal to the host via the compute fast interconnect input / output protocol after the asymmetric encryption / decryption computation subunit enabled by the read operation mask has completed its computation, in order to notify the host to read output data from a non-target storage area in the device memory.

[0009] Optionally, the packet filtering module includes a filtering configuration module and a packet parsing module. The filtering configuration module includes an upper address bound register and an lower address bound register.

[0010] The filtering configuration module is configured to identify write access requests from the host to the target storage area in the device memory via the Compute Fast Interconnect Memory Protocol, and send the write access requests to the packet parsing module.

[0011] The packet parsing module is configured to parse the payload of write access requests in order to update the control status register module based on the parsing results in the payload.

[0012] Optionally, the parsing results in the payload include an opcode field, a value array field, and a selection mask field. The opcode field is used to specify the configuration operation type for the control status register module. The configuration operation type includes register configuration operation, direct memory access triggered operation, or status query operation. The value array field is used to specify the register value to be written when performing a register configuration operation. The selection mask field is used to select the asymmetric encryption / decryption computation subunit to participate in this operation.

[0013] Optionally, the control status register module includes read / write registers and control registers. The read / write registers include at least a read address register, a read data length register, a read operation mask register, a direct memory access read operation register, a write address register, and a write data length register. The control registers include at least a reset register and a computation subunit status register.

[0014] Optionally, the acceleration device also includes a cache module, which includes an input cache submodule and an output cache submodule. The number of input cache submodules and the number of output cache submodules are the same as the number of asymmetric encryption and decryption computation subunits. Each asymmetric encryption and decryption computation subunit corresponds to one input cache submodule and one output cache submodule, respectively.

[0015] The input caching submodule is configured to cache the input data of the corresponding asymmetric encryption / decryption computation subunit;

[0016] The output buffer submodule is configured to buffer the output data of the corresponding asymmetric encryption / decryption calculation subunit.

[0017] Optionally, the state machine module is also configured to monitor the direct memory access read operation register in the idle state, and in response to the direct memory access read operation register being written with a first identifier value, control the direct memory access module to read input data from the non-target storage area of ​​the device memory to the input buffer submodule; in response to the value of the direct memory access read operation register being a second identifier value, start the asymmetric encryption / decryption computation subunit specified by the read operation mask to perform the operation; and in response to the computation subunit status register of the asymmetric encryption / decryption computation subunit specified by the read operation mask being a third identifier value, control the direct memory access module to write the output data from the output buffer submodule back to the non-target storage area of ​​the device memory.

[0018] Optionally, the cache consistency mode of the target storage region is host-biased mode.

[0019] Optionally, the asymmetric encryption / decryption module uses the elliptic curve key negotiation algorithm for asymmetric encryption / decryption.

[0020] The second aspect of this application provides an acceleration system, including a host and the acceleration device of any one of the first aspects.

[0021] A third aspect of this application provides an acceleration method, comprising:

[0022] The host identifies write access requests to the target storage area in the device memory by calculating the Fast Interconnect Memory Protocol and parses the payload of the write access request. The control status register module is updated according to the parsing result in the payload. The address range of the target storage area is configured by the host by calculating the Fast Interconnect Input / Output Protocol. The control status register module stores the read address, write address, read data length, write data length and read operation mask of each asymmetric encryption / decryption calculation subunit.

[0023] Based on the read address and read data length in the control status register module, the input data is read from the non-target storage area in the device memory, and after the calculation is completed, the output data is written back to the non-target storage area in the device memory based on the write address and write data length.

[0024] After the asymmetric encryption / decryption computation subunit enabled by the read operation mask completes the computation, it sends an interrupt signal to the host via the computation fast interconnect input / output protocol to notify the host to read the output data from the non-target storage area of ​​the device memory.

[0025] The acceleration device, system, and method provided in this application are connected to a host via Compute Fast Interconnect (CHI). The acceleration device includes a control status register module, a packet filtering module, a direct memory access (DMI) module, an asymmetric encryption / decryption module, and a state machine module. The asymmetric encryption / decryption module includes multiple parallel asymmetric encryption / decryption computation subunits. The control status register module is configured to store the read address, write address, read data length, write data length, and read operation mask for each asymmetric encryption / decryption computation subunit. The packet filtering module is configured to identify write access requests from the host to a target storage area in the device's memory via CHI, and to parse the payload of the write access request. The control status register module is updated based on the parsing result in the payload. The address range of the target storage area is determined by the host via CHI. Input / output protocol configuration; Direct Memory Access (DMI) module, configured to read input data from the non-target memory area of ​​the device memory according to the read address and read data length in the control status register module, and write the output data back to the non-target memory area of ​​the device memory according to the write address and write data length after the calculation is completed; State machine module, configured to send an interrupt signal to the host through the compute fast interconnect input / output protocol after the asymmetric encryption / decryption calculation subunit enabled by the read operation mask completes the calculation, so as to notify the host to read the output data from the non-target memory area of ​​the device memory. By adopting the compute fast interconnect memory protocol, the host can configure and manage the accelerated device, so that the device memory and the host memory can be used as a unified address space, reducing redundant data movement operations and thus reducing data transmission latency. Attached Figure Description

[0026] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of an acceleration device in a related solution provided in an embodiment of this application;

[0028] Figure 2 A schematic diagram illustrating latency and bandwidth test results provided in an embodiment of this application;

[0029] Figure 3 This is a schematic diagram of the structure of an acceleration device provided in an embodiment of this application;

[0030] Figure 4 This is a schematic diagram of the structure of a packet filtering module provided in an embodiment of this application;

[0031] Figure 5A schematic diagram of a payload provided in an embodiment of this application;

[0032] Figure 6 This is a schematic diagram of the structure of an acceleration system provided in an embodiment of this application;

[0033] Figure 7 This is a flowchart illustrating an acceleration method provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0035] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0036] To facilitate a better understanding of the technical solutions described in the embodiments of this disclosure by those skilled in the art, the technical terms in the embodiments of this disclosure are explained as follows before introducing the embodiments of this disclosure.

[0037] PCIe refers to the high-speed interconnect channel between the host and the device.

[0038] Direct Memory Access (DMA): A hardware data transfer mechanism that allows peripherals to bypass the CPU and directly read and write host memory, used for efficient data transfer and reducing CPU load.

[0039] CXL is a new high-speed interconnect protocol built on top of the PCIe physical layer. Its core objective is to enable CPUs, memory, and various computing accelerators, such as graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and artificial intelligence (AI) chips, to communicate with each other in a shared memory and cache-coherent manner, thereby significantly reducing latency, reducing data copying, and improving overall system performance and resource utilization.

[0040] The CXL protocol consists of three sub-protocols: CXL.io, the Compute Fast Interconnect Cache Protocol (CXL.cache), and CXL.mem. CXL.io, PCIe compatible, is used for control operations such as configuration, interrupts, and register access. CXL.mem allows the host to access device memory via memory read / write, supports cache coherency, and has significantly lower latency than traditional Memory-Mapped Input / Output (MMIO). Based on the functions of these three sub-protocols, CXL defines three device types. Type-1 is a lightweight accelerator with no local memory, accessing only host memory and supporting only the CXL.io protocol. Type-2 is a device with both computing power and local memory, such as a GPU or FPGA. It can access both host memory and allow the host to access its own memory, and there is cache coherency between the device and the host. It supports the CXL.io, CXL.cache, and CXL.mem protocols. Type-3 is a pure memory device, supporting both CXL.io and CXL.mem protocols, used to expand or share system memory capacity. Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of an acceleration device in a related solution provided in an embodiment of this application. The device is a type-2 device. The type-2 device has all the features of the CXL protocol, which allows the host and the device to share their respective memory. That is, the host / device can directly access the memory on the host / device side, and can also directly access the memory on the device / host side. Furthermore, there is cache consistency between the host and the device.

[0041] It should be noted that, in order to be compatible with existing PCIe physical interfaces, regardless of whether the CXL protocol or the PCIe protocol is used, the underlying physical link is still in the form of PCIe.

[0042] CXL.io is essentially equivalent to the traditional PCIe protocol and is a mandatory component for all types of CXL devices. Existing research indicates that in type-2 devices, when the data volume is small, host-to-device (H2D) memory access offers a significant latency advantage over the PCIe protocol. Figure 2 As shown, Figure 2 This diagram illustrates the latency and bandwidth test results provided in an embodiment of this application. In the upper part of the diagram, the circular and triangular nodes represent the latency of two H2D protocols based on PCIe, while the gray area represents the memory access latency of H2D based on the CXL protocol. It can be observed that when the data volume is less than 1KB, the performance (small square lines) of H2D under the CXL protocol has a higher latency than that under the PCIe protocol. Figure 2 The bandwidth performance of CXL protocol's H2D is lower than that of PCIe-DMA (both circular and triangular nodes). Figure 2 The lower circular node line is also consistent with the memory-mapped I / O access method via the PCIe bus, i.e., PCIe-MMIO ( Figure 2 The lines of the triangle nodes are close together. Therefore, for H2D, i.e., host-to-memory access to device memory operations, the CXL protocol has a latency advantage when dealing with small amounts of data.

[0043] For Device to Host (D2H) memory access operations, the latency performance of the CXL protocol is worse than or equal to that of the PCIe-DMA protocol, regardless of the data volume. However, the bandwidth performance of the CXL protocol is inferior to that of PCIe-DMA. Therefore, for D2H operations, the CXL protocol offers lower latency but lower bandwidth regardless of the data volume. The CXL protocol is also more suitable for D2H operations with smaller data volumes.

[0044] When devices are based on the traditional PCIe protocol, the host and device cannot directly access each other's memory; instead, data migration is required. For example, when an accelerator device needs to use data in the host's memory, the host CPU needs to move the data from the host memory to the device's memory via the PCIe protocol for the accelerator device to use; conversely, when the host needs to use data in the device's memory, the host CPU needs to move the data from the device's memory to the host memory via the PCIe protocol. Therefore, PCIe-based hosts and devices naturally require an additional data migration step compared to CXL-based hosts and devices when they need to access data in each other's memory.

[0045] Asymmetric encryption and decryption are security algorithms widely used in network communication protocol stacks. Compared to symmetric encryption and decryption algorithms like Advanced Encryption Standard (AES), which have large input and output data, asymmetric encryption and decryption algorithms typically use small data sets of a few hundred bytes, but their computational complexity is far greater. Therefore, traditional CPUs usually have built-in hardware accelerators for symmetric encryption and decryption algorithms like AES, while asymmetric encryption and decryption are implemented using software programming. Asymmetric encryption and decryption typically occur during the stage of establishing a communication link between two parties. For example, when a user opens a webpage, they are essentially establishing a communication link with the web service provider. In real-world applications, there are often numerous communication links established concurrently.

[0046] Some current smart network interface cards (NICs) offer hardware acceleration for asymmetric encryption and decryption based on the PCIe protocol. This means that the non-interface encryption and decryption calculations originally handled by the CPU are offloaded to the smart NIC via the PCIe protocol. However, as mentioned before, the redundant data transfer operations of the PCIe protocol introduce additional communication latency. Furthermore, the frequent small-data-volume communications between the host and device in asymmetric encryption and decryption scenarios exacerbate this problem, as the communication latency of the PCIe protocol is higher than that of CXL for small data volumes.

[0047] On the other hand, even for accelerator devices that use the CXL protocol, the host still usually relies on the CXL.io protocol (equivalent to the PCIe protocol) to configure, start, and manage the accelerator device. The communication latency of CXL.io between the host and the device is usually about 1 microsecond, while the communication latency of CXL.mem is about 300 nanoseconds. In high-concurrency asymmetric encryption and decryption scenarios, the latency of CXL.io is relatively high.

[0048] In summary, existing asymmetric encryption and decryption implementations rely on CPU software programming or hardware acceleration provided by PCIe-based smart network cards, which presents the following problems:

[0049] 1. Solutions based on CPU software programming require CPU time and are inefficient;

[0050] 2. Hardware accelerators based on the PCIe protocol, such as smart network cards, not only require additional data transfer operations, but also have higher communication latency than the CXL protocol when transferring small amounts of data.

[0051] 3. Whether it is a traditional PCIe-based device or a CXL-based device, the host usually needs to use the high-latency PCIe / CXL.io protocol when configuring, starting and managing the accelerator device for asymmetric encryption and decryption.

[0052] To address the technical issues in related solutions, this application provides an acceleration device that connects to a host via compute-fast interconnect, including a control status register module, a packet filtering module, a direct memory access module, an asymmetric encryption / decryption module, and a state machine module. The asymmetric encryption / decryption module comprises multiple parallel asymmetric encryption / decryption computation subunits. The control status register module is configured to store the read address, write address, read data length, write data length, and read operation mask for each asymmetric encryption / decryption computation subunit. The packet filtering module is configured to identify write access requests from the host to a target storage area in the device's memory via compute-fast interconnect memory protocol, and to parse the payload of the write access request to update the control status register module based on the parsing result in the payload. The address range of the target storage area is determined by the host via compute-fast interconnect memory protocol. Interconnect input / output protocol configuration; Direct Memory Access module, configured to read input data from the non-target memory area of ​​the device memory according to the read address and read data length in the control status register module, and write the output data back to the non-target memory area of ​​the device memory according to the write address and write data length after the calculation is completed; State machine module, configured to send an interrupt signal to the host through the compute fast interconnect input / output protocol after the asymmetric encryption / decryption calculation subunit enabled by the read operation mask completes the calculation, so as to notify the host to read the output data from the non-target memory area of ​​the device memory. By adopting the compute fast interconnect memory protocol, the host configuration and management of the accelerated device is realized, so that the device memory and the host memory can be used as a unified address space, reducing redundant data movement operations, thereby reducing data transmission latency.

[0053] The acceleration device provided in this disclosure can be applied to scenarios such as high-concurrency network services, cloud computing, distributed storage, and data security.

[0054] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] Figure 3 This is a schematic diagram of the structure of an acceleration device provided in an embodiment of this disclosure.

[0056] like Figure 3 As shown, the acceleration device connects to the host via computational fast interconnect and includes a control status register module, a packet filtering module, a direct memory access module, an asymmetric encryption / decryption module, and a state machine module. The asymmetric encryption / decryption module includes multiple parallel asymmetric encryption / decryption computation subunits.

[0057] The control status register module is configured to store the read address, write address, read data length, write data length, and read operation mask for each asymmetric encryption / decryption computation subunit;

[0058] The packet filtering module is configured to identify write access requests from the host to the target storage area in the device memory via the Fast Interconnect Memory Protocol, and to parse the payload of the write access request in order to update the control status register module based on the parsing result in the payload. The address range of the target storage area is configured by the host via the Fast Interconnect Input / Output Protocol.

[0059] The direct memory access module is configured to read input data from a non-target memory area in the device memory according to the read address and read data length in the control status register module, and write the output data back to the non-target memory area in the device memory according to the write address and write data length after the calculation is completed.

[0060] The state machine module is configured to send an interrupt signal to the host via the compute fast interconnect input / output protocol after the asymmetric encryption / decryption computation subunit enabled by the read operation mask has completed its computation, in order to notify the host to read output data from a non-target storage area in the device memory.

[0061] In some embodiments, the target storage area is a special area in the device memory used to receive write access requests sent by the host through the Compute Fast Interconnect Memory Protocol, i.e., CXL.mem. The address range of the target storage area is configured by the host through the Compute Fast Interconnect Input / Output Protocol, i.e., CXL.io. For ease of description, the target storage area will be referred to as the Special Memory Input / Output (SMIO) area. The non-target storage area refers to the memory area in the device memory other than the SMIO area, i.e., the non-SMIO area. The non-SMIO area is used to store actual input data and output data, such as keys and public keys.

[0062] In some embodiments, each asymmetric encryption / decryption computation subunit can independently execute an elliptic curve algorithm, supporting parallel batch processing.

[0063] In some embodiments, each bit of the read operation mask corresponds to an asymmetric encryption / decryption computation subunit, with 1 indicating enabled and 0 indicating disabled, used to select the asymmetric encryption / decryption computation subunit to participate in this round of computation.

[0064] In some embodiments, by monitoring the CXL.mem bus, it is determined whether the destination address in the write access request belongs to the address range of the SMIO region, thereby identifying the host's write access request to the target storage region in the device memory through the calculation of the Fast Interconnect Memory Protocol.

[0065] In some embodiments, the interrupt signal may be a message signaled interrupt (MSI) or a message signaled interrupt eXtended (MSI-X), and this application does not limit it to this.

[0066] In some embodiments, the transmission of write access requests is migrated from a traditional high-latency path to a low-latency memory access path, thereby optimizing the interaction efficiency between the host and the acceleration device, especially for small-data-volume, high-concurrency computing tasks. The acceleration device in this application connects to the host via a compute-fast interconnect and integrates key functional modules: a Control Status Register (CSR) module for centralized management and storage of resource configuration parameters for each computing unit, including but not limited to data address, length, and enable flags; a packet filtering module, acting as the intelligent scheduling center of the communication interface, dynamically identifies and intercepts write access requests sent by the host to specific target areas in the device's memory via the CXL.mem protocol based on the host's preset address range, parses the payload in the request, and converts it into an update operation for the CSR module. This mechanism replaces the traditional configuration method via the CXL.io protocol; a DMA module responds to the configuration state of the CSR module, transferring input and output data between the device's memory and internal computing units; and a state machine module, acting as the control center, coordinates the entire lifecycle of the computing task and notifies the host of the result via the CXL.io protocol upon task completion. The acceleration device also includes an asymmetric encryption / decryption module with multiple parallel computing subunits to support high-concurrency processing.

[0067] This application first leverages the inherent latency advantage of the CXL.mem protocol compared to the CXL.io / PCIe protocol to transmit write access requests, reducing the overhead of host configuration, startup, and management of acceleration devices, making it particularly suitable for scenarios with frequent interactions involving small amounts of data. Secondly, by using packet filtering and parsing mechanisms to convert write access requests into configuration commands for the CSR module, the interaction process is simplified, avoiding the necessary data transfer operations in traditional solutions, further reducing system latency and improving overall throughput.

[0068] In some embodiments, the packet filtering module includes a filtering configuration module and a packet parsing module, and the filtering configuration module includes an upper address bound register and an lower address bound register.

[0069] The filtering configuration module is configured to identify write access requests from the host to the target storage area in the device memory via the Compute Fast Interconnect Memory Protocol, and send the write access requests to the packet parsing module.

[0070] The packet parsing module is configured to parse the payload of write access requests in order to update the control status register module based on the parsing results in the payload.

[0071] In some embodiments, the upper address bound register and the lower address bound register are two programmable registers that are written by the host during the system initialization phase via the CXL.io protocol to define the address range of the SMIO region.

[0072] In some embodiments, leveraging the PCIe compatibility of CXL.io, registers can be written via the standard PCIe configuration cycle or via device-specific configuration registers defined by CXL.

[0073] Furthermore, the size and location of the SMIO region can be dynamically configured by the host via CXL.io, adapting to different system memory layouts.

[0074] In some embodiments, the filtering configuration module is a submodule of the packet filtering module, which determines whether the CXL.mem write access request hits the SMIO region by comparing the target address of the write access request with the address range of the SMIO region.

[0075] In some embodiments, the packet parsing module is another submodule of the packet filtering module, responsible for parsing the payload of the CXL.mem write access request that hits the SMIO region.

[0076] In some embodiments, such as Figure 4 As shown, Figure 4 This is a schematic diagram of a packet filtering module provided in an embodiment of this application. It includes a filtering configuration module and a packet parsing / encapsulation module (i.e., the packet parsing module in this application). The packet parsing module is used to configure the CSR module, bypass (skip certain operations), accelerator (i.e., acceleration device) reset, and response encapsulation (after completing the configuration, generate the corresponding response signal to ensure protocol integrity). Specifically, the filtering configuration module determines whether the current write access request is a target control area (SMIO area) based on the address range. If it is a match, it forwards the request to the packet parsing / encapsulation module. The packet parsing / encapsulation module parses the payload and updates the control status register module according to the parsing result.

[0077] In some embodiments, the parsed results in the payload are typically in a fixed format, such as 64 bytes, including but not limited to opcode fields, value array fields, and selection mask fields.

[0078] In some embodiments, after the host writes to the SMIO area via CXL.mem, the hardware automatically completes the parsing and register update without driver or operating system intervention.

[0079] In some embodiments, the parsing result in the payload includes an opcode field, a value array field, and a selection mask field. The opcode field is used to specify the configuration operation type for the control status register module. The configuration operation type includes register configuration operation, direct memory access triggered operation, or status query operation. The value array field is used to specify the register value to be written when performing the register configuration operation. The selection mask field is used to select the asymmetric encryption / decryption computation subunit to participate in this operation.

[0080] In some embodiments, such as Figure 5 As shown, Figure 5 The schematic diagram of a payload provided in the embodiments of this application includes an opcode field (CSR Op field), a value array field (CSR Val Array field), and a selection mask field (CSRSel Array field). The CSR Val Array field is used to carry specific numerical parameters, such as address, data length, etc., and its length is usually matched with the number of computation subunits.

[0081] In some embodiments, register configuration operation refers to writing data from the value array into a control status register, such as the read address register or the read data length register. Direct memory access triggered operation refers to starting the DMA module and beginning data transfer by writing a specific opcode (e.g., CSR Op is 8'd3). This operation typically ignores the value array and the selection mask.

[0082] In some embodiments, a status query operation refers to the host reading the device status, such as whether each asymmetric encryption / decryption computation subunit has completed the computation. In this application, this can be achieved by triggering a status readback or a CXL.io read operation through a write access request.

[0083] In some embodiments, the opcode mechanism makes the protocol well maintainable, and opcodes can be added in the future to support new functions, such as performance counters.

[0084] In some embodiments, multiple asymmetric encryption / decryption computation subunits can be configured with a single CXL.mem write access request by using the opcode field, value array field, and selection mask field, thus avoiding the overhead of writing one by one.

[0085] In some embodiments, the upper and lower address bound registers are configured by the host during system initialization via the CXL.io protocol, jointly defining a specific target storage area in the device memory, namely the SMIO region. The filtering configuration module continuously monitors all write access requests from the host via the CXL.mem protocol, identifies requests whose target addresses fall within the SMIO region as control operations on the accelerated device, and forwards them to the packet parsing module for processing. The packet parsing module is responsible for parsing the payload of the CXL.mem write access request. This payload has a specific format and includes three key fields: the opcode (CSR Op) field, the value array (CSR Val Array) field, and the selection mask array (CSR Sel Array) field. The opcode field is 8 bits wide and is used to precisely specify the operation type. For example, 8'd0 to 8'd5 correspond to configuring the read address, read data length, read operation mask, configuring DMA read operation, configuring the write address, and configuring the write data length register, respectively, and 8'd6 corresponds to the read computation subunit status register. The value array field is a collection of NUM_ENC 64-bit values, providing the specific values ​​to be written during write configuration operations. The selection mask array field is a collection of NUM_ENC 1-bit values, where each bit corresponds to a computational sub-unit, used for batch selection of one or more computational sub-units involved in the current operation. The packet parsing module, based on the parsed opcode and in conjunction with the selection mask array and value array, performs precise batch updates to the corresponding registers in the control status register module.

[0086] In some embodiments, address filtering and protocol parsing mechanisms are used to convert general memory write operations into configuration instructions for accelerated devices, achieving low-latency transmission. The use of a field-based payload structure, particularly the selection mask array, supports parallel and selective configuration of multiple computing units, improving control efficiency and flexibility.

[0087] In some embodiments, the control status register module includes a read / write register and a control register. The read / write register includes at least a read address register, a read data length register, a read operation mask register, a direct memory access read operation register, a write address register, and a write data length register. The control register includes at least a reset register and a computation subunit status register.

[0088] In some embodiments, a read address register is configured to store the address of the input data of the asymmetric encryption / decryption computation subunit in the device memory; a read data length register is configured to store the data length of the input data; a read operation mask register is configured to indicate the asymmetric encryption / decryption computation subunit participating in the current operation in the form of bits, wherein each bit corresponds to one asymmetric encryption / decryption computation subunit; a direct memory access read operation register is configured to trigger the direct memory access module to read the input data from the address specified by the read address register when a valid value is written; a write address register is configured to store the target address of the output data of the asymmetric encryption / decryption computation subunit in the device memory; and a write data length register is configured to store the data length of the output data.

[0089] In some embodiments, the reset register is configured to reset the state of the asymmetric encryption / decryption computation subunit; the computation subunit status register is configured to store the current working state of the corresponding asymmetric encryption / decryption computation subunit, the current working state including idle state, computation in progress state and result pending write-back state, and the current working state is determined by at least two status codes.

[0090] In some embodiments, the two-bit status code has a width of 2 bits: 2'b00, 2'b01, 2'b10, and 2'b11. Three of these four can be used to represent the idle state, the computational state, and the result pending write-back state. Specifically, 2'b00, 2'b01, and 2'b10 can represent the idle state, the result pending write-back state, and the computational state, respectively; alternatively, 2'b01, 2'b10, and 2'b11 can represent the idle state, the result pending write-back state, and the computational state, respectively.

[0091] In some embodiments, by independently addressing and managing the key parameters of each computing subunit, fine-grained control and status monitoring of computing tasks are achieved, ensuring the accuracy of multi-task parallel processing.

[0092] In some embodiments, the acceleration device further includes a cache module, which includes an input cache submodule and an output cache submodule. The number of input cache submodules and the number of output cache submodules are the same as the number of asymmetric encryption / decryption computation subunits. Each asymmetric encryption / decryption computation subunit corresponds to one input cache submodule and one output cache submodule, respectively.

[0093] The input caching submodule is configured to cache the input data of the corresponding asymmetric encryption / decryption computation subunit;

[0094] The output buffer submodule is configured to buffer the output data of the corresponding asymmetric encryption / decryption calculation subunit.

[0095] In some embodiments, the cache module is a high-speed storage unit inside the acceleration device used to temporarily store computation input data and output data. It is a dedicated data buffer used to decouple the speed difference between DMA and the computing engine. The input cache submodule is a dedicated input data temporary storage area for each asymmetric encryption / decryption computation subunit, used to store input data read from non-SMIO areas, such as a 64-byte private key. The output cache submodule is a dedicated result temporary storage area for each asymmetric encryption / decryption computation subunit, used to store output data after computation, such as a 32-byte shared key.

[0096] In some embodiments, resource contention can be avoided by having each asymmetric encryption / decryption computation subunit correspond to an input buffer submodule and an output buffer submodule, respectively.

[0097] In some embodiments, the DMA module can preload input data into the input buffer, so that the asymmetric encryption / decryption computation subunit can start performing asymmetric encryption / decryption operations without waiting for the bus transaction to complete.

[0098] In some embodiments, the aforementioned caching module decouples the data transfer process of DMA from the computation process of the computation subunit, allowing data prefetching and computation to be performed in parallel, thus hiding memory access latency.

[0099] In some embodiments, the state machine module is further configured to monitor the direct memory access read operation register in an idle state, and in response to the direct memory access read operation register being written with a first identifier value, control the direct memory access module to read input data from a non-target storage area of ​​the device memory to the input buffer submodule, in response to the value of the direct memory access read operation register being a second identifier value, start the asymmetric encryption / decryption computation subunit specified by the read operation mask to perform operations, and in response to the computation subunit status register of the asymmetric encryption / decryption computation subunit specified by the read operation mask being a third identifier value, control the direct memory access module to write output data from the output buffer submodule back to the non-target storage area of ​​the device memory.

[0100] In some embodiments, the state machine module is the control core inside the acceleration device, used to coordinate the operation timing between DMA, asymmetric encryption / decryption calculation subunits, and cache modules.

[0101] In some embodiments, the idle state refers to the initial or waiting state of the state machine, where the device has completed the previous round of tasks and is waiting for a new task to be triggered.

[0102] In some embodiments, the first identifier value is a command value used to initiate the DMA read operation register to read input data, which is typically 1 or a non-zero value. The second identifier value is a value used to indicate that the DMA read operation register reading is complete and automatically jumps to the next step, which is typically 0.

[0103] In some embodiments, the state machine continuously polls the DMA read operation register or detects the DMA read operation register by edge detection. If a 1 is detected written to the DMA read operation register, the state machine enters the read data state.

[0104] In some embodiments, the DMA module reads data from the non-target storage area according to the read address, length, and mask in the CSR module, and writes the data into the input buffer submodule of the corresponding subunit.

[0105] In some embodiments, the state machine reads the DMA read operation mask register, sends a start signal to the corresponding computation subunit for each bit in the mask that is 1, the computation subunit reads the input data from the input buffer submodule, starts the asymmetric encryption and decryption operation, and the subunit status register is updated to compute or working, such as 2'b10.

[0106] In some embodiments, the third identifier value is the completion status code in the status register of the asymmetric encryption / decryption computation subunit, typically 2'b01.

[0107] In some embodiments, the state machine continuously monitors the status registers of all masked sub-units. When all corresponding status registers are 2'b01, it enters the result pending write-back state, controls the DMA to read the result from the output buffer, and writes it back to the non-SMIO area.

[0108] For example, in the idle state, the DMA read operation register is monitored. When it is set to the first flag value of 1, the state machine transitions to the read data state and notifies the DMA module to start working. The DMA module moves data from the target area of ​​the device memory to the input buffer submodule corresponding to each enabled subunit according to the read operation mask register, read address register, and read data length register. When the DMA read is complete (the DMA read operation register is automatically cleared, i.e., the second flag value is 0), the state machine jumps to the calculation state and starts the corresponding calculation subunit according to the read operation mask. The state machine continuously monitors the status registers of each enabled subunit. When they all change to the third flag value 2'b01, i.e., the calculation is complete, the state machine enters the result-pending-write-back state and commands the DMA module to write the data from each output buffer submodule back to the target address in the device memory. Further, after the write-back is complete, the state machine enters the result notification state, initiates an interrupt via the CXL.io protocol, and finally returns to the idle state.

[0109] In some embodiments, the cache consistency mode of the target storage region is host-biased mode.

[0110] In some embodiments, host bias mode is a cache consistency strategy for CXL device memory, which means that the memory region is owned by the host CPU by default. When the device accesses it, it needs to request the latest data through CXL.cache. After the host writes, the device can see the update immediately without additional synchronization operations.

[0111] In some embodiments, by setting the cache consistency mode of the target storage region to host-biased mode, data written by the host via the CXL.mem protocol can be immediately perceived by the device without any explicit cache flushing or memory barrier operations, thereby reducing data transmission latency.

[0112] In some embodiments, the asymmetric encryption / decryption module uses an elliptic curve key negotiation algorithm for encryption / decryption.

[0113] In some embodiments, the elliptic curve key negotiation algorithm can be the X25519 key exchange algorithm (Elliptic Curve Diffie-Hellman over Curve25519, X25519) elliptic curve algorithm, or the Elliptic Curve Diffie-Hellman (ECDH) algorithm, and this application does not limit it.

[0114] This disclosure also provides an acceleration system, including a host and any of the above-described acceleration devices.

[0115] In some embodiments, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of an acceleration system provided in an embodiment of this application. The host includes host memory and CPU, wherein the CPU includes host-side cache. The device includes CXL IP, accelerator device (acceleration device) and device memory. CXL IP is a commercial product provided by a vendor, which provides CXL protocol support for developers to develop various hardware. CXL IP includes device-side cache. The accelerator device includes packet filter module, memory controller module, CSR module, DMA module, cache module, asymmetric encryption / decryption module and state machine module.

[0116] It should be noted that, Figure 6 The asymmetric encryption / decryption module, not shown in the diagram, includes multiple parallel asymmetric encryption / decryption computation subunits.

[0117] like Figure 7 As shown, Figure 7 A flowchart illustrating an acceleration method provided in an embodiment of this application includes:

[0118] Step 701: Identify the host's write access request to the target storage area in the device memory through the calculation of the Fast Interconnect Memory Protocol, and parse the payload of the write access request. Update the control status register module according to the parsing result in the payload. The address range of the target storage area is configured by the host through the calculation of the Fast Interconnect Input / Output Protocol. The control status register module stores the read address, write address, read data length, write data length and read operation mask of each asymmetric encryption / decryption calculation subunit.

[0119] Step 702: Read input data from the non-target storage area in the device memory according to the read address and read data length in the control status register module, and write the output data back to the non-target storage area in the device memory according to the write address and write data length after the calculation is completed;

[0120] Step 703: After the asymmetric encryption / decryption computation subunit enabled by the read operation mask completes the computation, an interrupt signal is sent to the host via the computation fast interconnect input / output protocol to notify the host to read the output data from the non-target storage area of ​​the device memory.

[0121] In some embodiments, the control status register module includes: 1. Read / write data types: a) Read address registers: NUM_ENC in total, each 64 bits, representing the address of the input data of NUM_ENC asymmetric encryption / decryption calculation sub-modules; b) Read data length registers: NUM_ENC in total, each 32 bits, representing the length of the input data required by NUM_ENC asymmetric encryption / decryption calculation sub-modules; c) Read operation mask registers: NUN_ENC in total, each 1 bit; since there are NUM_ENC calculation sub-modules, and each round of calculation may not use all the calculation sub-modules, it is necessary to specify which calculation sub-modules to read input data; a value of 1 indicates that the current read operation will read the input data from the corresponding calculation sub-unit; d) DMA read operation registers: 1 in total, each 1 bit; representing whether to start the DMA module to move data from the address specified by the read address register to the cache, and the length of the moved data is specified by the read data length register. A value of 1 indicates startup. At this time, the DMA will read the corresponding input data into the buffer according to the read operation mask register, read address register, and read data length register. After the DMA module completes all data read operations, it will write this register to 0. e) Write address register: There are NUM_ENC read address registers, each 64 bits, representing the address of the output data of NUM_ENC asymmetric encryption and decryption calculation submodules. f) Write data length register: There are NUM_ENC registers, each 32 bits, representing the length of the output result data of NUM_ENC asymmetric encryption and decryption calculation submodules. Similarly, to maintain maximum compatibility, a sharing scheme is not adopted. 2. Logic control type (except for the reset register, other registers can only be read by the host): a) Reset register: 1, each 1 bit; when this register is written to 1, it forces all NUM_ENC calculation submodules to stop calculation and reset immediately; then this register will automatically become 0. b) Calculation subunit status register: NUM_ENC, each 2 bits wide; each corresponding to the status of NUM_ENC calculation subunits. 2'b00 indicates that the device is in an idle state, 2'b01 indicates that the device is not working but the previous result data is still in the cache and has not been written back to memory, and 2'b10 indicates that the device is working.

[0122] In some embodiments, the filtering configuration module mainly includes two registers: an upper address bound register and an lower address bound register. The host can access this module via the traditional CXL.io / PCIe protocol, read and write the module's registers, and specify the range of addresses to be filtered. The address range between the upper and lower address bounds is called SMIO memory. By comparing the addr field of the CXL.mem protocol with the upper and lower address bound registers, it is determined whether the memory region of the operation is located in the SMIO region. If so, it will be filtered by this module, and the payload will be handed over to the packet parsing / encapsulation module for parsing / encapsulation, executing the host configuration, startup, and management of accelerator devices operations encapsulated in CXL.mem. Operations accessing other memory regions will be directly forwarded to the memory controller module to execute normal CXL.mem operations.

[0123] 2) Packet parsing / encapsulation module: When the filtering configuration module determines that the current CXL.mem operation accesses SMIO memory, the packet parsing / encapsulation module will parse the payload of CXL.mem, where: 1) CSR Sel Array field: NUM_ENC, each 1 bit, each 1 bit represents that the operation will configure the corresponding register to the value of CSR Val Array; for example, assuming the current operation is to configure the read address register, when CSR Sel Array is 3, that is, only the lowest 2 bits are 1, then only the last and second to last values ​​in CSR Val Array will be written into the last and second to last registers of NUM_ENC read address registers. 2) CSR Val Array field: NUM_ENC entries, each 64 bits, because the maximum bit width of a single register in the CSR module is 64 bits; this field contains the values ​​of the configured NUM_ENC registers; only values ​​where the corresponding bit in the CSR Sel Array is 1 will be written to the register to be configured. 3) CSR Op field: 8 bits; its function is as described above. Figure 5As shown; based on the CSR Sel Array and CSR Val Array fields sent by the host, configure the read address register, read data length register, read operation mask register, DMA read operation register, write address register, and write data length register; when CSR Op == 8'd3, ignore the CSR Sel Array and CSR Val Array fields, and directly write the DMA read operation register to 1; when CSR Op == 8'd6, obtain the data from the computation subunit status register, encapsulate it according to the standard format, and return it to the CXL IP. When CSR Op == 8'd2, ignore the CSR Val Array field, and directly write the value of the CSR Sel Array field to the read operation mask register.

[0124] For CXL.mem operations that do not require parsing, they will be directly bypassed and processed by the standard memory controller module.

[0125] The cache module actually contains NUM_ENC × 2 cache sub-modules, numbered 0, 1, 2, ..., NUM_ENC × 2 - 1. Each computation sub-unit is allocated two cache sub-modules: one to store the input data needed for the computation, and the other to store the output data. That is, the 0th computation sub-unit is allocated the 0th and 1st cache sub-modules, the 1st computation sub-unit is allocated the 2nd and 3rd cache sub-modules, and so on. It's important to note that whether the computation sub-unit or the DMA module reads or writes to the cache sub-modules, the addresses start from 0; therefore, it's not necessary to configure the memory access addresses of the cache sub-modules.

[0126] Write cache module: For the 0th calculation sub-unit, the DMA module reads the amount of data specified by the 0th data length register from the address in the configured 0th read address register and puts it into the 0th cache sub-module; the calculation sub-module uses the data in the 0th cache sub-module to perform calculations and writes the calculation results into the 1st cache sub-module.

[0127] Read cache module: For the 0th calculation sub-unit, the DMA module reads the result data from the 1st cache sub-module according to the data length specified by the 0th write data length register, and writes this result data back to the address in the configured 0th write address register.

[0128] The state machine module is mainly responsible for the sequential control of the entire process, and includes the following states:

[0129] 1. Idle state: The current device is idle; in this state, if the DMA read operation register is detected to be 1, it will jump to the read data state; otherwise, it will remain in the idle state; in this state, each value of the calculation sub-unit status register is 2'b00.

[0130] 2. Read data state: This indicates that the DMA module is reading data from a given memory address and length into the corresponding input buffer. In this state, after detecting that the DMA read operation register is 0 (i.e., the DMA has completed all read data operations), it jumps to the calculation state. At the same time, the state machine module sets each value of the corresponding calculation subunit status register to 2'b10 according to whether the corresponding bit of the read operation mask register is 1, indicating that the corresponding calculation subunit is working.

[0131] 3. Calculation State: In this state, the state machine module will start the corresponding calculation subunit in the asymmetric encryption / decryption module to perform calculations based on whether the corresponding bit in the read operation mask register is 1. These calculation subunits will automatically read the data in the corresponding input buffer and perform calculations. After each calculation subunit completes the calculation, it will set its corresponding calculation subunit status register to 2'b01. The state machine module will check whether all the status registers of the calculation subunits specified by the read operation mask register are 2'b01. If so, it will jump to the result waiting to be written back state and set each value of the corresponding calculation subunit status register to 2'b01.

[0132] 4. Result Write-Back State: In this state, the state machine module will notify the DMA module to initiate the result data write-back operation. The DMA module will read the result data of the corresponding length from the corresponding output buffer according to the read operation mask register, write address register, and write data length register, and write it back to the specified SMIO memory address. After completing the write-back operation, the DMA module will set each value of the corresponding computation sub-unit status register to 2'b00. When the state machine module detects that each value of the corresponding computation sub-unit status register is set to 2'b00 in this state, it will jump to the result notification state.

[0133] 5. Result Notification State: In this state, the state machine module will notify the host that the computation has been completed through the standard interrupt mechanism of the CXL.io protocol, and then unconditionally jump to the idle state. The host can then directly use the result data from SMIO memory.

[0134] For example, the system has a total of NUM_ENC=32 X25519 elliptic curve asymmetric encryption / decryption computation subunits (each subunit has 64 bytes of input data and 32 bytes of output data), requiring a total of (64+32)×32=3072 bytes of memory. A certain round requires 16 X2559 elliptic curve (64 bytes of input, 32 bytes of output) asymmetric encryption / decryption subunits for computation. Assuming the base address of the memory used by the accelerator is ADDR_BASE, the overall workflow is as follows:

[0135] 1) The host sets the lower address bound register of the filter configuration module in the packet filter module to ADDR_BASE and the upper address bound register to ADDR_BASE+3072 via the CXL.io protocol. The operation latency for controlling the device via the CXL.io protocol will be relatively long, but after the system starts, this method is only needed when configuring the filter configuration module. Subsequent operations of the host to configure, start and manage the accelerator device will be implemented by accessing the SMIO memory area using CXL.mem. In addition, it is specified that the SMIO memory is physically a region of the device memory, and this memory region is set to the Host Bias mode defined by the CXL standard specification to achieve cache-consistent access between the host and the device for this region.

[0136] 2) The host will receive 16 64-byte input data packets via the network or generate them locally, and use H2D operations to store them sequentially at the starting address ADDR_BASE. That is, the starting address of the first 64-byte packet is ADDR_BASE, the starting address of the second 64-byte packet is ADDR_BASE+64, and so on, for a total of 16 starting addresses of input data. Similarly, the starting address of the first 32-byte output data is ADDR_BASE+16×64+32×0, the starting address of the second 32-byte output data is ADDR_BASE+16×64+32×1, and so on, for a total of 16 starting addresses of output data.

[0137] 3) The host sends multiple write operations sequentially to the SMIO memory region via the CXL.mem protocol: 1) Configure read address register operation. In the payload of this operation, CSR Op is set to 8'd0, and the CSR Sel Array field is 32'b0000_0000_0000_0000_1111_1111_1111_1111 (i.e., only 16 computation sub-units are used). In the CSR Val Array field, the first 16 64 bits of the high-order bits are 0, and the last 16 64 bits of the low-order bits store the starting addresses of 16 input data, which are used to assign values ​​to 16 read address registers; 2) Configure read data length register. In the payload of this operation, CSR Op is set to 8'd1, and CSR Sel The Array field is 32'b0000_0000_0000_0000_1111_1111_1111_1111 (i.e., only 16 computational sub-units are used). In the CSR Val Array field, the first 16 64 bits of the high-order bits are 0, and the last 16 64 bits of the low-order bits are all 64, meaning the length of the input data to be read is 64 bytes; 3) Configure the read operation mask register. In the payload of this operation, CSR Op is set to 8'd2, and the CSR Sel Array field is 32'b0000_0000_0000_0000_1111_1111_1111_1111 (i.e., only 16 computational sub-units are used). CSR Val Array is invalid in this operation, and the value of the CSR Sel Array field is directly written to the read operation mask register; 4) Configure the write address register: In the payload of this operation, CSR Op is set to 8'd4, and the CSR Sel Array field is 32'b0000_0000_0000_0000_1111_1111_1111_1111 (i.e., only 16 computational sub-units are used). In the CSR Val Array field, the first 16 high-order 64 bits are 0, and the last 16 low-order 64 bits store the starting addresses of 16 output data, which are used to assign values ​​to 16 write address registers; 5) Configure the write data length register. In the payload of this operation, CSR Op is set to 8'd5, and the CSR SelArray field is 32'b0000_0000_0000_0000_1111_1111_1111_1111 (i.e., only 16 computational sub-units are used), CSR Val In the Array field, the first 16 64 bits of the high-order bits are 0, and the last 16 64 bits of the low-order bits are all 32, meaning that the length of the output data to be written back is 32 bytes.6) Configure the DMA read operation register. In the payload of this operation, CSR Op is set to 8'd3, the other two fields are ignored, and the DMA read operation register is directly written to 1; the state machine module enters the read data state.

[0138] 3) After the DMA module detects that the DMA read operation register is 1, it can know through the read operation mask register that 16 calculation sub-modules are used in this calculation. It reads the input data from the corresponding address in the SMIO memory according to the address in the 16 valid read address registers and the length in the 16 valid read data length registers, and writes it into the input buffer corresponding to the 16 calculation sub-modules respectively; the state machine module enters the calculation state.

[0139] 4) The calculation subunit will automatically read the data in the corresponding input buffer and perform calculations; after the calculation is completed, it will set the status register of its corresponding calculation subunit to 2'b01; after all calculation subunits have completed the calculation, the state machine module enters the state of waiting to write back the result.

[0140] 5) The DMA module will read the result data of the corresponding length from the corresponding output buffer according to the read operation mask register, write address register, and write data length register, and write it back to the specified SMIO memory address; the state machine will then jump to the result notification state.

[0141] 6) The CXL.io protocol's standard interrupt mechanism notifies the host that the computation is complete and the result is available. The host can then initiate an H2D operation to use the result data, totaling 16×32 bytes.

[0142] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0143] The above provides a detailed description of the acceleration device, system, and method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An acceleration device, wherein the acceleration device is connected to a host computer via a computational high-speed interconnect, characterized in that, It includes a control status register module, a packet filtering module, a direct memory access module, an asymmetric encryption / decryption module, and a state machine module. The asymmetric encryption / decryption module includes multiple parallel asymmetric encryption / decryption computation subunits. The control status register module is configured to store the read address, write address, read data length, write data length, and read operation mask for each asymmetric encryption / decryption calculation subunit; The packet filtering module is configured to identify write access requests from the host to a target storage area in the device memory via the Fast Interconnect Memory Protocol (HIP). It then parses the payload of the write access request and updates the control status register module based on the parsing result in the payload. The address range of the target storage area is configured by the host via the HIP. The parsing result in the payload includes an opcode field, a value array field, and a selection mask field. The opcode field specifies the configuration operation type for the control status register module, including register configuration, direct memory access triggered, or status query operations. The value array field specifies the register value to be written when performing a register configuration operation. The selection mask field selects the asymmetric encryption / decryption computation subunit to participate in this operation. The direct memory access module is configured to read input data from a non-target storage area in the device memory according to the read address and read data length in the control status register module, and write the output data back to the non-target storage area in the device memory according to the write address and write data length after the calculation is completed. The state machine module is configured to send an interrupt signal to the host via the compute fast interconnect input / output protocol after the asymmetric encryption / decryption computation subunit enabled by the read operation mask has completed its computation, so as to notify the host to read output data from the non-target storage area of ​​the device memory.

2. The acceleration device according to claim 1, characterized in that, The packet filtering module includes a filtering configuration module and a packet parsing module. The filtering configuration module includes an upper address bound register and a lower address bound register. The filtering configuration module is configured to identify write access requests from the host to the target storage area in the device memory via the Fast Interconnect Memory Protocol, and send the write access requests to the packet parsing module. The packet parsing module is configured to parse the payload of the write access request in order to update the control status register module based on the parsing result in the payload.

3. The acceleration device according to claim 1, characterized in that, The control status register module includes a read / write register and a control register. The read / write register includes at least a read address register, a read data length register, a read operation mask register, a direct memory access read operation register, a write address register, and a write data length register. The control register includes at least a reset register and a computation subunit status register.

4. The acceleration device according to claim 1, characterized in that, The acceleration device further includes a cache module, which includes an input cache submodule and an output cache submodule. The number of input cache submodules and the number of output cache submodules are the same as the number of asymmetric encryption / decryption computation subunits. Each asymmetric encryption / decryption computation subunit corresponds to one input cache submodule and one output cache submodule, respectively. The input caching submodule is configured to cache the input data of the corresponding asymmetric encryption / decryption calculation subunit; The output cache submodule is configured to cache the output data of the corresponding asymmetric encryption / decryption calculation subunit.

5. The acceleration device according to claim 4, characterized in that, The state machine module is further configured to monitor the direct memory access read operation register in the idle state; in response to the direct memory access read operation register being written with a first identifier value, control the direct memory access module to read input data from the non-target storage area of ​​the device memory to the input buffer submodule; in response to the value of the direct memory access read operation register being a second identifier value, start the asymmetric encryption / decryption computation subunit specified by the read operation mask to perform the operation; and in response to the computation subunit status register of the asymmetric encryption / decryption computation subunit specified by the read operation mask being a third identifier value, control the direct memory access module to write the output data from the output buffer submodule back to the non-target storage area of ​​the device memory.

6. The acceleration device according to claim 1, characterized in that, The cache consistency mode of the target storage area is host-biased mode.

7. The acceleration device according to claim 1, characterized in that, The asymmetric encryption / decryption module uses the elliptic curve key negotiation algorithm.

8. An acceleration system, characterized in that, Includes the host computer and the acceleration device as described in any one of claims 1 to 7.

9. An acceleration method based on the acceleration device of any one of claims 1-7, characterized in that, include: The host identifies write access requests to a target storage area in the device memory via the Fast Interconnect Memory Protocol (HIP). The host parses the payload of the write access request and updates the control status register module based on the parsing result in the payload. The address range of the target storage area is configured by the host via the HIP. The control status register module stores the read address, write address, read data length, write data length, and read operation mask for each asymmetric encryption / decryption computation subunit. Based on the read address and read data length in the control status register module, the input data is read from the non-target storage area in the device memory, and after the calculation is completed, the output data is written back to the non-target storage area in the device memory based on the write address and write data length. After the asymmetric encryption / decryption computation subunit enabled by the read operation mask completes the computation, it sends an interrupt signal to the host via the computation fast interconnect input / output protocol to notify the host to read the output data from the non-target storage area of ​​the device memory.

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