Oscillator device
By using a control circuit and a differential input design for the oscillator device, the problems of inaccurate oscillator frequency control and high high-frequency current consumption are solved, achieving flexible frequency control and low-power output.
Patent Information
- Application Number
- CN202411669521.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-07-10
- Filing Date
- 2024-11-21
- Publication Date
- 2026-01-13
AI Technical Summary
Existing oscillators cannot accurately control the frequency under the limitation of the control voltage range, and the current consumption is too large when operating at high frequency, making it difficult to maintain current stability under low power consumption conditions.
The control circuit receives two input signals and generates two control signals, which in turn control the oscillator circuit to output two oscillation signals. By using differential input design and switching unit to adjust capacitor discharge current, flexible frequency control can be achieved.
This technology enables the oscillator to output oscillation signals of the same or different frequencies without being limited by the input signal, reducing dependence on the input signal, lowering power consumption, and maintaining current stability.
Smart Images
Figure CN121333232A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an oscillator, and more particularly to an oscillator device for outputting oscillating signals of the same or different frequencies. Background Technology
[0002] Generally, oscillators primarily control their oscillation frequency by adjusting the bias current of the oscillating stage through control of the control voltage. However, since the control voltage has a limited operating range, when the control voltage is below the lower limit of the operating range, the oscillator generates no bias current. In this case, because there is no bias current, the oscillator's bias current comes from component leakage current, and therefore the oscillator's output frequency cannot be controlled. Furthermore, when the control voltage is above the upper limit of the operating range, the oscillator's oscillation frequency cannot be further increased; this limits the highest frequency the oscillator can output.
[0003] Furthermore, when the oscillator operates at high frequencies, the operating current is typically much greater than that at low frequencies. Additionally, when considering low-power applications, it is desirable that the current in the oscillator's analog circuitry does not vary significantly with different output frequencies. Therefore, a new design is needed to address these issues. Summary of the Invention
[0004] The present invention provides an oscillator device that allows the oscillator circuit to simultaneously output two oscillation signals of the same or different frequencies by changing the magnitude of the input signal, without worrying about the limitations of the input signal or the need for any monitoring circuits or protection mechanisms for the input signal.
[0005] This invention provides an oscillator device, including a control circuit and an oscillator circuit. The control circuit receives a first input signal and a second input signal, and generates a first control signal and a second control signal. The oscillator circuit is coupled to the control circuit, receives the first control signal and the second control signal, and generates a first oscillation signal and a second oscillation signal based on the first control signal and the second control signal.
[0006] The oscillator device disclosed in this invention receives a first input signal and a second input signal through a control circuit, generates a first control signal and a second control signal, and the oscillator circuit generates a first oscillation signal and a second oscillation signal based on the first control signal and the second control signal. In this way, by changing the magnitude of the input signal, the oscillator circuit can simultaneously output two oscillation signals of the same or different frequencies, without needing to worry about limitations on the input signal or to implement any monitoring circuits or protection mechanisms for the input signal. Attached Figure Description
[0007] Figure 1 This is a schematic diagram of an oscillator device according to an embodiment of the present invention.
[0008] Figure 2 for Figure 1 A detailed circuit diagram of the oscillator device.
[0009] Figure 3 This is a schematic diagram illustrating the correspondence between the voltage difference between input signals IN1 and IN2, the current flowing through transistor NM1, and the current flowing through transistor NM2 according to an embodiment of the present invention.
[0010] Symbol Explanation
[0011] 100: Oscillator device
[0012] 110: Control Circuit
[0013] 120: Oscillator Circuit
[0014] 210, 230: Inverters
[0015] 220, 240: Switching units
[0016] NM1, NM2, PM1, PM2: Transistors
[0017] C1, C2: Capacitors
[0018] IS0, IS1, IS2: Current sources
[0019] IN1, IN2: Input signals
[0020] CS1, CS2: Control signals
[0021] OS1, OS2: Oscillation signals
[0022] V1, V2: Reference voltages
[0023] I1, I2: Current
[0024] +VD, -VD: Maximum voltage difference Detailed Implementation
[0025] In the embodiments listed below, the same or similar elements or components will be represented by the same reference numerals.
[0026] Figure 1 This is a schematic diagram of an oscillator device according to an embodiment of the present invention. In this embodiment, the oscillator device 100 is, for example, a voltage-controlled oscillator (VCO), but the embodiments of the present invention are not limited thereto. Please refer to... Figure 1 The oscillator device 100 may include a control circuit 110 and an oscillator circuit 120.
[0027] The control circuit 110 can receive input signals IN1 and IN2 and generate control signals CS1 and CS2. In other words, the control circuit 110 can generate control signals CS1 and CS2 based on input signals IN1 and IN2.
[0028] The oscillator circuit 120 can be coupled to the control circuit 110. The oscillator circuit 120 can receive control signals CS1 and CS2, and generate oscillation signals OS1 and OS2 based on the control signals CS1 and CS2.
[0029] In some embodiments, when the input signal IN1 received by the control circuit 110 is the same as the input signal IN2, the frequencies of the oscillation signal OS1 and the oscillation signal OS2 generated by the oscillator circuit 120 can be the same.
[0030] In some embodiments, when the input signal IN1 received by the control circuit 110 is different from the input signal IN2, the frequencies of the oscillation signal OS1 and the oscillation signal OS2 generated by the oscillator circuit 120 are different. For example, when the input signal IN1 is higher than the input signal IN2, the frequency of the oscillation signal OS1 will be higher than the frequency of the oscillation signal OS2. When the input signal IN1 is lower than the input signal IN2, the frequency of the oscillation signal OS1 will be lower than the frequency of the oscillation signal OS2.
[0031] In some embodiments, the input signal IN2 can be used as the input reference signal of the oscillator device 100, and the input signal IN1 can be used to control the frequency of the oscillation signal OS1 and the oscillation signal OS2 output by the oscillator device 100, but the embodiments of the present invention are not limited thereto.
[0032] Figure 2 for Figure 1 A detailed circuit diagram of the oscillator device is provided. Please refer to [link / reference]. Figure 2 The control circuit 110 may include transistor NM1, transistor NM2, and current source IS0. In this embodiment, transistor NM1 and transistor NM2 may form a differential pair input terminal, and input signals IN1 and IN2 may be differential pair input signals.
[0033] Transistor NM1 may have a first terminal, a second terminal, and a control terminal. The first terminal of transistor NM1 can generate a control signal CS1. The control terminal of transistor NM1 can receive an input signal IN1. Furthermore, transistor NM1 can be controlled by the input signal IN1 and turn on or off according to the input signal IN1. For example, when the input signal IN1 is high, transistor NM1 is on. When the input signal IN1 is low, transistor NM1 is not on.
[0034] Transistor NM2 may have a first terminal, a second terminal, and a control terminal. The first terminal of transistor NM2 can generate a control signal CS2. The second terminal of transistor NM2 can be coupled to the second terminal of transistor NM1. The control terminal of transistor NM2 can receive the input signal IN2. Furthermore, transistor NM2 can be controlled by the input signal IN2, and will turn on or off according to the input signal IN2. For example, when the input signal IN2 is high, transistor NM2 is on. When the input signal IN2 is low, transistor NM2 is not on.
[0035] The current source IS0 may have a first terminal and a second terminal. The first terminal of the current source IS0 is coupled to the second terminal of the transistor NM1. The second terminal of the current source IS0 may be coupled to a reference voltage V2. In some embodiments, the reference voltage V2 may be a low-potential voltage, such as ground voltage, but the embodiments of the present invention are not limited thereto.
[0036] In some embodiments, transistors NM1 and NM2 can be N-type transistors, wherein the first terminal of transistors NM1 and NM2 can be the drain terminal of the N-type transistor, the second terminal of transistors NM1 and NM2 can be the source terminal of the N-type transistor, and the control terminal of transistors NM1 and NM2 can be the gate terminal of the N-type transistor; however, the embodiments of the present invention are not limited thereto. In other embodiments, transistors NM1 and NM2 can be P-type transistors or other suitable transistors.
[0037] The oscillator circuit 120 includes transistor PM1, capacitor C1, current source IS1, inverter 210, switching unit 220, transistor PM2, capacitor C2, current source IS2, inverter 230 and switching unit 240.
[0038] Transistor PM1 may have a first terminal, a second terminal, and a control terminal. The second terminal of transistor PM1 may be coupled to a reference voltage V1. The control terminal of transistor PM1 may receive a control signal CS1. Furthermore, transistor PM1 may be controlled by the control signal CS1 and may turn on or off according to the control signal CS1. For example, when the control signal CS1 is low, transistor PM1 is on. When the control signal CS1 is high, transistor PM1 is off.
[0039] Capacitor C1 can have a first terminal and a second terminal. The first terminal of capacitor C1 can be coupled to the control terminal of transistor PM1. The second terminal of capacitor C1 can be coupled to the reference voltage V1.
[0040] The current source IS1 can have a first terminal and a second terminal. The first terminal of the current source IS1 can be coupled to the first terminal of the transistor PM1. The second terminal of the current source IS1 can be coupled to the reference voltage V2.
[0041] Inverter 210 may have an input terminal and an output terminal. The input terminal of inverter 210 may be coupled to the first terminal of transistor PM1. The output terminal of inverter 210 may generate an oscillation signal OS1.
[0042] Switching unit 220 may have a first terminal, a second terminal, and a control terminal. The first terminal of switching unit 220 may be coupled to the first terminal of capacitor C1. The second terminal of switching unit 220 may be coupled to the second terminal of capacitor C1. The control terminal of switching unit 220 is coupled to the output terminal of inverter 210 and receives the oscillation signal OS1. Furthermore, switching unit 220 may be controlled by the oscillation signal OS1 and may be turned on or off according to the oscillation signal OS1. For example, when the oscillation signal OS1 is at a low potential, switching unit 220 is turned on. When the oscillation signal OS1 is at a high potential, switching unit 220 is not turned on.
[0043] Transistor PM2 may have a first terminal, a second terminal, and a control terminal. The second terminal of transistor PM2 may be coupled to a reference voltage V1. The control terminal of transistor PM2 may receive a control signal CS2. Furthermore, transistor PM2 may be controlled by the control signal CS2 and may turn on or off according to the control signal CS2. For example, when the control signal CS2 is low, transistor PM2 is on. When the control signal CS2 is high, transistor PM2 is off.
[0044] Capacitor C2 can have a first terminal and a second terminal. The first terminal of capacitor C2 can be coupled to the control terminal of transistor PM2. The second terminal of capacitor C2 can be coupled to the reference voltage V1.
[0045] The current source IS2 can have a first terminal and a second terminal. The first terminal of the current source IS2 can be coupled to the first terminal of the transistor PM2. The second terminal of the current source IS2 can be coupled to the reference voltage V2.
[0046] Inverter 230 may have an input terminal and an output terminal. The input terminal of inverter 230 may be coupled to the first terminal of transistor PM2. The output terminal of inverter 230 may generate an oscillation signal OS2.
[0047] Switching unit 240 may have a first terminal, a second terminal, and a control terminal. The first terminal of switching unit 240 may be coupled to the first terminal of capacitor C2. The second terminal of switching unit 240 may be coupled to the second terminal of capacitor C2. The control terminal of switching unit 240 may be coupled to the output of inverter 230 and receive the oscillation signal OS2. Furthermore, switching unit 240 may be controlled by the oscillation signal OS2 and may be turned on or off according to the oscillation signal OS2. For example, when the oscillation signal OS2 is at a low potential, switching unit 240 is turned on. When the oscillation signal OS2 is at a high potential, switching unit 240 is not turned on.
[0048] In some embodiments, transistors PM1 and PM2 can be P-type transistors, wherein the first terminal of transistors PM1 and PM2 can be the drain terminal of the P-type transistor, the second terminal of transistors PM1 and PM2 can be the source terminal of the P-type transistor, and the control terminal of transistors PM1 and PM2 can be the gate terminal of the P-type transistor, but the embodiments of the present invention are not limited thereto. In other embodiments, transistors PM1 and PM2 can be N-type transistors or other suitable transistors.
[0049] In some embodiments, switching units 220 and 240 can be P-type transistors, wherein the first terminal of switching units 220 and 240 can be the drain terminal of the P-type transistor, the second terminal of switching units 220 and 240 can be the source terminal of the P-type transistor, and the control terminal of switching units 220 and 240 can be the gate terminal of the P-type transistor; however, the embodiments of the present invention are not limited thereto. In other embodiments, switching units 220 and 240 can be N-type transistors or other suitable transistors.
[0050] In some embodiments, the reference voltage V1 may be different from the reference voltage V2. Furthermore, the reference voltage V1 may be a high-potential voltage, such as the system voltage, and the reference voltage V2 may be a low-potential voltage, such as the ground voltage, but the embodiments of the present invention are not limited thereto.
[0051] In the overall operation of the oscillator device 100, firstly, when the input signals IN1 and IN2 are at low potentials, transistors NM1 and NM2 are not turned on. Additionally, the voltages at the input terminals of inverter 210 and inverter 230 are preset to low potentials, causing switching units 220 and 240 to turn on. This couples control signals CS1 and CS2 to a reference voltage V1 (e.g., a high potential voltage), meaning that control signals CS1 and CS2 are equal to the reference voltage V1 (e.g., a high potential voltage).
[0052] When control signals CS1 and CS2 are coupled to a reference voltage V1 (e.g., a high-level voltage), transistors PM1 and PM2 are not turned on, resulting in low-level voltages at the input terminals of inverter 210 and inverter 230. When both the input terminals of inverter 210 and inverter 230 are low-level, the output terminals of inverter 210 and inverter 230 will generate, for example, a high-level oscillation signal OS1 and OS2, respectively. Subsequently, when both oscillation signals OS1 and OS2 are high-level, switching units 220 and 240 are not turned on.
[0053] Subsequently, when the input signals IN1 and IN2 are at high potentials, transistors NM1 and NM2 will be turned on, and the current source IS0 will begin to discharge capacitors C1 and C2, causing the voltages of control signals CS1 and CS2 to drop.
[0054] Next, when the voltage of control signal CS1 is lower than the turn-on voltage of transistor PM1 (e.g., reference voltage V1 minus the threshold voltage of transistor PM1 (i.e., V1-Vth_PM1)) and the voltage of control signal CS2 is lower than the turn-on voltage of transistor PM2 (e.g., reference voltage V1 minus the threshold voltage of transistor PM2 (i.e., V1-Vth_PM2)), transistors PM1 and PM2 can be turned on and start outputting current.
[0055] Subsequently, when the output current of transistor PM1 is greater than the current of current source IS1 and the output current of transistor PM2 is greater than the current of current source IS2, the voltage at the input terminal of inverter 210 is, for example, high, and the voltage at the input terminal of inverter 230 is, for example, high, causing the output terminal of inverter 210 to generate, for example, a low-potential oscillation signal OS1 and the output terminal of inverter 230 to generate, for example, a low-potential oscillation signal OS2.
[0056] Next, when the oscillation signals OS1 and OS2 are at low potential, the switching unit 220 and the switching unit 240 are turned on, so that the voltage of the control signals CS1 and CS2 is pulled back to the reference voltage V1 (e.g., high potential voltage), that is, the control signals CS1 and CS2 are reset to the reference voltage V1 (e.g., high potential voltage).
[0057] Subsequently, when the voltages of control signals CS1 and CS2 are pulled back to the reference voltage V1 (e.g., a high potential voltage), transistors PM1 and PM2 are de-conducted, causing the voltages at the input terminals of inverter 210 and inverter 230 to be low. When the voltages at the input terminals of inverter 210 and inverter 230 are low, the oscillation signals OS1 and OS2 generated at the output terminals of inverter 210 and inverter 230 are also pulled to high potentials, causing the oscillation signals OS1 and OS2 of the oscillator device 100 to complete a pulse output.
[0058] Next, by repeating the above operations, oscillation signals OS1 and OS2 can output corresponding periodic signals. In some embodiments, further, when input signals IN1 and IN2 are the same (i.e., the voltage of input signal IN1 is the same as the voltage of input signal IN2), the current from current source IS0 will be evenly distributed and begin to discharge capacitors C1 and C2. Therefore, the period of oscillation signal OS1 will be the same as the period of oscillation signal OS2, that is, the frequency of oscillation signal OS1 will be the same as the frequency of oscillation signal OS2.
[0059] When the input signal IN1 is higher than the input signal IN2 (i.e., the voltage of input signal IN1 is higher than the voltage of input signal IN2), the discharge current of capacitor C1 will be greater than the discharge current of capacitor C2. Therefore, the period of the output oscillation signal OS1 will be shorter than the period of the oscillation signal OS2, that is, the frequency of the oscillation signal OS1 will be higher than the frequency of the oscillation signal OS2.
[0060] Conversely, when the input signal IN1 is lower than the input signal IN2 (i.e., the voltage of input signal IN1 is lower than the voltage of input signal IN2), the discharge current of capacitor C1 will be less than the discharge current of capacitor C2. Therefore, the period of the output oscillation signal OS1 will be longer than the period of the oscillation signal S2, that is, the frequency of the oscillation signal OS1 will be lower than the frequency of the oscillation signal OS2.
[0061] Figure 3 This is a schematic diagram illustrating the correspondence between the voltage difference between input signals IN1 and IN2, the current flowing through transistor NM1, and the current flowing through transistor NM2 according to an embodiment of the present invention.
[0062] exist Figure 3In the diagram, "I1" represents the current flowing through transistor NM1, "I2" represents the current flowing through transistor NM2, "+VD" represents the maximum voltage difference between input signals IN1 and IN2 when input signal IN1 is higher than input signal IN2, and "-VD" represents the maximum voltage difference between input signals IN1 and IN2 when input signal IN1 is lower than input signal IN2.
[0063] Depend on Figure 3 It can be seen that when the input signals IN1 and IN2 are the same, the voltage difference between the input signals IN1 and IN2 is 0. At this time, the current of the current source IS0 is approximately equal to the current I1 flowing through transistor NM1 (i.e., 1 / 2 of the maximum value of current I1) or the current I2 flowing through transistor NM2 (i.e., 1 / 2 of the maximum value of current I2).
[0064] When the input signal IN1 is higher than the input signal IN2 and the voltage difference between the two signals IN1 and IN2 reaches or exceeds the maximum voltage difference +VD, the current in the current source IS0 will be almost exactly equal to the current I1 flowing through the transistor NM1 (i.e., the maximum value of current I1). At this time, the frequency of the oscillation signal OS1 is the highest output frequency of the oscillator device 100, and this frequency of OS1 is almost twice that of the oscillation signal OS1 when the input signals IN1 and IN2 are the same. Furthermore, the frequency of the oscillation signal OS2 is the lowest output frequency of the oscillator device 100.
[0065] Conversely, when the input signal IN1 is lower than the input signal IN2 and the voltage difference between the input signals IN1 and IN2 reaches or exceeds the maximum voltage difference -VD, the current in the current source IS0 will be almost exactly equal to the current I2 flowing through the transistor NM2 (i.e., the maximum value of current I2). At this time, the frequency of the oscillation signal OS2 is the highest output frequency of the oscillator device 100, and this frequency of OS2 is almost twice that of the oscillation signal OS2 when the input signals IN1 and IN2 are the same. Furthermore, the frequency of the oscillation signal OS1 is the lowest output frequency of the oscillator device 100.
[0066] Furthermore, since the oscillator device 100 uses a differential input design, even if the voltage of the input signal IN1 is zero, it will not affect the operation of the oscillator device 100. There is no need to worry that the low voltage of the input signal IN1 will affect the accuracy of the output of the oscillator device 100, nor is it necessary to implement any monitoring circuits or protection mechanisms for the input signal IN1.
[0067] In summary, the oscillator circuit disclosed in this invention receives a first input signal and a second input signal through a control circuit, generates a first control signal and a second control signal, and generates a first oscillation signal and a second oscillation signal based on the first control signal and the second control signal. In this way, by changing the magnitude of the input signal, the oscillator circuit can output two oscillation signals of the same or different frequencies, without needing to worry about limitations on the input signal or to implement any monitoring circuits or protection mechanisms for the input signal.
[0068] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.
Claims
1. An oscillator device, characterized in that, include: A control circuit receives a first input signal and a second input signal, and generates a first control signal and a second control signal; as well as An oscillator circuit, coupled to the control circuit, receives the first control signal and the second control signal, and generates a first oscillation signal and a second oscillation signal based on the first control signal and the second control signal.
2. The oscillator device as claimed in claim 1, characterized in that, When the first input signal is the same as the second input signal, the first oscillation signal has the same frequency as the second oscillation signal.
3. The oscillator device as claimed in claim 1, characterized in that, When the first input signal is different from the second input signal, the frequencies of the first oscillation signal and the second oscillation signal are different.
4. The oscillator device as claimed in claim 3, characterized in that, When the first input signal is higher than the second input signal, the frequency of the first oscillation signal is higher than the frequency of the second oscillation signal.
5. The oscillator device as claimed in claim 3, characterized in that, When the first input signal is lower than the second input signal, the frequency of the first oscillation signal is lower than the frequency of the second oscillation signal.
6. The oscillator device as claimed in claim 1, characterized in that, The control circuit includes: A first transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor generates the first control signal and the control terminal of the first transistor receives the first input signal; A second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor generates the second control signal. The second terminal of the second transistor is coupled to the second terminal of the first transistor. The control terminal of the second transistor receives the second input signal. A current source having a first terminal and a second terminal, the first terminal of the current source being coupled to the second terminal of the first transistor, and the second terminal of the current source being coupled to a reference voltage.
7. The oscillator device as claimed in claim 6, characterized in that, The reference voltage is a low potential voltage.
8. The oscillator device as claimed in claim 6, characterized in that, The first transistor and the second transistor are N-type transistors.
9. The oscillator device as claimed in claim 1, characterized in that, The oscillator circuit includes: A first transistor has a first terminal, a second terminal and a control terminal, the second terminal of the first transistor is coupled to a first reference voltage, and the control terminal of the first transistor receives the first control signal. A first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the control terminal of the first transistor, and the second terminal of the first capacitor being coupled to the first reference voltage. A first current source having a first terminal and a second terminal, the first terminal of the first current source being coupled to the first terminal of the first transistor, and the second terminal of the first current source being coupled to a second reference voltage; A first inverter has an input terminal and an output terminal, the input terminal of the first inverter is coupled to a first terminal of the first transistor, and the output terminal of the first inverter generates the first oscillation signal; A first switching unit has a first terminal, a second terminal and a control terminal. The first terminal of the first switching unit is coupled to the first terminal of the first capacitor, the second terminal of the first switching unit is coupled to the second terminal of the first capacitor, and the control terminal of the first switching unit is coupled to the output terminal of the first inverter and receives the first oscillation signal. A second transistor has a first terminal, a second terminal and a control terminal, the second terminal of the second transistor is coupled to the first reference voltage, and the control terminal of the second transistor receives the second control signal; A second capacitor has a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the control terminal of the second transistor, and the second terminal of the second capacitor being coupled to the first reference voltage; A second current source having a first terminal and a second terminal, the first terminal of the second current source being coupled to the first terminal of the second transistor, and the second terminal of the second current source being coupled to the second reference voltage; A second inverter having an input terminal and an output terminal, the input terminal of the second inverter being coupled to a first terminal of the second transistor, and the output terminal of the second inverter generating the second oscillation signal; and A second switching unit has a first terminal, a second terminal and a control terminal. The first terminal of the second switching unit is coupled to the first terminal of the second capacitor, the second terminal of the second switching unit is coupled to the second terminal of the second capacitor, and the control terminal of the second switching unit is coupled to the output terminal of the second inverter and receives the second oscillation signal.
10. The oscillator device as claimed in claim 9, characterized in that, The first transistor and the second transistor are P-type transistors.
11. The oscillator device as claimed in claim 9, characterized in that, The first reference voltage is different from the second reference voltage.
12. The oscillator device as claimed in claim 11, characterized in that, The first reference voltage is a high potential voltage, and the second reference voltage is a low potential voltage.