Method for forming surface acoustic wave resonator
By using an amorphous silicon layer as a mask material in a piezoelectric surface acoustic wave filter and employing a dry etching process to form an interdigital transducer, the problems of uneven sidewalls and metal residues on the interdigital electrodes in traditional methods are solved, thereby improving the performance and reliability of the device.
Patent Information
- Application Number
- CN202511416099.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-29
- Publication Date
- 2026-01-13
AI Technical Summary
Traditional piezoelectric surface acoustic wave filters have the risk of uneven sidewalls and metal residues when fabricating interdigitated electrodes, which affects the reliability and performance of the device.
Using an amorphous silicon layer as a mask material, interdigitated transducers are formed on the piezoelectric layer through a dry etching process. The amorphous silicon layer has a stable refractive index and extinction coefficient, which reduces the standing wave effect and reflection noise at the bottom of the photoresist, improves the pattern resolution, and avoids the residue of reaction byproducts through physical reaction.
It improves the steepness and linewidth uniformity of the interdigitated electrodes, enhances the reliability of the device, simplifies the process flow, and avoids the need for additional post-etching and cleaning processes.
Smart Images
Figure CN121333261A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a surface acoustic wave resonator. Background Technology
[0002] Radio frequency (RF) front-end chips in wireless communication devices include power amplifiers, antenna switches, RF filters, multiplexers, and low-noise amplifiers. Among these, RF filters include surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, micro-electro-mechanical system (MEMS) filters, and integrated passive device (IPD) filters.
[0003] Piezoelectric surface acoustic wave (SAW) filters are widely used in radio frequency (RF) front-ends. The linewidth accuracy and topography quality of their interdigital transducers (IDTs) directly determine the filter's performance parameters (such as passband bandwidth, insertion loss, and out-of-band rejection). Traditional IDT fabrication methods typically employ a lift-off process, first forming a photoresist pattern, then depositing a metal film, and finally removing the metal by dissolving the photoresist, leaving only the metal in the pre-defined patterned area to form the interdigital electrodes. However, the sidewalls of the interdigital electrodes fabricated by the lift-off process are not steep, and there is a risk of metal residue, affecting the reliability of the device.
[0004] Therefore, the performance of piezoelectric surface acoustic wave filters still needs continuous improvement. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a method for forming a surface acoustic wave resonator to improve the performance of piezoelectric surface acoustic wave filters.
[0006] To address the aforementioned technical problems, the present invention provides a method for forming a surface acoustic wave resonator, comprising: providing a piezoelectric layer; forming an electrode material layer on the piezoelectric layer; forming an amorphous silicon layer on the electrode material layer, the thickness of the amorphous silicon layer being less than 300 angstroms; forming a photoresist layer on the amorphous silicon layer; exposing and developing the photoresist layer to form a patterned layer, the patterned layer exposing a portion of the surface of the amorphous silicon layer; etching the amorphous silicon layer and the electrode material layer using the patterned layer as a mask until the surface of the piezoelectric layer is exposed; forming an interdigitated transducer on the piezoelectric layer, the interdigitated transducer comprising a plurality of interdigitated electrodes arranged along a first direction.
[0007] Optionally, the interdigitated electrode has a first width in a first direction, the first width being less than or equal to 0.5 micrometers.
[0008] Optionally, the amorphous silicon layer has a preset thickness T = λ / 4N, where λ is the exposure wavelength and N is the refractive index of the amorphous silicon layer.
[0009] Optionally, the exposure wavelength ranges from 248 nanometers to 365 nanometers, and the thickness of the amorphous silicon layer ranges from 80 angstroms to 250 angstroms.
[0010] Optionally, when the exposure wavelength is 248 nanometers, the thickness of the amorphous silicon layer ranges from 80 angstroms to 200 angstroms.
[0011] Optionally, when the exposure wavelength is 365 nanometers, the thickness of the amorphous silicon layer ranges from 150 angstroms to 250 angstroms.
[0012] Optionally, when the exposure wavelength is 248 nanometers, the thickness of the amorphous silicon layer ranges from 0.59T to 1.41T.
[0013] Optionally, when the exposure wavelength is 365 nanometers, the thickness of the amorphous silicon layer ranges from 0.76T to 1.24T.
[0014] Optionally, the refractive index of the amorphous silicon layer is in the range of 3.6 to 4.5.
[0015] Optionally, the extinction coefficient of the amorphous silicon layer ranges from 0.8 to 2.0.
[0016] Optionally, the thickness of the amorphous silicon layer is proportional to the exposure wavelength.
[0017] Optionally, the thickness of the patterned layer ranges from 550 nanometers to 920 nanometers.
[0018] Optionally, the angle between the sidewall of the patterned layer and the surface of the amorphous silicon layer ranges from 85° to 90°.
[0019] Optionally, after forming the interdigitated transducer, the process further includes removing the amorphous silicon layer.
[0020] Optionally, the process for removing the amorphous silicon layer includes a dry etching process.
[0021] Optionally, the etching process for the amorphous silicon layer and the electrode material layer includes a dry etching process.
[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0023] The method for forming a surface acoustic wave resonator of the present invention includes an amorphous silicon layer with a relatively stable range of refractive index and extinction coefficient. The optical properties of the amorphous silicon layer are relatively stable. When the photoresist layer is exposed to form a patterned layer, it can effectively absorb scattered light, reduce the standing wave effect and reflection noise at the bottom of the photoresist, thereby improving the pattern resolution and obtaining a patterned layer with steeper sidewalls. This allows for better downward transmission of the pattern of the patterned layer and improves the steepness and linewidth uniformity of the interdigitated electrodes.
[0024] In addition, the thickness of the amorphous silicon layer is less than 300 angstroms, which reduces the optical path difference at the interface between the photoresist and the piezoelectric layer, further suppresses pattern distortion, improves the steepness and linewidth uniformity of the interdigitated electrodes, and thus improves device performance.
[0025] In addition, the amorphous silicon layer has relatively stable chemical properties and is not prone to chemical reaction with the etching gas in the dry etching process. The etching process of the amorphous silicon layer is a physical reaction, which makes it less likely to produce reaction byproducts that remain on the sidewall or top surface of the subsequently formed interdigitated electrode, thus avoiding corrosion of the interdigitated electrode and improving its reliability. Furthermore, there is no need to add a cleaning process to remove reaction byproducts, which simplifies the process flow. Attached Figure Description
[0026] Figure 1 and Figure 2 This is a schematic diagram of the formation process of a surface acoustic wave resonator;
[0027] Figures 3 to 8 This is a schematic diagram of the formation process of the surface acoustic wave resonator in an embodiment of the present invention. Detailed Implementation
[0028] As described in the background section, the performance of piezoelectric surface acoustic wave filters still needs continuous improvement. This will be analyzed and explained in conjunction with specific embodiments.
[0029] Compared to traditional stripping processes, dry etching can produce interdigitated electrodes with steep sidewalls and does not produce metal residues, thus improving device reliability.
[0030] Figure 1 and Figure 2 This is a schematic diagram of the formation process of a surface acoustic wave resonator.
[0031] Please refer to Figure 1 A piezoelectric layer 100 is provided; an electrode material layer 101 is formed on the piezoelectric layer 100; a mask structure is formed on the electrode material layer 101, the mask structure including an anti-reflection layer 102 and a patterned layer 103 located on the anti-reflection layer 102, the patterned layer 103 exposing a portion of the surface of the anti-reflection layer 102.
[0032] Please refer to Figure 2 Using the patterned layer 103 as a mask, the anti-reflection layer 102 and the electrode material layer 101 are etched by a dry etching process until the surface of the piezoelectric layer 100 is exposed, and an interdigital transducer is formed on the piezoelectric layer 100. The interdigital transducer includes a plurality of interdigital electrodes 105 arranged along a first direction.
[0033] During the formation of the surface acoustic wave resonator (SAW), the patterned layer 103 is formed by photoresist exposure and development, and the anti-reflection layer 102 is a bottom anti-reflection coating (BARC). The material of the bottom anti-reflection coating is usually an organic material. On the one hand, the adjustment range of the optical parameters (N value, k value) of the BARC material is limited by the material's chemical system, making it difficult to achieve optimal anti-reflection effects for all exposure wavelengths and substrate types. Furthermore, it has poor high-temperature stability, resulting in poor photoresist morphology steepness after photolithography, which affects the morphology steepness and linewidth uniformity of the IDT after etching. On the other hand, the material of the bottom anti-reflection coating is prone to chemically reacting with the etching gas in the dry etching process to form reaction byproducts 106 (such as...). Figure 2 As shown, the interdigitated electrodes 105 are distributed within the etching area. Due to the small linewidth of the interdigitated electrodes 105, the reaction byproducts 106 are difficult to remove completely during the cleaning process after the formation of the interdigitated electrodes 105. As a result, the reaction byproducts 106 remain on the sidewall or top surface of the interdigitated electrodes 105, leading to post-corrosion of the interdigitated electrodes 105. This can easily cause defects such as arcing in subsequent processes, which can easily lead to reliability failure.
[0034] To address the aforementioned problems, this invention provides a method for forming a surface acoustic wave resonator. The amorphous silicon layer possesses a relatively stable range of refractive index and extinction coefficient values. Its optical properties are also relatively stable. During the exposure of the photoresist layer to form a patterned layer, it effectively absorbs scattered light, reducing the standing wave effect and reflection noise at the bottom of the photoresist, thereby improving pattern resolution and obtaining a patterned layer with steeper sidewalls. This allows for better downward transfer of the pattern, improving the steepness and linewidth uniformity of the interdigitated electrodes. Furthermore, the thickness of the amorphous silicon layer is less than 300 angstroms, reducing the lithography... The optical path difference at the interface between the adhesive and the piezoelectric layer further suppresses pattern distortion, improves the steepness and linewidth uniformity of the interdigitated electrodes, thereby enhancing device performance. Furthermore, the amorphous silicon layer is chemically stable and does not readily react with the etching gases in dry etching processes. The etching process of the amorphous silicon layer is a physical reaction, thus minimizing the generation of reaction byproducts that remain on the sidewalls or top surface of the subsequently formed interdigitated electrodes. This results in a better morphology of the formed amorphous silicon pattern, preventing post-corrosion of the interdigitated electrodes and improving their reliability. Additionally, no additional cleaning process is required to remove reaction byproducts, simplifying the process flow.
[0035] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0036] Figures 3 to 8 This is a schematic diagram of the formation process of the surface acoustic wave resonator in an embodiment of the present invention.
[0037] Please refer to Figure 3 A piezoelectric layer 200 is provided; an electrode material layer 201 is formed on the piezoelectric layer 200; an amorphous silicon layer 202 is formed on the electrode material layer 201; and a photoresist layer 203 is formed on the amorphous silicon layer 202.
[0038] The materials of the piezoelectric layer 200 include: lithium tantalate (LiTaO3, abbreviated as LT), lithium niobate (LiNbO3, abbreviated as LN), quartz, zinc oxide (ZnO) or aluminum nitride (AlN), etc.
[0039] The electrode material layer 201 includes one or more electrode layers, and the material of the electrode layer includes metal or metal alloy; the metal includes one or more combinations of copper, aluminum, magnesium, molybdenum, gold, platinum, titanium, tungsten, cobalt, nickel and tantalum.
[0040] In this embodiment, the process for forming the electrode material layer 201 includes evaporation deposition or sputtering deposition.
[0041] In this embodiment, the process for forming the amorphous silicon layer 202 includes chemical vapor deposition (CVD) or physical vapor deposition (PVD). The reaction gas in the CVD process is a silane precursor; the reaction material in the PVD process is a silicon target.
[0042] In this embodiment, the amorphous silicon layer 202 has a preset thickness T = λ / 4N, where λ is the exposure wavelength and N is the refractive index of the amorphous silicon layer 202.
[0043] In this embodiment, the refractive index N of the amorphous silicon layer 202 ranges from 3.6 to 4.5. The amorphous silicon layer 202 with the refractive index N range has better refractive index matching, which can optimize the light field distribution, reduce constructive interference at the interface of the piezoelectric layer 200, reduce reflectivity, and make the contrast between the exposed and unexposed areas of the photoresist higher and the pattern edges sharper.
[0044] In this embodiment, the extinction coefficient of the amorphous silicon layer 202 ranges from 0.8 to 2.0. The amorphous silicon layer 202 with the extinction coefficient range can more effectively absorb scattered light, reduce the standing wave effect and reflection noise at the bottom of the photoresist, thereby improving the pattern resolution.
[0045] In this embodiment, the thickness of the amorphous silicon layer 202 is less than 300 angstroms. The amorphous silicon layer 202 within this thickness range can reduce the optical path difference at the interface between the photoresist and the piezoelectric layer 200, further suppressing pattern distortion, improving the steepness and linewidth uniformity of the interdigitated electrodes, thereby improving device performance.
[0046] Please refer to Figure 4 The photoresist layer 203 is exposed and developed to form a patterned layer 204, which exposes part of the surface of the amorphous silicon layer 202.
[0047] The amorphous silicon layer 202 is located at the bottom of the photoresist layer 203 and plays an anti-reflection role. It can prevent light with high refractive index and high absorption coefficient from penetrating the photoresist layer 203 and reaching the surface of the piezoelectric layer 200 during exposure, thereby reducing scattering and reflection on the surface of the piezoelectric layer 200 and reducing the photolithography standing wave effect.
[0048] The amorphous silicon layer 202 has a relatively stable range of refractive index and extinction coefficient. The optical properties of the amorphous silicon layer 202 are relatively stable. When the photoresist layer 203 is exposed to form the patterned layer 204, it can effectively absorb scattered light, reduce the standing wave effect and reflection noise at the bottom of the photoresist, thereby improving the pattern resolution and obtaining a patterned layer 204 with relatively steep sidewalls. This allows for better downward transmission of the pattern of the patterned layer 204, improving the steepness and linewidth uniformity of the interdigitated electrodes 206.
[0049] In this embodiment, the thickness of the amorphous silicon layer 202 is directly proportional to the exposure wavelength λ. This allows the thickness of the amorphous silicon layer 202 to be adjusted according to the wavelength of the light source used during exposure, ensuring that the amorphous silicon layer 202 provides good anti-reflection protection for the piezoelectric layer 200 and resulting in a patterned layer 204 with relatively steep sidewalls.
[0050] In this embodiment, the wavelength range of the exposure wavelength λ is 248 nm to 365 nm, and the thickness range of the amorphous silicon layer 202 is 80 angstroms to 250 angstroms.
[0051] In one embodiment, when the exposure wavelength is 248 nanometers, the thickness of the amorphous silicon layer 202 ranges from 80 angstroms to 200 angstroms.
[0052] In one embodiment, when the exposure wavelength is 365 nanometers, the thickness of the amorphous silicon layer 202 ranges from 150 angstroms to 250 angstroms.
[0053] In one embodiment, when the exposure wavelength is 248 nanometers, the thickness of the amorphous silicon layer 202 ranges from 0.59T to 1.41T. Here, T is a preset thickness of the amorphous silicon layer 202.
[0054] In one embodiment, when the exposure wavelength is 365 nanometers, the thickness of the amorphous silicon layer 202 ranges from 0.76T to 1.24T. Here, T is a preset thickness of the amorphous silicon layer 202.
[0055] In this embodiment, the thickness of the patterned layer 204 ranges from 550 nanometers to 920 nanometers.
[0056] In this embodiment, the angle α between the sidewall of the patterned layer 204 and the surface of the amorphous silicon layer 202 ranges from 85° to 90°. It should be noted that... Figure 4 The included angle α shown in the diagram is the angle between the patterned layer 204 and the surface of the amorphous silicon layer 202 at the bottom of the patterned layer 204.
[0057] The included angle α ranges from 85° to 90°, resulting in relatively steep sidewalls of the patterned layer 204 and high dimensional accuracy of the formed patterned layer 204.
[0058] Next, the amorphous silicon layer 202 and the electrode material layer 201 are etched using the patterned layer 204 as a mask until the surface of the piezoelectric layer 200 is exposed, forming an interdigital transducer on the piezoelectric layer 200. The interdigital transducer includes a plurality of interdigital electrodes 206 arranged along the first direction X. For the process of forming the interdigital transducer, please refer to [reference needed]. Figures 5 to 7 .
[0059] Please refer to Figure 5 Using the patterned layer 204 as a mask, the amorphous silicon layer 202 is etched to form an amorphous silicon pattern 205 on the electrode material layer 201.
[0060] In this embodiment, the process of etching the amorphous silicon layer 202 using the patterned layer 204 as a mask includes a dry etching process. During the etching of the amorphous silicon layer 202, the patterned layer 204 naturally loses some thickness during the etching process.
[0061] In this embodiment, the process of etching the amorphous silicon layer 202 using the patterned layer 204 as a mask includes a dry etching process. The dry etching process has strong directionality and can effectively transfer the pattern of the patterned layer 204 to the amorphous silicon layer 202.
[0062] The amorphous silicon layer 202 exhibits high etching selectivity, reducing undercut during the etching process and maintaining pattern perpendicularity. The amorphous silicon layer 202 is chemically stable and does not readily react with the etching gases used in dry etching processes. The etching process of the amorphous silicon layer 202 is a physical reaction, thus minimizing the generation of reaction byproducts that remain on the sidewall or top surface of the subsequently formed interdigitated electrodes, preventing post-corrosion of the interdigitated electrodes and improving their reliability. Furthermore, no additional cleaning process is required to remove reaction byproducts, simplifying the process flow.
[0063] In this embodiment, the etching gas in the dry etching process includes one or more combinations of SF6, CF4, CHF3, HBr, Cl2, O2, CHCl3, Ar, and He.
[0064] Please refer to Figure 6 Using the patterned layer 204 and the amorphous silicon pattern 205 as masks, the electrode material layer 201 is etched until the surface of the piezoelectric layer 200 is exposed, and an interdigital transducer is formed on the piezoelectric layer 200. The interdigital transducer includes a plurality of interdigital electrodes 206 arranged along the first direction X.
[0065] In this embodiment, the etching process for the electrode material layer 201 includes a dry etching process. The etching gas used in the dry etching process includes one or more combinations of Cl2, BCl3, CCl4, CHF3, O2, N2, and Ar.
[0066] The patterned layer 204 and the amorphous silicon pattern 205 have good morphology, and there are fewer reaction byproducts from etching the amorphous silicon layer 202. As a result, the pattern of the patterned layer 204 and the amorphous silicon pattern 205 is transferred downward to form the interdigitated electrode 206. The interdigitated electrode 206 has good morphology, good size uniformity, and improved reliability.
[0067] In this embodiment, a plurality of interdigitated electrodes 206 are arranged in parallel along a first direction X; each interdigitated electrode 206 has a first width d1 in the first direction X, the first width d1 being less than or equal to 0.5 micrometers. The interdigitated electrodes 206 are relatively small in size, and the method can form interdigitated electrodes 206 with good dimensional uniformity and small linewidth, improving the flexibility of small linewidth design.
[0068] In this embodiment, the material of the interdigital electrode 206 includes metal or metal alloy; the metal includes one or more combinations of copper, aluminum, magnesium, molybdenum, gold, platinum, titanium, tungsten, cobalt, nickel and tantalum.
[0069] In this embodiment, after forming the interdigital transducer, the remaining patterning layer 204 is removed.
[0070] The process for removing the patterned layer 204 includes wet etching.
[0071] Please refer to Figure 7 Remove the amorphous silicon pattern 205.
[0072] The process for removing the amorphous silicon pattern 205 includes a dry etching process. The etching gas used in the dry etching process includes one or more combinations of SF6, CF4, CHF3, HBr, Cl2, O2, CHCl3, Ar, and He.
[0073] The dry etching process has a large etching selectivity for the amorphous silicon pattern 205 and the piezoelectric layer 200, thereby causing less damage to the surface of the piezoelectric layer 200 during the removal of the amorphous silicon pattern 205.
[0074] Please refer to Figure 8 A first dielectric layer 207 is formed on the piezoelectric layer 200, and the first dielectric layer 207 covers the sidewall surface and top surface of the interdigitated electrode 206.
[0075] The material of the first dielectric layer 207 includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and aluminum nitride.
[0076] In this embodiment, the material of the first dielectric layer 207 includes silicon nitride. The silicon nitride material has a dense structure and good ability to block water vapor and chemical corrosion, which can effectively protect the interdigitated electrode 206 from corrosion and oxidation in subsequent processes.
[0077] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method of forming a surface acoustic wave resonator, characterized by, The method comprises the following steps: providing a piezoelectric layer; forming an electrode material layer on the piezoelectric layer; forming an amorphous silicon layer on the electrode material layer, the thickness of the amorphous silicon layer being less than 300 angstroms; forming a photoresist layer on the amorphous silicon layer, exposing and developing the photoresist layer to form a patterned layer, the patterned layer exposing part of the surface of the amorphous silicon layer; using the patterned layer as a mask to etch the amorphous silicon layer and the electrode material layer until the surface of the piezoelectric layer is exposed, forming an interdigital transducer on the piezoelectric layer, the interdigital transducer comprising a plurality of interdigital electrodes arranged in a first direction.
2. The method of forming a surface acoustic wave resonator of claim 1, wherein, The interdigital electrodes have a first width in the first direction, and the first width is less than or equal to 0.5 microns.
3. The method of forming a surface acoustic wave resonator of claim 1, wherein, The amorphous silicon layer has a predetermined thickness T = λ / 4N, where λ is the exposure wavelength and N is the refractive index of the amorphous silicon layer.
4. The method of forming a surface acoustic wave resonator of claim 3, wherein, The exposure wavelength ranges from 248 nanometers to 365 nanometers, and the thickness of the amorphous silicon layer ranges from 80 angstroms to 250 angstroms.
5. The method of forming a surface acoustic wave resonator of claim 4, wherein, When the exposure wavelength is 248 nanometers, the thickness of the amorphous silicon layer ranges from 80 angstroms to 200 angstroms.
6. The method of forming a surface acoustic wave resonator of claim 4, wherein, When the exposure wavelength is 365 nanometers, the thickness of the amorphous silicon layer ranges from 150 angstroms to 250 angstroms.
7. The method of forming a surface acoustic wave resonator of claim 3, wherein, When the exposure wavelength is 248 nanometers, the thickness of the amorphous silicon layer ranges from 0.59T to 1.41T.
8. The method of forming a surface acoustic wave resonator of claim 3, wherein, When the exposure wavelength is 365 nanometers, the thickness of the amorphous silicon layer ranges from 0.76T to 1.24T.
9. The method of forming a surface acoustic wave resonator of claim 1, wherein, The refractive index of the amorphous silicon layer ranges from 3.6 to 4.
5.
10. The method of forming a surface acoustic wave resonator of claim 1, wherein, The extinction coefficient of the amorphous silicon layer ranges from 0.8 to 2.
0.
11. The method of forming a surface acoustic wave resonator of claim 1, wherein, The thickness of the amorphous silicon layer is directly proportional to the exposure wavelength.
12. The method of forming a surface acoustic wave resonator of claim 1, wherein, The angle between the sidewall of the patterned layer and the surface of the amorphous silicon layer ranges from 85° to 90°.
13. The method of forming a surface acoustic wave resonator of claim 1, wherein, After forming the interdigital transducer, the method further comprises removing the amorphous silicon layer.
14. The method of forming a surface acoustic wave resonator of claim 13, wherein, The process of removing the amorphous silicon layer comprises a dry etching process.