Chip package and method of forming same

Abstract

The invention discloses a chip package and a forming method thereof, the package comprises a plastic package body, a heat dissipation substrate, an insulating substrate, a first chip and a second chip, the plastic package body is provided with an upper surface and a lower surface, the heat dissipation substrate is provided with a first surface and a second surface, and the first surface of the heat dissipation substrate is exposed from the upper surface or the lower surface of the plastic package body. The insulating substrate is provided with a third surface and a fourth surface, wherein the third surface of the insulating substrate is arranged on the second surface of the heat dissipation substrate through the first medium. The first chip is provided with a first substrate surface, wherein the first substrate surface is arranged on the fourth surface of the insulating substrate through a second medium. The second chip is provided with a second substrate surface, wherein the second substrate surface is arranged on the fourth surface of the insulating substrate through a third medium. And each chip is insulated from the heat dissipation substrate in the packaging body, so that the cost and the wiring difficulty during system application are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a chip package and a forming method thereof. BACKGROUND

[0002] In the field of semiconductor manufacturing, packaging is a key link to ensure the realization of chip functions and reliable connection with external circuits. In semiconductor packaging, the heat dissipation substrate in the package can efficiently release the heat generated by the chip.

[0003] In the power system application scenario, multiple unidirectional switching devices or multiple bidirectional switching devices are needed. In each integrated driving or controlled unidirectional switching device (including a driving or control chip and a power device) or integrated driving or controlled bidirectional switching device (including a driving or control chip and a power device), the substrate potential of the driving or control chip and the substrate potential of the power device can be the same or different according to design requirements. In the existing multi-chip packaging structure, the substrate potential of the driving or control chip and the substrate potential of the power device cannot be effectively isolated, and the heat dissipation substrate cannot be effectively isolated from each chip. Therefore, external isolation treatment of the heat dissipation substrate is usually required outside the package, increasing the complexity and cost of system assembly.

[0004] Therefore, a packaging structure is needed, in which each chip is insulated from the heat dissipation substrate in the package. SUMMARY

[0005] The present application provides a multi-chip package structure and a forming method thereof. The package structure can insulate each chip from the heat dissipation substrate in the package, and set the substrate insulation or non-insulation between each chip according to requirements, and achieve substrate isolation between multiple semiconductor devices in the package.

[0006] According to at least one embodiment of the present application, a chip package is provided, comprising: a plastic package body having an upper surface and a lower surface; a heat dissipation substrate having a first surface and a second surface, wherein the first surface of the heat dissipation substrate is exposed from the upper surface or the lower surface of the plastic package body; an insulating substrate having a third surface and a fourth surface, wherein the third surface of the insulating substrate is disposed on the second surface of the heat dissipation substrate through a first medium; a first chip having a first substrate surface, wherein the first substrate surface is disposed on the fourth surface of the insulating substrate through a second medium; and a second chip having a second substrate surface, wherein the second substrate surface is disposed on the fourth surface of the insulating substrate through a third medium.

[0007] A chip package is provided according to the present invention, comprising: a plastic package having an upper surface and a lower surface; a heat dissipation substrate having a first surface and a second surface, wherein the first surface of the heat dissipation substrate is exposed from the upper surface or the lower surface of the plastic package; an insulating substrate having a third surface and a fourth surface, wherein the third surface of the insulating substrate is disposed on the second surface of the heat dissipation substrate by a first medium, wherein the insulating substrate comprises a first insulating region and a second insulating region separated; a first chip having a first substrate surface, wherein the first substrate surface is disposed on the fourth surface of the first insulating region by a second medium; and a second chip having a second substrate surface, wherein the second substrate surface is disposed on the fourth surface of the second insulating region by a third medium.

[0008] A method of forming a chip package is provided according to the present invention, comprising: forming a heat dissipation substrate, wherein the heat dissipation substrate has a first surface and a second surface; forming an insulating substrate, wherein the insulating substrate has a third surface and a fourth surface, wherein the third surface of the insulating substrate is disposed on the second surface of the heat dissipation substrate by a first medium; disposing a first chip on the fourth surface of the insulating substrate by a second medium, and disposing a second chip on the fourth surface of the insulating substrate by a third medium; and forming a plastic package, wherein the first surface of the heat dissipation substrate is exposed from an upper surface or a lower surface of the plastic package. BRIEF DESCRIPTION OF DRAWINGS

[0009] For a better understanding of the present invention, embodiments thereof will now be described in connection with the following drawings. The drawings are only for the purpose of illustrating embodiments and are not intended to limit the present invention. The drawings generally only illustrate part of the features of the systems or devices in the embodiments. The size and proportions of the drawings can not correspond to the actual size and proportions.

[0010] Figure 1 A top view of a chip package 100 according to an embodiment of the present invention is shown;

[0011] Figure 2 A top view of a chip package 200 according to an embodiment of the present invention is shown; Figure 1 A cross-sectional view of the chip package 100 shown taken along AA' is shown;

[0012] Figure 3 A top view of a chip package 300 according to another embodiment of the present invention is shown; Figure 1 A cross-sectional view of the chip package 300 shown taken along AA' is shown;

[0013] Figure 4 A top view of a chip package 400 according to an embodiment of the present invention is shown;

[0014] Figure 5 A top view of a chip package 500 according to an embodiment of the present invention is shown; Figure 4 A cross-sectional view of the chip package 400 shown taken along BB' is shown;

[0015] Figure 6 A cross-sectional view of the chip package 400 taken along BB' is shown. Figure 4 A cross-sectional view of the chip package 400 taken along BB' is shown.

[0016] Figure 7 A circuit schematic diagram of the first chip 103 and the second chip 110 according to an embodiment of the application is shown.

[0017] Figure 8 A top view of the chip package 800 according to an embodiment of the application is shown.

[0018] Figure 9 A cross-sectional view of the chip package 800 taken along CC' is shown. Figure 8 A cross-sectional view of the chip package 800 taken along CC' is shown.

[0019] Figure 10 A cross-sectional view of the chip package 800 taken along CC' is shown. Figure 8 A cross-sectional view of the chip package 800 taken along CC' is shown.

[0020] Figure 11 A top view of the chip package 1100 according to an embodiment of the application is shown.

[0021] Figure 12 A cross-sectional view of the chip package 100 taken along DD' is shown. Figure 11 A cross-sectional view of the chip package 100 taken along DD' is shown.

[0022] Figure 13 A cross-sectional view of the chip package 100 taken along DD' is shown. Figure 11 A cross-sectional view of the chip package 100 taken along DD' is shown.

[0023] Figure 14 A cross-sectional view of the chip package 100 taken along DD' is shown. Figure 11 A cross-sectional view of the chip package 100 taken along DD' is shown.

[0024] Figure 15 A circuit schematic diagram of the first chip 103 and the second chip 110 according to an embodiment of the application is shown.

[0025] Figure 16 A method 1600 of forming a chip package according to an embodiment of the application is shown. DETAILED DESCRIPTION

[0026] The following description of drawings is included to assist with understanding of various embodiments of the present disclosure, as defined by the claims and their equivalents. This description, included in various specific details, is to be considered as illustrative only. Thus, those skilled in the art will recognize that various changes and modifications of the various embodiments described herein can be made without departing from the scope and spirit of the present disclosure. In addition, descriptions of well-known functions and constructions can be omitted for clarity and conciseness.

[0027] The terms and words used in the following description and claims are not limited to the bibliographical meanings, but are merely used to enable a clear and consistent understanding of the present disclosure. Accordingly, it should be apparent to those skilled in the art that the following description of various embodiments of the present disclosure is provided for illustration purpose only and not for the purpose of limiting the present disclosure as defined by the appended claims and their equivalents.

[0028] It should be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more of such surfaces.

[0029] The terms "comprise" or "may comprise" refer to the existence of the corresponding disclosed function, operation, or component in the various embodiments of the present disclosure, and do not limit the existence of one or more additional functions, operations, or features. In addition, the terms "comprise" or "have" can be interpreted to denote the presence of certain characteristics, numbers, steps, operations, constituent elements, components, or combinations thereof, but should not be interpreted as excluding the possibility of the presence of one or more other characteristics, numbers, steps, operations, constituent elements, components, or combinations thereof.

[0030] The term "or" used in the various embodiments of the present disclosure includes any of the listed terms and all combinations thereof. For example, "A or B" can include A, can include B, or can include both A and B.

[0031] Unless defined differently, all terms used in the present disclosure, including technical or scientific terms, have the same meaning as understood by a person skilled in the art to which the present disclosure pertains. The commonly used terms are interpreted to have meanings consistent with the context in the related technical fields, and should not be ideally or overly formally interpreted, unless clearly defined in the present disclosure.

[0032] In top or bottom heat dissipation package, the heat dissipation substrate for dissipating heat of the chip is made of conductive material, and the outer side of the heat dissipation substrate is exposed outside the package, while the substrate of the chip (such as a power chip) is directly attached to the inner side of the heat dissipation substrate. In order to achieve electrical isolation of the chip from the outside, an insulating material needs to be arranged on the outer side of the heat dissipation substrate, and the wiring needs to be designed, which reduces the heat dissipation capacity of the package and increases the complexity of the circuit wiring.

[0033] In high-density integration scheme, multiple semiconductor devices (such as power chips, control chips or passive devices (resistor / capacitor / inductor) etc.) need to be integrated in a single plastic package. The substrate potentials of multiple chips can be non-uniform, or the potentials between the pads of passive devices and chips can be different. Since multiple semiconductor devices are arranged on the heat dissipation substrate, the substrates of multiple chips or the chips and passive devices will be electrically connected through the heat dissipation substrate, causing problems such as potential or signal interference. For integrated schemes such as drive and power device integration, if multiple chips are combined and each chip needs to be isolated from the substrate, the power chip and the drive chip that need to be isolated from the substrate are usually arranged on the heat dissipation substrate and the pins respectively (for example, the substrate of the power chip is arranged on the heat dissipation substrate, and the substrate of the drive chip is arranged on the pin) to achieve physical isolation. In order to meet the high voltage level of the device and the high creepage requirement between chips, the size of the heat dissipation substrate will be greatly affected, and the heat dissipation effect will be reduced.

[0034] To solve the above problems, the present application provides a multi-chip combined package structure and a forming method thereof. The multi-chip combined package structure according to the embodiment of the present application can realize the insulation of multiple chips and the heat dissipation substrate without affecting the size of the package pin, and at the same time, the top heat dissipation substrate or the bottom heat dissipation substrate is insulated from the multiple chips, which reduces the complexity of system heat dissipation and board-level wiring of unidirectional power devices or bidirectional power devices in half-bridge and full-bridge applications.

[0035] Figure 1 A top view of a chip package 100 according to an embodiment of the present application is given. In Figure 1 The chip package 100 includes a heat dissipation substrate 101, an insulating substrate 102, a first chip 103 and a second chip 110, wherein the heat dissipation substrate 101 is made of conductive material. In an embodiment, the heat dissipation substrate 101 includes copper, aluminum or alloy, etc. The insulating substrate 102 includes various insulating materials, such as ceramic sheet, AlN (aluminum nitride), diamond, SiC (silicon carbide) and the like. In Figure 1 The insulating substrate 102 can be arranged on the heat dissipation substrate 101 in various ways, for example, the insulating substrate 102 can be attached to the heat dissipation substrate 101 through a first medium (such as a dielectric paste, etc.). Figure 1 The first medium is not shown, and the subsequent Figure 2(Illustrated) is disposed on the heat dissipation substrate 101. In one embodiment, the first medium includes solder, conductive adhesive, non-conductive adhesive, or epoxy resin adhesive, etc. In one embodiment, the thickness of the insulating substrate 102 is 100um-1000um. The thickness of the insulating substrate 102 is determined by the substrate material. In one embodiment, the thinner the insulating substrate 102, the better the heat dissipation performance of the chip package. The first chip 103 is disposed on the heat dissipation substrate 101 through the second medium (…). Figure 1 The second medium was not shown, and the following... Figure 2 (Illustrated) The chip 103 is disposed on an insulating substrate 102. In one embodiment, the first chip 103 is a power device, such as a wide-bandgap semiconductor power device. In another embodiment, the first chip 103 is a gallium nitride power device. The chip package 100 also includes a plurality of pins 104 extending from both sides of the molding compound (not shown). It should be noted that... Figure 1 The chip package 100 also includes a plastic encapsulation body, for illustrative purposes. Figure 1 The plastic seal is not shown.

[0036] Figure 2 An embodiment of the present invention is given. Figure 1 The image shows a cross-sectional view of the chip package 100 along plane AA'. Figure 2In the illustrated embodiment, the chip package 100 includes a heat dissipation substrate 101, an insulating substrate 102, a first chip 103, and a plastic package 105. The plastic package 105 has an upper surface SU and a lower surface SD. The heat dissipation substrate 101 includes a first surface SI and a second surface S2, wherein the first surface SI of the heat dissipation substrate 101 is exposed from the upper surface SU of the plastic package 105. The heat dissipation substrate 101 can dissipate heat generated by the first chip 103 when the first chip 103 is in operation. The insulating substrate 102 has a third surface S3 and a fourth surface S4, wherein the insulating substrate 102 is disposed on the second surface S2 of the heat dissipation substrate 101 by a first medium 106. The first medium 106 serves to connect and fix the insulating substrate 102 and the heat dissipation substrate 101. In one embodiment, the first medium 106 includes solder, conductive, non-conductive glue, or epoxy glue. The first chip 103 has a first substrate surface SUB1, wherein the first substrate surface SUB1 is disposed on the fourth surface S4 of the insulating substrate 102 by a second medium 107. The second medium 107 serves to connect and fix the insulating substrate 102 and the first chip 103. In one embodiment, because the first chip 103 is a power chip and requires higher heat dissipation performance, and solder or conductive glue has better heat dissipation performance, the second medium 107 includes solder or conductive glue. The second chip 110 has a second substrate surface SUB2, wherein the second substrate surface SUB2 is disposed on the fourth surface S4 of the insulating substrate 102 by a third medium 112. The third medium 112 serves to connect and fix the insulating substrate 102 and the second chip 110. In one embodiment, the second chip 110 includes a driver chip for controlling the power chip. In one embodiment, the third medium 112 includes solder, conductive glue, or non-conductive glue. The chip package further includes a plurality of pins 104 extending from both sides of the plastic package 105. In Figure 2 In the illustrated embodiment, the heat dissipation substrate 101 is located on the top of the plastic package 105.

[0037] Figure 3 A top view of a chip package 400 according to another embodiment of the present application is shown. Figure 1 A cross-sectional view of the chip package 100 along the plane AA' is shown. And Figure 2 In the illustrated embodiment, the heat dissipation substrate 101 is located on the top of the plastic package 105. Figure 3 In the illustrated embodiment, the heat dissipation substrate 101 is located on the bottom of the plastic package 105 and the first surface SI of the heat dissipation substrate 101 is exposed from the lower surface SD of the plastic package 105.

[0038] Figure 4 A top view of a chip package 400 according to another embodiment of the present application is shown. Figure 1 In the illustrated chip package, the fourth surface S4 of the insulating substrate 102 of the chip package 400 has a first metal layer 108. Compared to Figure 2In the shown embodiment, the first metal layer 108 makes the heat dissipation of the chip package 400 and the adhesion of the first chip 103 and the insulating substrate 102 better. In an embodiment, the thickness of the first metal layer 108 is 50-600um. In another embodiment, the thickness of the first metal layer 108 is 100um. In an embodiment, the first metal layer 108 includes copper. In another embodiment, the first metal layer 108 includes tin or aluminum alloy or the like. In Figure 4 In the shown embodiment, the first chip 103 and the second chip 110 have the same substrate potential, and the first chip 103 and the second chip 110 are both on the first metal layer 108.

[0039] Figure 5 Fig. 2 shows a cross-sectional view of the chip package 400 along BB' according to an embodiment of the present application. In the shown embodiment, the first chip 103 and the second chip 110 have the same substrate potential, and the first chip 103 and the second chip 110 are both on the first metal layer 108. Figure 4 In the shown embodiment, the first chip 103 and the second chip 110 have the same substrate potential, and the first chip 103 and the second chip 110 are both on the first metal layer 108. Figure 5 In the shown embodiment, the first chip 103 and the second chip 110 have the same substrate potential, and the first chip 103 and the second chip 110 are both on the first metal layer 108. Figure 5 In the shown embodiment, the first chip 103 has a first substrate surface SUB1, and the first substrate surface SUB1 and the fourth surface S4 of the insulating substrate 102 are connected by the second medium 107. In an embodiment, the second medium 107 is solder. The second chip 110 has a second substrate surface SUB2, and the second substrate surface SUB2 and the fourth surface S4 of the insulating substrate 102 are connected by the third medium 112. In an embodiment, the third medium 112 is solder.

[0040] Figure 6 Fig. 4 shows a cross-sectional view of the chip package 400 along BB' according to another embodiment of the present application. In the shown embodiment, the first chip 103 and the second chip 110 have the same substrate potential, and the first chip 103 and the second chip 110 are both on the first metal layer 108. Figure 4 In the shown embodiment, the first chip 103 and the second chip 110 have the same substrate potential, and the first chip 103 and the second chip 110 are both on the first metal layer 108. Figure 5 In the shown embodiment, the first chip 103 and the second chip 110 have the same substrate potential, and the first chip 103 and the second chip 110 are both on the first metal layer 108. Figure 6 In the shown embodiment, the third surface S3 of the insulating substrate 102 further has a second metal layer 109, and the second metal layer 109 and the first metal layer 108 have no through hole, i.e. the first metal layer 108 and the second metal layer 109 have no electrical connection. In an embodiment, the second metal layer 109 and the first metal layer 108 have the same thickness and material. Compared with the insulating substrate 102 having only the first metal layer 108, the insulating substrate 102 having the first metal layer 108 and the second metal layer 109 makes the coefficient of thermal expansion of the insulating substrate 102 better.

[0041] Figure 7Fig. 1 shows a circuit diagram of a first chip 103 and a second chip 110 according to an embodiment of the present application. In the figure, the first chip 103 comprises a unidirectional gallium nitride power device, and the second chip 110 comprises a driving or control chip, wherein the substrate potential of the first chip 103 and the substrate potential of the second chip 110 are the same, so the substrate potential of the first chip 103 and the substrate potential of the second chip 110 do not need to be isolated. Figure 7 The circuit shown can be used in a chip package. Figures 1-6 The chip package shown. Figure 7 In the first chip 103, the gallium nitride transistor has an input terminal G, a first terminal D and a second terminal S. In the first chip 103, the substrate potential of the first terminal D and the substrate potential of the second terminal S are the same. Figure 7 In the embodiment shown, the first chip 103 has a voltage resistance value of 100 V to 1800 V, wherein the voltage resistance value refers to the maximum voltage that the source terminal and the drain terminal of the first chip 103 can withstand.

[0042] Figure 8 Fig. 2 shows a top view of a chip package 800 according to an embodiment of the present application. The chip package 800 is similar to the chip package 400 shown in Fig. 1, and the same components are denoted by the same reference numerals. Figure 4 The difference between the chip package 400 shown in Fig. 1 and the chip package 800 shown in Fig. 2 is that in the chip package 800, the substrate potential of the first chip 103 and the substrate potential of the second chip 110 are not the same, so in the chip package 800, the substrate potential of the first chip 103 and the substrate potential of the second chip 110 need to be isolated. Figure 8 In the embodiment shown, the first chip 103 and the second chip 110 are arranged on the first metal layer 108, and the first chip 103 and the second chip 110 are electrically isolated by the first metal layer 108. Figure 8 In the embodiment shown, the first metal layer 108 has a first region 108-1 and a second region 108-2, wherein the first region 108-1 and the second region 108-2 are electrically isolated, the first chip 103 is arranged on the first region 108-1, and the second chip 110 is arranged on the second region 108-2. Figure 8 In the embodiment shown, only the first metal layer 108 is shown to comprise two regions 108-1 and 108-2 that are electrically isolated from each other, but the present application is not limited thereto, and according to an example embodiment of the present application, the first metal layer 108 can comprise any number of regions that are electrically isolated from each other.

[0043] Figure 9 Fig. 3 shows a cross-sectional view of the chip package 800 along the section CC’ according to an embodiment of the present application. Figure 8 The first metal layer 108 has a first region 108-1 and a second region 108-2, wherein the first region 108-1 and the second region 108-2 are electrically isolated, the first chip 103 is arranged on the first region 108-1, and the second chip 110 is arranged on the second region 108-2.

[0044] Figure 10 Fig. 4 shows a cross-sectional view of the chip package 800 along the section CC’ according to another embodiment of the present application. Figure 8 The chip package 800 shown in Fig. 4 is similar to the chip package 800 shown in Fig. 3, and the same components are denoted by the same reference numerals. Figure 9 The difference between the chip package 800 shown in Fig. 3 and the chip package 800 shown in Fig. 4 is that in the chip package 800 shown in Fig. 4, the first chip 103 and the second chip 110 are arranged on the second metal layer 109, and the first chip 103 and the second chip 110 are electrically isolated by the second metal layer 109. Figure 10A second metal layer 109 is provided on the third surface S3 of the insulating substrate 102. Figure 10 In this embodiment, the third surface S3 of the insulating substrate 102 has a second metal layer 109, wherein there are no through holes between the second metal layer 109 and the first metal layer 108, meaning that the first metal layer 108 and the second metal layer 109 are not electrically connected. In one embodiment, the second metal layer 109 and the first metal layer 108 have the same thickness and material. Compared to an insulating substrate 102 that only has a first metal layer 108, Figure 10 The insulating substrate 102 has a better coefficient of thermal expansion because it has a first metal layer 108 and a second metal layer 109.

[0045] Figure 11 A top view of a chip package 1100 according to an embodiment of the present invention is provided. Figure 1 Unlike the chip package 100 shown, the insulating substrate 102 of the chip package 1100 includes separate first insulating region 102-1 and second insulating region 102-2. Figure 11 In this configuration, the first chip 103 is located on the first insulating region 102-1, and the second chip 110 is located on the second insulating region 102-2. The first chip 103 is insulated from the heat dissipation substrate 101 through the second insulating region 102-1, and the second chip 110 is insulated from the heat dissipation substrate 101 through the second insulating region 102-2. Figure 11 In the illustrated embodiment, the insulating substrate 102 of the package 1100 consists of a separate first insulating region 102-1 and a second insulating region 102-2, but this application is not limited thereto. According to an example embodiment of this application, any number of separated insulating substrates 102 can be provided on the heat dissipation substrate 101. Figure 11 The chip package 1100 shown has a first insulating region 102-1 and a second insulating region 102-2 on the heat dissipation substrate 101. That is, the insulating substrate 102 is not a single piece, but two pieces set according to the area of ​​the first chip 103 and the second chip 110. This arrangement can reduce the material of the insulating substrate and reduce the cost while meeting the insulation and heat dissipation requirements of the device.

[0046] Figure 12 Given Figure 11 The image shows a cross-sectional view of the chip package 100 along DD'. From Figure 12 As can be seen, the first chip 103 has a first substrate surface SUB1, which is disposed on the first insulating region 102-1 through a second dielectric 107. The first chip 103 is insulated from the heat dissipation substrate 101 through the first insulating region 102-1. The second chip 110 has a second substrate surface SUB2, which is disposed on the second insulating region 102-2 through a third dielectric 112. The second chip 110 is insulated from the heat dissipation substrate 101 through the second insulating region 102-2.

[0047] Figure 13 Given Figure 11 The image shows a cross-sectional view of chip package 100 along DD'. Figure 12 The packaging shown is different, Figure 13 In this embodiment, a first metal layer 108 is present on the fourth surface S4 of the insulating substrate 102. Figure 13 In the first metal layer 108, there are a first region 108-1 and a second region 108-2, wherein the first region 108-1 and the second region 108-2 are electrically insulated. The first metal layer 108 makes the adhesion between the first chip 103 and the first insulating region 108-1 stronger.

[0048] Figure 14 Given Figure 11 The image shows a cross-sectional view of chip package 100 along DD'. Figure 13 The packaging shown is different, Figure 14 In this embodiment, a third metal layer 109 is provided on the third surface S3 of the insulating substrate 102. The second metal layer 109 strengthens the adhesion between the insulating substrate 102 and the heat dissipation substrate 101. Figure 14 In the second metal layer 109, there are a third region 109-1 and a fourth region 109-2, wherein the third region 109-1 and the fourth region 109-2 are electrically insulating. Figure 14 In this embodiment, the third surface S3 of the insulating substrate 102 has a second metal layer 109, wherein there are no through holes between the second metal layer 109 and the first metal layer 108, meaning that the first metal layer 108 and the second metal layer 109 are not electrically connected. In one embodiment, the second metal layer 109 and the first metal layer 108 have the same thickness and material. Compared to an insulating substrate 102 that only has a first metal layer 108, Figure 14 The insulating substrate 102 has a better coefficient of thermal expansion because it has a first metal layer 108 and a second metal layer 109.

[0049] Figure 15 A circuit diagram of a first chip 103 and a second chip 110 according to an embodiment of the present invention is provided. Figure 15 In the first chip 103, a bidirectional common-drain gallium nitride transistor is included. The second chip 110 includes a second driver or control chip, wherein the substrate potential of the first chip 103 and the substrate potential of the second chip 110 are different. Figure 15 The first chip 103 and the second chip 110 shown can be adopted Figure 8The package shown has a first metal layer 108 having a first region 108-1 and a second region 108-2. The first region 108-1 and the second region 108-2 are electrically isolated to isolate the substrate potential of the first chip 103 and the substrate potential of the second chip 110. Figure 15 The first chip 103 and the second chip 110 shown can also be adopted Figure 11 The package shown isolates the substrate potential of the first chip 103 and the substrate potential of the second chip 110 by setting a first insulating region 102-1 and a second insulating region 102-2. Figure 15 The first chip 103 and the second chip 110 shown can also be used Figure 2 The package shown, i.e., the fourth surface S4 of the insulating substrate 102 does not have the first metal layer 108, and the substrate potential of the first chip 103 and the second chip 110 are insulated.

[0050] Figure 16 A method 1600 for forming a chip package according to an embodiment of the present invention is provided. (See reference...) Figures 1-15 Method 1600 is described below. Method 1600 includes:

[0051] 1601: Forming a heat dissipation substrate 101, wherein the heat dissipation substrate 101 has a first surface S1 and a second surface S2. For example, the heat dissipation substrate 101 may also be called a heat sink, a heat dissipation island, etc. The heat dissipation substrate 101 may be a conductive substrate (e.g., copper, aluminum, or alloy).

[0052] 1602: An insulating substrate 102 is disposed on the second surface of a heat dissipation substrate 101 via a first medium 106, wherein the insulating substrate 102 has a third surface S3 and a fourth surface S4. According to an example of the present invention, the insulating substrate 102 can be disposed on the heat dissipation substrate 101 in various ways. For example, the insulating substrate 102 can be fixed to the heat dissipation substrate 101 by means of bonding, welding, or adhesive, but the present invention is not limited thereto. The insulating substrate 102 can be made of a purely insulating ceramic sheet, AlN (aluminum nitride), diamond, SiC (silicon carbide), or other materials. In one embodiment, the fourth surface S4 of the insulating substrate 102 has a first metal layer 108. In one embodiment, the fourth surface S4 of the insulating substrate 102 has a first metal layer 108, wherein the first metal layer 108 includes a divided first region 108-1 and a second region 108-2. In another embodiment, the fourth surface S4 of the insulating substrate 102 has a first metal layer 108, and the third surface S3 of the insulating substrate 102 has a second metal layer 109. In another embodiment, the fourth surface S4 of the insulating substrate 102 has a first metal layer 108, wherein the first metal layer 108 includes a separated first region 108-1 and a second region 108-2, and the third surface S3 of the insulating substrate 102 has a second metal layer 109. In one embodiment, the insulating substrate 102 includes a separated first insulating region 102-1 and a second insulating region 102-2. It should be noted that the first insulating region 102-1 and the second insulating region 102-2 described here are merely illustrative, and this application may also include multiple insulating regions.

[0053] 1603: A first chip 103 is disposed on the fourth surface S4 of an insulating substrate 102 via a second medium 107, and a second chip 110 is disposed on the fourth surface S4 of the insulating substrate 102 via a third medium 112. According to an exemplary embodiment of the present invention, the first chip 103 can be disposed on the fourth surface S4 of the insulating substrate 102 in various ways. For example, the first chip 103 can be fixed to the insulating substrate 102 by means of bonding, welding, or adhesive, but the present invention is not limited thereto. In one embodiment, the first chip 103 is disposed on the fourth surface S4 of the first insulating region 102-1 via the second medium 107, and the second chip 110 is disposed on the fourth surface S4 of the second insulating region 102-2 via the third medium 112. In one embodiment, the first chip 103 is disposed on the fourth surface S4 of the first region 108-1 via the second medium 107, and the second chip 110 is disposed on the fourth surface S4 of the first region 108-2 via the third medium 112.

[0054] 1604: Form a molding compound 105, wherein a first surface S1 of the heat dissipation substrate 101 is exposed from either the upper surface SU or the lower surface SD of the molding compound 105. The first surface S1 of the heat dissipation substrate 101 may be exposed to the outside of the molding compound 105 for heat dissipation.

[0055] The packaging method of this application eliminates the need to coat the outside of the heat sink substrate with insulating material or set an insulating layer, thereby improving the heat dissipation effect of top- or bottom-heat sink packages without affecting the package and pin dimensions. Furthermore, in the integrated solution, the substrate potentials of one or more semiconductor devices are not electrically connected via the heat sink substrate, achieving effective electrical isolation between the substrate potentials of the semiconductor devices. This satisfies the high voltage withstand ratings and high creepage requirements between devices without affecting the size of the heat sink substrate. When one or more semiconductor devices include novel power devices such as bidirectional gallium nitride, multiple substrates, such as insulating substrates, can be used to meet the isolation requirements supporting dynamic potential changes. Simultaneously, due to the electrical insulation between the heat sink substrate and the inner semiconductor devices, the package with internal insulation according to the exemplary embodiments of the present invention can also reduce the complexity of system heat dissipation and board-level wiring.

[0056] The improved top- or bottom-heat-dissipating packages with internal insulation and their formation methods according to various exemplary embodiments of the present invention can achieve insulation between the device and the heat dissipation substrate without affecting the package and package pin dimensions, thereby improving the heat dissipation effect of the top- or bottom-heat-dissipating package. This also achieves package-level insulation between multiple semiconductor devices within the top- or bottom-heat-dissipating package, enabling the top- or bottom-heat-dissipating package to support dynamic potential changes in novel power devices such as bidirectional gallium nitride, and reducing the complexity of system heat dissipation and board-level wiring in half-bridge and full-bridge applications. The improved top- or bottom-heat-dissipating packages with internal insulation and their formation methods according to various embodiments of the present invention can be applied to, for example, wide-bandgap semiconductor devices (such as SiC, GaN, Ga2O3, AlN, diamond, etc., and for bidirectional GaN devices).

[0057] Those skilled in the art will understand that the illustrative embodiments described above are not intended to be limiting. It should be understood that any two or more of the embodiments disclosed herein can be combined in any combination. Furthermore, other embodiments may be utilized and other changes may be made without departing from the spirit and scope of the subject matter presented herein. It will be readily understood that aspects of the invention disclosed herein, as generally described herein and illustrated in the accompanying drawings, can be arranged, substituted, combined, separated, and designed in a variety of different configurations, all of which are contemplated herein.

[0058] The exemplary embodiments described herein are not intended to be limiting. The aspects of this disclosure, as generally described herein and shown in the accompanying drawings, can be arranged, substituted, combined, separated, and designed in a variety of different configurations, all of which are conceivable herein. Furthermore, unless the context otherwise requires, the features shown in each drawing can be used in combination with each other. Therefore, the accompanying drawings should be considered... Figure 1 These features are generally considered to be part of one or more overall embodiments, but it should be understood that not all of the illustrated features are necessary for each embodiment.

[0059] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can make various changes or substitutions within the technical scope disclosed in this disclosure, and such changes or substitutions should all be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip package, comprising: A plastic sealant having a top surface and a bottom surface; A heat dissipation substrate has a first surface and a second surface, wherein the first surface of the heat dissipation substrate is exposed from the upper or lower surface of a molding compound; An insulating substrate has a third surface and a fourth surface, wherein the third surface of the insulating substrate is disposed on the second surface of a heat dissipation substrate via a first medium; A first chip has a first substrate surface, wherein the first substrate surface is disposed on a fourth surface of an insulating substrate via a second medium; as well as The second chip has a second substrate surface, wherein the second substrate surface is disposed on a fourth surface of an insulating substrate via a third medium.

2. The chip package according to claim 1, wherein the first chip includes a power device, and the second chip includes a driver or control chip or a passive device.

3. The chip package according to claim 1, wherein the first medium includes solder, conductive adhesive or non-conductive adhesive, the second medium includes solder or conductive adhesive, and the third medium includes solder, conductive adhesive or non-conductive adhesive.

4. The chip package according to claim 1, wherein the fourth surface of the insulating substrate has a first metal layer.

5. The package according to claim 4, wherein the first metal layer has a first region and a second region, the first region and the second region are electrically isolated, wherein the first chip is disposed on the first region and the second chip is disposed on the second region.

6. The chip package according to claim 4 or 5, wherein the third surface of the insulating substrate has a second metal layer.

7. The chip package according to claim 6, wherein, There is no through-hole connection between the first metal layer and the second metal layer.

8. A chip package, comprising: A plastic sealant having a top surface and a bottom surface; A heat dissipation substrate has a first surface and a second surface, wherein the first surface of the heat dissipation substrate is exposed from the upper or lower surface of a molding compound; An insulating substrate has a third surface and a fourth surface, wherein the third surface of the insulating substrate is disposed on the second surface of a heat dissipation substrate through a first medium, and wherein the insulating substrate includes a separate first insulating region and a second insulating region. A first chip has a first substrate surface, wherein the first substrate surface is disposed on a fourth surface of a first insulating region via a second medium; as well as The second chip has a second substrate surface, wherein the second substrate surface is disposed on the fourth surface of the second insulating region by a third medium.

9. The chip package according to claim 8, wherein the first chip includes a power device and the second chip includes a driver or control chip or a passive device.

10. The chip package of claim 8, wherein the fourth surface of the insulating substrate has a first metal layer.

11. The chip package of claim 8, wherein the third surface of the insulating substrate has a second metal layer.

12. The chip package according to claim 8, wherein the first medium comprises solder, conductive adhesive or non-conductive adhesive, the second medium comprises solder or conductive adhesive, and the third medium comprises solder, conductive adhesive or non-conductive adhesive.

13. A method for forming a chip package, the method comprising: A heat dissipation substrate is formed, wherein the heat dissipation substrate has a first surface and a second surface; An insulating substrate is formed, the insulating substrate having a third surface and a fourth surface, wherein the third surface of the insulating substrate is disposed on the second surface of the heat dissipation substrate through a first medium; The first chip is disposed on the fourth surface of the insulating substrate through the second medium, and the second chip is disposed on the fourth surface of the insulating substrate through the third medium. as well as A molding compound is formed, wherein a first surface of the heat dissipation substrate is exposed from the upper or lower surface of the molding compound.

14. The method of claim 13, wherein the insulating substrate includes an isolated first insulating region and a second insulating region, wherein the first chip is disposed in the first insulating region and the second chip is disposed in the second insulating region.

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