Driving circuit, driving method, and display device

Abstract

The application discloses a driving circuit, a driving method and a display device. The driving circuit comprises a gate driving circuit and a gate driving signal compensation circuit. The gate driving signal compensation circuit mainly comprises a driving strengthening module and a charging strengthening module. The driving strengthening module is connected with a first node and controls the voltage stored in a first storage module based on the voltage of the first node. One end of the charging strengthening module is connected with the first storage module, and the other end is connected with the first node and a second level signal output end respectively, receives a second level signal, and increases the charging capacity of the first storage module. A gate driving signal generation module generates a gate driving compensation signal based on the voltage signal transmitted by the first storage module and a clock signal, and stores the gate driving compensation signal to be output to the scanning line of a display panel. The voltage of the first node is strengthened and stabilized by the charging strengthening module and the driving strengthening module, so that the stability of the gate driving signal output is ensured.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit, driving method and display device. Background Technology

[0002] Gate Driver on Array (GOA), also known as gate drive circuit or gate drive circuit, integrates the gate drive circuit on the array substrate of the display panel to achieve a line-by-line scanning drive method. This eliminates the need for a separate gate drive circuit, which has the advantages of reducing production costs and enabling narrow bezel designs on the panel. It is used in a variety of displays.

[0003] Currently, the GOA signal is scanned continuously level by level, and it is not possible to turn on a specific row independently at a certain time. Because of this limitation, the existing compensation mechanism will continuously compensate for each row without selectivity, which will consume a lot of time. This is especially true for applications where the threshold voltage in the display changes due to temperature drift, and it is impossible to achieve real-time compensation. When the thin-film transistor is in the on state most of the time, the thin-film transistor will be forward biased, causing the threshold voltage to be forward biased, which will reduce the transmission capability of the thin-film transistor and is not conducive to the stability of the circuit output. Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit, driving method, and display device that can improve the stability of the signal output by the gate driving circuit.

[0005] This application discloses a driving circuit, which includes a gate driving circuit and a gate driving signal compensation circuit. The gate driving signal compensation circuit includes a gate driving signal control module, a first storage module, a driving enhancement module, a charging enhancement module, a control module, and a gate driving signal generation module. The gate driving signal control module is connected to the gate driving circuit, receives the gate driving signal corresponding to any scan line output by the gate driving circuit, and outputs it to a first node. One end of the first storage module is connected to the first node, and the other end is connected to a first level signal output terminal to receive a first level signal. The driving enhancement module is connected to the first node and outputs the voltage stored in the first storage module based on the voltage of the first node. One end of the charging enhancement module is connected to the first storage module, and the other end is connected to the first node and a second level signal output terminal respectively to receive a second level signal and increase the charging capability of the first storage module. One end of the control module is connected to the driving enhancement module, and the other end is connected to the gate driving signal generation module. The gate driving signal generation module generates a gate driving compensation signal based on the voltage signal and clock signal transmitted from the first storage module, stores it, and outputs it to the scan line of the display panel.

[0006] Optionally, the gate drive signal compensation circuit further includes a release module, which is disposed between the first node and the second level signal output terminal, and is used to release the voltage at the first node. The voltage corresponding to the first level signal is the first-order high voltage at the first node, and the voltage corresponding to the second level signal is the low voltage.

[0007] Optionally, the gate drive signal control module includes a first drive transistor, the first storage module includes a first storage capacitor, the control module includes a second drive transistor, the gate drive signal generation module includes a third drive transistor and a second storage capacitor, the charge enhancement module includes a sixth drive transistor, the release module includes a seventh drive transistor, and the drive enhancement module includes an eighth drive transistor; the input terminal of the first drive transistor is connected to the gate drive circuit and receives the gate drive signal output by the gate drive circuit, the output terminal is connected to the first node, and the control terminal receives a first control signal; the input terminal of the first storage capacitor is connected to a first level signal output terminal and receives the first level signal, the output terminal is connected to the first node; the control terminal of the second drive transistor receives a second control signal, and the input terminal is connected to the output terminal of the eighth drive transistor. The output terminal of the third driving transistor is connected to the second node. The control terminal of the third driving transistor is connected to the second node. The input terminal receives a clock signal, and the output terminal outputs an adjusted gate driving signal. One end of the second storage capacitor is connected to the second node, and the other end is connected to the output terminal of the third driving transistor. The control terminal and input terminal of the sixth driving transistor are connected between the first node and the output terminal of the seventh driving transistor, and the output terminal is connected between the first storage capacitor and the first level signal output terminal. The control terminal of the seventh driving transistor receives a third control signal, the input terminal is connected to the second level signal output terminal, and the output terminal is connected to the input terminal of the sixth driving transistor. The input terminal of the eighth driving transistor is connected between the first storage capacitor and the first level signal output terminal, the output terminal is connected to the input terminal of the second driving transistor, and the control terminal is connected to the first node.

[0008] Optionally, the gate drive signal compensation circuit further includes a first pull-down module and a second pull-down module. One end of the first pull-down module is connected to the gate drive signal generation module, and the other end is connected to the third level signal output terminal to receive the third level signal. One end of the second pull-down module is connected to the control module, and the other end is connected to the second level signal output terminal to receive the second level signal. The voltage value corresponding to the second level signal is different from the voltage value corresponding to the third level signal.

[0009] Optionally, the first pull-down module includes a fourth driving transistor, and the second pull-down module includes a fifth driving transistor. The output terminal of the fourth driving transistor is connected to the output terminal of the gate driving signal generation module, and its input terminal is connected to the second level signal output terminal to receive the second level signal. The control terminal receives a third control signal. The output terminal of the fifth driving transistor is connected between the control module and the gate driving signal generation module, and its input terminal is connected to the third level signal output terminal to receive the third level signal. The control terminal receives the third control signal.

[0010] Optionally, the driving circuit further includes a frame calculation module, which calculates the number of frames output to the display panel. The frame calculation module is connected to the gate drive signal compensation circuit. The frame includes idle time and display time. During the display time, the display panel receives and displays corresponding gate drive signals and data signals. During the idle time, the display panel does not display anything. In each frame's idle time, the frame calculation module controls the gate drive signal compensation circuit to compensate the gate drive signal of any row in the current frame and controls the currently compensated row to be turned on. In different frames, the frame calculation module controls the gate drive signal compensation circuit to compensate the gate drive signals of different rows and controls the currently compensated row to be turned on in different frames.

[0011] Optionally, the display panel is divided into multiple display areas based on scan lines, each display area including at least one scan line. During the idle time of each frame, the frame calculation module controls the gate drive signal compensation circuit to compensate the gate drive signal of any row in any display area of ​​the current frame. In different frames, the frame calculation module controls the gate drive signal compensation circuit to compensate the gate drive signals of different rows in different display areas. In adjacent frames, the two scan lines compensated by the gate drive signal compensation circuit correspond to two non-adjacent display areas.

[0012] This application also discloses a driving method for using the driving circuit described in any of the above to drive a display panel, the driving method comprising:

[0013] Obtain the gate drive signal at the input of the gate drive circuit corresponding to the current scan line;

[0014] The gate drive signal is controlled to be input to the first node, thereby increasing the charging capability of the first memory module through the charging enhancement module;

[0015] The drive enhancement module and the control module are turned on to transmit the voltage signal of the first storage module to the gate drive signal generation module; and

[0016] The gate drive signal generation module generates a gate drive compensation signal based on the voltage signal and clock signal transmitted from the first storage module, stores it, and outputs it to the scan line of the display panel.

[0017] Optionally, the gate drive signal compensation circuit further includes a release module disposed between the first node and the second level signal output terminal. The drive circuit further includes a frame calculation module that calculates the number of frames output to the display panel. The frame calculation module is connected to the gate drive signal compensation circuit. The frame includes idle time and display time. The driving method further includes the following steps:

[0018] During the idle time of each frame, the frame calculation module controls the gate drive signal compensation circuit to compensate the gate drive signal of any row in any display area of ​​the current frame, and controls the opening of the corresponding pixel row. After a preset time, the release module is controlled to open to reset the first storage module.

[0019] This application also discloses a display device, which includes a display panel and a driving circuit as described above, wherein the driving circuit drives the display panel using a driving method as described above.

[0020] Compared to the scheme where the GOA circuit continuously compensates and enhances the gate drive signal of the GOA circuit for each scan line, this application provides a driving circuit including a gate drive circuit and a gate drive signal compensation circuit. The gate drive signal compensation circuit includes a drive enhancement module and a charging enhancement module. By adding a set of circuits next to the GOA circuit, the long-term compensation of the entire screen is changed to short-term random compensation of a single line. By controlling the drive enhancement module and the charging enhancement module, the charging enhancement capability of the first storage module is realized. Based on the voltage signal and clock signal transmitted from the enhanced first storage capacitor, a gate drive compensation signal is generated and stored for output to the scan line of the display panel, ensuring the stability of the gate drive signal output. Attached Figure Description

[0021] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0022] Figure 1This is a schematic diagram of an exemplary gate driving unit of this application;

[0023] Figure 2 This application is Figure 1 Timing diagram of the gate drive unit;

[0024] Figure 3 This is a schematic diagram of an exemplary compensation circuit of this application;

[0025] Figure 4 This is a schematic diagram of the driving circuit of the first embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the driving circuit of the second embodiment of this application;

[0027] Figure 6 This is a schematic diagram of the driving circuit according to the third embodiment of this application;

[0028] Figure 7 This is a schematic diagram of the driving circuit of the fourth embodiment of this application;

[0029] Figure 8 This is a schematic diagram of the driving circuit of the fifth embodiment of this application;

[0030] Figure 9 This is a schematic diagram of the gate drive signal latching of the drive circuit in the fifth embodiment of this application;

[0031] Figure 10 This is a schematic diagram of the gate drive signal storage of the drive circuit in the fifth embodiment of this application;

[0032] Figure 11 This is a schematic diagram of the driving circuit of the fifth embodiment of this application during charging;

[0033] Figure 12 This is a schematic diagram of the drive circuit in the fifth embodiment of this application during reset;

[0034] Figure 13 This is a schematic diagram of the drive signal waveform according to the fifth embodiment of this application;

[0035] Figure 14 This is a schematic flowchart of the driving method according to the sixth embodiment of this application;

[0036] Figure 15 This is a schematic diagram of the structure of the display device according to the seventh embodiment of this application.

[0037] Among them, 100 is the driving circuit; 110 is the gate driving circuit; 120 is the gate driving signal compensation circuit; 121 is the gate driving signal control module; 122 is the first storage module; 123 is the first level signal output terminal; 124 is the driving enhancement module; 125 is the charging enhancement module; 126 is the second level signal output terminal; 127 is the control module; 128 is the gate driving signal generation module; 129 is the release module; 130 is the frame calculation module; 131 is the first pull-down module; 132 is the second pull-down module; and 133 is the third level signal output terminal. 200, Display panel; 300, Display device; First storage capacitor - C1; Second storage capacitor - C2; First node - Q1; Second node - Q2; First driving transistor - TFT1; Second driving transistor - TFT2; Third driving transistor - TFT3; Fourth driving transistor - TFT4; Fifth driving transistor - TFT5; Sixth driving transistor - TFT6; Seventh driving transistor - TFT7; Eighth driving transistor - TFT8; First level signal - GVDD; Second level signal - VSS1; Third level signal - VSS 0； Gate drive signal - Gate n Gate drive compensation signal - Gate' n； First control signal - RS; Second control signal - VBS; Third control signal - VST; Clock signal - CLK RS . Detailed Implementation

[0038] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0039] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0040] refer to Figure 1 and Figure 2 As shown, an exemplary GOA circuit, GVDD, is disclosed. G It is the first step high voltage at point Q, GVDD 0是 QB1's high voltage, GVDD E It is the high voltage of QB2, the control signal is all the input control signals of GOA, and the gate... n It is the scan line output signal, i.e., the gate drive signal. Figure 1 Work sequence as follows Figure 2 As shown, it is divided into four stages:

[0041] VST is the start of frame signal. When it is high, the voltage at point Q becomes GVDD.G Voltage level, this is stage T1, at which time Q controls T. UP Open, Gate n The voltage is equal to the voltage level VGL of CLK2;

[0042] In phase T2, Q controls T. UP Open, Gate n The voltage is equal to the voltage GVDD of CLK2. G Level; Q-point voltage becomes 2GVDD G Voltage level (C) Q (bootstrapping effect)

[0043] In phase T3, Q controls T. UP Open, Gate n The voltage equals the voltage level VGL of CLK2; the voltage at point Q becomes GVDD. G Voltage level (C) Q (bootstrapping effect)

[0044] T4 phase, next line Gate n+1 GVDD G Level, at this time the Q point potential is controlled by the Gate n+1 The signal is reset to VGL, T UP Closed; QB was boosted, T down The Gate was opened. n Voltage equals VGL level;

[0045] In summary, it can be seen that the existing GOA signal is scanned continuously step by step and cannot be turned on independently for a certain row at a certain time. Because of this limitation, each row will be compensated continuously without selectivity, which will consume a lot of time. Especially for applications where the threshold voltage in the display changes due to temperature drift, it is impossible to achieve real-time compensation.

[0046] like Figure 3 As shown, this is the random access memory circuit in the real-time compensation principle. When the circuit at point Q1 charges C1, the Gate... n It's a high / low signal with limited driving capability. At point Q1, after C1 is fully charged and RS is turned off, there's leakage current, which can cause voltage instability and lead to malfunctions. Gate'... n After opening, C1 needs to be discharged to ensure the consistency of the drive's starting point; obviously... Figure 3 The circuit cannot be implemented.

[0047] refer to Figure 4As shown, in the first embodiment of this application, a driving circuit 100 is disclosed. The driving circuit 100 includes a gate driving circuit 110 and a gate driving signal compensation circuit 120. The gate driving signal compensation circuit 120 includes a gate driving signal control module 121, a first storage module 122, a driving enhancement module 124, a charging enhancement module 125, a control module 127, and a gate driving signal generation module 128. The gate driving signal control module 121 is connected to the gate driving circuit 110 and receives the gate driving signal Gate corresponding to any row of scan lines output by the gate driving circuit 110. n And output to the first node; one end of the first storage module 122 is connected to the first node Q1, and the other end is connected to the first level signal output terminal 123 to receive the first level signal GVDD, where GVDD is equal to Figure 2 The first step high voltage GVDD at point Q in G The drive enhancement module 124 is connected to the first node and outputs the voltage stored in the first storage module 122 based on the voltage control of the first node. One end of the charging enhancement module 125 is connected to the first storage module 122, and the other end is connected to the first node Q1 and the second level signal output terminal 126 respectively, receiving the second level signal VSS1 to increase the charging capability of the first storage module 122. One end of the control module 127 is connected to the drive enhancement module 124, and the other end is connected to the gate drive signal generation module 128. The gate drive signal generation module 128 generates a gate drive compensation signal Gate' based on the voltage signal and clock signal transmitted from the first storage module 122. n The signal is stored and output to the scan lines of the display panel to improve the stability of the signal output by the gate drive circuit 110.

[0048] In this embodiment, an additional circuit is added to the gate drive circuit 110 (also known as the GOA circuit), namely, the gate drive signal compensation circuit 120. The gate drive signal compensation circuit 120 adds a drive enhancement module 124 and a charging enhancement module 125 to improve the charging storage capability of the first storage module 122. The first storage module 122 (e.g., a capacitor) stores the transient voltage of the gate drive signal in real time, providing a reference for subsequent compensation. Even if the input signal is affected by noise, the stored voltage can be used as a reference, reducing output jitter. The drive enhancement module 124 dynamically enhances the drive capability based on the stored voltage, especially during high load or high-frequency switching, ensuring steep signal edges and avoiding display abnormalities caused by excessively long rise / fall times. The charging enhancement module 125... The second-level signal (such as a higher voltage or high current source) quickly replenishes the charge of the storage module, shortening the charging cycle. For high-resolution panels, this can alleviate the delay problem caused by the increase of parasitic capacitance. The charging enhancement module 125 shortens the charging and discharging time of the storage capacitor, enabling the system to adapt to sudden load changes (such as instantaneous high brightness scenes) more quickly, reducing ghosting and trailing phenomena. By enabling the drive enhancement and charging enhancement modules 125 on demand (instead of continuous full power operation), static power consumption can be reduced while ensuring performance. The control module 127 coordinates the timing of each module to ensure that the compensation action is synchronized with the clock signal and avoids phase conflict. The generation module combines the storage voltage and clock to output a precisely compensated signal, improving timing consistency and ensuring the stability of the gate drive signal output.

[0049] refer to Figure 5 As shown, as a second embodiment of this application, it is a further refinement and improvement of the first embodiment described above. The gate drive signal compensation circuit 120 further includes a release module 129. The release module 129 is disposed between the first node Q1 and the second level signal output terminal 126, and is used to release the voltage at the first node Q1. The voltage corresponding to the first level signal GVDD is the first-order high voltage GVDD at the first node Q1. G The voltage corresponding to the second level signal VSS1 is a low voltage.

[0050] In this embodiment, considering that in the first embodiment, after the gate drive signal ends, the first node Q1 maintains a high voltage solely by the first storage module 122 (such as a capacitor) and the first level signal, if the voltage of the first node needs to be re-established in subsequent scan cycles, residual charge may cause charging delay and signal distortion. The residual voltage raises the initial charging starting point, prolonging the time to reach the target voltage. The superposition of old and new charges causes voltage overshoot, resulting in output signal jitter or phase shift. Therefore, a release module 129 is set up to directly bridge the first node Q1 and the second level signal terminal (VSS1, low voltage) to form a low-impedance discharge path. This forces the residual charge at Q1 to be discharged to VSS1, allowing the voltage to quickly return to a low level, eliminating the influence of historical states, and ensuring that the next cycle of charging starts from a clean starting point, avoiding the "memory effect" of the preceding signal. The release module 129 constructs a complete "charging-compensation-reset" closed loop, fundamentally solving the systemic risks caused by residual charge.

[0051] refer to Figure 6 As shown, as a third embodiment of this application, it is a further refinement and improvement of any of the above embodiments. The driving circuit 100 further includes a frame calculation module 130, which calculates the number of frames output to the display panel. The frame calculation module 130 is connected to the gate drive signal compensation circuit 120. The frame includes an idle time V-blanking and a display time. During the display time, the display panel receives the corresponding gate drive signal and data signal for display. During the idle time, the display panel does not display. In each frame's idle time, the frame calculation module 130 controls the gate drive signal compensation circuit 120 to compensate the gate drive signal of any row in the current frame and controls the currently compensated row to be turned on. In different frames, the frame calculation module 130 controls the gate drive signal compensation circuit 120 to compensate the gate drive signal of different rows and controls the currently compensated row to be turned on in different frames.

[0052] Generally, the display panel is divided into multiple display areas based on scan lines, and each display area includes at least one scan line. During the idle time of each frame, the frame calculation module 130 controls the gate drive signal compensation circuit 120 to compensate the gate drive signal of any row in any display area of ​​the current frame. In different frames, the frame calculation module 130 controls the gate drive signal compensation circuit 120 to compensate the gate drive signals of different rows in different display areas. In adjacent frames, the two scan lines compensated by the gate drive signal compensation circuit 120 correspond to two non-adjacent display areas.

[0053] In this embodiment, the frame calculation module 130 counts frames in real time, accurately locates the compensation interval, and triggers the gate drive signal compensation circuit 120 to perform preventive calibration on a single line / single display area instead of full-screen scanning, which greatly reduces power consumption. Through frame-level rotation compensation, each display area experiences a similar "stress-recovery" cycle, avoiding overwork in a single area. When only part of the screen is refreshed, the idle time is concentrated in the inactive area. This solution can compensate the edge of the active area in a targeted manner to eliminate the "black border and bright line" problem. In the paused state of the screen (long idle time), depth compensation is started to clear the accumulated charge and completely solve the static ghosting problem.

[0054] like Figure 7 As shown, as the fourth embodiment of this application, it is a further refinement and improvement of any of the above embodiments. The gate drive signal compensation circuit 120 further includes a first pull-down module 131 and a second pull-down module 132. One end of the first pull-down module 131 is connected to the gate drive signal generation module 128, and the other end is connected to the third level signal output terminal 133 to receive the third level signal. One end of the second pull-down module 132 is connected to the control module 127, and the other end is connected to the second level signal output terminal 126 to receive the second level signal VSS1. The voltage value corresponding to the second level signal is different from the voltage value corresponding to the third level signal.

[0055] This embodiment is a further improvement based on the above embodiment. The charging enhancement module 125 is responsible for dynamic acceleration, while the first pull-down module 131 in this application ensures static safety. Through the dual-level hierarchical pull-down architecture, it fills the key gap in the static protection layer of the gate drive circuit 110, thereby improving signal integrity, ensuring the stability of the final output stage signal, and preventing false triggering (such as scan line crosstalk) caused by the "floating" of the drive signal. The second pull-down module 132 ensures the stability of the voltage signal transmission of the intermediate control circuit and avoids noise from polluting the compensation logic through the feedback loop.

[0056] As a fifth embodiment of this application, it is a further refinement and improvement of any of the above embodiments, referring to... Figures 7 to 14 As shown, the gate drive signal control module 121 includes a first drive transistor TFT1, the first storage module 122 includes a first storage capacitor C1, the control module 127 includes a second drive transistor TFT2, the gate drive signal generation module 128 includes a third drive transistor TFT3 and a second storage capacitor C2, the charge enhancement module 125 includes a sixth drive transistor TFT6, the release module 129 includes a seventh drive transistor TFT7, and the drive enhancement module 124 includes an eighth drive transistor TFT8.

[0057] Specifically, the input terminal of the first driving transistor TFT1 is connected to the gate driving circuit 110, and receives the gate driving signal Gate output by the gate driving circuit 110. n The output terminal is connected to the first node Q1, and the control terminal receives the first control signal RS; the input terminal of the first storage capacitor C1 is connected to the first level signal output terminal 123, receives the first level signal GVDD, and its output terminal is connected to the first node Q1; the control terminal of the second driving transistor TFT2 receives the second control signal VBS, its input terminal is connected to the output terminal of the eighth driving transistor TFT8, and its output terminal is connected to the second node Q2; the control terminal of the third driving transistor TFT3 is connected to the second node Q2, and its input terminal receives the clock signal CLK. RS The output terminal outputs the adjusted gate drive compensation signal Gate' n One end of the second storage capacitor C2 is connected to the second node Q2, and the other end is connected to the output terminal of the third driving transistor TFT3; the control terminal and input terminal of the sixth driving transistor TFT6 are connected between the first node Q1 and the output terminal of the seventh driving transistor TFT7, and the output terminal is connected between the first storage capacitor C1 and the first level signal output terminal 123; the control terminal of the seventh driving transistor TFT7 receives the third control signal VST, the input terminal is connected to the second level signal output terminal 126, and the output terminal is connected to the input terminal of the sixth driving transistor; the input terminal of the eighth driving transistor TFT8 is connected between the first storage capacitor C1 and the first level signal output terminal 123, the output terminal is connected to the input terminal of the second driving transistor TFT2, and the control terminal is connected to the first node Q1.

[0058] The gate drive signal compensation circuit 120 further includes a first pull-down module 131 and a second pull-down module 132. One end of the first pull-down module 131 is connected to the gate drive signal generation module 128, and the other end is connected to the third level signal output terminal 133 to receive the third level signal VSS0. One end of the second pull-down module 132 is connected to the control module 127, and the other end is connected to the second level signal output terminal 126 to receive the second level signal VSS1. The voltage value corresponding to the second level signal VSS1 is different from the voltage value corresponding to the third level signal VSS0. The first pull-down module 131 includes a fourth driving transistor TFT4, and the second pull-down module 132 includes a fifth driving transistor TFT5. The output terminal of the fourth driving transistor TFT4 is connected to the output terminal of the gate driving signal generation module 128, and its input terminal is connected to the second level signal output terminal 126 to receive the second level signal VSS1. The control terminal receives the third control signal VST. The output terminal of the fifth driving transistor TFT5 is connected between the control module 127 and the gate driving signal generation module 128, and its input terminal is connected to the third level signal output terminal 133 to receive the third level signal VSS0. The control terminal receives the third control signal VST.

[0059] This embodiment focuses on adding a drive enhancement module 124, a charge enhancement module 125, and a release module 129 to the conventional gate drive signal compensation circuit 120. The function of the charge enhancement module 125 is to ensure that when RS turns on the first drive transistor TFT1, the Gate... n When VBS is high, TFT2 is turned on, and the state of the first storage capacitor C1 is transferred to the second storage capacitor C2, enhancing the charging capability of the second storage capacitor C2; after the V-blanking area has been turned on for a long time, the release unit needs to reset C1 and C2 to ensure that the starting point of each turn is consistent and the stability of the entire system (ensuring that the Gate' is not working). n Stablize).

[0060] During the normal display phase, all driving transistors (TFTs) are turned off, and there is no gate signal for any particular line of scanning. n When latched, no gate drive signal is stored, adjusted, or compensated; after entering the non-display stage, also known as the storage stage, RS is high, the first driving transistor TFT1 is turned on, and the Gate... n The state is stored there, when Gate... n When the voltage is high, the Q1 potential is pulled high, the sixth driving transistor TFT6 is turned on, and GVDD synchronously charges Q1 to ensure the storage gate.n High signals are more complete, such as Figure 11 When the V-blanking period arrives, VBS is high, such as... Figure 12 When RS is low, the first driving transistor TFT1 is off, and the second driving transistor TFT2, the sixth driving transistor TFT6, and the eighth driving transistor TFT8 are on; GVDD maintains Q1 at a high potential while charging Q2, and the third driving transistor TFT3 is turned on, and the clock signal CLK... RS Charge C2, Gate' n =CLK RS ; in CLK RS When it is high, Gate' n This row is now open for detection tasks; after the release unit has completed opening a row in the V-blanking region for an extended period, it needs to reset C1 and C2, such as... Figure 12 As shown, when VST is high, TFTs 4 / 5 / 7 are on, and RS and VBS are both low. The potentials of Q1 and Q2 are released to VSS1, and TFTs 1 / 2 / 3 / 6 / 8 are off. When Q1 is charging, GVDD is added to charge; when it is maintaining, GVDD is also added to maintain; when it is releasing, VSS1 is added, thus achieving the purpose of voltage regulation.

[0061] refer to Figure 14 As shown, in the sixth embodiment of this application, a driving method is disclosed for driving the display panel using the driving circuit 100 as described in any of the above embodiments. The driving method includes:

[0062] S1: Obtain the gate drive signal at the input terminal of the gate drive circuit corresponding to the current row scan line;

[0063] S2: Control the gate drive signal to be input to the first node, and increase the charging capability of the first memory module through the charging enhancement module;

[0064] S3: Control the drive enhancement module and the control module to open, and transmit the voltage signal of the first storage module to the gate drive signal generation module; and

[0065] S4: The gate drive signal generation module generates a gate drive compensation signal based on the voltage signal and clock signal transmitted from the first storage module, stores it, and outputs it to the scan line of the display panel.

[0066] In this embodiment, by capturing the original gate drive signal in real time as a compensation reference, the charging enhancement module actively injects a large current to improve the charging rate of the first storage module (capacitor), the drive enhancement module provides gain, the control module acts as a "valve" to open the transmission path only after the signal stabilizes, and the generation module fuses the storage voltage (representing the historical state) and the clock signal (representing the real-time timing) to dynamically generate compensation values ​​to ensure the stability of the gate drive signal when it is working.

[0067] As a seventh embodiment of this application, a driving method is disclosed, which is a further refinement and improvement of the fifth embodiment described above. (Refer to...) Figures 6 to 14 As shown, the gate drive signal compensation circuit 120 further includes a release module 129, which is disposed between the first node and the second level signal output terminal 126. The drive circuit 100 further includes a frame calculation module 130, which calculates the number of frames output to the display panel. The frame calculation module 130 is connected to the gate drive signal compensation circuit 120. The frame includes idle time and display time. The driving method also includes the following steps:

[0068] During the idle time of each frame, the frame calculation module controls the gate drive signal compensation circuit 120 to compensate the gate drive signal of any row in any display area of ​​the current frame, and controls the opening of the corresponding pixel row. After a preset time, the release module 129 is controlled to open to reset the first storage module 122.

[0069] The frame calculation module 130 counts frames in real time, accurately locates the compensation interval, and triggers the gate drive signal compensation circuit 120 to perform preventive calibration on a single line / single display area instead of full-screen scanning, which greatly reduces power consumption. Through frame-level rotation compensation, each display area experiences a similar "stress-recovery" cycle, avoiding overwork in a single area. The release module 129 is set up to form a low-impedance discharge path between the first node Q1 and the second level signal terminal (VSS1, low voltage), forcibly discharging the residual charge at Q1 to VSS1, so that the voltage quickly returns to a low level, eliminating the influence of historical state, and ensuring that the next cycle of charging starts from a clean starting point.

[0070] refer to Figure 15 As shown, as the eighth embodiment of this application, a display device 300 is disclosed. The display device 300 includes a display panel 200 and a driving circuit 100 as described in any of the above embodiments. The driving circuit 100 drives the display panel 200 using the driving method described in any of the above embodiments.

[0071] It should be noted that the limitations on the steps involved in this solution, without affecting the implementation of the specific solution, are not considered as limiting the order of the steps. That is, the steps listed first can be performed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the protection scope of this application. The inventive concept of this application can form many embodiments, but due to space limitations in the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. The combination of embodiments or technical features will enhance the original technical effect.

[0072] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A drive circuit characterized by comprising: The driving circuit comprises a gate driving circuit and a gate driving signal compensation circuit, and the gate driving signal compensation circuit comprises: a gate driving signal control module connected with the gate driving circuit, receiving a gate driving signal corresponding to any one row of scanning lines output by the gate driving circuit and outputting to a first node; a first storage module having one end connected with the first node and the other end connected with a first level signal output end, receiving a first level signal; a driving enhancement module connected with the first node, controlling the voltage stored in the first storage module based on the voltage of the first node; a charging enhancement module having one end connected with the first storage module and the other end connected with the first node and a second level signal output end respectively, receiving a second level signal and increasing the charging capacity of the first storage module; and a control module having one end connected with the driving enhancement module and the other end connected with a gate driving signal generation module; wherein the gate driving signal generation module generates a gate driving compensation signal based on the voltage signal transmitted by the first storage module and a clock signal, and stores the gate driving compensation signal for output to the scanning lines of the display panel.

2. The drive circuit of claim 1, wherein The gate driving signal compensation circuit further comprises a release module arranged between the first node and the second level signal output end, for releasing the voltage at the first node, the voltage corresponding to the first level signal being a first-order high voltage at the first node, and the voltage corresponding to the second level signal being a low voltage.

3. The drive circuit of claim 2, wherein, The gate driving signal control module comprises a first driving transistor, the first storage module comprises a first storage capacitor, the control module comprises a second driving transistor, the gate driving signal generation module comprises a third driving transistor and a second storage capacitor, the charging enhancement module comprises a sixth driving transistor, the release module comprises a seventh driving transistor, and the driving enhancement module comprises an eighth driving transistor; The input end of the first driving transistor is connected with the gate driving circuit, receiving the gate driving signal output by the gate driving circuit, the output end is connected with the first node, and the control end receives a first control signal; The input end of the first storage capacitor is connected with the first level signal output end, receiving the first level signal, and the output end is connected with the first node; The control end of the second driving transistor receives a second control signal, the input end is connected with the output end of the eighth driving transistor, the output end is connected with a second node, the control end of the third driving transistor is connected with the second node, the input end receives a clock signal, and the output end outputs an adjusted gate driving signal; One end of the second storage capacitor is connected with the second node, and the other end is connected with the output end of the third driving transistor; The control end and the input end of the sixth driving transistor are connected between the first node and the output end of the seventh driving transistor, and the output end is connected between the first storage capacitor and the first level signal output end; the control end of the seventh driving transistor receives a third control signal, the input end is connected with the second level signal output end, and the output end is connected with the input end of the sixth driving transistor; An input end of the eighth driving transistor is connected between the first storage capacitor and the first level signal output end, an output end is connected to an input end of the second driving transistor, and a control end is connected to the first node.

4. The drive circuit according to any one of claims 1 to 3, wherein The gate drive signal compensation circuit further comprises a first pull-down module and a second pull-down module, one end of the first pull-down module is connected to the gate drive signal generation module, the other end is connected to a third level signal output end, and the third level signal is received; One end of the second pull-down module is connected to the control module, and the other end is connected to the second level signal output end to receive the second level signal. The voltage value corresponding to the second level signal is different from the voltage value corresponding to the third level signal.

5. The drive circuit of claim 4, wherein, The first pull-down module comprises a fourth driving transistor, the second pull-down module comprises a fifth driving transistor, the output end of the fourth driving transistor is connected to the output end of the gate drive signal generation module, the input end is connected to the second level signal output end, the second level signal is received, and the control end receives a third control signal. The output end of the fifth driving transistor is connected between the control module and the gate drive signal generation module, the input end of the fifth driving transistor is connected to the third level signal output end, the third level signal is received, and the control end receives the third control signal.

6. The drive circuit of claim 1, wherein, The driving circuit further comprises a frame calculation module, the frame calculation module calculates the number of frame pictures output to the display panel, and the frame calculation module is connected with the gate drive signal compensation circuit; the frame picture comprises an idle time and a display time, in the display time, the display panel receives the corresponding gate drive signal and data signal for display, and in the idle time, the display panel does not display; In the idle time of each frame, the frame calculation module controls the gate drive signal compensation circuit to compensate the gate drive signal of any row of the current frame, and controls the current compensated row to be turned on, and in different frames, the frame calculation module controls the gate drive signal compensation circuit to compensate the gate drive signal of different rows, and controls the current compensated row to be turned on in different frames.

7. The drive circuit of claim 6, wherein, The display panel is divided into a plurality of display areas based on scan lines, each display area comprises at least one scan line, in the idle time of each frame, the frame calculation module controls the gate drive signal compensation circuit to compensate the gate drive signal of any row in any display area of the current frame, and in different frames, the frame calculation module controls the gate drive signal compensation circuit to compensate the gate drive signal of different rows in different display areas. In adjacent two frames, the two rows of scan lines compensated by the gate drive signal compensation circuit correspond to two non-adjacent display areas.

8. A driving method for the driving circuit according to any one of claims 1 to 7, characterized by, The driving method comprises: obtaining the gate drive signal of the input end of the gate drive circuit corresponding to the current row of scan lines; controlling the gate drive signal to input to the first node, and increasing the charging capacity of the first storage module through the charging enhancement module; controlling the driving enhancement module and the control module to open, and transmitting the voltage signal of the first storage module to the gate driving signal generation module; and The gate driving signal generation module generates a gate driving compensation signal based on the voltage signal transmitted by the first storage module and a clock signal, and stores the gate driving compensation signal for output to the scan lines of the display panel.

9. The driving method of claim 8, wherein, The gate driving signal compensation circuit further comprises a release module arranged between the first node and the second level signal output end, and the driving circuit further comprises a frame calculation module configured to calculate the number of frame pictures output to the display panel, and the frame calculation module is connected to the gate driving signal compensation circuit; the frame picture comprises an idle time and a display time, and the driving method further comprises the following steps: In the idle time of each frame, the frame calculation module controls the gate driving signal compensation circuit to compensate the gate driving signal of any one row in any one display area of the current frame, and controls the corresponding pixel row to be opened, and controls the release module to be opened after a preset time to reset the first storage module.

10. A display device, characterized by comprising: The display device comprises a display panel and the driving circuit according to any one of claims 1-7, and the driving circuit is driven by the driving method according to any one of claims 8-9.

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