Semiconductor device, memory device and method for automatically generating wafer identifier for semiconductor dies in

Abstract

A semiconductor device, a memory device, and a method of automatically generating a wafer identifier for a semiconductor die in a stacked structure using a logic gate are provided. The method comprises the following steps: obtaining a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die respectively comprise a first identifier generating circuit and a second identifier generating circuit; stacking a second semiconductor die on the first semiconductor die to form a stacked structure, wherein the first identifier generating circuit is electrically connected to the second identifier generating circuit; and generating a first wafer identifier and a second wafer identifier for the first semiconductor die and the second semiconductor die by means of a first identifier generation circuit and a second identifier generation circuit, respectively. The second wafer identifier is generated using the first wafer identifier and the auxiliary input signal.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 777,811 (priority date July 19, 2024), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to electronic circuits. In particular, it relates to a semiconductor device, a memory device, and a method for automatically generating wafer identifiers for semiconductor dies in a stacked structure. Background Technology

[0004] With the advancement of technology, memory devices can now achieve greater storage capacity using three-dimensional memory stacking. Furthermore, it is crucial that each memory chip in the stack has a unique identifier. However, if chip identifiers are set before stacking during memory stack manufacturing, conflicts may occur, causing problems because different memory chips may have the same identifier. Therefore, a method is needed to automatically generate chip identifiers for semiconductor dies in a stacked structure, and semiconductor devices and memory devices using this method are required to solve the aforementioned problems.

[0005] The prior art description above is merely to provide background information and does not acknowledge that the prior art description above discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the prior art above should be considered part of the prior art in this case. Summary of the Invention

[0006] One aspect of this disclosure provides a semiconductor device comprising a plurality of semiconductor dies arranged in a stacked structure. Each semiconductor die includes an identifier generation circuit electrically connected to identifier generation circuits of other semiconductor dies. In response to a first semiconductor die not being a bottom semiconductor die in the stacked structure, a first identifier generation circuit of the first semiconductor die is configured to automatically generate a first wafer identifier based on an auxiliary input signal and a second wafer identifier generated by a second identifier generation circuit of a second semiconductor die adjacent to and below the first semiconductor die.

[0007] Another aspect of the present disclosure provides a method for automatically generating a die identifier for a stacked structure. The method includes the steps of obtaining a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die respectively include a first identifier generation circuit and a second identifier generation circuit; stacking the second semiconductor die on the first semiconductor die to form a stacked structure, wherein the first identifier generation circuit is electrically connected to the second identifier generation circuit; and generating a first die identifier and a second die identifier for the first semiconductor die and the second semiconductor die, respectively, by the first identifier generation circuit and the second identifier generation circuit, wherein the second die identifier is generated using the first die identifier and an auxiliary input signal.

[0008] Yet another aspect of the present disclosure provides a memory device including a stacked structure having a first memory die and a second memory die. The first memory die is stacked on the second memory die. The first memory die and the second memory die respectively include a first identifier generation circuit and a second identifier generation circuit. The second identifier generation circuit is configured to automatically generate a second die identifier for the second memory die using a preset value and a first auxiliary input signal, and the first identifier generation circuit is configured to automatically generate a first die identifier using the second die identifier and a second auxiliary input signal.

[0009] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter. It should be appreciated that the conception of the present disclosure can be readily utilized as the basis for the designing or modifying a still further structure or process as the same can occur to those skilled in the art, and such equi valent constructions are intended to fall within the scope of the present disclosure. It should also be understood that the intended scope of the present disclosure is not to be limited to the particular implementations described herein but is intended to include any implementation falling within the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0010] The disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which like reference numerals refer to like elements throughout the figures.

[0011] According to some embodiments of the present disclosure, Figure 1 is a block diagram of an electronic device 100.

[0012] According to some embodiments of the present disclosure, Figure 2 is a diagram of a stacked structure.

[0013] According to some embodiments of the present disclosure, Figure 3 is a schematic diagram of an identifier generation circuit.

[0014] Figures 4A to 4F FIG. 1 is a diagram showing the operation of a stack structure of a display identifier generation circuit according to an embodiment of the present disclosure. Figure 3 FIG. 2 is a diagram showing different logic gates used by a semiconductor die identifier generation circuit.

[0015] According to some embodiments of the present disclosure, Figure 5 FIG. 3 is a diagram showing the operation of a stack structure of a display identifier generation circuit according to an embodiment of the present disclosure.

[0016] According to some embodiments of the present disclosure, Figure 6 FIG. 4 is a diagram showing the operation of a stack structure of a display identifier generation circuit according to an embodiment of the present disclosure.

[0017] According to some embodiments of the present disclosure, Figure 7 FIG. 5 is a diagram showing the operation of a stack structure of a display identifier generation circuit according to an embodiment of the present disclosure.

[0018] According to some embodiments of the present disclosure, Figure 8 FIG. 6 is a diagram showing the operation of a stack structure of a display identifier generation circuit according to an embodiment of the present disclosure.

[0019] According to some embodiments of the present disclosure, Figure 9 FIG. 7 is a diagram showing the operation of a stack structure of a display identifier generation circuit according to an embodiment of the present disclosure.

[0020] According to some embodiments of the present disclosure, Figure 10 FIG. 8 is a diagram showing the operation of a stack structure of a display identifier generation circuit according to an embodiment of the present disclosure.

[0021] According to some embodiments of the present disclosure, Figure 11 FIG. 9 is a flowchart of a method for automatically generating a wafer identifier for a semiconductor die in a stack structure according to an embodiment of the present disclosure.

[0022] In the drawings, the same reference numerals are used to denote the same elements throughout the several views.

[0023] 11: instruction control signal and address signal

[0024] 12: data signal

[0025] 13N: memory die

[0026] 15: bus

[0027] 100: electronic device

[0028] 110: memory controller

[0029] 120: memory device

[0030] 121: interface circuit

[0031] 122: control circuit

[0032] 130: stack structure

[0033] 131: memory die

[0034] 132: memory die

[0035] 133: memory die

[0036] 200: stacked structure

[0037] 202: package substrate

[0038] 203: solder ball

[0039] 204: bump

[0040] 204A: bump

[0041] 204B: bump

[0042] 210: semiconductor die

[0043] 211: logic circuit

[0044] 212: decoder circuit

[0045] 213: memory cell array

[0046] 214: identifier generation circuit

[0047] 215: through silicon via

[0048] 218: solder ball

[0049] 220: semiconductor die

[0050] 221: logic circuit

[0051] 222: decoder circuit

[0052] 223: memory cell array

[0053] 224: identifier generation circuit

[0054] 225: through silicon via

[0055] 228: solder ball

[0056] 230: semiconductor die

[0057] 231: logic circuit

[0058] 232: decoder circuit

[0059] 233: memory cell array

[0060] 234: identifier generation circuit

[0061] 235: through silicon via

[0062] 238: solder ball

[0063] 240: semiconductor die

[0064] 241: logic circuit

[0065] 242: decoder circuit

[0066] 243: memory cell array

[0067] 244: identifier generation circuit

[0068] 300: identifier generation circuit

[0069] 311: logic gate

[0070] 312: logic gate

[0071] 313: logic gate

[0072] 314: logic gate

[0073] 410A: logic gate

[0074] 410B: logic gate

[0075] 410C: logic gate

[0076] 410D: logic gate

[0077] 410E: logic gate

[0078] 410F: logic gate

[0079] 500: stacked structure

[0080] 510: identifier generation circuit

[0081] 520: identifier generation circuit

[0082] 530: identifier generation circuit

[0083] 540: identifier generation circuit

[0084] 600: stacked structure

[0085] 610: identifier generation circuit

[0086] 620: identifier generation circuit

[0087] 630: identifier generation circuit

[0088] 640: identifier generation circuit

[0089] 700: stacked structure

[0090] 710: identifier generation circuit

[0091] 720: identifier generation circuit

[0092] 730: identifier generation circuit

[0093] 740: identifier generation circuit

[0094] 800: stacked structure

[0095] 810: identifier generation circuit

[0096] 820: identifier generation circuit

[0097] 830: identifier generation circuit

[0098] 840: identifier generation circuit

[0099] 900: stacked structure

[0100] 910: identifier generation circuit

[0101] 920: identifier generation circuit

[0102] 930: identifier generation circuit

[0103] 940: identifier generation circuit

[0104] 1000: stacked structure

[0105] 1010: identifier generation circuit

[0106] 1011: logic gate

[0107] 1012: logic gate

[0108] 1013: logic gate

[0109] 1014: logic gate

[0110] 1015: silicon through via

[0111] 1020: identifier generation circuit

[0112] 1021: logic gate

[0113] 1022: logic gate

[0114] 1023: logic gate

[0115] 1024: logic gate

[0116] 1025: silicon through via

[0117] 1030: identifier generation circuit

[0118] 1031: logic gate

[0119] 1032: logic gate

[0120] 1033: logic gate

[0121] 1034: logic gate

[0122] 1035: silicon through via

[0123] 1040: identifier generation circuit

[0124] 1041: logic gate

[0125] 1042: logic gate

[0126] 1043: logic gate

[0127] 1044: logic gate

[0128] 5101: logic gate

[0129] 5102: logic gate

[0130] 5103: logic gate

[0131] 5104: logic gate

[0132] 5105: silicon through via

[0133] 5201: logic gate

[0134] 5202: logic gate

[0135] 5203: logic gate

[0136] 5204: logic gate

[0137] 5205: silicon through via

[0138] 5301: logic gate

[0139] 5302: logic gate

[0140] 5303: logic gate

[0141] 5304: logic gate

[0142] 5305: silicon through via

[0143] 5401: logic gate

[0144] 5402: logic gate

[0145] 5403: logic gate

[0146] 5404: logic gate

[0147] 6101: logic gate

[0148] 6102: logic gate

[0149] 6103: logic gate

[0150] 6104: logic gate

[0151] 6105: silicon through via

[0152] 6201: logic gate

[0153] 6202: logic gate

[0154] 6203: logic gate

[0155] 6204: logic gate

[0156] 6205: silicon through via

[0157] 6301: logic gate

[0158] 6302: logic gate

[0159] 6303: logic gate

[0160] 6304: logic gate

[0161] 6305: silicon through via

[0162] 6401: logic gate

[0163] 6402: logic gate

[0164] 6403: logic gate

[0165] 6404: logic gate

[0166] 7101: logic gate

[0167] 7102: logic gate

[0168] 7103: logic gate

[0169] 7104: logic gate

[0170] 7105: silicon through via

[0171] 7201: logic gate

[0172] 7202: logic gate

[0173] 7203: logic gate

[0174] 7204: logic gate

[0175] 7205: silicon through via

[0176] 7301: logic gate

[0177] 7302: logic gate

[0178] 7303: logic gate

[0179] 7304: logic gate

[0180] 7305: silicon through via

[0181] 7401: logic gate

[0182] 7402: logic gate

[0183] 7403: logic gate

[0184] 7404: logic gate

[0185] 8101: logic gate

[0186] 8102: logic gate

[0187] 8103: logic gate

[0188] 8104: logic gate

[0189] 8105: silicon through via

[0190] 8201: logic gate

[0191] 8202: logic gate

[0192] 8203: logic gate

[0193] 8204: logic gate

[0194] 8205: silicon through via

[0195] 8301: logic gate

[0196] 8302: logic gate

[0197] 8303: logic gate

[0198] 8304: logic gate

[0199] 8305: silicon through via

[0200] 8401: logic gate

[0201] 8402: logic gate

[0202] 8403: logic gate

[0203] 8404: logic gate

[0204] 9101: logic gate

[0205] 9102: logic gate

[0206] 9103: logic gate

[0207] 9104: Logic gate

[0208] 9105: Silicon through via

[0209] 9201: Logic gate

[0210] 9202: Logic gate

[0211] 9203: Logic gate

[0212] 9204: Logic gate

[0213] 9205: Silicon through via

[0214] 9301: Logic gate

[0215] 9302: Logic gate

[0216] 9303: Logic gate

[0217] 9304: Logic gate

[0218] 9305: Silicon through via

[0219] 9401: Logic gate

[0220] 9402: Logic gate

[0221] 9403: Logic gate

[0222] 9404: Logic gate

[0223] A: Input signal

[0224] B: Input signal

[0225] C: Output signal

[0226] ChipID1: Chip identifier

[0227] ChipID2: Chip identifier

[0228] ChipID3: Chip identifier

[0229] ChipID4: Chip identifier

[0230] DQS_c: Data strobe signal

[0231] DQS_t: Data strobe signal

[0232] GND: Ground voltage

[0233] IN[0]: Input signal

[0234] IN[1]: Input signal

[0235] IN[2]: Input signal

[0236] IN[3]: input signal

[0237] OUT[0]: output signal

[0238] OUT[1]: output signal

[0239] OUT[2]: output signal

[0240] OUT[3]: output signal

[0241] P1: micro bump / input port

[0242] P2: micro bump / input port

[0243] P3: micro bump / input port

[0244] P4: micro bump / input port

[0245] P5: micro bump / output port

[0246] P6: micro bump / output port

[0247] P7: micro bump / output port

[0248] P8: micro bump / output port

[0249] PX: micro bump

[0250] PY: micro bump

[0251] R1: resistor

[0252] VDD: supply voltage

[0253] X: auxiliary input signal DETAILED DESCRIPTION

[0254] Embodiments or examples of the present disclosure illustrated in the drawings are now described using specific language. This is done for the purpose of clarity and no limitation of the scope of the present disclosure is intended by such language. Alternatives or modifications to any of the embodiments described in this document, as well as any further principles or applications of the concepts described in this document, should be considered as falling within the scope of the disclosure. Reference signs can be repeated in the embodiments, even though they share the same reference sign, but this does not necessarily mean that one or more features of an embodiment are applicable to another embodiment.

[0255] It is to be understood that the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and sections but do not connote any hierarchy, order or priority among the elements, components, regions, layers or sections so described. On the contrary, these terms are used merely as labels to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

[0256] As used herein in this specification, the term "one example" or "one embodiment" refers to a specific feature, structure, or characteristic described in connection with one example. A discussion of one example or embodiment does not mean that the feature, structure, or characteristic is required in all examples or embodiments. Further, the appearance of the phrases "in one example" or "in one embodiment" in various places in the specification are not necessarily all referring to the same example or embodiment.

[0257] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the inventive concept. As used herein in this specification, the singular forms "a", "an" and "the" include plural referents unless the content clearly dictates otherwise. It should be further understood that the term "comprising" as used in this specification, specifically when used in a claim, does not exclude other elements or steps than those listed in the claim.

[0258] In addition, spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Likewise, descriptions of movement along or within a plane can be used, such as upwards, downward, upwardly, downwardly, upward, downward, etc. Such relative terms can be interpreted to encompass different orientations of devices in use or operation in addition to the orientations depicted in the figures.

[0259] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0260] It will be understood that when an element or layer is referred to as being "formed on" another element or layer, it can be directly or indirectly formed on the other element or layer. That is, for example, intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly formed on" another element, there are no intervening elements or layers present. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0261] According to some embodiments of the present disclosure, Figure 1 FIG. 1 is a block diagram of an electronic device 100 according to some embodiments of the present disclosure.

[0262] In some embodiments, as shown in FIG. 1, the electronic device 100 can include a memory controller 110 and a memory device 120. The memory controller 110 can be implemented by a central processing unit (CPU), a microprocessor, a digital signal processor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a radio frequency integrated circuit (RFIC). Figure 1 In some embodiments, the memory device 120 can be a dynamic random access memory (DRAM). In other embodiments, other types of memory can be used. For the purpose of the description, the present disclosure can focus on a double data rate synchronous dynamic random access memory (DDR SDRAM), such as DDR5, but the scope of the embodiments is not limited to any particular memory technology or standard.

[0263] In some embodiments, as shown in FIG. 1, the memory device 120 can include an interface circuit 121, a control circuit 122, and a stack structure 130. The interface circuit 121 is configured to transmit and receive data signals 12 over the bus 15, and to receive command control signals and address signals 11, as well as data strobe signals DQS c and DQS t from the memory controller 110 over the bus 15. In other words, the interface circuit 121 can include TXm circuitry (not explicitly shown) for the data signals 12, and RX circuitry (not explicitly shown) for the command control signals and address signals 11, the data signals 12, and the data strobe signals DQS c and DQS t.

[0264] Figure 1 In some embodiments, as shown in FIG. 1, the memory device 120 can include an interface circuit 121, a control circuit 122, and a stack structure 130. The interface circuit 121 is configured to transmit and receive data signals 12 over the bus 15, and to receive command control signals and address signals 11, as well as data strobe signals DQS c and DQS t from the memory controller 110 over the bus 15. In other words, the interface circuit 121 can include TXm circuitry (not explicitly shown) for the data signals 12, and RX circuitry (not explicitly shown) for the command control signals and address signals 11, the data signals 12, and the data strobe signals DQS c and DQS t.​

[0265] The stack structure 130 can be a three-dimensional (3D) stacked memory architecture including a plurality of memory dies 131-13N. The memory dies 131-13N can be vertically stacked using through-silicon vias (TSVs) and microbumps (μβumps), details of which will be described later.

[0266] In some embodiments, the data strobe signal DQS_c can be a complementary signal of the data strobe signal DQS_t. For example, when the data strobe signal DQS_t is in a high logic state (e.g., 1), the data strobe signal DQS_c is in a low logic state (e.g., 0). When the data strobe signal DQS_t is in a low logic state (e.g., 0), the data strobe signal DQS_c is in a high logic state (e.g., 1).

[0267] In some embodiments, the control circuit 122 can perform a read operation or a write operation according to the instruction control signal 11 and the data strobe signals DQS_c and DQS_t. For example, during a write operation, the memory device 120 can receive a write instruction (e.g., including the instruction control signal 11 and the data signal 12) from the memory controller 110 through the bus 15, and then the control circuit 122 can store the received data in the stack structure 130. During a read operation, the memory device 120 can receive a read instruction signal (e.g., the instruction control signal 11) from the memory controller 110 through the bus 15, and then the control circuit 122 can access data from the individual memory cells of the stack structure 130 and transmit those data bits (e.g., the data signal 12) to the memory controller 110 through the bus 15.

[0268] According to some embodiments of the present disclosure, Figure 2 A diagram of a stack structure is shown. See Figure 1 and Figure 2 .

[0269] In some embodiments, Figure 1 The stack structure 130 shown can be implemented using Figure 2 The stack structure 200 shown can be implemented. To describe, Figure 2 Four semiconductor dies 210, 220, 230, and 240 are shown in FIG. 1. In some embodiments, the semiconductor dies 210, 220, 230, and 240 correspond to the memory dies 131-13N, respectively. Figure 1The memory chips 131, 132, 133, and 134 are described. Semiconductor chip 210 may include logic circuitry 211, memory cell array 213, and identifier generation circuitry 214. Similarly, semiconductor chip 220 may include logic circuitry 221, memory cell array 223, and identifier generation circuitry 224; semiconductor chip 230 may include logic circuitry 231, memory cell array 233, and identifier generation circuitry 234; and semiconductor wafer 240 may include logic circuitry 241, memory cell array 243, and identifier generation circuitry 244.

[0270] In some embodiments, the semiconductor die 210 may include microbumps PX and PY formed on opposite sides of the logic circuit 211, and microbumps P1 to P4 and P5 to P8 formed on opposite sides of the identifier generation circuit 214. For example, microbumps PX and P1 to P4 may be formed on the front side of the semiconductor die 210. The semiconductor die 210 may be electrically connected to the package substrate 202 via solder balls 203 on the logic circuit 211 and microbumps PX. In addition, the package substrate 202 may be electrically connected to the memory controller 110 via bumps 204 (e.g., copper bumps). Furthermore, bumps 204A and 204B are electrically connected to the power supply voltage VDD and the ground voltage GND, respectively, via a redistribution layer (not shown) in the package substrate 202. It should be noted that the semiconductor die 210 may include a plurality of through-silicon vias (TSVs) 215, and each TSV corresponds to a microbump PY on the logic circuit 211 and microbumps P5 to P8 on the identifier generation circuit 214.

[0271] Similarly, semiconductor die 220 may include microbumps PX and PY formed on opposite sides of logic circuit 221, and microbumps P1 to P4 and P5 to P8 formed on opposite sides of identifier generation circuit 224. For example, microbumps PX and P1 to P4 may be formed on the front side of semiconductor die 220. Figure 2 As shown, semiconductor die 220 can be electrically connected to semiconductor die 210 via microbumps PX, solder balls 218, and through-silicon vias 215 formed on logic circuit 221, as well as microbumps PY and P5 to P8 on semiconductor die 210. It should be noted that semiconductor die 220 may include a plurality of through-silicon vias (TSVs) 225, and each TSV 225 corresponds to one of the microbumps PY on logic circuit 221 and microbumps P5 to P8 on identifier generation circuit 224.

[0272] Similarly, semiconductor die 230 may include microbumps PX and PY formed on opposite sides of logic circuit 231, and microbumps P1 to P4 and P5 to P8 formed on opposite sides of identifier generation circuit 234. For example, microbumps PX and P1 to P4 may be formed on the front side of semiconductor die 230.Figure 2 As shown, semiconductor die 230 can be electrically connected to semiconductor die 220 via micro bumps PX formed on logic circuit 231, solder balls 228, through silicon via 225, and micro bumps PY and P5-P8 of semiconductor die 220.

[0273] Similarly, semiconductor die 240 can include micro bumps PX and PY formed on opposite sides of logic circuit 241, and micro bumps PI- P4 and P5-P8 formed on opposite sides of identifier generation circuit 244. For example, micro bumps PX and PI- P4 can be formed on a front side of semiconductor die 240. As shown, semiconductor die 240 can be electrically connected to semiconductor die 230 via micro bumps PX formed on logic circuit 241, solder balls 238, through silicon via 235, and micro bumps PY and P5-P8 of semiconductor die 230. Figure 2 As shown, semiconductor die 230 can be electrically connected to semiconductor die 220 via micro bumps PX formed on logic circuit 231, solder balls 228, through silicon via 225, and micro bumps PY and P5-P8 of semiconductor die 220.

[0274] In some embodiments, logic circuits 211, 221, 231, and 241 can be or include memory control logic to control data access of memory cell arrays 213, 223, 233, and 243, respectively. In addition, logic circuits 211, 221, 231, and 241 can include decoder circuits 212, 222, 232, and 242 to coordinate wafer identifiers received from identifier generation circuits 214, 224, 234, and 244 on semiconductor dies 210, 220, 230, and 240, respectively, to allow memory controller 110 to access instruction control signals and address signals 11 and one of memory cell arrays 213, 223, 233, and 243 disposed on semiconductor dies 210, 220, 230, and 240, respectively.

[0275] In some embodiments, memory cell arrays 213, 223, 233, and 243 on semiconductor dies 210, 220, 230, and 240 can form a memory space. Each of memory cell arrays 213, 223, 233, and 243 can be a portion of one or more most significant bits (MSBs) of address signals from memory controller 110 for the memory space. In some embodiments, by setting the two most significant bits to 2’b00, 2’b01, 2’b10, and 2’b11, memory controller 110 can access memory cell arrays 213, 223, 233, and 243 disposed on semiconductor dies 210, 220, 230, and 240, respectively.

[0276] For example, the decoder circuit 212 can receive the wafer identifier generated by the identifier generation circuit 214 of the semiconductor die 210, and then transmit the received wafer identifier to the decoder circuits 222, 232, and 242 disposed on other semiconductor dies, such as the semiconductor dies 220, 230, and 240. Similarly, the decoder circuits 222, 232, and 242 can receive the wafer identifiers generated by the identifier generation circuits 224, 234, and 244 disposed on the semiconductor dies 220, 230, and 240, respectively, and then transmit the received wafer identifiers to the decoder circuits disposed on other semiconductor dies.

[0277] More specifically, the identifier generation circuits 214, 224, 234, and 244 having the same circuit design are electrically connected in series. Each of the identifier generation circuits 214, 224, 234, and 244 can generate a unique wafer identifier (or die identifier) for the semiconductor die on which it is disposed, and each of the identifier generation circuits 214, 224, 234, and 244 can generate the wafer identifier based on the input signals to the respective identifier generation circuits 214, 224, 234, and 244.

[0278] In some embodiments, the semiconductor die 210 is a bottom semiconductor die or a first die in the stacked structure 200, and the identifier generation circuit 214 can generate a first 4-bit unique wafer identifier (or die identifier) representing the bottom die or the first die in the stacked structure 200. It should be noted that the micro bumps PI to P4 disposed on the identifier generation circuit 214 of the semiconductor die 210 can be electrically connected to the bump 204A (e.g., connected to a power supply voltage VDD) or the bump 204B (e.g., connected to a ground voltage GND) via the respective solder balls 203 on the package substrate 202, and the identifier generation circuit 214 can automatically generate the 4-bit wafer identifier by performing the respective logical operations between the two input signals of each logic gate (e.g., AND, NAND, OR, NOR, XOR, and XNOR gates) used in the identifier generation circuit 214.

[0279] In some embodiments, the semiconductor die 220 is a second die in the stacked structure 200, and the identifier generation circuit 224 can generate a second 4-bit unique wafer identifier (or die identifier) representing the second die in the stacked structure 200. For example, the wafer identifier generated by the identifier generation circuit 214 can be used as an input signal to the identifier generation circuit 224, and the identifier generation circuit 224 can perform the respective logical operations between the two input signals of each logic gate inside the identifier generation circuit 224 to obtain the output wafer identifier for the semiconductor die 220.

[0280] In some embodiments, semiconductor die 230 is the third die in stack structure 200, and identifier generation circuit 234 can generate a third 4-bit unique wafer identifier (or die identifier) representing the third die in stack structure 200. For example, the wafer identifier generated by identifier generation circuit 224 can be used as an input signal to identifier generation circuit 234, and identifier generation circuit 234 can perform logical operations corresponding to the two input signals of each of its internal logic gates to obtain the output wafer identifier of semiconductor die 230.

[0281] In some embodiments, semiconductor die 240 is the fourth die or the topmost die in stack structure 200, and identifier generation circuit 244 can generate a fourth 4-bit unique wafer identifier (or die identifier) representing the fourth die in stack structure 200. For example, the wafer identifier generated by identifier generation circuit 234 can be used as an input signal to identifier generation circuit 244, and identifier generation circuit 244 can perform logical operations corresponding to the two input signals of each of its internal logic gates to obtain the output wafer identifier of semiconductor die 240.

[0282] It should be noted that semiconductor dies 210, 220, 230, and 240 can have substantially the same circuit design. Regardless of whether the order of semiconductor dies 210, 220, 230, and 240 in stack structure 200 is changed, identifier generation circuits 214, 224, 234, and 244 are still able to generate correct and unique wafer identifiers for semiconductor dies 210, 220, 230, and 240 according to their positions in stack structure 200.

[0283] According to some embodiments of the present disclosure, Figure 3 A schematic diagram of an identifier generation circuit.

[0284] In some embodiments, Figure 2 Each of identifier generation circuits 214, 224, 234, and 244 shown in FIG. 2 can be implemented using Figure 3 An identifier generation circuit 300 is shown in FIG. 3. Identifier generation circuit 300 can include input ports P1-P4, output ports P5-P8, and a plurality of logic gates 311-314. Each of logic gates 311-314 can be a 2-input logic gate of the same type (e.g., AND, NAND, OR, NOR, XOR, or XNOR). For the sake of description, the left input terminal and the right input terminal of each of logic gates 311-314 can be considered as a first input terminal and a second input terminal.

[0285] In some embodiments, the first input terminal of the logic gate 311 receives an input signal IN[3] from the input port P1 of the identifier generation circuit 300, and the second input terminal receives an input signal IN[2] from the input port P2 of the identifier generation circuit 300. Based on the received input signals IN[3] and IN[2], the logic gate 311 generates an output signal OUT[3] at the output port P5 of the identifier generation circuit 300. The input signals IN[3] and IN[2] can be either a power supply voltage VDD representing a high logic state (e.g., "1") or a ground voltage GND representing a low logic state (e.g., "0").

[0286] Similarly, the first and second input terminals of the logic gate 312 receive input signals IN[2] and IN[1] from the input ports P2 and P3 of the identifier generation circuit 300, respectively. Based on the received input signals IN[2] and IN[1], the logic gate 312 generates an output signal OUT[2] at the output port P6 of the identifier generation circuit 300. The input signals IN[2] and IN[1] can be either a power supply voltage VDD representing a high logic state (e.g., "1") or a ground voltage GND representing a low logic state (e.g., "0").

[0287] In addition, the first and second input terminals of the logic gate 313 receive input signals IN[1] and IN[0] from the input ports P3 and P4 of the identifier generation circuit 300, respectively. Based on the received input signals IN[1] and IN[0], the logic gate 313 generates an output signal OUT[1] at the output port P7 of the identifier generation circuit 300. The input signals IN[1] and IN[0] can be either a power supply voltage VDD representing a high logic state (e.g., "1") or a ground voltage GND representing a low logic state (e.g., "0").

[0288] Further, the first input terminal of the logic gate 314 receives an input signal IN[0] from the input port P4 of the identifier generation circuit 300, and the second input terminal of the logic gate 314 receives a source voltage (e.g., GND or VDD) via the resistor Rl. For example, when the second input terminal of the logic gate 314 is connected to the power supply voltage VDD and the ground voltage GND, the auxiliary input signal X is a high logic state (e.g., "1") and a low logic state (e.g., "0"), respectively. It should be noted that the source voltage (e.g., GND or VDD) can depend on the type of logic gate 311-314 used, the details of which will be described later.

[0289] Figures 4A to 4F For example, the logic gate 311 can be an AND gate, the logic gate 312 can be an OR gate, the logic gate 313 can be an XOR gate, and the logic gate 314 can be an XNOR gate. Figure 3 FIG. 2 is a diagram of different logic gates used in the identifier generation circuit.

[0290] In some embodiments, the first input terminal of the logic gate 311 receives an input signal IN[3] from the input port P1 of the identifier generation circuit 300, and the second input terminal receives an input signal IN[2] from the input port P2 of the identifier generation circuit 300. Based on the received input signals IN[3] and IN[2], the logic gate 311 generates an output signal OUT[3] at the output port P5 of the identifier generation circuit 300. The input signals IN[3] and IN[2] can be either a power supply voltage VDD representing a high logic state (e.g., "1") or a ground voltage GND representing a low logic state (e.g., "0"). Figure 3Each of the logic gates 311-314 can be implemented using Figure 4A For example, the logic gate 410A can be a two-input AND gate that receives input signals A and B. Table 1 shows a truth table for the logic gate 410A.

[0291] A B C 0 0 0 0 1 0 1 0 0 1 1 1

[0292] Table 1

[0293] In other words, the logic gate 410A can perform an AND operation on the input signals A and B to produce an output signal C. For example, when either of the input signals A and B is in a low logic state (e.g., "0"), the output signal C is in a low logic state (e.g., "0"). When both of the input signals A and B are in a high logic state (e.g., "1"), the output signal C is in a high logic state (e.g., "1").

[0294] Figure 4B Table 1 Figure 3 Another set of configurations of the logic gates 311-314 can be implemented using Figure 3 Each of the logic gates 311-314 can be implemented using Figure 4B For example, the logic gate 410B can be a two-input NAND gate that receives input signals A and B. Table 2 shows a truth table for the logic gate 410B.

[0295] A B C 0 0 1 0 1 1 1 0 1 1 1 0

[0296] Table 2

[0297] In other words, the logic gate 410B can perform a NAND operation on the input signals A and B to produce an output signal C. For example, when either of the input signals A and B is in a low logic state (e.g., "0"), the output signal C is in a high logic state (e.g., "1"). When both of the input signals A and B are in a high logic state (e.g., "1"), the output signal C is in a low logic state (e.g., "0").

[0298] Figure 4C Table 2 Figure 3 Yet another set of configurations of the logic gates 311-314 can be implemented using Figure 3 Each of the logic gates 311-314 can be implemented using Figure 4C For example, the logic gate 410C can be a two-input OR gate that receives input signals A and B. Table 3 shows a truth table for the logic gate 410C.

[0299] A B C 0 0 0 0 1 1 1 0 1 1 1 1

[0300] Table 3

[0301] In other words, logic gate 410C can perform an OR operation on input signals A and B to produce output signal C. For example, when either of input signals A and B is in a high logic state (e.g., "1"), output signal C is in a high logic state (e.g., "1"). When both of input signals A and B are in a low logic state (e.g., "0"), output signal C is in a low logic state (e.g., "0").

[0302] Figure 4D Display Figure 3 Another set of states of the logic gate 410C. In some embodiments, Figure 3 Each of the logic gates 311-314 can be implemented using Figure 4D the logic gate 410D shown. For example, logic gate 410D can be a two-input NOR gate that receives input signals A and B. Table 4 shows a truth table for logic gate 410D.

[0303] A B C 0 0 1 0 1 0 1 0 0 1 1 0

[0304] Table 4

[0305] In other words, logic gate 410D can perform a NOR operation on input signals A and B to produce output signal C. For example, when either of input signals A and B is in a high logic state (e.g., "1"), output signal C is in a low logic state (e.g., "0"). When both of input signals A and B are in a low logic state (e.g., "0"), output signal C is in a high logic state (e.g., "1").

[0306] Figure 4E Display Figure 3 Another set of states of the logic gate 410D. In some embodiments, Figure 3 Each of the logic gates 311-314 can be implemented using Figure 4E the logic gate 410E shown. For example, logic gate 410E can be a two-input XOR gate that receives input signals A and B. Table 5 shows a truth table for logic gate 410E.

[0307] A B C 0 0 0 0 1 1 1 0 1 1 1 0

[0308] Table 5

[0309] In other words, logic gate 410E can perform an XOR operation on input signals A and B to produce output signal C. For example, when input signals A and B have different logic states (e.g., A = 1, B = 0, or A = 0, B = 1), output signal C is in a high logic state (e.g., "1"). When input signals A and B both have the same logic state (e.g., A = B = 1, or A = B = 0), output signal C is in a low logic state (e.g., "0").

[0310] Figure 4F display Figure 3 of another set of logic gates. In some embodiments, Figure 3 Each of the logic gates 311-314 can be implemented using Figure 4F the logic gate 410F shown. For example, the logic gate 410F can be a two-input XNOR gate that receives input signals A and B. Table 6 shows a truth table for the logic gate 410F.

[0311] A B C 0 0 1 0 1 0 1 0 0 1 1 1

[0312] Table 6

[0313] In other words, the logic gate 410F can perform an XNOR operation on the input signals A and B to generate the output signal C. For example, when the input signals A and B have different logic states (e.g., A = 1, B = 0, or A = 0, B = 1), the output signal C is a low logic state (e.g., "0"). When the input signals A and B both have the same logic state (e.g., A = B = 1, or A = B = 0), the output signal C is a high logic state (e.g., "1").

[0314] It should be noted that, Figures 4A to 4F The logic gates 410A-410F shown in FIG. 4A-4F are for the purpose of description, except that Figures 4A to 4F The logic gates 410A-410F shown in FIG. 4A-4F are for the purpose of description, except that Figure 3 The logic gates 311-314 shown in FIG. 3 can be implemented using any other two-input logic gates (e.g., A and NOT B, B and NOT A, A or NOT B, B or NOT A), except that

[0315] According to some embodiments of the present disclosure, Figure 5 FIG. 6 is a diagram showing the operation of a stack structure of identifier generation circuits.

[0316] In some embodiments, Figure 5 The identifier generation circuits 510, 520, 530, and 540 in the stack structure 500 shown can correspond to the identifier generation circuits 214, 224, 234, and 244, respectively, shown in FIG. 2A-2D. Figure 2 In other words, the identifier generation circuits 510, 520, 530, and 540 are disposed on different semiconductor dies (not explicitly shown in FIG. 2A-2D). In addition, Figure 5 FIG. 5 shows a schematic diagram of the identifier generation circuits 510, 520, 530, and 540, and their respective input and output signals. Figure 5

[0317] ​In some embodiments, an identifier generation circuit 510 can be provided on the bottom semiconductor die in the stacked structure 500, and the input ports P1-P4 of the identifier generation circuit 510 are connected to the power supply voltage VDD to input the signal IN[3:0] = 4'b1111 (e.g., 0xF in hexadecimal). In addition, since the second input terminal of the logic gate 5104 is connected to the ground voltage GND via the resistor R1, the auxiliary input signal of the logic gate 5104 will be in a low logic state (e.g., "0"). Each of the logic gates 5101-5104 can perform an AND operation on the respective bit of the input signal IN and its adjacent lower bit. For example, the logic gate 5101 performs an AND operation on the respective bit IN[3] received from the respective input port P1 and the adjacent lower bit IN[2] received from the adjacent input port P2. The operations of the logic gates 5102-5104 can be derived in a similar manner.

[0318] It should be noted that the auxiliary input signal is the adjacent lower bit of the logic gate 5104. Thus, based on the truth table shown in Table 1, the output signals of the logic gates 5101-5104 are "1", "1", "1", and "0", and are transmitted to the output ports P5, P6, P7, and P8 of the identifier generation circuit 510, respectively. Thus, the output signals "1", "1", "1", and "0" generated by the logic gates 5101-5104 at the output ports P5-P8 of the identifier generation circuit 510 will simultaneously serve as the wafer identifier ChipID1 (e.g., 4'b1110 or 0xE in hexadecimal) and the input signals of the input ports P1-P4 of the identifier generation circuit 520.

[0319] Since the identifier generation circuit 520 is provided on the second semiconductor die in the stacked structure 500, the input ports P1-P4 of the identifier generation circuit 520 are connected to the output ports P5-P8 of the identifier generation circuit 510 via the through-silicon via 5105, respectively. Thus, the input signals of the first terminals of the logic gates 5201-5204 of the identifier generation circuit 520 will follow the input signals "1", "1", "1", and "0" received by the input ports P1-P4 of the identifier generation circuit 520, respectively. Thus, the output signals "1", "1", "0", and "0" generated by the logic gates 5201-5204 at the output ports P5-P8 of the identifier generation circuit 520 will simultaneously serve as the wafer identifier ChipID2 (e.g., 4'b1100 or 0xC in hexadecimal) and the input signals of the input ports P1-P4 of the identifier generation circuit 530.

[0320] Similarly, since the identifier generation circuit 530 is disposed on the third semiconductor die in the stacked structure 500, the input ports P1 to P4 of the identifier generation circuit 530 are connected to the output ports P5 to P8 of the identifier generation circuit 520 via the through-silicon vias 5205, respectively. Thus, the input signals to the first terminals of the logic gates 5301 to 5304 of the identifier generation circuit 530 will follow the input signals "1", "1", "0", and "0" received by the input ports P1 to P4 of the identifier generation circuit 530, respectively. Thus, the output signals "1", "0", "0", and "0" generated by the logic gates 5301 to 5304 at the output ports P5 to P8 of the identifier generation circuit 530 will be simultaneously the chip identifier ChipID3 (e.g., 4'b1000 or 0x8 in hexadecimal) and the input signals to the input ports P1 to P4 of the identifier generation circuit 540.

[0321] Similarly, since the identifier generation circuit 540 is disposed on the fourth semiconductor die (or the topmost semiconductor die) in the stacked structure 500, the input ports P1 to P4 of the identifier generation circuit 540 are connected to the output ports P5 to P8 of the identifier generation circuit 530 via the through-silicon vias 5305, respectively. Thus, the input signals to the first terminals of the logic gates 5401 to 5404 of the identifier generation circuit 540 will follow the input signals "1", "0", "0", and "0" received by the input ports P1 to P4 of the identifier generation circuit 540, respectively. Thus, the output signals "0", "0", "0", and "0" generated by the logic gates 5401 to 5404 at the output ports P5 to P8 of the identifier generation circuit 540 will be the chip identifier ChipID4 (e.g., 4'b0000 or 0x0 in hexadecimal).

[0322] It should be noted that the output signals of the identifier generation circuits 510, 520, 530, and 540 can be transmitted to respective decoder circuits, such as Figure 2 the decoder circuits 212, 222, 232, and 242 shown, to allow logic circuits disposed on different semiconductor dies to use the output signals from the identifier generation circuits 510, 520, 530, and 540 to control respective memory cell arrays, such as Figure 2 the memory cell arrays 213, 223, 233, and 243 shown.

[0323] According to some embodiments of the present disclosure, Figure 6 a diagram showing the operation of the stacked structure of identifier generation circuits.

[0324] In some embodiments, Figure 6 The identifier generation circuits 610, 620, 630, and 640 in the stacked structure 600 shown can correspond to the identifier generation circuits 510, 520, 530, and 540, respectively. Figure 2The image shows identifier generation circuits 214, 224, 234, and 244 disposed on semiconductor dies 210, 220, 230, and 240. In other words, identifier generation circuits 610, 620, 630, and 640 are disposed on different semiconductor dies. Figure 6 (Not explicitly shown in the drawing). Additionally... Figure 6 The diagram shows the identifier generation circuits 610, 620, 630 and 640, as well as their respective input and output signals.

[0325] In some embodiments, an identifier generation circuit 610 may be provided on the bottom semiconductor die in the stacked structure 600. Input ports P1 to P3 of the identifier generation circuit 610 are connected to ground voltage GND, while input port P4 of the identifier generation circuit 610 is connected to the power supply voltage VDD, represented by the input signal IN[3:0] = 4'b0001 (e.g., hexadecimal 0x1). In addition, since the second input terminal of logic gate 6104 is connected to the power supply voltage VDD via resistor R1, the auxiliary input signal of logic gate 6104 is in a high logic state (e.g., "1"). Each of logic gates 6101 to 6104 may perform a NAND operation on the corresponding bit of the input signal IN and its adjacent low bit. For example, logic gate 6101 performs a NAND operation on the corresponding bit IN[3] received from the corresponding input port P1 and the adjacent low bit IN[2] received from the adjacent input port P2. The operation of logic gates 6102 to 6104 can be derived in a similar manner.

[0326] It should be noted that the auxiliary input signal is the adjacent low-order bit of logic gate 6104. Therefore, based on the truth table shown in Table 2, the output signals of logic gates 6101 to 6104 are "1", "1", "1", and "0", respectively, and are transmitted to the output ports P5, P6, P7, and P8 of the identifier generation circuit 610. Therefore, the output signals "1", "1", "1", and "0" generated by logic gates 6101 to 6104 at the output ports P5 to P8 of the identifier generation circuit 610 will simultaneously serve as the chip identifier ChipID1 (e.g., 4'b1110 or hexadecimal 0xE) and the input signals of the input ports P1 to P4 of the identifier generation circuit 620.

[0327] Since the identifier generation circuit 620 is disposed on the second semiconductor die in the stacked structure 600, the input ports P1 to P4 of the identifier generation circuit 620 are connected to the output ports P5 to P8 of the identifier generation circuit 610 via the through-silicon vias 6105, respectively. Thus, the input signals to the first terminals of the logic gates 6201 to 6204 of the identifier generation circuit 620 will follow the input signals “1”, “1”, “1”, and “0” received by the input ports P1 to P4 of the identifier generation circuit 620, respectively. Thus, the output signals “0”, “0”, “1”, and “1” generated by the logic gates 6201 to 6204 at the output ports P5 to P8 of the identifier generation circuit 620 will simultaneously serve as the chip identifier ChipID2 (e.g., 4’b0011 or 0x3 in hexadecimal) and the input signals to the input ports P1 to P4 of the identifier generation circuit 630.

[0328] Similarly, since the identifier generation circuit 630 is disposed on the third semiconductor die in the stacked structure 600, the input ports P1 to P4 of the identifier generation circuit 630 are connected to the output ports P5 to P8 of the identifier generation circuit 620 via the through-silicon vias 6205, respectively. Thus, the input signals to the first terminals of the logic gates 6301 to 6304 of the identifier generation circuit 630 will follow the input signals “0”, “0”, “1”, and “1” received by the input ports P1 to P4 of the identifier generation circuit 630, respectively. Thus, the output signals “1”, “1”, “0”, and “0” generated by the logic gates 6301 to 6304 at the output ports P5 to P8 of the identifier generation circuit 630 will simultaneously serve as the chip identifier ChipID3 (e.g., 4’b1100 or 0xC in hexadecimal) and the input signals to the input ports P1 to P4 of the identifier generation circuit 640.

[0329] Similarly, since the identifier generation circuit 640 is disposed on the fourth semiconductor die (or the topmost semiconductor die) in the stacked structure 600, the input ports P1 to P4 of the identifier generation circuit 640 are connected to the output ports P5 to P8 of the identifier generation circuit 630 via the through-silicon vias 6305, respectively. Thus, the input signals to the first terminals of the logic gates 6401 to 6404 of the identifier generation circuit 640 will follow the input signals “1”, “1”, “0”, and “0” received by the input ports P1 to P4 of the identifier generation circuit 640, respectively. Thus, the output signals “0”, “1”, “1”, and “1” generated by the logic gates 6401 to 6404 at the output ports P5 to P8 of the identifier generation circuit 640 will serve as the chip identifier ChipID4 (e.g., 4’b0111 or 0x7 in hexadecimal).

[0330] It should be noted that the output signals of the identifier generation circuits 610, 620, 630, and 640 can be transmitted to the corresponding decoder circuits, for example... Figure 2 The decoder circuits 212, 222, 232, and 242 shown allow logic circuits located on different semiconductor dies to use output signals from identifier generation circuits 610, 620, 630, and 640 to control their respective memory cell arrays (e.g., Figure 2 The memory cell arrays shown are 213, 223, 233, and 243.

[0331] According to some embodiments of this disclosure Figure 7 A diagram illustrating the operation of the stacked structure of the identifier generation circuit.

[0332] In some embodiments, Figure 7 The identifier generation circuits 710, 720, 730, and 740 in the displayed stacked structure 700 can respectively correspond to... Figure 2 The image shows identifier generation circuits 214, 224, 234, and 244 disposed on semiconductor dies 210, 220, 230, and 240. In other words, identifier generation circuits 710, 720, 730, and 740 are disposed on different semiconductor dies. Figure 7 (Not explicitly shown in the drawing). Additionally... Figure 7 The diagram shows the identifier generation circuits 710, 720, 730 and 740, as well as their respective input and output signals.

[0333] In some embodiments, an identifier generation circuit 710 may be provided on the bottom semiconductor die in the stacked structure 700. The input ports P1 to P4 of the identifier generation circuit 710 are connected to the ground voltage GND and are represented by the input signal IN[3:0] = 4'b0000 (e.g., hexadecimal 0x0). In addition, since the second input terminal of the logic gate 7104 is connected to the power supply voltage VDD via resistor R1, the auxiliary input signal of the logic gate 7104 is in a high logic state (e.g., "1"). Each of the logic gates 7101 to 7104 may perform an OR operation on the corresponding bit of the input signal IN and its adjacent low bit. For example, the logic gate 7101 performs an OR operation on the corresponding bit IN[3] received from the corresponding input port P1 and the adjacent low bit IN[2] received from the adjacent input port P2. The operation of the logic gates 7102 to 7104 can be derived in a similar manner.

[0334] It should be noted that the auxiliary input signals are adjacent low bits of the logic gate 7104. Thus, based on the truth table shown in Table 3, the output signals of the logic gates 7101 to 7104 are "0", "0", "0" and "1", and are transmitted to the output ports P5, P6, P7 and P8 of the identifier generation circuit 710, respectively. Thus, the output signals "0", "0", "0" and "1" generated by the logic gates 7101 to 7104 at the output ports P5 to P8 of the identifier generation circuit 710 will simultaneously serve as the wafer identifier ChipID1 (e.g. 4'b0001 or 0x1 in hexadecimal) and the input signals of the input ports P1 to P4 of the identifier generation circuit 720.

[0335] Since the identifier generation circuit 720 is disposed on the second semiconductor die in the stacked structure 700, the input ports P1 to P4 of the identifier generation circuit 720 are connected to the output ports P5 to P8 of the identifier generation circuit 710 via the through-silicon vias 7105, respectively. Thus, the input signals of the first terminals of the logic gates 7201 to 7204 of the identifier generation circuit 720 will follow the input signals "0", "0", "0" and "1" received by the input ports P1 to P4 of the identifier generation circuit 720, respectively. Thus, the output signals "0", "0", "1" and "1" generated by the logic gates 7201 to 7204 at the output ports P5 to P8 of the identifier generation circuit 720 will simultaneously serve as the wafer identifier ChipID2 (e.g. 4'b0011 or 0x3 in hexadecimal) and the input signals of the input ports P1 to P4 of the identifier generation circuit 730.

[0336] Similarly, since the identifier generation circuit 730 is disposed on the third semiconductor die in the stacked structure 700, the input ports P1 to P4 of the identifier generation circuit 730 are connected to the output ports P5 to P8 of the identifier generation circuit 720 via the through-silicon vias 7205, respectively. Thus, the input signals of the first terminals of the logic gates 7301 to 7304 of the identifier generation circuit 730 will follow the input signals "0", "0", "1" and "1" received by the input ports P1 to P4 of the identifier generation circuit 730, respectively. Thus, the output signals "0", "1", "1" and "1" generated by the logic gates 7301 to 7304 at the output ports P5 to P8 of the identifier generation circuit 730 will simultaneously serve as the wafer identifier ChipID3 (e.g. 4'b0111 or 0x7 in hexadecimal) and the input signals of the input ports P1 to P4 of the identifier generation circuit 740.

[0337] Similarly, since the identifier generation circuit 740 is disposed on the fourth semiconductor die (or the topmost semiconductor die) in the stacked structure 700, the input ports P1 to P4 of the identifier generation circuit 740 are connected to the output ports P5 to P8 of the identifier generation circuit 730 via the through-silicon vias 7305, respectively. Thus, the input signals to the first terminals of the logic gates 7401 to 7404 of the identifier generation circuit 740 will follow the input signals "0", "1", "1", and "1" received by the input ports P1 to P4 of the identifier generation circuit 740, respectively. Thus, the output signals "1", "1", "1", and "1" generated at the output ports P5 to P8 of the identifier generation circuit 740 will be ChipID4 (e.g., 4'b1111 or 0xF in hexadecimal) as the wafer identifier.

[0338] It should be noted that the output signals of the identifier generation circuits 710, 720, 730, and 740 can be transmitted to respective decoder circuits, such as Figure 2 the decoder circuits 212, 222, 232, and 242 shown, to allow the logic circuits disposed on the different semiconductor dies to use the output signals from the identifier generation circuits 710, 720, 730, and 740 to control the respective memory cell arrays (such as Figure 2 the memory cell arrays 213, 223, 233, and 243 shown).

[0339] According to some embodiments of the present disclosure, Figure 8 a diagram showing the operation of the stacked structure of the identifier generation circuits.

[0340] In some embodiments, Figure 8 The identifier generation circuits 810, 820, 830, and 840 in the stacked structure 800 shown can correspond to Figure 2 the identifier generation circuits 214, 224, 234, and 244 disposed on the semiconductor dies 210, 220, 230, and 240, respectively, in Figure 8 (not explicitly shown in). In addition, Figure 8 a schematic diagram showing the identifier generation circuits 810, 820, 830, and 840, and their respective input and output signals, in

[0341] In some embodiments, an identifier generation circuit 810 can be disposed on the bottom semiconductor die in the stacked structure 800. The input ports P1-P3 of the identifier generation circuit 810 are connected to the ground voltage GND, while the input port P4 of the identifier generation circuit 810 is connected to the power supply voltage VDD to input the signal IN[3:0] = 4’b0001 (e.g., 0x1 in hexadecimal). In addition, since the second input terminal of the logic gate 8104 is connected to the power supply voltage VDD via the resistor R1, the auxiliary input signal of the logic gate 8104 will be in a high logic state (e.g., “1”). Each of the logic gates 8101-8104 can perform a NOR operation on the respective bit of the input signal IN and its adjacent lower bit. For example, the logic gate 8101 performs a NOR operation on the respective bit IN[3] received from the respective input port P1 and the adjacent lower bit IN[2] received from the adjacent input port P2. The operations of the logic gates 8102-8104 can be derived in a similar manner.

[0342] It is noted that the auxiliary input signal serves as the adjacent lower bit of the logic gate 8104. Thus, based on the truth table shown in Table 4, the output signals of the logic gates 8101-8104 are “1”, “1”, “0”, and “0”, and are transmitted to the output ports P5, P6, P7, and P8 of the identifier generation circuit 810, respectively. Thus, the output signals “1”, “1”, “0”, and “0” generated by the logic gates 8101-8104 at the output ports P5-P8 of the identifier generation circuit 810 will simultaneously serve as the wafer identifier ChipID1 (e.g., 4’b1100 or 0xC in hexadecimal) and the input signals of the input ports P1-P4 of the identifier generation circuit 820.

[0343] Since the identifier generation circuit 820 is disposed on the second semiconductor die in the stacked structure 800, the input ports P1-P4 of the identifier generation circuit 820 are connected to the output ports P5-P8 of the identifier generation circuit 810 via the through-silicon via 8105, respectively. Thus, the input signals of the first terminals of the logic gates 8201-8204 of the identifier generation circuit 820 will follow the input signals “1”, “1”, “0”, and “0” received by the input ports P1-P4 of the identifier generation circuit 820, respectively. Thus, the output signals “0”, “0”, “1”, and “0” generated by the logic gates 8201-8204 at the output ports P5-P8 of the identifier generation circuit 820 will simultaneously serve as the wafer identifier ChipID2 (e.g., 4’b0010 or 0x2 in hexadecimal) and the input signals of the input ports P1-P4 of the identifier generation circuit 830.

[0344] Similarly, since the identifier generation circuit 830 is disposed on the third semiconductor die in the stacked structure 800, the input ports P1 to P4 of the identifier generation circuit 830 are connected to the output ports P5 to P8 of the identifier generation circuit 820 via the through-silicon vias 8205, respectively. Thus, the input signals to the first terminals of the logic gates 8301 to 8304 of the identifier generation circuit 830 will follow the input signals "0", "0", "1", and "0" received by the input ports P1 to P4 of the identifier generation circuit 830, respectively. Thus, the output signals "1", "0", "0", and "0" generated by the logic gates 8301 to 8304 at the output ports P5 to P8 of the identifier generation circuit 830 will simultaneously serve as the chip identifier ChipID3 (e.g., 4'b1000 or 0x8 in hexadecimal) and the input signals to the input ports P1 to P4 of the identifier generation circuit 840.

[0345] Similarly, since the identifier generation circuit 840 is disposed on the fourth semiconductor die (or the topmost semiconductor die) in the stacked structure 800, the input ports P1 to P4 of the identifier generation circuit 840 are connected to the output ports P5 to P8 of the identifier generation circuit 830 via the through-silicon vias 8305, respectively. Thus, the input signals to the first terminals of the logic gates 8401 to 8404 of the identifier generation circuit 840 will follow the input signals "1", "0", "0", and "0" received by the input ports P1 to P4 of the identifier generation circuit 840, respectively. Thus, the output signals "0", "1", "1", and "0" generated by the logic gates 8401 to 8404 at the output ports P5 to P8 of the identifier generation circuit 840 will serve as the chip identifier ChipID4 (e.g., 4'b0110 or 0x6 in hexadecimal).

[0346] It should be noted that the output signals of the identifier generation circuits 810, 820, 830, and 840 can be transmitted to respective decoder circuits, such as Figure 2 the decoder circuits 212, 222, 232, and 242 shown, to allow logic circuits disposed on different semiconductor dies to use the output signals from the identifier generation circuits 810, 820, 830, and 840 to control respective memory cell arrays, such as Figure 2 the memory cell arrays 213, 223, 233, and 243 shown.

[0347] According to some embodiments of the present disclosure, Figure 9 a diagram showing the operation of the stacked structure of identifier generation circuits.

[0348] In some embodiments, Figure 9 The identifier generation circuits 910, 920, 930, and 940 in the stacked structure 900 shown can correspond to the identifier generation circuits 810, 820, 830, and 840, respectively. Figure 2The identifier generation circuits 214, 224, 234, and 244 are shown disposed on the semiconductor dies 210, 220, 230, and 240, respectively. In other words, the identifier generation circuits 910, 920, 930, and 940 are disposed on different semiconductor dies (not explicitly shown in FIG. 9). In addition, Figure 9 The schematic diagram of the identifier generation circuits 910, 920, 930, and 940, and their respective input and output signals are shown in FIG. 9. Figure 9

[0349] In some embodiments, the identifier generation circuit 910 can be disposed on the bottom semiconductor die in the stacked structure 900. The input ports P1-P4 of the identifier generation circuit 910 are connected to the supply voltage VDD to represent the input signal IN[3:0] = 4'b1111 (e.g., 0xF in hexadecimal). In addition, since the second input terminal of the logic gate 9104 is connected to the supply voltage VDD via the resistor R1, the auxiliary input signal of the logic gate 9104 will be in a high logic state (e.g., "1"). Each of the logic gates 9101-9104 can perform an XOR operation on the respective bit of the input signal IN and its adjacent lower bit. For example, the logic gate 9101 performs an XOR operation on the respective bit IN[3] received from the respective input port P1 and the adjacent lower bit IN[2] received from the adjacent input port P2. The operations of the logic gates 9102-9104 can be derived in a similar manner.

[0350] It should be noted that the auxiliary input signal serves as the adjacent lower bit of the logic gate 9104. Thus, based on the truth table shown in Table 5, the output signals of the logic gates 9101-9104 are "0", "0", "0", and "0", and are transmitted to the output ports P5, P6, P7, and P8 of the identifier generation circuit 910, respectively. Thus, the output signals "0", "0", "0", and "0" generated by the logic gates 9101-9104 at the output ports P5-P8 of the identifier generation circuit 910 will simultaneously serve as the wafer identifier ChipID1 (e.g., 4'b0000 or 0x0 in hexadecimal) and the input signals of the input ports P1-P4 of the identifier generation circuit 920.

[0351] ​Since the identifier generation circuit 920 is disposed on the second semiconductor die in the stacked structure 900, the input ports P1 to P4 of the identifier generation circuit 920 are connected to the output ports P5 to P8 of the identifier generation circuit 910 via the through-silicon vias 9105, respectively. Thus, the input signals to the first terminals of the logic gates 9201 to 9204 of the identifier generation circuit 920 will follow the input signals “0”, “0”, “0”, and “0” received by the input ports P1 to P4 of the identifier generation circuit 920, respectively. Thus, the output signals “0”, “0”, “0”, and “1” generated by the logic gates 9201 to 9204 at the output ports P5 to P8 of the identifier generation circuit 920 will simultaneously serve as the wafer identifier ChipID2 (e.g., 4’b0001 or 0x1 in hexadecimal) and the input signals to the input ports P1 to P4 of the identifier generation circuit 930.

[0352] Similarly, since the identifier generation circuit 930 is disposed on the third semiconductor die in the stacked structure 900, the input ports P1 to P4 of the identifier generation circuit 930 are connected to the output ports P5 to P8 of the identifier generation circuit 920 via the through-silicon vias 9205, respectively. Thus, the input signals to the first terminals of the logic gates 9301 to 9304 of the identifier generation circuit 930 will follow the input signals “0”, “0”, “0”, and “1” received by the input ports P1 to P4 of the identifier generation circuit 930, respectively. Thus, the output signals “0”, “0”, “1”, and “0” generated by the logic gates 9301 to 9304 at the output ports P5 to P8 of the identifier generation circuit 930 will simultaneously serve as the wafer identifier ChipID3 (e.g., 4’b0010 or 0x2 in hexadecimal) and the input signals to the input ports P1 to P4 of the identifier generation circuit 940.

[0353] Similarly, since the identifier generation circuit 940 is disposed on the fourth semiconductor die (or the topmost semiconductor die) in the stacked structure 900, the input ports P1 to P4 of the identifier generation circuit 940 are connected to the output ports P5 to P8 of the identifier generation circuit 930 via the through-silicon vias 9305, respectively. Thus, the input signals to the first terminals of the logic gates 9401 to 9404 of the identifier generation circuit 940 will follow the input signals “0”, “0”, “1”, and “0” received by the input ports P1 to P4 of the identifier generation circuit 940, respectively. Thus, the output signals “0”, “1”, “1”, and “1” generated by the logic gates 9401 to 9404 at the output ports P5 to P8 of the identifier generation circuit 940 will serve as the wafer identifier ChipID4 (e.g., 4’b0111 or 0x7 in hexadecimal).

[0354] It should be noted that the output signals of the identifier generation circuits 910, 920, 930, and 940 can be transmitted to the corresponding decoder circuits, for example... Figure 2 The decoder circuits 212, 222, 232, and 242 shown allow logic circuits located on different semiconductor dies to use output signals from identifier generation circuits 910, 920, 930, and 940 to control their respective memory cell arrays (e.g., Figure 2 The memory cell arrays shown are 213, 223, 233, and 243.

[0355] According to some embodiments of this disclosure Figure 10 A diagram illustrating the operation of the stacked structure of the identifier generation circuit.

[0356] In some embodiments, Figure 10 The identifier generation circuits 1010, 1020, 1030, and 1040 in the displayed stacked structure 1000 can respectively correspond to Figure 2 The image shows identifier generation circuits 214, 224, 234, and 244 disposed on semiconductor dies 210, 220, 230, and 240. In other words, identifier generation circuits 1010, 1020, 1030, and 1040 are disposed on different semiconductor dies. Figure 10 (Not explicitly shown in the drawing). Additionally... Figure 10 The diagram shows the identifier generation circuits 1010, 1020, 1030 and 1040, as well as their respective input and output signals.

[0357] In some embodiments, an identifier generation circuit 1010 may be provided on the bottom semiconductor die in the stacked structure 1000. The input ports P1 to P4 of the identifier generation circuit 1010 are connected to the ground voltage GND and are represented by the input signal IN[3:0] = 4'b0000 (e.g., hexadecimal 0x0). In addition, since the second input terminal of the logic gate 1014 is connected to the power supply voltage VDD via resistor R1, the auxiliary input signal of the logic gate 1014 is in a high logic state (e.g., "1"). Each of the logic gates 1011 to 1014 may perform an XNOR operation on the corresponding bit of the input signal IN and its adjacent low bit. For example, the logic gate 1011 performs an XNOR operation on the corresponding bit IN[3] received from the corresponding input port P1 and the adjacent low bit IN[2] received from the adjacent input port P2. The operation of the logic gates 1012 to 1014 can be derived in a similar manner.

[0358] It should be noted that the auxiliary input signals are adjacent low bits of the logic gate 1014. Therefore, based on the truth table shown in Table 6, the output signals of the logic gates 1011-1014 are "1", "1", "1", and "0", and are transmitted to the output ports P5, P6, P7, and P8 of the identifier generation circuit 1010, respectively. Thus, the output signals "1", "1", "1", and "0" generated by the logic gates 1011-1014 at the output ports P5-P8 of the identifier generation circuit 1010 will simultaneously serve as the wafer identifier ChipID1 (e.g., 4'b1110 or hexadecimal 0xE) and the input signals of the input ports P1-P4 of the identifier generation circuit 1020.

[0359] Since the identifier generation circuit 1020 is disposed on the second semiconductor die in the stacked structure 1000, the input ports P1-P4 of the identifier generation circuit 1020 are connected to the output ports P5-P8 of the identifier generation circuit 1010 via the through-silicon vias 1015, respectively. Thus, the input signals of the first terminals of the logic gates 1021-1024 of the identifier generation circuit 1020 will follow the input signals "1", "1", "1", and "0" received by the input ports P1-P4 of the identifier generation circuit 1020, respectively. Therefore, the output signals "1", "1", "0", and "0" generated by the logic gates 1021-1024 at the output ports P5-P8 of the identifier generation circuit 1020 will simultaneously serve as the wafer identifier ChipID2 (e.g., 4'b1100 or hexadecimal 0xC) and the input signals of the input ports P1-P4 of the identifier generation circuit 1030.

[0360] Similarly, since the identifier generation circuit 1030 is disposed on the third semiconductor die in the stacked structure 1000, the input ports P1-P4 of the identifier generation circuit 1030 are connected to the output ports P5-P8 of the identifier generation circuit 1020 via the through-silicon vias 1025, respectively. Thus, the input signals of the first terminals of the logic gates 1031-1034 of the identifier generation circuit 1030 will follow the input signals "1", "1", "0", and "0" received by the input ports P1-P4 of the identifier generation circuit 1030, respectively. Therefore, the output signals "1", "0", "1", and "0" generated by the logic gates 1031-1034 at the output ports P5-P8 of the identifier generation circuit 1030 will simultaneously serve as the wafer identifier ChipID3 (e.g., 4'b1010 or hexadecimal 0xA) and the input signals of the input ports P1-P4 of the identifier generation circuit 1040.

[0361] Similarly, since the identifier generation circuit 1040 is disposed on the fourth semiconductor die (or the topmost semiconductor die) in the stacked structure 1000, the input ports P1 to P4 of the identifier generation circuit 1040 are connected to the output ports P5 to P8 of the identifier generation circuit 1030 via the through-silicon vias 1035, respectively. Thus, the input signals to the first terminals of the logic gates 1041 to 1044 of the identifier generation circuit 1040 will follow the input signals "1", "0", "1", and "0" received by the input ports P1 to P4 of the identifier generation circuit 1040, respectively. Thus, the output signals "0", "0", "0", and "0" generated at the output ports P5 to P8 of the identifier generation circuit 1040 will be Chip ID4 (e.g., 4'b0000 or 0x0 in hexadecimal).

[0362] It should be noted that the output signals of the identifier generation circuits 1010, 1020, 1030, and 1040 can be transmitted to respective decoder circuits, such as Figure 2 the decoder circuits 212, 222, 232, and 242 shown, to allow the logic circuits disposed on different semiconductor dies to use the output signals from the identifier generation circuits 1010, 1020, 1030, and 1040 to control respective memory cell arrays, such as Figure 2 the memory cell arrays 213, 223, 233, and 243 shown.

[0363] It should be noted that Figures 5 to 10 The preset values of the input signals IN[3:0] in the embodiments shown are for illustrative purposes only. By appropriately designing the preset values of the input signals IN[3:0], each of the identifier generation circuits in the stacked structure can generate a unique identifier that represents the respective position of the identifier generation circuit in the stacked structure. It should be noted that the chip identifier of each semiconductor die is not limited to 4 bits. When there are more semiconductor dies in the stacked structure, the width of the identifier of each semiconductor die can be extended in a similar manner.

[0364] According to some embodiments of the present disclosure, Figure 11 is a flowchart of a method for automatically generating chip identifiers for semiconductor dies in a stacked structure. Please refer to Figure 2 , Figure 3 and Figure 11 .

[0365] In step 1110, a first semiconductor die (e.g., semiconductor die 210) and a second semiconductor die (e.g., semiconductor die 220) are obtained, where the first semiconductor die and the second semiconductor die include a first identifier generation circuit (e.g., identifier generation circuit 214) and a second identifier generation circuit (e.g., identifier generation circuit 224), respectively.

[0366] In step 1120, the second semiconductor die is stacked on the first semiconductor die to form a stacked structure, where the first identifier generation circuit is electrically connected to the second identifier generation circuit.

[0367] In step 1130, a first wafer identifier and a second wafer identifier are generated for the first semiconductor die and the second semiconductor die by the first identifier generation circuit and the second identifier generation circuit, respectively, where the second wafer identifier is generated using the first wafer identifier and an auxiliary input signal. For example, the second identifier generation circuit can receive the first wafer identifier generated by the first identifier generation circuit, and each logic gate in the second identifier generation circuit can perform a corresponding logical operation on a corresponding bit and its adjacent lower bit to generate a respective bit of the second wafer identifier. For the logic gate corresponding to the least significant bit of the first wafer identifier, the auxiliary input signal can serve as the adjacent lower bit of the least significant bit of the first wafer identifier.

[0368] In one aspect of the present disclosure, a semiconductor device includes a plurality of semiconductor dies arranged in a stacked structure. Each semiconductor die includes an identifier generation circuit electrically connected to the identifier generation circuits of other semiconductor dies. In response to a first semiconductor die not being a bottom semiconductor die in the stacked structure, a first identifier generation circuit of the first semiconductor die is configured to automatically generate a first wafer identifier for the first semiconductor die based on an auxiliary input signal and a second wafer identifier generated by a second identifier generation circuit of a second semiconductor die adjacent to and below the first semiconductor die.

[0369] In some embodiments, the stacked structure is a three-dimensional stacked structure.

[0370] In some embodiments, a first input signal of the first identifier generation circuit of the first semiconductor die is the second wafer identifier generated by the second identifier generation circuit.

[0371] In some embodiments, in response to the second semiconductor die being the bottom semiconductor die in the stacked structure, the second identifier generation circuit of the second semiconductor die is configured to automatically generate the second wafer identifier for the second semiconductor die using the auxiliary input signal and a second input signal.

[0372] In some embodiments, the first wafer identifier is different from the second wafer identifier.

[0373] In some embodiments, the first identifier generation circuit includes a plurality of first logic gates, a plurality of first input ports, and a plurality of first output ports, and the plurality of first logic gates correspond to the plurality of first input ports and the plurality of first output ports. Each of the plurality of first logic gates receives a corresponding bit in the second wafer identifier and an adjacent lower bit adjacent thereto from the corresponding first input port.

[0374] In some embodiments, the first identifier generation circuit includes a plurality of first logic gates, a plurality of first input ports, and a plurality of first output ports. The plurality of first logic gates correspond to the plurality of first input ports and the plurality of first output ports. Each of the plurality of first logic gates receives a corresponding bit in the second wafer identifier from the corresponding first input port.

[0375] In some embodiments, the auxiliary input signal is as the adjacent lower bit of the first logic gate corresponding to at least one significant bit of the first input signal.

[0376] In some embodiments, the plurality of first logic gates are the same type of two-input logic gates. The plurality of two-input logic gates are AND gates, NAND gates, OR gates, NOR gates, XOR gates, or XNOR gates.

[0377] In some embodiments, the second identifier generation circuit includes a plurality of second logic gates, a plurality of second input ports, and a plurality of second output ports, and the plurality of second logic gates correspond to the plurality of second input ports and the plurality of second output ports. In response to the second semiconductor die being the bottom semiconductor die in the stack structure, the plurality of second input ports of the second identifier generation circuit of the second semiconductor die receive the second input signal.

[0378] In some embodiments, a preset value of the second input signal is determined according to the type of the plurality of second logic gates.

[0379] In some embodiments, when a particular bit of the second input signal is 1, a power supply voltage is provided to the second input port corresponding to the particular bit; and when the particular bit of the second input signal is 0, a ground voltage is provided to the second input port corresponding to the particular bit.

[0380] In some embodiments, the plurality of first logic gates and the plurality of second logic gates are the same type.

[0381] In some embodiments, the first identifier generation circuit is electrically connected to the second identifier generation circuit via a plurality of through silicon vias in the second semiconductor die.

[0382] In some embodiments, the first wafer identifier and the second wafer identifier are transmitted by the first identifier generation circuit and the second identifier generation circuit, respectively, to a first decoder circuit and a second decoder circuit disposed on the first semiconductor die and the second semiconductor die, respectively.

[0383] In another aspect of the present disclosure, a method for automatically generating wafer identifiers for semiconductor dies in a stacked structure is provided. The method includes the steps of obtaining a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die include a first identifier generation circuit and a second identifier generation circuit, respectively; stacking the second semiconductor die on the first semiconductor die to form a stacked structure, wherein the first identifier generation circuit is electrically connected to the second identifier generation circuit; and generating a first wafer identifier and a second wafer identifier for the first semiconductor die and the second semiconductor die, respectively, by the first identifier generation circuit and the second identifier generation circuit, wherein the second wafer identifier is generated using the first wafer identifier and an auxiliary input signal.

[0384] In some embodiments, the method further includes the step of electrically connecting the first identifier generation circuit to the second identifier generation circuit via a plurality of through silicon vias in the first semiconductor die.

[0385] In some embodiments, the method further includes the step of generating the first wafer identifier using a preset value and the auxiliary input signal in response to the first semiconductor die being a bottom semiconductor die in the stacked structure.

[0386] In some embodiments, the preset value corresponds to a type of a plurality of first logic gates in the first identifier generation circuit.

[0387] In some embodiments, the plurality of first logic gates are two-input logic gates of the same type. The two-input logic gates are AND gates, NAND gates, OR gates, NOR gates, XOR gates, or XNOR gates.

[0388] In some embodiments, the method further includes the step of transmitting the first wafer identifier and the second wafer identifier by the first identifier generation circuit and the second identifier generation circuit, respectively, to a first decoder circuit and a second decoder circuit disposed on the first semiconductor die and the second semiconductor die, respectively.

[0389] Yet another aspect of the present disclosure provides a memory device including a stack structure having a first memory die and a second memory die. The first memory die is stacked on the second memory die. The first memory die and the second memory die respectively include a first identifier generation circuit and a second identifier generation circuit. The second identifier generation circuit is configured to automatically generate a second die identifier for the second memory die using a preset value and a first auxiliary input signal, and the first identifier generation circuit is configured to automatically generate a first die identifier using the second die identifier and a second auxiliary input signal.

[0390] In some embodiments, the first identifier generation circuit is electrically connected to the second identifier generation circuit via a plurality of through silicon vias in the second memory die.

[0391] In some embodiments, the first auxiliary input signal is equal to the second auxiliary input signal.

[0392] In some embodiments, the first identifier generation circuit includes a plurality of first logic gates, a plurality of first input ports, and a plurality of first output ports, and each of the plurality of first logic gates receives a corresponding bit in the second die identifier and an adjacent lower bit adjacent thereto from the corresponding first input port.

[0393] In some embodiments, the first auxiliary input signal is the adjacent lower bit of the first logic gate corresponding to at least one significant bit of the second die identifier.

[0394] In some embodiments, the second identifier generation circuit includes a plurality of second logic gates, a plurality of second input ports, and a plurality of second output ports, and each of the plurality of second logic gates corresponds to a corresponding second input port and a corresponding second output port. In response to the second memory die being a bottom semiconductor die in the stack structure, the plurality of second input ports of the second identifier generation circuit of the second memory die receives the preset value.

[0395] In some embodiments, the plurality of first logic gates and the plurality of second logic gates are the same type of two-input logic gates.

[0396] In some embodiments, the plurality of two-input logic gates are AND gates, NAND gates, OR gates, NOR gates, XOR gates, or XNOR gates.

[0397] While the disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes can be under taken in an alternate order, and / or the illustrated processes can be modified or combined. Moreover, certain materials or substrates can be substituted for those illustrated or described herein and still be within the scope of the disclosure.

[0398] Further, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will understand, processes, machines, manufacture, compositions of matter, means, methods or steps for carrying out the described processes can be used in accordance with the present disclosure, or future equivalents, without departing from the scope of the disclosure. Accordingly, the appended claims are intended to include within their scope all processes, machines, manufacture, compositions of matter, means, methods or steps for carrying out the described processes, or future equivalents.

Claims

1. A semiconductor device, comprising: Multiple semiconductor chips are arranged in a stacked structure. Each of the plurality of semiconductor chips includes an identifier generation circuit electrically connected to the identifier generation circuits of the other semiconductor chips in the plurality of semiconductor chips. In response to a situation where a first semiconductor die is not a bottom semiconductor die in the stacked structure, a first identifier generation circuit for the first semiconductor die is configured to automatically generate a first chip identifier for the first semiconductor die. The generation of the first chip identifier is based on an auxiliary input signal and a second chip identifier, which is generated by a second identifier generation circuit for a second semiconductor die that is adjacent to and below the first semiconductor die.

2. The semiconductor device of claim 1, wherein the stacked structure is a three-dimensional stacked structure.

3. The semiconductor device of claim 1, wherein a first input signal of the first identifier generation circuit of the first semiconductor die is the second wafer identifier generated by the second identifier generation circuit.

4. The semiconductor device of claim 3, wherein in response to the second semiconductor die being the bottom semiconductor die in the stacked structure, the second identifier generation circuit of the second semiconductor die is configured to automatically generate the second wafer identifier for the second semiconductor die using the auxiliary input signal and a second input signal.

5. The semiconductor device of claim 4, wherein the first chip identifier is different from the second chip identifier.

6. The semiconductor device of claim 5, wherein the first identifier generation circuit includes a plurality of first logic gates, a plurality of first input ports, and a plurality of first output ports, and the plurality of first logic gates correspond to the plurality of first input ports and the plurality of first output ports. Each of the plurality of first logic gates receives a corresponding bit and an adjacent low bit from the second chip identifier from the corresponding first input port.

7. The semiconductor device of claim 6, wherein the auxiliary input signal is the adjacent low bit of the first logic gate corresponding to at least one valid bit of the first input signal.

8. The semiconductor device of claim 7, wherein the plurality of first logic gates are two-input logic gates of the same type.

9. The semiconductor device of claim 8, wherein the two-input logic gate is an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, or an XNOR gate.

10. The semiconductor device of claim 6, wherein the second identifier generation circuit includes a plurality of second logic gates, a plurality of second input ports, and a plurality of second output ports, and the plurality of second logic gates correspond to the plurality of second input ports and the plurality of second output ports. In response to the second semiconductor die being the bottom semiconductor die in the stacked structure, the plurality of second input ports of the second identifier generation circuit of the second semiconductor die receive the second input signal.

11. The semiconductor device of claim 10, wherein a preset value of the second input signal is determined according to the type of the plurality of second logic gates.

12. The semiconductor device of claim 11, wherein: When a specific bit of the second input signal is 1, a power supply voltage is provided to the second input port corresponding to the specific bit. as well as When the specific element of the second input signal is 0, a ground voltage is provided to the second input port corresponding to the specific element.

13. The semiconductor device of claim 11, wherein the plurality of first logic gates and the plurality of second logic gates are of the same type.

14. The semiconductor device of claim 4, wherein the first identifier generation circuit is electrically connected to the second identifier generation circuit via a plurality of silicon through-holes in the second semiconductor die.

15. The semiconductor device of claim 1, wherein the first wafer identifier and the second wafer identifier are transmitted to a first decoder circuit and a second decoder circuit disposed on the first semiconductor die and the second semiconductor die, respectively.

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