Nor flash and its read operation module, and its power supply circuit

Abstract

The present disclosure provides a Nor Flash, a read operation module thereof, and a power supply circuit thereof. The power supply circuit of the read operation module of the Nor Flash includes a first charge pump unit, a second charge pump unit, and a read operation voltage generation unit. The first charge pump unit is configured to output a first voltage to the read operation voltage generation unit. The second charge pump unit is configured to output a second voltage to the read operation voltage generation unit. The read operation voltage generation unit is configured to output a read operation voltage to a storage array module based on the first voltage and the second voltage, so as to provide a standby state read operation standby voltage or a read operation state read operation working voltage to the storage array module. Since the read operation standby voltage is substantially equal to the read operation working voltage, the read operation voltage is stable when the Nor Flash switches from any moment of the standby state to the read operation state, and the read operation voltage will not change with the chip power supply voltage of the Nor Flash.

Description

Technical Field

[0001] This disclosure relates to the field of non-volatile memory technology, and more particularly to a Nor Flash (a non-volatile flash memory technology) and its read operation module and power supply circuit. Background Technology

[0002] Nor Flash memory technology is a non-volatile memory technology primarily used for storing program code and data. Compared to traditional Electrically Erasable Programmable Read-Only Memory (EEPROM), it offers advantages such as large capacity, small size, low power consumption, stable performance, and high domestic production rate. Therefore, Nor Flash is widely used in various intelligent fields, including motherboard basic input / output systems, digital set-top boxes, home gateways, routers, the Internet of Things (IoT), automotive electronics, wearable devices, security monitoring, and artificial intelligence, serving as a code storage medium. Its versatility and reliability make our lives more convenient and intelligent.

[0003] Nor Flash read operations require high voltage, while low power consumption is needed in standby mode. Nor Flash arrays have a large capacitance along the read operation path, and the time from standby to normal operation is only tens of nanoseconds (ns). Therefore, it is difficult to charge this large capacitor to the required high voltage within this time. Existing Nor Flash read operation modules use a voltage refresh mechanism in their power supply circuits. If the target voltage is 6V, it is charged to 6V when the Nor Flash is powered on, and then the charge pump circuit is turned off. Internal parasitic leakage paths cause the voltage to gradually decrease. This voltage is detected by a low-power detection circuit. Once the voltage drops to 5.6V, the charge pump circuit is restarted to charge it back to 6V.

[0004] The main problem with this design is that when the Nor Flash read operation module switches from standby to operation, there are two extreme cases. The first is that the high voltage required for the read operation has reached 6V, and the second is 5.6V. Since a read operation is about to be performed, the first case does not require much charge replenishment, while the second case requires a large amount of charge replenishment. The charge is provided by a very powerful charge pump. Because the entire Nor Flash takes a certain amount of time to establish the reference voltage, detect the voltage, and determine whether to replenish the charge, the operating voltage for the first read operation is not very stable, especially under different Nor Flash chip power supply voltages (VDD). Since the operating voltage for the read operation is sensitive to changes in VDD, overshoot may occur at high VDD and undershoot may occur at low VDD. This causes the operating voltage for the read operation to vary greatly with the chip power supply voltage (VDD), which may lead to errors in the read operation. Summary of the Invention

[0005] The technical problem to be solved by this disclosure is to overcome the defect in the existing Nor Flash read operation module, where the difference between the read operation standby voltage and the read operation working voltage is large, resulting in the read operation working voltage being sensitive to changes in VDD. This disclosure provides a Nor Flash, its read operation module, and its power supply circuit.

[0006] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0007] In a first aspect, a power supply circuit is provided for a Nor Flash read operation module, wherein the Nor Flash includes a storage array module composed of several storage arrays;

[0008] The power supply circuit includes a first charge pump unit, a second charge pump unit, and a read operation voltage generation unit;

[0009] The read operation voltage generation unit is electrically connected to the first charge pump unit, the second charge pump unit, and the storage array module, respectively.

[0010] The first charge pump unit is used to convert the chip power supply voltage of the NorFlash to a first voltage and output it to the read operation voltage generation unit based on the read operation signal and the first standby refresh signal;

[0011] The second charge pump unit is used to convert the chip power supply voltage into a second voltage and output it to the read operation voltage generation unit based on the read operation signal and the second standby refresh signal;

[0012] The read operation voltage generating unit is used to output a read operation voltage to the storage array module based on the first voltage and the second voltage, so as to provide the storage array module with the read operation standby voltage of the Nor Flash in standby state or the read operation working voltage in read operation state.

[0013] Wherein, the actual difference between the standby voltage of the read operation and the working voltage of the read operation is less than or equal to a first preset value.

[0014] Optionally, the read operation voltage generation unit includes a capacitor and a first MOS transistor, a second MOS transistor and a first switch;

[0015] The width-to-length ratio of the second MOS transistor is greater than that of the first MOS transistor;

[0016] The output terminal of the second charge pump unit is electrically connected to the gate of the first MOS transistor and the gate of the second MOS transistor, respectively.

[0017] The drain of the first MOS transistor is electrically connected to the output terminal of the first charge pump unit;

[0018] The drain of the second MOS transistor is electrically connected to the output terminal of the first charge pump unit via the first switch;

[0019] The source of the first MOS transistor and the source of the second MOS transistor are electrically connected to the memory array module, respectively.

[0020] One end of the capacitor is electrically connected to the output terminal of the second charge pump unit, and the other end of the capacitor is grounded.

[0021] Optionally, the read operation voltage generation unit further includes a second switch and a current source;

[0022] One end of the current source is grounded, and the other end of the current source is electrically connected to one end of the second switch;

[0023] The other end of the second switch is electrically connected to the source of the second MOSFET;

[0024] The current value output by the current source is the same as the current value flowing through the second MOS transistor when the target memory cell in the target memory array is in the read operation state.

[0025] Optionally, the standby state includes a standby no-refresh state and a standby refresh state;

[0026] When the Nor Flash is in a standby no-refresh state, the read operation signal is invalid, the first standby refresh signal and the second standby refresh signal are both invalid, the first switch and the second switch are both in the off state, and the current voltage difference between the first voltage and the read operation voltage is greater than or equal to the second preset value.

[0027] Alternatively, when the Nor Flash is in standby refresh state, the read operation signal is invalid. If the current voltage difference between the first voltage and the read operation voltage is less than the second preset value, then both the first standby refresh signal and the second standby refresh signal are valid, the first switch and the second switch are both closed, and the first charge pump unit and the second charge pump unit are in working state, so that the current voltage difference is greater than or equal to the second preset value.

[0028] Optionally, when the Nor Flash is in a read operation state, the read operation signal is valid, the first standby refresh signal and the second standby refresh signal are both invalid, the first switch and the second switch are both closed, and the first charge pump unit and the second charge pump unit are both in operation, so that the current voltage difference between the first voltage and the read operation voltage is greater than or equal to a second preset value.

[0029] Optionally, the power supply circuit further includes a voltage detection unit;

[0030] The voltage detection unit is electrically connected to the first charge pump unit, the second charge pump unit, and the read operation voltage generation unit, respectively.

[0031] The voltage detection unit is used to detect the current voltage difference between the first voltage and the read operation voltage, and based on the read operation signal and the current voltage difference, to set both the first standby refresh signal and the second standby refresh signal to an invalid state or an effective state.

[0032] Optionally, the power supply circuit further includes a frequency divider;

[0033] The frequency divider is used to receive the first standby refresh signal, perform a frequency division operation, and then output the second standby refresh signal.

[0034] Optionally, each storage array is equipped with a third switch and a fourth switch;

[0035] One end of the third switch is electrically connected to the storage unit, and the other end of the third switch is used to receive the write operation power supply voltage;

[0036] One end of the fourth switch is electrically connected to the storage unit, and the other end of the fourth switch is electrically connected to the output terminal of the read operation voltage generating unit.

[0037] Secondly, a Nor Flash read operation module is provided, the Nor Flash read operation module including a read operation signal generation circuit, the read operation signal generation circuit being used to generate a read operation signal;

[0038] The Nor Flash read operation module also includes the power supply circuit of the Nor Flash read operation module described above.

[0039] Thirdly, a Nor Flash is provided, which includes the Nor Flash read operation module described above and a storage array module composed of several storage arrays.

[0040] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.

[0041] The positive and progressive effects of this disclosure are as follows:

[0042] This disclosure discloses a Nor Flash, its read operation module, and its power supply circuit. The power supply circuit includes a first charge pump unit, a second charge pump unit, and a read operation voltage generation unit. The read operation voltage generation unit is electrically connected to the first charge pump unit, the second charge pump unit, and the memory array module, respectively. The read operation voltage generation unit outputs a read operation voltage to the memory array module in the Nor Flash based on a first voltage output by the first charge pump unit and a second voltage output by the second charge pump unit. This provides the memory array module with a read operation standby voltage for the Nor Flash in standby mode or a read operation working voltage for read operation mode. Since the actual difference between the read operation standby voltage and the read operation working voltage is less than or equal to a first preset value, the read operation standby voltage and the read operation working voltage are essentially equal. This ensures that the read operation voltage remains stable when the system switches from standby mode to read operation mode at any time and does not change with the Nor Flash chip power supply voltage. This solves the problem in existing read operation modules where the large difference between the read operation standby voltage and the read operation working voltage causes the read operation working voltage to be highly sensitive to changes in the Nor Flash chip power supply voltage. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the first structure of the power supply circuit of an existing Nor Flash read operation module;

[0044] Figure 2 This is a schematic diagram of the second structure of the power supply circuit for an existing Nor Flash read operation module;

[0045] Figure 3 This is a first structural schematic diagram of the power supply circuit of the Nor Flash read operation module provided in Embodiment 1 of this disclosure;

[0046] Figure 4 This is a second structural schematic diagram of the power supply circuit of the Nor Flash read operation module provided in Embodiment 1 of this disclosure;

[0047] Figure 5 This is a third structural diagram of the power supply circuit of the Nor Flash read operation module provided in Embodiment 1 of this disclosure;

[0048] Figure 6 This is a fourth structural diagram of the power supply circuit of the Nor Flash read operation module provided in Embodiment 1 of this disclosure;

[0049] Figure 7 This is a fifth structural schematic diagram of the power supply circuit of the Nor Flash read operation module provided in Embodiment 1 of this disclosure;

[0050] Figure 8 This is a schematic diagram of the Nor Flash read operation module provided in Embodiment 2 of this disclosure;

[0051] Figure 9 This is a schematic diagram of the structure of the Nor Flash provided in Embodiment 3 of this disclosure. Detailed Implementation

[0052] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.

[0053] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the claims or the context of the embodiments, and should not be construed as an unnecessary limitation. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.

[0054] Figure 1This describes the operation of the existing Nor Flash read operation module in standby mode. The read pump and standby pump are high-voltage power supplies. The memory array module has N+1 memory arrays, numbered from Array 0 to Array N. Each array has two high-voltage switches (read switch and standby switch) to select different high-voltage power supplies. The read switches correspond to S0…SN, and the standby switches correspond to S0B…SNB. In standby mode, the read operation signal is invalid (i.e., read_en=0), and the standby pump operates. The standby pump's output voltage is read_stb (read operation standby voltage). At this time, all standby switches are connected to read_stb, which is provided by the standby pump. The read_stb has a low-power detection circuit. In standby mode, there is a parasitic leakage current of about 50nA at the array terminal, which causes the read_stb voltage, which was already at the target value at power-on, to gradually decrease. When the detector detects that the read_stb voltage has dropped by a preset value (e.g., 0.4V) from the target value, the refresh control signal is set to 1 (refresh_en=1), causing the standby pump to start working again and bringing the read_stb voltage back to the target value. Therefore, in standby mode, read_stb will fluctuate by about 0.4V; the read pump does not work during the entire standby period.

[0055] Figure 2 The existing Nor Flash read operation module operates during read active mode, and Figure 1 Compared to the standby state shown, the read operation signal is valid (i.e., read_en=1) at this time. The read pump and the standby pump operate simultaneously, and their target voltages are the same, which is the aforementioned target value. That is, the output voltage read_act (read operation operating voltage) of the read pump is equal to the output voltage read_stb of the standby pump, both equal to read_act (read operation operating voltage). Assuming that the array to be read is Array 0, then the S0 and S0B switches of Array 0 change compared to the standby state. S0 is closed, and S0B is open. The power supply of Array 0 switches to read_act output by the read pump, while the other unselected arrays remain unchanged.

[0056] The problem with the existing Nor Flash read operation module is that a sufficient margin (i.e., the aforementioned preset value) must be left between read_stb and read_act to ensure standby power consumption. Therefore, the difference between the two cannot be too small, typically 0.4V. During read active operation, the read pump, in addition to supporting WL (word line) switching consumption, needs to replenish additional charge. The capacitive load of one array is typically in the range of 30~50pF. If the Nor Flash chip power supply voltage VDD is 2.6V, read_stb is 5.6V, and the target value of read_act is 6V, meaning the chip power supply voltage is low and the difference between read_stb and read_act is large, the read pump capability is weak due to the strong correlation between pump capability and VDD. At the start of the read operation, it is insufficient to make Array0's read_act reach the target value. If the Nor Flash chip power supply voltage VDD is 3.7V, read_stb is already 6V, and the target value of read_act is 6V, meaning the chip power supply voltage is relatively high and there is no difference between read_stb and read_act, then the readpump capability is very strong. Since there are only tens of ns between the chip receiving the read instruction and the internal execution of the first read operation, the charge pump cannot wait until all internal signals are fully established before starting to work. Therefore, the charge pump may erroneously work for a few ns first, which will cause the read_act of Array 0 to exceed the target value of 6V, resulting in overshoot.

[0057] In existing technologies, sufficient margin must be left between read_stb and read_act, and the read operation operating voltage read_act is not very stable, especially under different Nor Flash chip power supply voltages VDD. Because the read operation operating voltage read_act is sensitive to changes in VDD, overshoot may occur at high VDD and undershoot may occur at low VDD, causing the read operation operating voltage read_act to vary greatly with changes in the chip power supply voltage VDD, resulting in read operation errors.

[0058] To address this issue, this disclosure provides a Nor Flash memory, its read operation module, and its power supply circuit, to at least solve the aforementioned technical problem. The specific details are as follows:

[0059] Example 1

[0060] This embodiment provides a power supply circuit for a Nor Flash read operation module, such as... Figure 3 As shown, Nor Flash comprises a storage array module consisting of several storage arrays;

[0061] The power supply circuit includes a first charge pump unit 1, a second charge pump unit 2, and a read operation voltage generation unit 3;

[0062] The read operation voltage generation unit 3 is electrically connected to the first charge pump unit 1, the second charge pump unit 2, and the storage array module, respectively.

[0063] The first charge pump unit 1 is used to convert the chip power supply voltage VDD of Nor Flash to the first voltage read_vd based on the read operation signal read_en and the first standby refresh signal Refresh_en_drain, and output it to the read operation voltage generation unit 3;

[0064] The second charge pump unit 2 is used to convert the chip power supply voltage VDD into the second voltage read_vg based on the read operation signal read_en and the second standby refresh signal Refresh_en_gate, and output it to the read operation voltage generation unit 3.

[0065] The read operation voltage generation unit 3 is used to output the read operation voltage read_power to the storage array module based on the first voltage read_vd and the second voltage read_vg, so as to provide the storage array module with the read operation standby voltage when the Nor Flash is in standby state, or the read operation working voltage when it is in read operation state.

[0066] Specifically, the actual difference between the read operation standby voltage and the read operation operating voltage is less than or equal to a first preset value. The first preset value needs to be as small as possible to ensure that the read operation standby voltage and the read operation operating voltage are equal or substantially equal. For example, the range of the first preset difference is -0.1V to +0.1V, and the first preset value can be 0.1V.

[0067] A Nor Flash memory array module consists of several memory arrays, each containing several memory cells. Each memory array module has a certain density (storage capacity), and each array has a specific size. If a memory array has a capacity of 4 Mbit, then a memory array module with four arrays has a storage capacity of 16 Mbits. If a memory array module with 32 arrays has a storage capacity of 128 Mbits, then in practical use, read operations on the corresponding memory arrays are required.

[0068] In this embodiment, the read operation voltage `read_power` is the read operation standby voltage in standby mode and the read operation working voltage in readactive mode. Its value is essentially equal in both states, ensuring that the read operation voltage remains stable when the Nor Flash switches from standby mode to read operation mode at any time and does not change with the Nor Flash chip power supply voltage. This solves the problem in existing read operation modules where the large difference between the read operation standby voltage and the read operation working voltage makes the read operation working voltage highly sensitive to changes in the Nor Flash chip power supply voltage.

[0069] In an alternative implementation, such as Figure 4 , 5 As shown in Figure 6, the read operation voltage generation unit 3 includes a capacitor C0, a first MOSFET NM0, a second MOSFET NM1, and a first switch K1;

[0070] The width-to-length ratio of the second MOSFET NM1 is greater than that of the first MOSFET NM0;

[0071] The output terminal of the second charge pump unit 2 is electrically connected to the gate of the first MOS transistor NM0 and the gate of the second MOS transistor NM1, respectively.

[0072] The drain of the first MOS transistor NM0 is electrically connected to the output terminal of the first charge pump unit 1;

[0073] The drain of the second MOSFET NM1 is electrically connected to the output terminal of the first charge pump unit 1 via the first switch K1.

[0074] The source of the first MOSFET NM0 and the source of the second MOSFET NM1 are electrically connected to the memory array module, respectively.

[0075] One end of capacitor C0 is electrically connected to the output terminal of the second charge pump unit 2, and the other end of capacitor C0 is grounded. (See also...) Figure 4 , 5 As can be seen from 6, the gate voltages of NM0 and NM1 are both the second voltage read_vg, the drain voltages of NM0 and NM1 are the first voltage read_vd, and the source voltages of NM0 and NM1 are the read operation voltage read_power. NM0 and NM1 form a source follower. By taking advantage of the characteristic of the MOS transistor being in the saturation region, even if the first voltage read_vd fluctuates, the first standby refresh signal and the read operation signal drive the first charge pump unit to work, replenishing read_vd, so that the read operation voltage read_power can also remain stable.

[0076] In an alternative implementation, such as Figure 4 , 5As shown in Figure 6, the read operation voltage generation unit 3 also includes a second switch K2 and a current source Ib0;

[0077] One end of the current source Ib0 is grounded, and the other end of the current source Ib0 is electrically connected to one end of the second switch K2.

[0078] The other end of the second switch K2 is electrically connected to the source of the second MOSFET NM1;

[0079] The current value output by the current source Ib0 is the same as the current value flowing through the second MOS transistor NM1 when the target memory cell in the target memory array is in the read operation state.

[0080] The target storage array is any one of the storage array modules, i.e., any one of Array0-ArrayN. The target storage unit can be any one storage unit, a row of storage units, a column of storage units, or all the storage units in the target storage array, depending on the rules of Nor Flash read operations.

[0081] During read active, the target memory array will have a real read current (for WL setup, the current during the word line establishment phase), which mainly flows through the second MOSFET NM1. During the standby refresh phase, since there is no real read operation, no real read current is generated. Therefore, a current source Ib0 is used to simulate the read current of the target memory array during read active. By setting the current source, the standby voltage during standby and the working voltage during read active are further ensured to be equal, thereby further reducing the fluctuation of the read operation voltage.

[0082] In an optional implementation, the standby state includes a standby no-refresh state and a standby refresh state. When the NorFlash is in the standby no-refresh state (i.e., standby no refresh phase), the read operation signal is invalid, i.e., read_en=0, the first standby refresh signal and the second standby refresh signal are both invalid, i.e., Refresh_en_drain=0 and Refresh_en_gate=0, the first switch K1 and the second switch K2 are both in the off state, and the current voltage difference between the first voltage read_vd and the read operation voltage read_power is greater than or equal to the second preset value vth, so as to ensure that the first MOS transistor is in the saturation state.

[0083] Among them, the first charge pump unit 1 is in a standby state under the control of the read operation signal read_en and the first standby refresh signal Refresh_en_drain; the second charge pump unit 2 is in a standby state under the control of the read operation signal read_en and the second standby refresh signal Refresh_en_gate.

[0084] When the Nor Flash is in the standby non-refresh state, read_en = 0, read_vd - read_power > vth, the second preset value vth is the threshold voltage vth(NM0) corresponding to the first MOS transistor NM0, as Figure 4 shown. At this time, both the first switch K1 and the second switch K2 are disconnected, the second MOS transistor NM1 does not work, and the power supplies of all Arrays are connected to read_power. Since read_power = read_vg - vth(NM0) - vov(NM0), vov(NM0) is the overdrive voltage (Overdrive Voltage) corresponding to the first MOS transistor NM0, the parasitic leakage current at the storage array module end will make the first voltage read_vd gradually decrease. However, since the first MOS transistor NM0 operates in the saturation region, the read operation standby voltage read_power is stable at this time.

[0085] In an optional implementation manner, when the Nor Flash is in the standby refresh state (standby refresh phase), the read operation signal is in an invalid state, that is, read_en = 0. If the current voltage difference between the first voltage read_vd and the read operation voltage read_power is less than the second preset value, then both the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate are in an effective state, that is, Refresh_en_drain = 1 and Refresh_en_gate = 1, both the first switch K1 and the second switch K2 are in a closed state, the first charge pump unit 1 is in a working state under the control of the read operation signal read_en and the first standby refresh signal Refresh_en_drain; the second charge pump unit 2 is in a working state under the control of the read operation signal read_en and the second standby refresh signal Refresh_en_gate, so that the current voltage difference is greater than or equal to the second preset value to ensure that both the first MOS transistor and the second MOS transistor are in the saturation state.

[0086] When the Nor Flash is in the standby refresh state, read_en = 0. If read_vd - read_power < vth, as Figure 5As shown, at this time, both the first switch K1 and the second switch K2 are closed, and both the first MOSFET NM0 and the second MOSFET NM1 are working and in saturation. The bias current flowing through the second switch K2 is on the order of several uA (microamps), so the difference between the read_power voltage of the standby no refresh phase and the standby refresh phase will become small.

[0087] Specifically, since read_vg remains unchanged, both NM0 and NM1 operate in the saturation region, and the threshold voltages vth of NM0 and NM1 are equal, i.e., vth(NM1) = vth(NM0). read_power = read_vg - vth(NM1) - vov(NM1). The second preset value is the threshold voltage vth(NM0) corresponding to the first MOS transistor NM0, which is also the threshold voltage vth(NM1) corresponding to the second MOS transistor NM1. vov(NM1) is the overdrive voltage (Overdrive Voltage) corresponding to the second MOS transistor NM1. The only difference is the overdrive voltage vov of NM0 and NM1, and vov is related to the aspect ratio and the current flowing through the MOS transistor. There is a significant difference in the currents flowing through NM0 and NM1 during the standby no refresh phase and the standby refresh phase. When in standby no refresh, the current flowing through NM0 is extremely small, but during the standby refresh phase, the current flowing through NM1 is relatively large, for example, it becomes 100 times larger. Therefore, the aspect ratio of the second MOS transistor NM1 needs to be greater than that of the first MOS transistor NM0, for example, NM1 is 100 times larger than NM0, to ensure that the overdrive voltages vov of NM0 and NM1 are also equal, i.e., to ensure vov(NM1) = vov(NM0). This enables a smaller MOS (NM0) to adapt to a small current (the leakage current of the Array) during the standby no refresh phase, and an additional current source (Ib0) to adapt to a larger MOS (NM1) during the standby refresh phase. Then, the voltage difference of read_power between the standby no refresh phase and the standby refresh phase will become smaller, and the two are basically equal. During this period, the first charge pump unit 1 is in the working state, and the second charge pump unit 2 is in an intermittent working state (i.e., it works when read_vd - read_power < vth, refresh_en_drain = 1, and refresh_en_gate = 1, and at this time, refresh_en_drain and refresh_en_gate have different frequencies) or the second charge pump unit is in the working state (at this time, refresh_en_drain and refresh_en_gate have different frequencies).

[0088] In an optional implementation, when the Nor Flash is in read active state, when the read operation signal is valid (read_en=1), the first standby refresh signal and the second standby refresh signal are both invalid (Refresh_en_drain=0 and Refresh_en_gate=0), the first switch K1 and the second switch K2 are both closed, and the first charge pump unit 1 and the second charge pump unit 2 are both in working state. The first charge pump unit 1 is in working state under the control of the read operation signal read_en and the first standby refresh signal Refresh_en_drain; the second charge pump unit 2 is in working state under the control of the read operation signal read_en and the second standby refresh signal Refresh_en_gate, so that the current voltage difference is greater than or equal to the second preset value, so as to ensure that the first MOSFET and the second MOSFET are both in saturation state.

[0089] When the Nor Flash is in read operation mode, read_en=1, read_vd-read_power > vth, as in Figure 6 As shown, the power supply circuit of the Nor Flash read operation module is in a state close to the standby refresh phase at this time. Figure 4 (As shown), the only difference is that the first charge pump unit 1 and the second charge pump unit 2 operate simultaneously, both controlled only by read_en=1, without the intervention of the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate. At this time, the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate are both in an invalid state, i.e., Refresh_en_drain=0 and Refresh_en_gate=0. The first charge pump unit 1, based on the read operation signal read_en, converts the Nor Flash chip power supply voltage VDD to the first voltage read_vd and outputs it to the read operation voltage generation unit 3. The second charge pump unit 2, based on the read operation signal read_en, converts the chip power supply voltage VDD to the second voltage read_vg and outputs it to the read operation voltage generation unit 3. read_power is well clamped by read_vg, read_vd-read_power >The read operation standby voltage, read_power, is stable and does not overshoot. Furthermore, since the current source Ib0 is used in the standby refresh phase to simulate the read current at the target memory array during read active, read_power is almost equal to its value in standby mode during read active.

[0090] Meanwhile, when a target memory array is selected for a read operation, the capacitive load corresponding to the read operation voltage read_power terminal of this disclosure is (N+1)*C1, where C1 is the capacitive load of a single memory array and N+1 is the total number of memory arrays in the memory array module; while the capacitive load corresponding to the read operation working voltage read_act terminal of the power supply circuit of the existing Nor Flash read operation module is 1*C1. That is, the load capacitance of the read operation of this disclosure is significantly increased. The large capacitance means that even if the read_vd response is not fast enough to replenish the charge, due to the charge sharing of the large capacitor, the charge consumed by a single WL switch will not cause the read_power to drop much. Therefore, the read_power is neither overshooted nor too low, and the read_power is very stable and will not change with the Nor Flash chip power supply voltage VDD, thus providing a guarantee for high-speed read operations.

[0091] In an alternative implementation, such as Figure 7 As shown, the power supply circuit also includes a voltage detection unit 4;

[0092] The voltage detection unit 4 is electrically connected to the first charge pump unit 1, the second charge pump unit 2, and the read operation voltage generation unit 3, respectively.

[0093] The voltage detection unit 4 is used to detect the current voltage difference between the first voltage read_vd and the read operation voltage read_power, and based on the read operation signal read_en, the first voltage read_vd, and the read operation voltage read_power, it sets both the first standby refresh signal and the second standby refresh signal to an invalid state or an effective state.

[0094] Specifically, the voltage detection unit 4 is configured to set both the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate to an invalid state (i.e., Refresh_en_drain=0, Refresh_en_gate=0) when the read operation signal is invalid (i.e., read_en=0) and the current voltage difference between the first voltage read_vd and the read operation voltage read_power is greater than or equal to the second preset value vth. Conversely, when the read operation signal is invalid (i.e., read_en=0) and the current voltage difference between the first voltage read_vd and the read operation voltage read_power is less than the second preset value, the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate are set to an active state (i.e., Refresh_en_drain=1, Refresh_en_gate=1). When the read operation signal is active (read_en=1), both the first standby refresh signal and the second standby refresh signal are set to inactive (Refresh_en_drain=0, Refresh_en_gate=0).

[0095] The power supply circuit of the Nor Flash read operation module in this embodiment detects the first voltage output by the first charge pump unit and the read operation voltage output by the read operation voltage generation unit through the voltage detection unit. It accurately controls the first standby refresh signal and the second standby refresh signal, thereby controlling the working state of the first charge pump unit and the second charge pump unit. This ensures that when the Nor Flash switches from the standby state to the read operation state at any time, the read operation voltage is stable and does not change with the Nor Flash chip power supply voltage.

[0096] In an alternative implementation, such as Figure 4 , 5 As shown in Figures 6 and 7, the power supply circuit also includes a frequency divider 5.

[0097] Frequency divider 5 is used to receive the first standby refresh signal refresh_en_drain, perform frequency division, and then output the second standby refresh signal refresh_en_gate.

[0098] For example, the input terminal of the frequency divider 5 is electrically connected to the output terminal of the voltage detection unit 4, and the output terminal of the frequency divider 5 is electrically connected to the second charge pump 2 unit. The first standby refresh signal refresh_en_drain is divided in parallel and then the second standby refresh signal refresh_en_gate is output.

[0099] When read_vd - read_power < vt, refresh_en_drain = 1. The first standby refresh signal refresh_en_drain is input into a frequency divider for frequency division operation, and then the second standby refresh signal Refresh_en_gate is output. That is, refresh_en_gate = 1 is obtained by frequency dividing refresh_en_drain = 1. For example, the first standby refresh signal refreshes read_vd 16 times (assuming a 16 - frequency division), and the second standby refresh signal only refreshes read_vg 1 time. Since the leakage voltage of read_vg is very small, power consumption during standby can be saved.

[0100] Specifically, set the frequency - division parameters according to actual needs, such as 32 - frequency division or others.

[0101] In an optional implementation manner, as Figure 4 、 5 shown in FIG. 6, each memory array is provided with a third switch and a fourth switch;

[0102] One end of the third switch is electrically connected to the memory array, and the other end of the third switch is used to receive the write - operation supply voltage write_power;

[0103] One end of the fourth switch is electrically connected to the memory array, and the other end of the third switch is electrically connected to the output end of the read - operation voltage generating unit.

[0104] Taking the memory array Array0 as an example, its third switch is S0 and its fourth switch is S0B. Taking the memory array ArrayN as an example, its third switch is SN and its fourth switch is SNB. One end of the third switch is electrically connected to the memory array, and the other end of the third switch is used to receive the write - operation supply voltage write_power; one end of the fourth switch is electrically connected to the memory array, and the other end of the fourth switch is electrically connected to the output end of the read - operation voltage generating unit and is used to receive the read - operation voltage read_power.

[0105] Embodiment 2

[0106] This embodiment provides a Nor Flash read - operation module. As Figure 8 shown, the Nor Flash read - operation module includes a read - operation signal generating circuit 6, and the read - operation signal generating circuit 6 is used to generate a read - operation signal read_en; the Nor Flash read - operation module further includes the power - supply circuit of the Nor Flash read - operation module provided in Embodiment 1.

[0107] The Nor Flash read operation module of this embodiment includes the power supply circuit of the Nor Flash read operation module in Embodiment 1. The read operation voltage read_power provided by the power supply circuit of the Nor Flash read operation module is the read operation standby voltage in standby mode and the read operation working voltage in read active mode. Since the actual difference between the read operation standby voltage and the read operation working voltage is less than or equal to a first preset value, their values ​​are basically equal in the two different states. This ensures that the read operation voltage is stable when the Nor Flash switches from standby mode to read operation mode at any time and does not change with the Nor Flash chip power supply voltage. This solves the problem in existing read operation modules where the large difference between the read operation standby voltage and the read operation working voltage makes the read operation working voltage highly sensitive to changes in the Nor Flash chip power supply voltage, thus ensuring high-speed reading of the Nor Flash read operation module.

[0108] Example 3

[0109] This embodiment provides a Nor Flash, such as Figure 9 As shown, the Nor Flash includes the NorFlash read operation module provided in Embodiment 2 and a storage array module composed of several storage arrays.

[0110] The Nor Flash in this embodiment includes the Nor Flash read operation module in embodiment 2. The read operation voltage (read_power) provided by the power supply circuit of the Nor Flash read operation module is the read operation standby voltage when in standby mode and the read operation working voltage when in readactive mode. Since the actual difference between the read operation standby voltage and the read operation working voltage is less than or equal to a first preset value, their values ​​are basically equal in the two different states. This ensures that the read operation voltage is stable when the Nor Flash switches from the standby state to the read operation state at any time and does not change with the Nor Flash chip power supply voltage. This solves the problem in existing read operation modules where the read operation working voltage is sensitive to changes in the Nor Flash chip power supply voltage due to the large difference between the read operation standby voltage and the read operation working voltage. This ensures high-speed reading of the Nor Flash read operation module and improves the stability of the Nor Flash.

[0111] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. A power supply circuit for a Nor Flash read operation module, characterized in that, The Nor Flash comprises a storage array module consisting of several storage arrays; The power supply circuit includes a first charge pump unit, a second charge pump unit, and a read operation voltage generation unit; The read operation voltage generation unit is electrically connected to the first charge pump unit, the second charge pump unit, and the storage array module, respectively. The first charge pump unit is used to convert the chip power supply voltage of the Nor Flash to a first voltage and output it to the read operation voltage generation unit based on the read operation signal and the first standby refresh signal; The second charge pump unit is used to convert the chip power supply voltage into a second voltage and output it to the read operation voltage generation unit based on the read operation signal and the second standby refresh signal; The read operation voltage generating unit is used to output a read operation voltage to the storage array module based on the first voltage and the second voltage, so as to provide the storage array module with the read operation standby voltage of the Nor Flash in standby state or the read operation working voltage in read operation state. Wherein, the actual difference between the read operation standby voltage and the read operation operating voltage is less than or equal to a first preset value; The read operation voltage generation unit includes a capacitor and a first MOS transistor, a second MOS transistor and a first switch; The output terminal of the second charge pump unit is electrically connected to the gate of the first MOS transistor and the gate of the second MOS transistor, respectively. The drain of the first MOS transistor is electrically connected to the output terminal of the first charge pump unit; The drain of the second MOS transistor is electrically connected to the output terminal of the first charge pump unit via the first switch; The source of the first MOS transistor and the source of the second MOS transistor are electrically connected to the memory array module, respectively. One end of the capacitor is electrically connected to the output terminal of the second charge pump unit, and the other end of the capacitor is grounded.

2. The power supply circuit according to claim 1, characterized in that, The width-to-length ratio of the second MOS transistor is greater than that of the first MOS transistor.

3. The power supply circuit according to claim 1, characterized in that, The read operation voltage generation unit also includes a second switch and a current source; One end of the current source is grounded, and the other end of the current source is electrically connected to one end of the second switch; The other end of the second switch is electrically connected to the source of the second MOSFET; The current value output by the current source is the same as the current value flowing through the second MOS transistor when the target memory cell in the target memory array is in the read operation state.

4. The power supply circuit according to claim 3, characterized in that, The standby state includes standby without refresh state and standby refresh state; When the Nor Flash is in a standby no-refresh state, the read operation signal is invalid, the first standby refresh signal and the second standby refresh signal are both invalid, the first switch and the second switch are both in the off state, and the current voltage difference between the first voltage and the read operation voltage is greater than or equal to the second preset value. Alternatively, when the Nor Flash is in standby refresh state, the read operation signal is invalid. If the current voltage difference between the first voltage and the read operation voltage is less than the second preset value, then both the first standby refresh signal and the second standby refresh signal are valid, the first switch and the second switch are both closed, and the first charge pump unit and the second charge pump unit are in working state, so that the current voltage difference is greater than or equal to the second preset value.

5. The power supply circuit according to claim 3, characterized in that, When the Nor Flash is in read operation mode, the read operation signal is valid, the first standby refresh signal and the second standby refresh signal are invalid, the first switch and the second switch are both closed, and the first charge pump unit and the second charge pump unit are both in working mode, so that the current voltage difference between the first voltage and the read operation voltage is greater than or equal to the second preset value.

6. The power supply circuit according to claim 1, characterized in that, The power supply circuit also includes a voltage detection unit; The voltage detection unit is electrically connected to the first charge pump unit, the second charge pump unit, and the read operation voltage generation unit, respectively. The voltage detection unit is used to detect the current voltage difference between the first voltage and the read operation voltage, and based on the read operation signal and the current voltage difference, to set both the first standby refresh signal and the second standby refresh signal to an invalid state or an effective state.

7. The power supply circuit according to claim 1, characterized in that, The power supply circuit also includes a frequency divider; The frequency divider is used to receive the first standby refresh signal, perform a frequency division operation, and then output the second standby refresh signal.

8. The power supply circuit according to claim 1, characterized in that, Each storage array is equipped with a third switch and a fourth switch; One end of the third switch is electrically connected to the storage array, and the other end of the third switch is used to receive the write operation power supply voltage; One end of the fourth switch is electrically connected to the storage array, and the other end of the fourth switch is electrically connected to the output terminal of the read operation voltage generating unit.

9. A Nor Flash read operation module, characterized in that, The Nor Flash read operation module includes a read operation signal generation circuit, which is used to generate a read operation signal. The Nor Flash read operation module further includes a power supply circuit for the Nor Flash read operation module as described in any one of claims 1-8.

10. A Nor Flash memory, characterized in that, The Nor Flash includes the Nor Flash read operation module as described in claim 9 and a storage array module consisting of several storage arrays.

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