Power supply circuit, mainboard and server

Abstract

The application discloses a power supply circuit, a mainboard and a server, and relates to the technical field of servers.In the technical scheme of the application, the power supply circuit comprises a main power supply circuit and at least one auxiliary power supply circuit, and the main power supply end is used for supplying power to a logic controller; a latch circuit is arranged in the circuit; when the latch circuit is in an activated state, the latch circuit is used for outputting a disable signal to the main power supply controller; and when the latch circuit is switched from the activated state to a deactivated state, the latch circuit is used for latching the disable signal.When the auxiliary power supply end stops supplying power, the latch circuit can be activated, so that the main power supply controller controls the main power supply end to stop supplying power; when the main power supply end stops supplying power, the main power supply end can continuously keep the state of stopping supplying power based on the disable signal latched by the latch circuit; and after the main power supply end stops supplying power, the logic controller is powered off, so that the auxiliary power supply controller controls the auxiliary power supply end to stop supplying power.Thus, full-board power-off protection of the mainboard can be realized.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to power supply circuits, motherboards, and servers. Background Technology

[0002] As server power consumption density continues to rise, many server motherboard power supply circuits need to be designed with burn-out protection. Burn-out protection refers to the circuit that cuts off power to the motherboard in case of abnormal power supply, thus preventing the motherboard from burning out due to excessive current and improving motherboard safety.

[0003] Currently, to accommodate the power supply requirements of different circuit components on the motherboard or to improve the flexibility of motherboard wiring, some motherboards include multiple independent power supply lines. However, when some power supply lines experience a power supply anomaly and temporarily stop supplying power, other power supply lines cannot be simultaneously disconnected, meaning that full-board power-off protection for the motherboard cannot be achieved, which requires improvement. Summary of the Invention

[0004] This application provides a power supply circuit, a motherboard, and a server to at least solve the problem in the related art of not being able to achieve full board power failure protection for the motherboard.

[0005] This application provides a power supply circuit, the power supply circuit comprising:

[0006] The main power supply circuit includes a main power supply controller and a main power supply terminal that are interconnected.

[0007] At least one auxiliary power supply circuit, each of the auxiliary power supply circuits including an auxiliary power supply controller and an auxiliary power supply terminal connected to each other;

[0008] A latching circuit is connected to the main power supply controller. When the latching circuit is in the active state, it is used to output a de-enable signal to the main power supply controller so that the main power supply controller controls the main power supply terminal to stop supplying power. When the latching circuit switches from the active state to the de-enable state, it is used to latch the de-enable signal so that the main power supply terminal remains in the state of not supplying power.

[0009] A logic controller is connected to the main power supply terminal, the latch circuit, and each of the auxiliary power supply controllers. The main power supply terminal is used to supply power to the logic controller. The logic controller can activate or deactivate the latch circuit, and when the logic controller is powered down, it can cause the auxiliary power supply controller to control the auxiliary power supply terminal to stop supplying power.

[0010] This application also provides a power supply control method applied to a logic controller, the method comprising:

[0011] Receive at least one auxiliary power supply signal from an auxiliary power supply controller, wherein the auxiliary power supply signal indicates whether the auxiliary power supply terminal connected to the auxiliary power supply controller has stopped supplying power;

[0012] If, based on the secondary power supply signal, it is determined that there is a secondary power supply terminal that has stopped supplying power, an activation signal is output to the latch circuit, so that the latch circuit outputs a de-enable signal to the main power supply controller. The main power supply controller is used to control the connected main power supply terminal to stop supplying power based on the de-enable signal. The main power supply terminal is used to supply power to the logic controller. When the main power supply terminal stops supplying power, the logic controller is powered down.

[0013] Stop outputting the activation signal to the latch circuit so that the latch circuit switches from the active state to the deactivated state. When the latch circuit switches from the active state to the deactivated state, the latch circuit is used to latch the de-enable signal so that the main power supply terminal remains in a state of no power supply.

[0014] This application also provides a motherboard, which includes the power supply circuit described in any of the above descriptions.

[0015] This application also provides a server, which includes a motherboard as described in any of the above descriptions.

[0016] In some embodiments of this application, when the power supply circuit includes a main power supply circuit and at least one auxiliary power supply circuit, and the main power supply terminal is used to supply power to the logic controller, a latch circuit is set in the circuit. When the latch circuit is in an active state, it outputs a de-enable signal to the main power supply controller. When the latch circuit switches from an active state to a deactivated state, it latches the de-enable signal. Thus, when the auxiliary power supply terminal stops supplying power, the main power supply controller can control the main power supply terminal to stop supplying power by activating the latch circuit. Furthermore, when the main power supply terminal stops supplying power, the main power supply terminal can be controlled to remain in a stopped-supply state based on the de-enable signal latched by the latch circuit. Simultaneously, after the main power supply terminal stops supplying power, the logic controller powers down, enabling the auxiliary power supply controller to control the auxiliary power supply terminal to stop supplying power. Therefore, after any power supply terminal stops supplying power, other power supply terminals can be linked to stop supplying power, achieving full-board power-off protection for the motherboard. Based on the above description, the power supply circuit of this application can solve the problem of some technologies failing to achieve full-board power-off protection for the motherboard. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a motherboard power supply circuit module in some technologies;

[0019] Figure 2 A schematic diagram of a motherboard power supply circuit module in some other technologies;

[0020] Figure 3 A schematic diagram of a power supply circuit provided for the first embodiment of this application;

[0021] Figure 4 A schematic diagram of a power supply circuit provided for a second embodiment of this application;

[0022] Figure 5 A schematic diagram of a power supply circuit provided for a third embodiment of this application;

[0023] Figure 6 A schematic diagram of a power supply circuit provided for the fourth embodiment of this application;

[0024] Figure 7 A schematic diagram of a motherboard module provided for some embodiments of this application;

[0025] Figure 8 A schematic diagram of a server module provided for some embodiments of this application;

[0026] Figure 9 This is a flowchart illustrating a power supply control method provided for some embodiments of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0028] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0029] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] See also Figure 1 This is a schematic diagram of a motherboard power supply circuit module in some technologies. Figure 1 In this circuit, the motherboard power supply circuit includes a first power supply line and a second power supply line. The first power supply line includes a first power supply controller and a first power supply terminal. The second power supply line includes a second power supply controller and a second power supply terminal. The first power supply controller is connected between the power supply terminal and the first power supply terminal. The second power supply controller is connected between the power supply terminal and the second power supply terminal.

[0031] The first power supply controller includes a first enable control terminal EN_1, and the second power supply controller includes a second enable control terminal EN_2. The first enable control terminal EN_1 and the second enable control terminal EN_2 are connected to an enable power supply terminal. The enable power supply terminal can provide an enable signal (such as a high level) to the first and second power supply controllers to enable the first and second power supply controllers (i.e., the working state).

[0032] Once the first power supply controller is enabled, it can control the connection between the power supply terminal and the first power supply terminal. Similarly, once the second power supply controller is enabled, it can control the connection between the power supply terminal and the second power supply terminal. The power supply terminal, through the first and second power supply terminals, can supply power to the circuit components on the motherboard. Specifically, the first and second power supply controllers can connect to different types of power supply terminals. This allows for the supply of power to different circuit components on the motherboard, thus meeting the power requirements of various components. For example, suppose the CPU on the motherboard requires a 15V operating voltage, and the memory requires a 5V operating voltage. Then, the first power supply controller can connect to the 15V power supply terminal, and the second power supply controller can connect to the 5V power supply terminal. The CPU is powered through the first power supply terminal, and the memory is powered through the second power supply terminal.

[0033] Of course, the first and second power supply controllers can also be connected to the same type of power supply terminal. Power can be supplied to circuit components located at different positions on the motherboard via the first and second power supply terminals, thus improving the flexibility of motherboard wiring. For example, both the first and second power supply controllers can be connected to a 15V power supply terminal, and the first power supply line can be placed on the first side of the motherboard, while the second power supply line can be placed on the second side. Power can be supplied to circuit components on the first side of the motherboard via the first power supply terminal, and to circuit components on the second side via the second power supply terminal. This avoids routing power lines from one side of the motherboard to the other, reducing the complexity of motherboard wiring.

[0034] Furthermore, the first power supply controller may include a main power supply detection circuit. This main power supply detection circuit may include, but is not limited to, current detection circuits, voltage detection circuits, and power detection circuits. After the power supply terminal and the first power supply terminal are connected, the main power supply detection circuit can detect whether there are any abnormalities in the power supply to the first power supply terminal, such as whether the supply current, supply voltage, or supply power is too high. If an abnormality occurs in the power supply to the first power supply terminal, the first power supply controller can disconnect the power supply terminal from the first power supply terminal to stop supplying power. This prevents circuit components on the motherboard from being burned out due to excessive current or other reasons.

[0035] Similarly, the second power supply controller may include a secondary power supply detection circuit. After the power supply terminal and the second power supply terminal are connected, the secondary power supply detection circuit can detect whether there is an abnormality in the power supply of the second power supply terminal. If there is an abnormality in the power supply of the second power supply terminal, the second power supply controller can control the power supply terminal and the second power supply terminal to disconnect, so that the second power supply terminal stops supplying power.

[0036] Furthermore, the first power supply controller includes a first state terminal PWRGD_1, and the second power supply controller includes a second state terminal PWRGD_2. The first state terminal PWRGD_1 and the second state terminal PWRGD_2 are respectively connected to a logic controller. The logic controller is connected to the baseboard management controller. The working principles of the first state terminal PWRGD_1 and the second state terminal PWRGD_2 are similar; the following explanation uses the first state terminal PWRGD_1 as an example. When power supply to the first power supply terminal stops, the first power supply controller can output an electrical signal indicating the stop of power supply through the first state terminal PWRGD_1. Based on the electrical signal from the first state terminal PWRGD_1, the logic controller sends a first log recording message to the baseboard management controller. Based on the first log recording message, the baseboard management controller can record and display log information indicating that power supply to the first power supply terminal has stopped. This facilitates timely handling of power supply anomalies by maintenance personnel.

[0037] Furthermore, the aforementioned logic controller may include, but is not limited to, a complex programmable logic device (CPLD).

[0038] exist Figure 1In the motherboard power supply circuit shown, the first and second power supply lines are independent of each other. When the power supply to one of these lines fails, although the power controller for that line can disconnect the power supply terminal from the power supply terminal, it cannot disconnect the power supply terminals of other power supply lines. This fails to meet the requirement of full-board power-off protection in practical applications. Specifically, full-board power-off protection means that when any power supply line on the motherboard experiences a power failure, all power supply lines on the motherboard must be de-energized, thus achieving system-wide power-off protection for the server.

[0039] See also Figure 2 This is a schematic diagram of a motherboard power supply circuit module in some other technologies. Figure 2 and Figure 1 They are basically similar, with the main difference being: the first power supply line also includes a switching circuit. The enable power supply terminal is grounded through the switching circuit. The first enable control terminal EN_1 of the first power supply controller is connected between the enable power supply terminal and the switching circuit. The logic controller is connected to the switching circuit and can control the switching circuit's on / off state. The first power supply terminal is connected to the logic controller. The first power supply line supplies power to the logic controller through the first power supply terminal. The second enable control terminal EN_2 of the second power supply controller is connected to the logic controller.

[0040] based on Figure 2 The motherboard power supply circuit shown has the logic controller powered on when the first power supply terminal is normally powered. The logic controller can output an enable signal to the second enable control terminal EN_2 to drive the second power supply controller into the enabled state. Simultaneously, the logic controller can output a default first control signal (e.g., a low level) to the switching circuit to keep the switching circuit off. Thus, an enable signal can be output to the first enable control terminal EN_1 via the enable power supply terminal to drive the first power supply controller into the enabled state.

[0041] When a power supply abnormality is detected at the first power supply terminal, the first power supply controller can disconnect the power supply terminal from the first power supply terminal, thereby stopping the first power supply terminal from supplying power. When the first power supply terminal stops supplying power and the second power supply terminal is in a power-on state, the logic controller is in a power-down state. The logic controller can stop outputting the enable signal to the second enable control terminal EN_2, thereby driving the second power supply controller to enter a de-enabled state (i.e., exiting the normal operation state). After entering the de-enabled state, the second power supply controller can disconnect the power supply terminal from the second power supply terminal. In this way, when the first power supply terminal stops supplying power, the second power supply terminal can be controlled to stop supplying power in conjunction with it, thereby realizing the full board power-off protection of the motherboard.

[0042] It should be noted that in a linkage control scenario where the first power supply terminal stops supplying power and the second power supply terminal is in a powered-on state, after the logic controller is powered down, it can continuously output a default first control signal (such as a low level) to the switching circuit to keep the switching circuit in an open state. While the switching circuit remains open, although the first power supply controller is in an enabled state, its internal circuitry will control the power supply terminal to disconnect from the first power supply terminal, thus stopping the first power supply terminal from supplying power. That is, in this linkage control scenario, by controlling the second power supply controller to enter a de-enabled state, the second power supply terminal can be controlled to stop supplying power; and while the first power supply controller remains enabled, its internal circuitry can control the first power supply terminal to stop supplying power.

[0043] When a power supply abnormality is detected at the second power supply terminal, the second power supply controller can disconnect the power supply terminal from the second power supply terminal and output an electrical signal indicating that the second power supply terminal has stopped supplying power through the second status terminal PWRGD_2. When the second power supply terminal stops supplying power and the first power supply terminal is in a power-on state, the logic controller is in a power-on state. Based on the electrical signal of the second status terminal PWRGD_2, after determining that the second power supply terminal has stopped supplying power, the logic controller can output a second control signal (such as a high level) to the switching circuit to turn on the switching circuit. When the switching circuit is on, the first enable control terminal EN_1 of the first power supply controller is grounded. In this case, the first enable control terminal EN_1 receives a de-enable signal (such as a low level), and the first power supply controller enters a de-enable state. After entering the de-enable state, the first power supply controller can disconnect the power supply terminal from the first power supply terminal. In this way, when the second power supply terminal stops supplying power, the first power supply terminal can be controlled to stop supplying power in conjunction with the second power supply terminal, thereby realizing full-board power-off protection of the motherboard.

[0044] However, after the first power supply terminal stops supplying power, the logic controller is in a power-down state. The logic controller continues to output a default first control signal (such as a low level) to the switching circuit, causing the switching circuit to disconnect. Consequently, the enable power supply terminal can continue to output an enable signal to the first enable control terminal EN_1, enabling the first power supply controller. After the first power supply controller enters the enabled state, it controls the power supply terminal to connect to the first power supply terminal, thus restoring power to the first power supply terminal. Conversely, after the logic controller powers on, it continues to control the switching circuit to connect, causing the first power supply controller to disconnect the power supply terminal from the first power supply terminal. Thus, the first power supply terminal repeatedly switches between power supply and power interruption, making it impossible to achieve a complete and continuous power-off of the entire motherboard.

[0045] In view of this, this application provides a power supply circuit that can solve the above problems. (See also...) Figure 3 This is a schematic diagram of a power supply circuit provided in the first embodiment of this application. Figure 3 In this system, the power supply circuit includes a latch circuit, a logic controller, a main power supply circuit, and at least one auxiliary power supply circuit. The main power supply circuit includes a main power controller and a main power supply terminal connected to each other. Each auxiliary power supply circuit includes an auxiliary power controller and an auxiliary power supply terminal connected to each other. The difference between the main and auxiliary power supply circuits is that the main power supply terminal in the main power supply circuit is connected to the logic controller and is used to supply power to the logic controller. The auxiliary power supply terminals in each of the auxiliary power supply circuits are not connected to the logic controller.

[0046] and Figure 1 and Figure 2 Similarly, the power supply circuit may also include a power supply terminal VCC1. A main power supply controller is connected between the power supply terminal VCC1 and the main power supply terminal, while a secondary power supply controller is connected between the power supply terminal VCC1 and the secondary power supply terminal. The main power supply controller controls the connection between the power supply terminal VCC1 and the main power supply terminal, supplying power to the circuit components on the motherboard through the main power supply terminal. The secondary power supply controller controls the connection between the power supply terminal VCC1 and the secondary power supply terminal, supplying power to the circuit components on the motherboard through the secondary power supply terminal. The main power supply terminal and each secondary power supply terminal can be used to supply power to different circuit components on the motherboard, thus meeting the power supply needs of different circuit components on the motherboard or improving the flexibility of motherboard wiring.

[0047] The main power supply controller may include a main power supply detection circuit (not shown), and the auxiliary power supply controller may include an auxiliary power supply detection circuit (not shown). The main power supply detection circuit is used to collect electrical signals from the main power supply terminal and, based on the collected electrical signals, controls the main power supply terminal to stop supplying power when an abnormality is detected. The auxiliary power supply detection circuit is used to collect electrical signals from the auxiliary power supply terminal and, based on the collected electrical signals, controls the auxiliary power supply terminal to stop supplying power when an abnormality is detected.

[0048] Specifically, the main power supply detection circuit and the auxiliary power supply detection circuit can include, but are not limited to, current detection circuits, voltage detection circuits, and power detection circuits. Taking the main power supply detection circuit as an example, when the main power supply detection circuit detects that the supply current at the main power supply terminal exceeds the current threshold, or the supply voltage exceeds the voltage threshold, or the supply power exceeds the power threshold, it can determine that the main power supply is abnormal and control the power supply terminal VCC1 to disconnect from the main power supply terminal. This can stop the main power supply from supplying power, preventing circuit components on the motherboard from being burned out due to excessive current. The working principle of the main power supply detection circuit is similar to that of the auxiliary power supply detection circuit, and will not be elaborated here.

[0049] Furthermore, the main power supply controller may include a main state terminal PWRGD_A, and the secondary power supply controller may include a secondary state terminal PWRGD_B. Both the main state terminal PWRGD_A and the secondary state terminal PWRGD_B are connected to the logic controller. When the main power supply stops supplying power, the main power supply controller can output an electrical signal indicating the stop supply to the logic controller through the main state terminal PWRGD_A. When the secondary power supply stops supplying power, the secondary power supply controller can output an electrical signal indicating the stop supply to the logic controller through the secondary state terminal PWRGD_B. Since the logic controller is powered down after the main power supply stops supplying power, the logic controller does not need to process the electrical signal sent by the main state terminal PWRGD_A. However, when the secondary power supply stops supplying power, if the main power supply is supplying power normally, the logic controller is in a powered-on state. In this case, the logic controller can determine whether each secondary power supply has stopped supplying power based on the electrical signals of each secondary state terminal PWRGD_B.

[0050] The latching circuit is connected to the main power supply controller. When the latching circuit is in the active state, it outputs a de-enable signal to the main power supply controller, causing the main power supply controller to stop supplying power to the main power supply terminal. When the latching circuit switches from the active state to the deactivated state, it latches the de-enable signal to keep the main power supply terminal in a state of no power supply. Latching means that after the latching circuit switches from the active state to the deactivated state, it can store and continuously output the de-enable signal output in the active state. In this way, after the latching circuit switches from the active state to the deactivated state, it can control the main power supply terminal to continuously maintain a state of no power supply.

[0051] In addition to being connected to the main power supply, the logic controller is also connected to the latch circuit and each auxiliary power supply controller. The logic controller can activate or deactivate the latch circuit, and when the logic controller is powered down, it can cause the auxiliary power supply controller to control the auxiliary power supply to stop supplying power.

[0052] Specifically, the main power supply controller includes a main enable terminal EN_A. A latch circuit is connected to the main enable terminal EN_A. The initial state of the latch circuit can be a deactivated state. When the latch circuit is in the initial deactivated state, an enable signal can be output to the main power supply controller through the main enable terminal EN_A to enable the main power supply controller. When the latch circuit switches from the deactivated state to the activated state, or from the activated state to the deactivated state, a de-enable signal can be output to the main power supply controller through the main enable terminal EN_A to de-enable the main power supply controller. When the main power supply controller is in the de-enable state, it can control the connected main power supply terminal to stop supplying power. When the main power supply controller is in the enabled state, if the main power supply detection circuit in the main power supply controller detects a power supply abnormality at the connected main power supply terminal, it can control the connected main power supply terminal to stop supplying power. Conversely, if the main power supply detection circuit detects no power supply abnormality at the connected main power supply terminal, it can control the connected main power supply terminal to supply power normally.

[0053] Each secondary power supply controller includes a secondary enable terminal EN_B. The logic controller is connected to each secondary enable terminal EN_B. When the logic controller is powered on, it can send enable signals to each secondary power supply controller via the secondary enable terminal EN_B, enabling the secondary power supply controllers. When the logic controller is powered off, it stops sending enable signals to the secondary power supply controllers, and the secondary power supply controllers enter a de-enabled state. Similar to the main power supply controller, when a secondary power supply controller enters the de-enabled state, it can control the connected secondary power supply terminals to stop supplying power. When a secondary power supply controller enters the enabled state, if the secondary power supply detection circuit in the secondary power supply controller detects a power supply abnormality at the connected secondary power supply terminal, it can control the connected secondary power supply terminal to stop supplying power. Conversely, if the secondary power supply detection circuit detects no power supply abnormality at the connected secondary power supply terminal, it can control the connected secondary power supply terminal to supply power normally.

[0054] based on Figure 3 The power supply circuit shown operates with the logic controller powered on when the main power supply is functioning normally. The logic controller can input enable signals to each secondary power supply controller via the secondary enable terminal EN_B, enabling each controller. Simultaneously, the logic controller can determine whether any secondary power supply terminals are shut down based on the electrical signals at the secondary status terminals PWRGD_B. If no such terminal is shut down, the logic controller can withhold the activation signal from the latch circuit, keeping it in its initial deactivated state, thus enabling the main power supply controller. At this point, both the main power supply and each secondary power supply terminal are in a normal power supply state.

[0055] When the main power supply detection circuit in the main power supply controller detects an abnormal power supply at the main power supply terminal and controls the main power supply terminal to stop supplying power, the logic controller is in a powered-down state. The logic controller stops sending enable signals to each secondary power supply controller, and each secondary power supply controller can control the corresponding secondary power supply terminal to stop supplying power. In this way, when the main power supply terminal stops supplying power, through linkage control, the secondary power supply terminals can also stop supplying power, thereby achieving the full-board power-off protection of the main board.

[0056] When the secondary power supply detection circuit in one or more secondary power supply controllers detects an abnormal power supply at the connected secondary power supply terminal and controls the connected secondary power supply terminal to stop supplying power, since the main power supply terminal is still in a normal power supply state, the logic controller is in a powered-on state. Based on the electrical signal of the secondary status terminal PWRGD_B, after the logic controller determines the secondary power supply terminal where the power supply stops, it can perform the following two operations: First, output an activation signal (such as a high level) to the latch circuit to make the latch circuit switch from the initial deactivated state to the activated state. After the latch circuit is converted to the activated state, a de-enable signal can be output to the main power supply controller to make the main power supply controller control the main power supply terminal to stop supplying power. Second, find the secondary power supply controller connected to the secondary power supply terminal in the powered-on state and send a de-enable signal to the corresponding secondary power supply controller to make the corresponding secondary power supply controller control the connected secondary power supply terminal to stop supplying power.

[0057] For example, assume that the power supply circuit includes secondary power supply terminals P1 to P4. After the logic controller determines that the secondary power supply terminals P1 and P2 stop supplying power based on the electrical signal of the secondary status terminal PWRGD_B, it can output an activation signal to the latch circuit to control the main power supply terminal to stop supplying power. At the same time, it can also send de-enable signals to the secondary power supply controllers connected to the power supply terminals P3 and P4 to make the corresponding secondary power supply controllers control the power supply terminals P3 and P4 to stop supplying power. In this way, when any secondary power supply terminal stops supplying power, through linkage control, the main power supply terminal and other secondary power supply terminals in the powered-on state can also stop supplying power, thereby achieving the full-board power-off protection of the main board.

[0058] After the secondary power supply terminal stops supplying power and the main power supply terminal is controlled to stop supplying power through linkage, the logic controller is in a powered-down state. At this time, the logic controller stops outputting an activation signal (such as a high level) to the latch circuit. The latch circuit switches from the activated state to the deactivated state. Since the de-enable signal for the main power supply controller can be latched when the latch circuit switches from the activated state to the deactivated state, after the logic controller is powered down, even if the logic controller stops outputting an activation signal to the latch circuit, the latch circuit can still control the main power supply terminal to continuously maintain the state of stopping supplying power, thus avoiding Figure 2 the problem that the main power supply terminal in

[0059] In summary, in some embodiments of this application, when the power supply circuit includes a main power supply circuit and at least one auxiliary power supply circuit, and the main power supply terminal is used to supply power to the logic controller, a latch circuit is provided in the circuit. When the latch circuit is in an active state, it outputs a de-enable signal to the main power supply controller. When the latch circuit switches from an active state to a deactivated state, it latches the de-enable signal. Thus, when the auxiliary power supply terminal stops supplying power, the main power supply controller can control the main power supply terminal to stop supplying power by activating the latch circuit. Furthermore, when the main power supply terminal stops supplying power, the main power supply terminal can be controlled to remain in a stopped-supply state based on the de-enable signal latched by the latch circuit. Simultaneously, after the main power supply terminal stops supplying power, the logic controller powers down, enabling the auxiliary power supply controller to control the auxiliary power supply terminal to stop supplying power. Therefore, after any power supply terminal stops supplying power, other power supply terminals can be linked to stop supplying power, achieving full-board power-off protection for the motherboard. Based on the above description, the power supply circuit of this application can solve the problem of some technologies failing to achieve full-board power-off protection for the motherboard.

[0060] See also Figure 4 This is a schematic diagram of a power supply circuit provided in the second embodiment of this application. Figure 4 In this circuit, the latch circuit includes a latch and an enable circuit. The enable circuit is connected between the latch and the main power supply controller. The logic controller connects to the latch and can activate or deactivate it. When the latch is active, it outputs a drive signal to the enable circuit, which then controls the enable circuit to output a de-enable signal to the main power supply controller. When the latch switches from active to deactivated, it latches the drive signal to control the enable circuit to continuously output a de-enable signal to the main power supply controller.

[0061] Specifically, based on Figure 4 The power supply circuit shown has the following characteristics: when the power supply circuit starts working, the logic controller is in a default off state. At this time, the logic controller cannot output an activation signal to the latch, nor can it output an enable signal to any of the auxiliary power supply controllers. Thus, on the one hand, each auxiliary power supply controller can control the connected auxiliary power supply terminals to pause power supply; on the other hand, the initial state of the latch remains deactivated, and it outputs a non-drive signal (e.g., low level) to the enable circuit. In response to receiving the non-drive signal, the enable circuit outputs an enable signal to the main power supply controller, enabling the main power supply controller to enter the enabled state and control the main power supply terminal to supply power.

[0062] After the main power supply is powered on normally, the logic controller is powered on and starts normal operation. At this time, the logic controller can output enable signals to each auxiliary power supply controller, enabling each auxiliary power supply controller to control the connected auxiliary power supply to supply power normally. In this way, both the main power supply and each auxiliary power supply can start supplying power. During the power supply process of the main power supply and each auxiliary power supply, the main power supply detection circuit in the main power supply controller can detect whether the power supply of the main power supply is abnormal in real time, and control the main power supply to stop supplying power when the power supply of the main power supply is abnormal. Similarly, the auxiliary power supply detection circuits in each auxiliary power supply controller can detect whether the power supply of the connected auxiliary power supply is abnormal in real time, and control the auxiliary power supply to stop supplying power when the auxiliary power supply is abnormal.

[0063] The logic controller can detect the presence of a power supply terminal that has stopped supplying power through the main status terminal PWRGD_A of the main power supply controller and the secondary status terminals PWRGD_B of each secondary power supply controller. Specifically, when one or more secondary power supply terminals stop supplying power while the main power supply terminal is supplying power normally, the logic controller sends an activation signal (e.g., a high level) to the driver to trigger the driver to output a drive signal to the enable circuit. In response to receiving the drive signal, the enable circuit can output a de-enable signal to the main power supply controller, causing the main power supply controller to control the main power supply terminal to stop supplying power. After the main power supply terminal stops supplying power, the logic controller is in a power-down state and stops outputting activation signals to the latch, which then switches from an active state to a deactivated state. Since the latch can latch the drive signal when switching from an active state to a deactivated state, even if the logic controller stops outputting activation signals to the latch, the latch can still continuously output drive signals to the enable circuit. Thus, the enable circuit can continuously output a de-enable signal to the main power supply controller, thereby keeping the main power supply control terminal in a state of continuous power supply interruption.

[0064] When a driver switches from a deactivated state to an activated state and then back to a deactivated state, the latch function ensures that the main power supply remains unpowered, thus keeping the logic controller powered down and consequently, all secondary power supplies remain unpowered. In other words, once the main and secondary power supplies are de-energized, the latch function prevents the logic controller from re-energizing them. This ensures the reliability of the motherboard's power-down operation and prevents the motherboard from being restarted.

[0065] Furthermore, to resolve power supply abnormalities in the power supply circuit, maintenance personnel can manually reconnect or restart the driver's power supply to restore it to its initial state (i.e., deactivated state). After the driver is restored to its initial state, it can output a non-drive signal (such as a low level) to the enable circuit. In response to receiving the non-drive signal, the enable circuit outputs an enable signal to the main power controller, enabling the main power controller to enter the enabled state and control the main power supply. In this way, the motherboard's power supply can be restarted.

[0066] In the above embodiments, the latching circuit includes a latch and an enable circuit, and latches the de-enable signal of the main power supply controller by combining the latch and the enable circuit. In this way, on the one hand, the latch is a readily available conventional electrical component, which improves the feasibility of the latching circuit. On the other hand, the actual state of the enable signal can be adapted through reasonable enable circuit design, improving the flexibility of circuit design. For example, suppose the de-enable signal is high. If only a latch is used to latch the de-enable signal of the main power supply controller, the latch needs to be able to output a high level when active. However, in actual circuit design, the latch may only output a low level when active. In this case, latching the de-enable signal cannot be completed using only a latch. But if a combination of latch and enable circuit is used, the enable circuit can output a high level (i.e., the de-enable signal of the main power supply controller) when it receives a low level (i.e., a drive signal) through reasonable enable circuit design. In this way, the electrical signal output by the latch circuit to the main power supply controller can be matched with the actual enable signal, thus improving the flexibility of circuit design.

[0067] Continue reading Figure 4 In some embodiments, the enable signal of the main power supply controller is high, and the de-enable signal is low. The enable circuit includes a switching circuit and a first power supply terminal VCC2. A latch is connected to the switching circuit, which is connected between the first power supply terminal and ground. The main enable terminal EN_A of the main power supply controller is connected between the switching circuit and the first power supply terminal VCC2. The drive signal output by the latch is used to control the switching circuit to turn on, so that the enable circuit outputs a de-enable signal to the main enable terminal.

[0068] Specifically, the first power supply terminal VCC2 can output a high level. When the latch is in its initial inactive state, it can output a non-drive signal to the switching circuit. Upon receiving the non-drive signal, the switching circuit disconnects. At this time, the first power supply terminal VCC2 outputs a high level to the main enable terminal EN_A of the main power supply controller, driving the main power supply controller into the enabled state. When the logic controller needs to control the main power supply terminal to stop supplying power, it can output an activation signal to the latch. After the latch is in the activated state, it can output a drive signal to the switching circuit. Upon receiving the drive signal, the switching circuit turns on. The main enable terminal EN_A of the main power supply controller is grounded through the switching circuit, and the electrical signal of the main enable terminal EN_A becomes low, which is equivalent to the latch circuit outputting a low level to the main enable terminal EN_A. At this time, the main power supply controller can control the main power supply terminal to stop supplying power.

[0069] In the above embodiment, the enabling circuit includes a switching circuit, and based on the electrical signal output by the latch, it can control the switching circuit to be on or off. When the switching circuit is off, the main enable terminal EN_A of the main power supply controller can be connected to the first power supply terminal VCC2, and when the switching circuit is on, the main enable terminal EN_A can be grounded. Thus, under the control of the latch, different level signals can be output to the main enable terminal EN_A, thereby controlling the main power supply controller to be in different states. This switching circuit design greatly simplifies circuit design, and the circuit components used are of lower cost, reducing circuit costs.

[0070] Continue reading Figure 4 In some embodiments, the switching circuit includes a switch control terminal P1, which is connected to a latch. Specifically, the switching circuit may include a transistor, such as a bipolar junction transistor (BJT) or a field-effect transistor (FET). When the switching circuit includes a BJT, the base of the BJT is the switch control terminal P1. The driver controls the BJT to turn on or off by controlling the magnitude of its base current (i.e., using a specified current as a drive signal). When the switching circuit includes a FET, the gate of the FET is the switch control terminal P1. The driver controls the FET to turn on or off by controlling the magnitude of its gate voltage (i.e., using a specified voltage as a drive signal).

[0071] Furthermore, the switching circuit may also include a first terminal P2 and a second terminal P3. The first terminal P2 is connected to the first power supply terminal VCC2, and the second terminal P3 is grounded. When the latch outputs a drive signal to the switching circuit, the first terminal P2 and the second terminal P3 are turned on. When the latch outputs a non-drive signal to the switching circuit, the first terminal P2 and the second terminal P3 are turned off. Specifically, when the switching circuit includes a bipolar junction transistor (BJT), one of the collector and emitter of the BJT can serve as the first terminal P2, and the other of the collector and emitter can serve as the second terminal P3. When the switching circuit includes a field-effect transistor (FET), one of the source and drain of the FET can serve as the first terminal P2, and the other of the source and drain can serve as the second terminal P3.

[0072] In this embodiment, the switching circuit includes a bipolar junction transistor (BJT). When the latch is in the active state, it outputs a high-level signal to the switch control terminal as a drive signal to control the switching circuit to turn on. When the latch is in the initial inactive state, it outputs a low-level signal to the switch control terminal as a non-drive signal to control the switching circuit to turn off.

[0073] In the above embodiments, since the switching circuit includes transistors, and the switching speed of transistors is relatively fast, the main power supply can be stopped in a timely manner when the power supply at the secondary power supply terminal is abnormal, thus improving the safety of the motherboard. Furthermore, the low power consumption of transistors reduces the overall power consumption of the motherboard, and the small size of transistors reduces the size of the power supply circuit, thereby reducing the size of the motherboard.

[0074] Continue reading Figure 4 In some embodiments, the enable circuit further includes a pull-up resistor R1, one end of which is grounded, and the other end is connected between the main enable terminal EN_A and the first power supply terminal VCC2. When the switch circuit is not turned on, the pull-up resistor R1 is used to control the enable circuit to output an enable signal to the main enable terminal EN_A. Specifically, when the switch circuit is turned off, the first power supply terminal VCC2 is grounded through the pull-up resistor R1, and the voltage of the main enable terminal EN_A is the voltage divided by the pull-up resistor R1. The voltage divided by the pull-up resistor R1 is positively correlated with the resistance value of the pull-up resistor R1. Therefore, by setting a reasonable resistance value for the pull-up resistor R1, the voltage divided by the pull-up resistor R1 can be kept within the voltage range corresponding to the high level, so that when the switch circuit is turned off, the voltage of the main enable terminal EN_A is at a high level.

[0075] In the above embodiment, a pull-up resistor R1 is provided in the enable circuit, with one end of the pull-up resistor R1 grounded and the other end connected between the main enable terminal EN_A and the first power supply terminal VCC2. This allows the voltage of the main enable terminal EN_A to be pulled high when the switching circuit is off, avoiding the problem of unstable voltage at the main enable terminal EN_A.

[0076] Continue reading Figure 4 In some embodiments, when a high level is used as the drive signal, the latch circuit further includes a second power supply terminal VCC3. The latch includes an input terminal P4, an enable control terminal P5, and an output terminal P6. The input terminal P4 is connected to the second power supply terminal VCC3, the enable control terminal P5 is connected to the logic controller, and the output terminal P6 is connected to the switching circuit. The logic controller activates or deactivates the latch through the enable control terminal P5. When the latch is activated, it uses the voltage signal provided by the second power supply terminal VCC3 as the drive signal and outputs the drive signal through the output terminal P6.

[0077] Specifically, when the latch is active, the voltage at output terminal P6 follows the voltage at input terminal P4 in real time; that is, the voltage at output terminal P6 is the same as the voltage at input terminal P4. When the latch switches from active to inactive, output terminal P6 latches the voltage at input terminal P4. In this case, changes in the voltage at input terminal P4 will not affect the voltage at output terminal P6. For example, if the voltage at input terminal P4 is high before the latch switches to inactive, then after the latch switches to inactive, output terminal P6 can latch the high level of input terminal P4 and continuously output a high level. That is, after the latch switches to inactive, if the voltage at input terminal P4 becomes low, the voltage at output terminal P6 will not follow the change in the voltage at input terminal P4. In other words, after the latch switches to inactive, if the voltage at input terminal P4 becomes low, output terminal P6 will continuously output a high level. At this time, the voltage at input terminal P4 can be different from the voltage at output terminal P6.

[0078] In the above embodiment, after connecting the input terminal P6 of the latch to the second power supply terminal VCC3, based on the operating characteristics of the latch, it can be ensured that the output terminal P6 of the latch outputs a high level as a drive signal to the switching circuit when the latch is in the active state. At the same time, when the latch switches from the active state to the inactive state, it can be ensured that the voltage of the output terminal P6 is not affected by the voltage of the input terminal P4, and it continues to output a high level as a drive signal to the switching circuit, thereby improving the reliability of the power supply circuit.

[0079] Continue reading Figure 4 In some embodiments, the enable circuit further includes a pull-down resistor R2, one end of which is grounded and the other end is connected between the latch and the switch control terminal P1. When the latch is not activated, the pull-down resistor R2 is used to pull down the voltage of the switch control terminal P1 so that the switch circuit remains in the off state.

[0080] Specifically, when the latch is not activated, the voltage at output terminal P6 does not follow the voltage at input terminal P4 in real time; that is, the voltage at output terminal P6 is unstable. In this case, assuming no pull-down resistor R2 is set, output terminal P6 may output a drive signal (i.e., a high level) to the switching circuit, which risks mis-energizing the switching circuit. To reduce this risk, a pull-down resistor R2 can be set, and the switch control terminal P1 can be grounded through the pull-down resistor R2. In this way, the voltage at the switch control terminal P1 can be pulled low, reducing the risk of mis-energizing the switching circuit.

[0081] In the above embodiment, a pull-down resistor R2 is provided, with one end of R2 grounded and the other end connected between the latch and the switch control terminal P1. This allows the voltage of the switch control terminal P1 to be pulled low when the latch is not activated, reducing the risk of the switch circuit being mistakenly turned on.

[0082] Continue reading Figure 4 In some embodiments, the power supply circuit further includes a third power supply terminal VCC4, which supplies power to the main power supply controller and the auxiliary power supply controller. The third power supply terminal is independent of the main power supply terminal and the auxiliary power supply terminal of the power supply circuit. The latch includes a power supply terminal P7, which is connected to the third power supply terminal VCC4. The third power supply terminal VCC4 supplies power to the latch through the power supply terminal P7.

[0083] Specifically, since the third power supply terminal VCC4 is independent of the main power supply terminal and the auxiliary power supply terminal, it can continue to supply power even after the main and auxiliary power supply terminals stop supplying power. Thus, the latch, main power supply controller, and each auxiliary power supply controller can continue to operate normally after the main and auxiliary power supply terminals stop supplying power. After the latch returns to its initial inactive state, it can send an enable signal to the main power supply terminal. In response to receiving the enable signal, the main power supply controller can control the main power supply terminal to resume power supply, and each auxiliary power supply controller can control its connected auxiliary power supply terminal to resume power supply.

[0084] In the above embodiments, since the power supply terminal of the latch is the same as the power supply terminals of the main power supply controller and the auxiliary power supply controller, and the third power supply terminal VCC4 that supplies power to the main and auxiliary power supply controllers is an independent power supply terminal from the main power supply terminal and the auxiliary power supply terminal of the power supply circuit, the third power supply terminal VCC4 can continue to maintain a power supply state after the main power supply terminal and the auxiliary power supply terminal stop supplying power. This allows the latch, the main power supply controller, and each auxiliary power supply controller to continue to maintain a normal working state. Furthermore, after the latch returns to its initial inactive state, the entire power supply circuit can be re-triggered to restore power supply, thus avoiding the problem of not being able to restore power supply after the power supply circuit stops supplying power.

[0085] Continue reading Figure 4 In some embodiments, the power supply circuit of this application may further include a baseboard management controller. The baseboard management controller is connected to the logic controller. After the baseboard management controller detects that the logic controller is powered down, it determines that the power supply terminal has stopped supplying power. At this time, the baseboard management controller can display prompt information indicating power supply abnormality in the operation log or human-machine interface to facilitate maintenance personnel in locating power supply abnormality problems.

[0086] See also Figure 5 This is a schematic diagram of a power supply circuit provided in the third embodiment of this application. Figure 5 and Figure 4 They are basically similar, with the main differences being: Figure 5 The logic controller in the main power supply is not directly connected to the secondary enable terminal EN_B of each secondary power supply controller. Instead, the main status terminal PWRGD_A of the main power supply controller is connected to each secondary enable terminal EN_B. When the main power supply stops supplying power, the main power supply controller also outputs a de-enable signal to the secondary enable terminal EN_B through the main status terminal PWRGD_A, so that the secondary power supply controller controls the secondary power supply to stop supplying power.

[0087] Specifically, in Figure 5 In the illustrated embodiment, when the main power supply is stopped, the electrical signal output by the main status terminal PWRGD_A indicating that the main power supply has stopped supplying power is the same as the de-enable signal of each secondary power supply controller. For example, when the main status terminal PWRGD_A outputs a low level, it indicates that the main power supply has stopped supplying power, and at the same time, the de-enable signal of each secondary power supply controller is also low. In this case, the main status terminal PWRGD_A can be directly connected to each secondary enable terminal EN_B. When the main status terminal PWRGD_A outputs the electrical signal indicating that the power supply has stopped to the logic controller, this electrical signal can also serve as the de-enable signal of each secondary power supply controller, without having to wait for the logic controller to power down before sending the de-enable signal to each secondary power supply controller.

[0088] exist Figure 5In the illustrated embodiment, on the one hand, the main status terminal PWRGD_A is directly connected to each of the secondary enable terminals EN_B, and the logic controller is not connected to the secondary enable terminals EN_B of each secondary power supply controller. This reduces the number of pins used by the logic controller. On the other hand, by directly outputting de-enable signals to each secondary power supply controller through the main status terminal PWRGD_A, the power-off speed of the secondary power supply terminals can be improved, thereby enhancing the safety of the motherboard. For example, some logic controllers may contain energy storage devices such as capacitors. After power to the logic controller is stopped, the electrical energy stored in these storage devices can power the logic controller to continue operating for a period of time. That is, after the main power supply terminal stops supplying power, the logic controller may continue to operate for a period of time. During this period of continued operation, since the logic controller is not powered down, it can still output enable signals to each secondary power supply controller, allowing each secondary power supply terminal to continue supplying power for a period of time, thereby increasing the risk of burnt-out circuit components on the motherboard. However, Figure 5 In the illustrated embodiment, since the main status terminal PWRGD_A is directly connected to each of the secondary enable terminals EN_B, when the main power supply terminal stops supplying power, even if the logic controller is still running, the main status terminal PWRGD_A can be used to synchronously control each secondary power supply terminal to stop supplying power, thereby reducing the risk of circuit components on the motherboard being burned out.

[0089] See also Figure 6 This is a schematic diagram of a power supply circuit provided in the fourth embodiment of this application. Figure 6 and Figure 5 They are basically similar, with the main differences being: Figure 6 In this configuration, the baseboard management controller is connected between the power supply terminal VCC1 and the main power supply controller, as well as between the power supply terminal VCC1 and each of the auxiliary power supply controllers. The logic controller is used to control the connection and disconnection between the power supply terminal and the main power supply controller, and between the power supply terminal and the auxiliary power supply controllers, through the baseboard management controller.

[0090] Specifically, the baseboard management controller can control the connection and disconnection between the power supply terminal VCC1 and the main power supply controller, as well as between the power supply terminal VCC1 and each of the auxiliary power supply controllers. Based on the electrical signal of the auxiliary status terminal PWRGD_B, when the logic controller determines that a auxiliary power supply terminal is experiencing a power outage (i.e., a power supply abnormality), it can send a power outage message to the baseboard management controller. In response to receiving the power outage message, the baseboard management controller can disconnect the power supply terminal VCC1 from the main power supply controller, and it can also disconnect the power supply terminal VCC1 from each of the auxiliary power supply controllers. This effectively disconnects the power supply terminal VCC1 from the main power supply terminal and each of the auxiliary power supply terminals, rendering them unable to supply power and improving the reliability of the motherboard during power outages.

[0091] Correspondingly, after resolving the motherboard power supply anomaly, a connection command can be sent to the baseboard management controller via its human-machine interface. Upon receiving the connection command, the baseboard management controller can restore the connection between the power supply terminal VCC1 and the main power supply controller, as well as between the power supply terminal VCC1 and each auxiliary power supply controller. Then, by restarting the latches, the latches can be restored to their initial inactive state, thereby restoring power to the power supply circuit.

[0092] exist Figure 6 In the embodiment shown, after a power supply failure at the secondary power supply terminal, the baseboard management controller can control the power supply terminal VCC1 to disconnect from the main power supply controller, and control the power supply terminal VCC1 to disconnect from each secondary power supply controller, so that the main power supply terminal and each secondary power supply terminal are not capable of supplying power, thereby improving the reliability of the motherboard power failure.

[0093] This application also provides a motherboard. (See also...) Figure 7 This is a schematic diagram of a motherboard module provided in some embodiments of this application. Figure 7 In the middle, the motherboard includes Figures 3-6 Any of the power supply circuits in it.

[0094] This application also provides a server. (See also...) Figure 8 The diagram below shows a module of a server provided in some embodiments of this application. Figure 8 In the middle, the server includes Figure 7 The motherboard in the middle.

[0095] Because the motherboard and server in this application include Figures 3-6 It can be used as any power supply circuit in the circuit, and therefore has the same beneficial effects as the power supply circuit, which will not be elaborated here.

[0096] Corresponding to the power supply circuit of this application, this application also provides a power supply control method. The power supply control method can be applied to the logic controller in the power supply circuit of this application. (See also...) Figure 9 This is a flowchart illustrating a power supply control method provided in some embodiments of this application. Figure 9 The power supply control method includes the following steps:

[0097] Step S901: Receive a secondary power supply signal sent by at least one secondary power supply controller. The secondary power supply signal indicates whether the secondary power supply terminal connected to the secondary power supply controller has stopped supplying power.

[0098] In step S902, if it is determined that there is a secondary power supply terminal that has stopped supplying power based on the secondary power supply signal, an activation signal is output to the latch circuit so that the latch circuit outputs a de-enable signal to the main power supply controller. The main power supply controller is used to control the connected main power supply terminal to stop supplying power based on the de-enable signal. The main power supply terminal is used to supply power to the logic controller. When the main power supply terminal stops supplying power, the logic controller is powered down.

[0099] Step S903: Stop outputting the activation signal to the latch circuit so that the latch circuit switches from the active state to the deactivated state. When the latch circuit switches from the active state to the deactivated state, the latch circuit is used to latch the de-enable signal so that the main power supply terminal remains in a state of no power supply.

[0100] In some embodiments, the power supply control method further includes:

[0101] When powered on, an enable signal is sent to each auxiliary power supply controller so that the auxiliary power supply controller controls the power supply of the connected auxiliary power supply terminal.

[0102] When the power is off, stop sending enable signals to each auxiliary power supply controller so that the auxiliary power supply controller can control the connected auxiliary power supply terminals to stop supplying power.

[0103] In some embodiments, the power supply control method further includes:

[0104] If, based on the secondary power supply signal, it is determined that there is a first secondary power supply terminal that has stopped supplying power and a second secondary power supply terminal that is in a power supply state, then an enable signal is sent to the secondary power supply controller connected to the second secondary power supply terminal so that the corresponding secondary power supply controller controls the second secondary power supply terminal to stop supplying power.

[0105] In some embodiments, the power supply control method further includes:

[0106] If, based on the secondary power supply signal, it is determined that at least some secondary power supply terminals have stopped supplying power, an interrupt signal is sent to the board management controller, wherein, in response to receiving the interrupt signal, the board management controller performs the following operations:

[0107] Disconnect the power supply terminal from the main power supply terminal;

[0108] Disconnect the power supply terminal from the auxiliary power supply terminal.

[0109] In some embodiments, the power supply control method further includes:

[0110] If, based on the secondary power supply signal, it is determined that at least some secondary power supply terminals have stopped supplying power, a log recording message is sent to the baseboard management controller so that the baseboard management controller records a power supply anomaly log.

[0111] For the specific principles of the power supply control method, please refer to the above description of the power supply circuit, which will not be repeated here. The power supply control method of this application has the same characteristics as... Figures 3-6 The same beneficial effects are found in any of the power supply circuits, which will not be elaborated here.

[0112] The power supply circuit, motherboard, and server provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A power supply circuit, characterized in that, include: The main power supply circuit includes a main power supply controller and a main power supply terminal that are interconnected. At least one auxiliary power supply circuit, each of the auxiliary power supply circuits including an auxiliary power supply controller and an auxiliary power supply terminal connected to each other; A latching circuit is connected to the main power supply controller. When the latching circuit is in the active state, it is used to output a de-enable signal to the main power supply controller so that the main power supply controller controls the main power supply terminal to stop supplying power. When the latching circuit switches from the active state to the de-enable state, it is used to latch the de-enable signal so that the main power supply terminal remains in the state of not supplying power. A logic controller is connected to the main power supply terminal, the latch circuit, and each of the auxiliary power supply controllers. The main power supply terminal is used to supply power to the logic controller. The logic controller can activate or deactivate the latch circuit, and when the logic controller is powered down, it can cause the auxiliary power supply controller to control the auxiliary power supply terminal to stop supplying power.

2. The power supply circuit according to claim 1, characterized in that, The latching circuit includes a latch and an enable circuit. The enable circuit is connected between the latch and the main power supply controller. The logic controller is used to connect to the latch and can activate or deactivate the latch. When the latch is in the active state, it is used to output a drive signal to the enable circuit to control the enable circuit to output a de-enable signal to the main power supply controller. When the latch switches from the active state to the deactivated state, it is used to latch the drive signal to control the enable circuit to continuously output a de-enable signal to the main power supply controller.

3. The power supply circuit according to claim 2, characterized in that, The enabling circuit includes a switching circuit and a first power supply terminal. The latch is connected to the switching circuit, which is connected between the first power supply terminal and ground. The main power supply controller includes a main enabling terminal, which is connected between the switching circuit and the first power supply terminal. The drive signal output by the latch is used to control the switching circuit to turn on, so that the enable circuit outputs a de-enable signal to the main enable terminal.

4. The power supply circuit according to claim 3, characterized in that, The enabling circuit further includes a pull-up resistor, one end of which is grounded and the other end is connected between the main enabling terminal and the first power supply terminal. When the switching circuit is not turned on, the pull-up resistor is used to control the enabling circuit to output an enabling signal to the main enabling terminal.

5. The power supply circuit according to claim 3, characterized in that, The switching circuit includes a switch control terminal, which is connected to the latch. When the latch is in an active state, the latch outputs a high level to the switch control terminal as the drive signal. Furthermore, the enabling circuit also includes a pull-down resistor, one end of which is grounded and the other end is connected between the latch and the switch control terminal. When the latch is not activated, the pull-down resistor is used to pull down the voltage of the switch control terminal so that the switch circuit remains in the off state.

6. The power supply circuit according to claim 3, characterized in that, The latch circuit further includes a second power supply terminal. The latch includes an input terminal, an enable control terminal, and an output terminal. The input terminal is connected to the second power supply terminal, the enable control terminal is connected to the logic controller, and the output terminal is connected to the switching circuit. The logic controller activates or deactivates the latch via the enable control terminal. When the latch is activated, it uses the voltage signal provided by the second power supply terminal as the drive signal and outputs the drive signal via the output terminal.

7. The power supply circuit according to claim 2, characterized in that, The power supply circuit also includes a third power supply terminal, which is used to supply power to the main power supply controller and the auxiliary power supply controller, and the third power supply terminal is an independent power supply terminal from the main power supply terminal and the auxiliary power supply terminal of the power supply circuit. The latch includes a power supply terminal, which is connected to the third power supply terminal, and the third power supply terminal supplies power to the latch through the power supply terminal.

8. The power supply circuit according to claim 1, characterized in that, The main power supply controller includes a main state terminal, which is connected to the logic controller. When the main power supply terminal stops supplying power, the main power supply controller outputs an electrical signal indicating that the power supply has stopped to the logic controller through the main state terminal.

9. The power supply circuit according to claim 8, characterized in that, The main power supply controller also includes a main power supply detection circuit, which is used to collect electrical signals from the main power supply terminal and, based on the collected electrical signals, control the main power supply terminal to stop supplying power when it determines that the power supply of the main power supply terminal is abnormal.

10. The power supply circuit according to claim 8, characterized in that, The secondary power supply controller includes a secondary enable terminal, which is connected to the primary status terminal; When the main power supply terminal stops supplying power, the main power supply controller also outputs a de-enable signal to the secondary enable terminal through the main status terminal, so that the secondary power supply controller controls the secondary power supply terminal to stop supplying power.

11. The power supply circuit according to claim 1, characterized in that, The secondary power supply controller includes a secondary state terminal, which is connected to the logic controller. When the secondary power supply terminal stops supplying power, the secondary power supply controller outputs an electrical signal indicating the cessation of power supply to the logic controller through the secondary state terminal.

12. The power supply circuit according to claim 11, characterized in that, The auxiliary power supply controller also includes an auxiliary power supply detection circuit, which is used to collect electrical signals from the auxiliary power supply terminal and, based on the collected electrical signals, control the auxiliary power supply terminal to stop supplying power when it determines that the power supply of the auxiliary power supply terminal is abnormal.

13. The power supply circuit according to claim 1, characterized in that, The power supply circuit also includes a power supply terminal and a baseboard management controller. The main power supply controller is connected between the power supply terminal and the main power supply terminal, and the auxiliary power supply controller is connected between the power supply terminal and the auxiliary power supply terminal. The baseboard management controller is connected to the logic controller. The logic controller is used to control the connection and disconnection between the power supply terminal and the main power supply controller, and to control the connection and disconnection between the power supply terminal and the auxiliary power supply controller, through the baseboard management controller.

14. A power supply control method, characterized in that, Applied to a logic controller, the method includes: Receive at least one auxiliary power supply signal from an auxiliary power supply controller, wherein the auxiliary power supply signal indicates whether the auxiliary power supply terminal connected to the auxiliary power supply controller has stopped supplying power; If, based on the secondary power supply signal, it is determined that there is a secondary power supply terminal that has stopped supplying power, an activation signal is output to the latch circuit, so that the latch circuit outputs a de-enable signal to the main power supply controller. The main power supply controller is used to control the connected main power supply terminal to stop supplying power based on the de-enable signal. The main power supply terminal is used to supply power to the logic controller. When the main power supply terminal stops supplying power, the logic controller is powered down. Stop outputting the activation signal to the latch circuit so that the latch circuit switches from the active state to the deactivated state. When the latch circuit switches from the active state to the deactivated state, the latch circuit is used to latch the de-enable signal so that the main power supply terminal remains in a state of no power supply.

15. The method according to claim 14, characterized in that, The method further includes: When powered on, an enable signal is sent to each of the auxiliary power supply controllers so that the auxiliary power supply controller controls the power supply of the connected auxiliary power supply terminals. When the power is off, stop sending enable signals to each of the auxiliary power supply controllers, so that the auxiliary power supply controllers control the connected auxiliary power supply terminals to stop supplying power.

16. The method according to claim 14, characterized in that, The method further includes: If, based on the secondary power supply signal, it is determined that there is a first secondary power supply terminal that has stopped supplying power and a second secondary power supply terminal that is in a power supply state, then an enable signal is sent to the secondary power supply controller connected to the second secondary power supply terminal so that the corresponding secondary power supply controller controls the second secondary power supply terminal to stop supplying power.

17. The method according to claim 14, characterized in that, The method further includes: If, based on the secondary power supply signal, it is determined that at least some of the secondary power supply terminals have stopped supplying power, an interrupt signal is sent to the baseboard management controller, wherein, in response to receiving the interrupt signal, the baseboard management controller performs the following operations: Disconnect the power supply terminal from the main power supply terminal; Disconnect the power supply terminal from the auxiliary power supply terminal.

18. The method according to claim 14, characterized in that, The method further includes: If, based on the secondary power supply signal, it is determined that at least some of the secondary power supply terminals have stopped supplying power, a log recording message is sent to the baseboard management controller so that the baseboard management controller records a power supply anomaly log.

19. A motherboard, characterized in that, The motherboard includes a power supply circuit as described in any one of claims 1 to 13.

20. A server, characterized in that, The server includes the motherboard as described in claim 19.

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