Chip live-line burning low-power-consumption awakening method based on double-line command code

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a chip live-line burning low-power-consumption awakening method based on a double-line command code. Comprising the following steps: respectively filling an external clock signal CLK and a data signal DATA into a clock port and a data port; the effective STOP signal is used as an enable bit to control a data buffer to shift and cache the data signal DATA according to the clock signal CLK, so that a stable wake-up command code to be matched is output; the awakening command code to be matched is input to a numerical value comparison module, and if the comparison result is that the awakening command code to be matched is matched, the numerical value comparison module outputs a high-level matching signal match to trigger system reset, so that the chip exits the STOP mode and is reset and awakened. The low-power-consumption awakening live-line burning function is achieved, it is guaranteed that the whole system completes the burning process in a low-power-consumption mode, and the overall power consumption of the system is effectively reduced.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a low-power wake-up method for chip power-on programming based on two-line command codes. Background Technology

[0002] With the rapid development of semiconductor technology, the complexity and integration of integrated circuits are constantly increasing, making programming technology an indispensable part of the electronic product manufacturing process. Programming technology mainly refers to the process of writing preset program code or data files into the non-volatile storage media of chips such as microcontrollers and memory using specific hardware devices and software protocols. Wake-up refers to the process of a device resuming from a low-power sleep state to normal operating mode. When the chip is running normally, it can exit the low-power sleep state and resume operation through wake-up sources such as timers, external pins, or specific communication, thereby reducing average power consumption.

[0003] In traditional powered programming, if the system enters a low-power mode, the system clock shuts down, communication between the chip and the programmer ceases, the connection is broken, and the programming process cannot continue. Wake-up during programming refers to forcibly switching the chip to a recognizable and programmable state by executing specific hardware operations when the chip is in deep sleep, low-power mode, or software-protected locked state. This is a crucial step in ensuring production yield and subsequent firmware updates.

[0004] Currently, the mainstream methods for achieving programmable wake-up all rely on hardware operations. These can be mainly divided into the following three categories: (1) Reset triggering method: The chip is guided to start from the system memory by operating the reset pin and the boot mode pin through specific timing operations. First, this method is vulnerable to security. It is essentially an open hardware universal key. Anyone who has access to it can wake up the system by shorting the test point. Second, this method has strict timing requirements and is easily affected by hardware. If the reset signal has a non-steep edge or the pin level is unstable due to line interference or ringing introduced by long lines, it will lead to sampling failure.

[0005] (2) Power cycling method: When a specific pin (such as BOOT0) is pulled up or down, the chip is powered off and then powered on again, forcing it to enter the next startup. First, this method is more cumbersome and slower. Complete power-off and power-on is much slower than the reset trigger method, affecting mass production efficiency and is not suitable for scenarios with requirements for programming speed. Second, this method depends on the power system. If there are large capacitors on the board, the voltage drop after the breakpoint will be slow, which may lead to incomplete power-off and wake-up failure. During board programming, the battery of some products is not removable, and the power-off cannot be complete, resulting in a lower programming success rate.

[0006] (3) Sequence loop method: Relying on protocols such as UART and SPI, in low-power mode, part of its serial port peripheral (wake-up receiving part) is still listening to the data line. When a specific byte sequence is received, the system can be woken up. This method can solve the security vulnerability problem of the reset trigger method, but its hardware complexity and cost are high. Reliable sequence code matching requires additional hardware circuits, which increases the silicon area and design complexity of the chip. Secondly, when packaging this method, the pins used for programming wake-up of UART or SPI need to be sealed out, which increases the difficulty of small packaging and may cause the small package circuit to lose its function. At the same time, this method has high baud rate consistency requirements for asynchronous communication UART, and is prone to frame errors in low-power and noisy environments, with low anti-interference ability and low reliability.

[0007] Therefore, this invention proposes a low-power wake-up method for chip power-on programming based on dual-line command codes to solve the above problems. Summary of the Invention

[0008] The purpose of this invention is to provide a low-power wake-up method for chip hot-programming based on dual-line command codes. This invention solves the defect that the system cannot continue programming after entering low-power mode during traditional hot-programming. By introducing a wake-up scheme that does not depend on the master clock and CPU clock, the low-power wake-up hot-programming function is realized, ensuring that the entire system completes the programming process in low-power mode, effectively reducing the overall power consumption of the system.

[0009] To address the aforementioned technical problems, this invention provides a low-power wake-up method for chip power-on programming based on dual-line command codes, comprising: By feeding external clock signal CLK and data signal DATA into the clock port and data port respectively; If the chip is in low-power STOP mode, the STOP signal is valid; By using the valid STOP signal as an enable bit, the data buffer is controlled to shift and buffer the data signal DATA according to the clock signal CLK, thereby outputting a stable wake-up command code to be matched. The wake-up command code to be matched is input into the numerical comparison module and compared bit by bit with the preset wake-up command code in the numerical comparison module. If the comparison result is a match, the numerical comparison module outputs a high-level match signal to trigger a system reset, causing the chip to exit the STOP mode and be reset and woken up. After the system is reset and woken up, it enters the programming mode by injecting the START signal and mode command code into the data port.

[0010] Preferred options also include: Power on the chip; By injecting a fixed level into the clock port and the data port, and waiting for a period of time, the operation of injecting the external clock signal CLK and data signal DATA into the clock port and the data port respectively is performed. The data signal DATA includes: START signal and wake-up command code.

[0011] Preferably, if the chip is in normal operating mode, the STOP signal is invalid and the system will not trigger a reset wake-up.

[0012] Preferably, regardless of whether the system reset wake-up is successfully triggered, after a fixed time period of sequentially injecting the START signal and the wake-up command code into the data port, the START signal and the mode command code must be sequentially injected again to enter the burning mode.

[0013] Preferably, in the operation of the control data buffer shifting and buffering the data signal DATA according to the clock signal CLK, the number of clock cycles of the clock signal CLK injected is two more than the number of clock cycles required to completely shift in the wake-up command code.

[0014] Preferably, when the trigger system is reset, it specifically includes: The matching signal `match` generates a reset signal `ICP_RST` for the programming module, which serves as one of the system reset sources. It performs logical operations with other reset source signals of the chip to generate a system reset signal. When the system reset signal is valid, the chip resets and exits the STOP mode.

[0015] Preferably, the reset signal ICP_RST is set when the match signal is high and the STOP signal is valid, and is cleared after the STOP signal is released and the STOP mode is exited.

[0016] This invention also provides a low-power wake-up system for chip hot-programming based on two-line command codes, which executes the low-power wake-up method for chip hot-programming based on two-line command codes as described above, including: The data buffer module has its enable terminal connected to the chip's STOP signal, and its clock terminal and data input terminal connected to the chip's CLK port and DATA port, respectively. When the STOP signal is valid, it shifts and buffers the data in the DATA port according to the signal in the CLK port, enhances the drive, and then outputs the wake-up command code to be matched. The numerical comparison module, whose input is connected to the output of the data buffer module, is used to compare the received wake-up command code to be matched with the internally pre-stored wake-up command code bit by bit, and output a matching signal match; The wake-up control module, whose input is connected to the output of the numerical comparison module, is used to generate a reset signal ICP_RST for the programming module when the matching signal match is successful. The system reset logic module receives the reset signal ICP_RST and other reset source signals at its input terminal. It performs logical processing on multiple reset sources and outputs a system reset signal. When the system reset signal is valid, it will cause the chip to exit the STOP mode. Subsequently, the chip enters the programming mode by feeding the START signal and mode command code into the DATA port.

[0017] Preferably, the data buffer module consists of an AND gate and a data buffer; wherein the two inputs of the AND gate are respectively connected to the data signal DATA and the STOP signal, the output is connected to the input of the data buffer, the clock terminal of the data buffer is connected to the clock signal CLK, and the output of the data buffer is connected to the input of the numerical comparison module.

[0018] The present invention also provides a chip that executes a low-power wake-up system based on two-line command codes for chip power-on programming, as described above.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. Improved reliability and anti-interference capability of wake-up operation in this invention: Based on long-bit wake-up command code, compared with simple pull-high or pull-low level, the introduction of wake-up command code in this invention can effectively solve the defects of false wake-up caused by misoperation and non-standard reset signal, eliminating the phenomenon of false trigger wake-up from the root; This invention does not rely on the master clock, is not controlled by circuit state, and does not rely on baud rate with high consistency requirements, so it will not be affected by power fluctuations, software errors, etc. in the main system. Even under extreme conditions of program crash, this solution can still maintain the wake-up function and has strong anti-interference capability.

[0020] 2. This invention is simple to operate, reduces costs, and has high hardware compatibility: This invention only requires programming its own CLK and DATA signals to complete the wake-up operation, making it simple to operate. The reduction of unnecessary peripheral modules lowers costs. Furthermore, unlike other inventions that require occupying and reusing communication pins such as UART and SPI, this invention does not require additional pins, avoiding disruption to normal system functions and the occupation of pin resources, resulting in higher hardware compatibility.

[0021] 3. Improved Programming Success Rate: This invention eliminates the need for a complete power-off step to achieve wake-up, avoiding incomplete power-off caused by non-removable batteries in some products during board programming, thus improving the programming success rate. The programming system mode entry process proposed in this invention uses the STOP signal as the criterion; a wake-up event only occurs when the STOP signal is set in STOP mode, preventing false wake-up operations caused by inputting wake-up command codes in normal working mode. Furthermore, this process is consistent whether the system is in STOP mode or normal working mode, making the hardware design of this invention universal and thus providing greater compatibility with different programmers. Attached Figure Description

[0022] Figure 1 This is a flowchart of a low-power wake-up method for chip programming based on dual-line command codes, provided by the present invention.

[0023] Figure 2 This is a schematic diagram of a low-power wake-up system for chip power-on programming based on dual-line command codes, provided by the present invention.

[0024] Figure 3 This is the timing diagram for successful wake-up in STOP mode provided by the present invention. Detailed Implementation

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0026] like Figure 1 As shown, this embodiment of the invention provides a low-power wake-up method for chip power-on programming based on two-line command codes, including: By feeding external clock signal CLK and data signal DATA into the clock port and data port respectively; If the chip is in low-power STOP mode, the STOP signal is valid; By using the valid STOP signal as an enable bit, the data buffer is controlled to shift and buffer the data signal DATA according to the clock signal CLK, thereby outputting a stable wake-up command code to be matched. The wake-up command code to be matched is input into the numerical comparison module and compared bit by bit with the preset wake-up command code in the numerical comparison module. If the comparison result is a match, the numerical comparison module outputs a high-level match signal to trigger a system reset, causing the chip to exit the STOP mode and be reset and woken up. After the system is reset and woken up, it enters the programming mode by injecting the START signal and mode command code into the data port.

[0027] In a preferred embodiment of the present invention, it further includes: Power on the chip; By injecting a fixed level into the clock port and the data port, and waiting for a period of time, the operation of injecting the external clock signal CLK and data signal DATA into the clock port and the data port respectively is performed. The data signal DATA includes: START signal and wake-up command code.

[0028] In a preferred embodiment of the present invention, if the chip is in normal operating mode, the STOP signal is invalid and the system will not trigger a reset wake-up.

[0029] In a preferred embodiment of the present invention, regardless of whether the system reset wake-up is successfully triggered, after a fixed time period of sequentially injecting the START signal and the wake-up command code into the data port, the START signal and the mode command code must be sequentially injected again to enter the burning mode.

[0030] In a preferred embodiment of the present invention, during the operation of the control data buffer shifting and buffering the data signal DATA according to the clock signal CLK, the number of clock cycles of the injected clock signal CLK is two more than the number of clock cycles required to completely shift in the wake-up command code.

[0031] In a preferred embodiment of the present invention, the reset of the trigger system specifically includes: The matching signal `match` generates a reset signal `ICP_RST` for the programming module, which serves as one of the system reset sources. It performs logical operations with other reset source signals of the chip to generate a system reset signal. When the system reset signal is valid, the chip resets and exits the STOP mode.

[0032] In a preferred embodiment of the present invention, the reset signal ICP_RST is set when the match signal is high and the STOP signal is valid, and is cleared after the STOP signal is released and the STOP mode is exited.

[0033] like Figure 2 As shown, the present invention also provides a low-power wake-up system for chip power-on programming based on dual-line command codes, comprising: The data buffer module has its enable terminal connected to the chip's STOP signal, and its clock terminal and data input terminal connected to the chip's CLK port and DATA port, respectively. When the STOP signal is valid, it shifts and buffers the data in the DATA port according to the signal in the CLK port, enhances the drive, and then outputs the wake-up command code to be matched. The numerical comparison module, whose input is connected to the output of the data buffer module, is used to compare the received wake-up command code to be matched with the internally pre-stored wake-up command code bit by bit, and output a matching signal match; The wake-up control module, whose input is connected to the output of the numerical comparison module, is used to generate a reset signal ICP_RST for the programming module when the matching signal match is successful. The system reset logic module receives the reset signal ICP_RST and other reset source signals at its input terminal. It performs logical processing on multiple reset sources and outputs a system reset signal. When the system reset signal is valid, it will cause the chip to exit the STOP mode. Subsequently, the chip enters the programming mode by feeding the START signal and mode command code into the DATA port.

[0034] In a preferred embodiment of the present invention, the data buffer module is composed of an AND gate and a data buffer; wherein the two input terminals of the AND gate are respectively connected to the data signal DATA and the STOP signal, the output terminal is connected to the input terminal of the data buffer, the clock terminal of the data buffer is connected to the clock signal CLK, and the output terminal of the data buffer is connected to the input terminal of the numerical comparison module.

[0035] The numerical comparison module has a preset wake-up command code as reference data. After entering STOP mode, the STOP signal is used as the enable bit of the data buffer. After the STOP signal is enabled, the clock CLK other than DATA is shifted into the data buffer. The buffer enhances the signal driving capability and stably outputs the data to be matched, which is the wake-up command code to be matched. When the enable signal arrives, the data to be matched is compared bit by bit with the reference data. If the data match, the matching signal match is output at a high level and held. Otherwise, the output is low.

[0036] The dual-line command code hot-programming wake-up method is based on the principle of numerical matching and comparison. Combined with other peripheral control signals, when `match` is 1, it indicates that the wake-up command code matches the injected DATA data, thus generating the programming module's reset signal ICP_RST. This reset signal, as one of the reset sources for the system reset event, is merged with other reset sources into the system reset signal, causing the system reset signal to be set, resetting the system, exiting STOP mode, and achieving the reset wake-up purpose. This reset method is, to some extent, equivalent to a power-on reset; after the system reset signal is set, the power-on counter restarts counting. After the system wakes up, it can re-encode the data according to the normal operating mode's encoding method to re-enter the programming mode and perform the programming operation.

[0037] In the dual-line command code hot-programming wake-up method, the number of CLK clock cycles is two more than the number required for the wake-up command code. This is to coordinate with the ICP_RST signal, which is set when a data match is detected and resets to zero after the STOP signal is detected and released, i.e., after exiting STOP mode. The specific timing is as follows: Figure 3 As shown, when the STOP signal is set, the system is in low-power mode. When attempting to perform a programming operation, clock and data signals are simultaneously injected from the CLK and DATA ports. The data signal changes value on the falling edge of the clock signal so that the value can be sampled on the rising edge. The number of clock cycles injected is the number of bits in the wake-up command code plus 2. After the wake-up command code is injected, the ICP_RST signal is set on the rising edge of the clock, exiting the STOP mode. The system generates a reset, and the system clock CLKSYS restarts counting, completing the wake-up process.

[0038] The present invention also provides a chip that executes a low-power wake-up system based on two-line command codes for chip power-on programming, as described above.

[0039] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A low-power wake-up method for chip hot-programming based on two-wire command codes, characterized in that, include: By feeding external clock signal CLK and data signal DATA into the clock port and data port respectively; If the chip is in low-power STOP mode, the STOP signal is valid; By using the valid STOP signal as an enable bit, the data buffer is controlled to shift and buffer the data signal DATA according to the clock signal CLK, thereby outputting a stable wake-up command code to be matched. The wake-up command code to be matched is input into the numerical comparison module and compared bit by bit with the preset wake-up command code in the numerical comparison module. If the comparison result is a match, the numerical comparison module outputs a high-level match signal to trigger a system reset, causing the chip to exit the STOP mode and be reset and woken up. After the system is reset and woken up, it enters the programming mode by injecting the START signal and mode command code into the data port.

2. The low-power wake-up method for chip hot-programming based on dual-line command codes as described in claim 1, characterized in that, Also includes: Power on the chip; By injecting a fixed level into the clock port and the data port, and waiting for a period of time, the operation of injecting the external clock signal CLK and data signal DATA into the clock port and the data port respectively is performed. The data signal DATA includes: START signal and wake-up command code.

3. The low-power wake-up method for chip hot-programming based on dual-line command codes as described in claim 2, characterized in that, If the chip is in normal operating mode, the STOP signal is invalid and the system will not trigger a reset wake-up.

4. The low-power wake-up method for chip hot-programming based on dual-line command codes as described in claim 3, characterized in that, Regardless of whether the system reset wake-up is successfully triggered, after a fixed time period of sequentially feeding the START signal and wake-up command code into the data port, the START signal and the mode command code must be sequentially fed back in order to enter the burning mode.

5. A low-power wake-up method for chip hot-programming based on dual-line command codes as described in claim 1, characterized in that, In the operation of the control data buffer shifting and buffering the data signal DATA according to the clock signal CLK, the number of clock cycles of the clock signal CLK injected is two more than the number of clock cycles required to completely shift in the wake-up command code.

6. The low-power wake-up method for chip hot-programming based on dual-line command codes as described in claim 1, characterized in that, When the trigger system is reset, the specific steps include: The matching signal `match` generates a reset signal `ICP_RST` for the programming module, which serves as one of the system reset sources. It performs logical operations with other reset source signals of the chip to generate a system reset signal. When the system reset signal is valid, the chip resets and exits the STOP mode.

7. A low-power wake-up method for chip hot-programming based on dual-line command codes as described in claim 6, characterized in that, The reset signal ICP_RST is set when the match signal is high and the STOP signal is valid, and is cleared after the STOP signal is released and the STOP mode is exited.

8. A chip hot-programming low-power wake-up system based on two-line command codes, executing the chip hot-programming low-power wake-up method based on two-line command codes as described in any one of claims 1 to 7, characterized in that, include: The data buffer module has its enable terminal connected to the chip's STOP signal, and its clock terminal and data input terminal connected to the chip's CLK port and DATA port, respectively. When the STOP signal is valid, it shifts and buffers the data in the DATA port according to the signal in the CLK port, enhances the drive, and then outputs the wake-up command code to be matched. The numerical comparison module, whose input is connected to the output of the data buffer module, is used to compare the received wake-up command code to be matched with the internally pre-stored wake-up command code bit by bit, and output a matching signal match; The wake-up control module, whose input is connected to the output of the numerical comparison module, is used to generate a reset signal ICP_RST for the programming module when the matching signal match is successful. The system reset logic module receives the reset signal ICP_RST and other reset source signals at its input terminal. It performs logical processing on multiple reset sources and outputs a system reset signal. When the system reset signal is valid, it will cause the chip to exit the STOP mode. Subsequently, the chip enters the programming mode by feeding the START signal and mode command code into the DATA port.

9. A low-power wake-up system for chip hot-programming based on dual-line command codes as described in claim 8, characterized in that, The data buffer module consists of an AND gate and a data buffer; wherein the two inputs of the AND gate are respectively connected to the data signal DATA and the STOP signal, the output is connected to the input of the data buffer, the clock input of the data buffer is connected to the clock signal CLK, and the output of the data buffer is connected to the input of the numerical comparison module.

10. A chip, characterized in that, The system implements a low-power wake-up system for chip power-on programming based on dual-line command codes as described in claim 8.

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