Implementing unique page table permissions with shared page table

Abstract

The invention relates to implementing unique page table permissions with a shared page table. A processor includes a processor core; the filter register is used for storing a first permission filter; and a memory management unit (MMU) coupled to the processor core, the filter register, and a first peripheral device associated with the first permission filter, where the MMU includes logic circuitry to manage a shared page table including entries corresponding to the processor core and the first peripheral device, wherein the logic circuitry is to: receive a memory access request to a first memory page from a first peripheral device; determining whether a set of privilege bits of the first entry matches a first combination of bits of a first privilege filter; granting the memory access request if the set of privilege bits matches a first combination of bits of the first privilege filter; and causing a page failure if the set of privilege bits does not match the first combination of bits.

Description

[0001] Divisional Application Instructions This application is a divisional application of Chinese invention patent application No. 202010124628.8, filed on February 17, 2020, entitled "Implementing Unique Page Table Rights with Shared Page Tables". Technical Field

[0002] This disclosure relates to computer systems; more specifically, to memory access permissions of computer systems. Background Technology

[0003] Computer systems can use a process called paging to map the virtual contiguous address space used by an application or process to the physical addresses of the memory storing the data. Paging uses a data structure called a page table to map from the virtual address space to the physical address space. Devices peripheral to the central processing unit (CPU) of a computer system can directly access memory without communicating with the CPU. These peripheral devices can also use page tables to map from the virtual address space to the physical address space in memory. The CPU can use the memory management unit (MMU) to access memory. Peripheral devices can use the input / output memory management unit (IOMMU) to directly access the computer system's memory. Summary of the Invention

[0004] According to one aspect of this disclosure, a processor is provided, comprising: a processor core; a filter register for storing a first permission filter; and a memory management unit (MMU) coupled to the processor core, the filter register, and a first peripheral device associated with the first permission filter, wherein the MMU includes logic circuitry for managing a shared page table including entries corresponding to the processor core and the first peripheral device, wherein the logic circuitry is configured to: receive a memory access request for a first memory page from the first peripheral device; determine whether a set of permission bits of a first entry in the shared page table matches a first combination of bits of the first permission filter, wherein the first combination of bits of the first permission filter defines access permissions for the first peripheral device; grant the memory access request in response to the set of permission bits of the first entry matching the first combination of bits of the first permission filter; and cause a page fault in response to the set of permission bits of the first entry not matching the first combination of bits of the first permission filter.

[0005] According to another aspect of this disclosure, a system is provided, comprising: a memory for storing a shared page table; a first peripheral device coupled to the memory; a second peripheral device coupled to the memory; and a memory management unit (MMU) coupled to the memory, the first peripheral device, and the second peripheral device, wherein the MMU includes: a first permission filter, wherein the first permission filter includes a first combination of bits defining access permissions of the first peripheral device to a first memory page associated with a first entry of the shared page table; and a second permission filter, wherein the second permission filter includes a second combination of bits defining access permissions of the second peripheral device to the first memory page associated with the first entry of the shared page table, wherein the first combination of bits is different from the second combination of bits.

[0006] According to another aspect of this disclosure, an operating method is provided, comprising: receiving a memory access request for a first memory page from a first device associated with a first permission filter, wherein the first permission filter includes a first combination of bits defining the first device's access permissions to the first memory page; determining whether a set of permission bits of a first entry in a page table matches the first combination of bits of the first permission filter, wherein the page table is shared by the first device and a second device; granting the memory access request in response to the first entry's permission bits matching the first combination of bits of the first permission filter; and causing a page fault in response to the first entry's permission bits not matching the first combination of bits of the first permission filter. Attached Figure Description

[0007] Figure 1 This is a system diagram illustrating an implementation of a system-on-chip that uses a permission filter to provide unique access permissions to the device's memory using a shared page table.

[0008] Figure 2 It is a block diagram illustrating the logical process flow for applying permission filters associated with different devices to allow unique access permissions to memory, based on an implementation method.

[0009] Figure 3A It is an example permission filter register that stores several different permission filters according to an implementation method.

[0010] Figure 3B This is a sample page table that illustrates several page table entries.

[0011] Figure 3CThis is an example logic circuit for applying permission filters to page table entries, based on one implementation.

[0012] Figure 4A This is a flowchart illustrating an example method for using permission filters to provide unique access permissions to a device using a shared page table, based on an implementation example.

[0013] Figure 4B This is a detailed flowchart illustrating an example method for using permission filters to provide unique access permissions to a device using a shared page table, based on an implementation example.

[0014] Figure 5A It is a block diagram illustrating the ordered pipeline and register renaming stage, and the unordered issue / execute pipeline, based on an implementation method.

[0015] Figure 5B This is a block diagram illustrating a microarchitecture of a processor or integrated circuit that can implement hardware support for a multi-key encryption engine, according to an implementation of this disclosure.

[0016] Figure 6 The present disclosure illustrates a block diagram of a microarchitecture of a processor or integrated circuit that implements hardware support for a multi-key encryption engine.

[0017] Figure 7 It is a block diagram of a computer system based on an implementation method.

[0018] Figure 8 It is a block diagram of a computer system based on another implementation.

[0019] Figure 9 It is a block diagram of a system-on-a-chip based on an implementation method.

[0020] Figure 10 The diagram illustrates another implementation of the block diagram of the computing system.

[0021] Figure 11 The diagram illustrates another implementation of the block diagram of the computing system. Detailed Implementation

[0022] Peripheral devices in a computer system may have direct access to the system's memory. To access memory directly, peripheral devices may need to consult page tables to map to physical addresses in memory. A page table can refer to any memory translation structure, such as a hash table, tree, table, etc. Currently, if a device is using the same page table as the CPU to access memory, the device must have the same access rights, or "views," to that memory as the CPU. This means that if the CPU has access to reads and writes to pages of memory, then the device using the same page table also has access rights. To solve this problem, each device could use a separate page table to allow different memory access permissions. However, using separate page tables is wasteful because there are two copies of the same structure in the system. Therefore, it would be advantageous for different devices to use a shared page table to access memory and to define different access permissions for devices sharing the same page table.

[0023] What is disclosed are systems and methods for implementing unique page table permissions using a shared page table. For each device, or CPU, accessing the system's memory, a separate filter can be used to determine each device's or CPU's memory access permissions to pages of memory from a single page table. Memory access permission filters can be associated with a device or CPU to allow the device or CPU to have its own specific view of the memory. Filters may include one or more bits, referred to as "software bits," that define which bits of a page table entry indicate permissions for a specific device or CPU.

[0024] For example, in one implementation, the first bit could be a bit that grants write access to the first device. If the first bit of a page table entry is set, the first device has write access; otherwise, it does not. The CPU can use a second bit that identifies the CPU's permissions. Alternatively, the CPU can forgo this filter and use only bits read by the hardware (e.g., traditional dirty / write / current bits). Thus, the CPU can ignore the first bit, or other software bits, when determining its permissions. In this way, the first device may have one view of the memory (write access) when the first bit is set, while the CPU has another view.

[0025] Furthermore, additional bits or combinations of bits are used to determine access permissions for devices and CPUs, and unique permissions can be extended to any number of additional devices or CPUs. For example, if the first bit is set, the first device may have write permissions; if the second bit is set, the second device may have write permissions; and if the third bit is set, the third device may have write permissions, and so on.

[0026] Figure 1This is a block diagram illustrating a system 100 including a system-on-a-chip (SOC) 110, one or more peripheral devices 130A-B, and main memory 140. SOC 110 may include a central processing unit (CPU) 112, a memory management unit (MMU) 114, and an input / output memory management unit (IOMMU) 120. Although depicted as discrete, IOMMU 120 and MMU 114 may also be a single unit for memory management. Additionally, although IOMMU 120 is depicted within SOC 110, its location may be separate from SOC 110. Main memory 140 may include one or more page tables 142 and addressable memory 144.

[0027] IOMMU 120 may include one or more scenario entries 122, filter register 124A, and filter logic circuitry 126A. IOMMU 120 may receive memory access requests from devices 130A-B, including read and write requests. Upon receiving a memory access request from one of devices 130A-B, IOMMU 120 may retrieve a page table entry from page table 142 from main memory 140. Once IOMMU 120 has retrieved the page table entry, filter logic circuitry 126A may retrieve a permission filter from filter register 124A to compare it with the permissions indicated by the set of permission bits of the page table entry. The set of permission bits of the page table entry may include one or more software bits that can be set and read by software, and one or more hardware bits that can be read or set by hardware (e.g., MMU 114). The software bits may be set by software to indicate memory access permissions for one or more devices 130A-B.

[0028] CPU 112 may include one or more processor cores. MMU 114 may be coupled to CPU 112 and manage CPU 112's access to main memory 140. MMU 114 may apply permission filters to page table entries accessed by CPU 112, or may simply use conventional hardware bits of page table entries to determine CPU 112's access permissions. MMU 114 may also include filter register 124B and filter logic circuitry 126B, both of which may function the same as or similarly to filter register 124A and filter logic circuitry 126A, respectively.

[0029] Filter registers 124A-B may store one or more permission filters associated with one or more devices 130A-B and CPU 112. Permission filters may include one or more bits associated with software bits of page table entries, and one or more bits corresponding to hardware bits of page table entries. Context entry 122 may include the root address of page table 142 to which devices 130A-B and / or CPU 112 are mapped or assigned, and may be consulted to determine one or more permission filters (i.e., software bits defined as filter settings associated with the device or CPU) for each device 130A-B and CPU 112.

[0030] The filter logic circuits 126A-B may include logic to compare the permission filter with the permission bits of the page table entry and provide an output consisting of the same bits of the permission filter and the page table entry (i.e., a logical AND of the permission filter and the page table entry). Once the output from this comparison is determined, it can be compared with the permission filter to determine whether the device or CPU has the appropriate permissions. If the output and the permission filter are the same, the device or CPU has the appropriate permissions. If the output and the permission filter are different, the device or CPU does not have the appropriate permissions and the memory access request will cause a page fault and fail. After the filter is applied to the page table entry, the filter logic circuits 126A-B may update the page table entry. In one example, if the request fails, the filter logic may update the page table entry to grant the device or CPU the appropriate permissions. The page table entry may be updated when there is preferably notification before granting access to the device or CPU to allow memory optimization, media wear optimization, etc. Furthermore, the page table may be updated to indicate that a permission filter for a particular device or CPU has been applied. For example, if a permission filter for a first device is used, the page table may be updated to prevent a second device from accessing the same memory. Although depicted as part of IOMMU 120 and MMU 114, the filter logic circuitry 126A-B can be implemented anywhere within SOC 110 or System 100.

[0031] Devices 130A-B can be coupled to IOMMU 120. Devices 130A-B can be any peripheral device or a hardware subsystem used by the computer system to perform any number of functions. Devices 130A-B can be, for example, a disk drive controller, a graphics card, a network card, or other devices capable of direct memory access. Main memory 140 can refer to any off-chip memory storage. Although page table 142 is depicted as residing in main memory 140, page tables can be stored on or off the chip, and on a disk or in any other storage device accessible by MMU 114 and IOMMU 120.

[0032] Page table 142 can refer to a memory translation data structure, such as a hash table, data tree, or any other data structure. Page table 142 maps contiguous virtual memory addresses used by an application or process to addresses in physical memory. Page table 142 may include multiple page table entries. Each page table entry may correspond to a mapping between virtual pages and physical pages in memory. Each page of memory may include several smaller blocks of memory. When a process executing on a device or CPU requests access to memory, the process may use a virtual address to request access to memory, which must be translated into a physical address. MMU 114 or IOMMU 120 may perform a page walk to find the page table entry that maps virtual pages to physical pages. The actual physical address of the memory block to be accessed can be determined by adding the offset provided by the virtual address to the base address of the page. In addition to including the physical address of the page in memory, page table entries may also include several bits that define memory access permissions for that page. The bits that define memory access permissions for the page may be bits that are compared with a permission filter in filter logic circuitry.

[0033] Addressable memory 144 can refer to any memory in the system that a process can store, access, and retrieve data and / or code from. Addressable memory 144 differs from the memory used to store page tables 142 in that the memory used to store page tables can be used only to store page tables and associated information. Pages requested for access by the CPU 112 or devices 130A-B can be stored in addressable memory 144.

[0034] Figure 2 This is a flowchart illustrating a logical process flow 200 of applying permission filters to one or more devices and CPUs using shared page tables. Device A 210, device B 214, and CPU 212 can access memory using the same one or more page tables 220. Page table 220, device A 210, device B, and CPU 212 can be respectively connected to reference... Figure 1 Page table 142, device 130A, device 130B, and CPU 112 are described as similar or identical. Page table 220 may include multiple page table entries. Each page table entry corresponds to a mapping between virtual pages and physical pages in memory. Each page of memory may include several smaller blocks of memory. When a process executing on a device or CPU requests access to memory, the process uses a virtual address to request access to memory, which must be translated into a physical address. The MMU or IOMMU may perform a page walk to find the page table entry that maps the virtual page to the physical page. The actual physical address of the memory block to be accessed can be determined by adding the offset provided by the virtual address to the base address of the page given by the page table entry. In addition to including the physical address of the page in memory, the page table entry may also include several bits defining the memory access permissions for that page.

[0035] Filter logic 222 can be referenced Figure 1 The described filter logic circuits 126A-B are logically similar or identical. Upon receiving a memory access request, filter logic 222 can apply different permission filters to the page table entries of page table 220 used by device A 210, device B 214, and CPU 212. For a memory access request from device A 210, the filter logic can apply device A filter 230 to provide device A 210 with unique access rights, independent of those provided to CPU 212 and device B 214. For a memory access request from CPU 212, filter logic 222 can apply CPU filter 232 to provide CPU 212 with its own unique rights, independent of those provided to device A 210 and device B 214. For a memory access request from device B 214, filter logic 222 can apply device B filter 234 to provide device B 214 with its own unique rights, independent of those provided to device A 230 and CPU 212. After applying filters to page table entries, the device and CPU each have independent permissions to access individual pages in memory 240.

[0036] In one implementation, notification prior to the device or CPU's first write to a page may be preferred (e.g., for memory optimization or to optimize media wear or write bandwidth). Initially, the permission bits of a page table entry may not allow the device or CPU to write to that page. However, after a filter is applied and the write request fails, the filter logic can update the page table entry permission bits to grant the device or CPU write permission to that page. For example, if the software bit "X" of device A filter 230 is set, and the corresponding "X" bit of the page table entry is not set, a failure will occur when the device requests a write to the page. After this failure, memory optimization can be performed, and the logic can update the page table entry by setting the "X" bit. The next time device A 210 attempts to write to a page in memory, it will have write permission because the "X" bit of the page table entry for that page will be set.

[0037] In one implementation, each device or CPU may have an assigned bit (which will be included in the associated filter). If the assigned bit is set in a page table entry, the device or CPU will have write access to the page of memory associated with that page table entry. In another implementation, a device or CPU may be assigned a combination of bits, which must be set in a page table entry to grant write access to that device or CPU. In yet another implementation, more than one device or CPU may be assigned the same permission filter and be assigned the same permissions. The MMU or IOMMU may include a root entry table that maps I / O devices to specified domains based on device ID, the I / O bus associated with the device, etc. Domains may be associated with a context table that provides devices or CPUs with access to the page table associated with each device or CPU. The context table may include one or more context entries that provide each device or CPU with access to a specific page table. In one implementation, a context entry may also define a permission filter to be associated with the device or CPU of the context entry. Permission filters can then be applied to page table entries when a device or CPU requests access to a page of memory. Multiple devices and / or CPUs can be associated with a single context entry, and multiple devices and / or CPUs can be associated with a single permission filter within a context entry.

[0038] Figure 3A This is an example filter register that stores several permission filters. Figure 3A Seven different filters are described, each using different combinations of three software bits (XYZ) along with three hardware bits (DWP - Dirty / Write / Present). The filter register can store any number of filters and is unaffected by... Figure 3A The limitations of the description. Each filter comprises a unique combination of three software bits, thus allowing seven different devices and / or CPUs to have independent views of the memory in this example. This scheme can be extended to any number of bits, and thus to any number of independent views of the memory.

[0039] As an example, filter 1 may be associated with a device. Whenever the device requests a write to a page in memory, the page table entry corresponding to that page is retrieved. If the "X" permission bit of the page table entry is set, the device has permission to write to that page in memory. However, if the "X" permission bit is not set, the device does not have permission to write to that page in memory. The same process applies to each filter. Furthermore, multiple devices and / or CPUs may be assigned the same filter if these devices and CPUs require the same view of memory.

[0040] Figure 3B This is an example page table that includes several page table entries. As shown in the figure, each page table entry may include the physical address of the page in memory ([ADDR]) and a set of bits defining memory access permissions to the page in memory. The set of software bits for the page table entry can be set by software to provide access permissions to the appropriate devices and CPUs. The set bits may be associated with a device or CPU that requires write permissions to the page in memory, while other bits may be left unset to prevent other devices or CPUs from writing to that page in memory.

[0041] For example, entry 1 has the "X" software bit set, while the "Y" and "Z" software bits are not set. Therefore, with... Figure 3A Any device or CPU associated with filter 1 (i.e., the "X" bit is set, but the others are not) will have write access to that page of memory. However, with Figure 3A Other filters associated with the device or CPU may not have write permissions to that page of memory.

[0042] Figure 3C This is an example logic circuit for applying a permission filter to page table entries. The logic circuit is depicted as a logical AND followed by an IS EQUAL comparator. An alternative depiction could be a logical AND on each bit of the input, followed by an ISEQUAL comparator. The initial input to the filter logic circuit is the permission filter, such as from... Figure 3A The filters, and page table entries, such as those from Figure 3B The initial input is processed by a logical AND operation, meaning that all bits set in the same position in both inputs will also be set in the output. After the logical AND operation, the output of the logical AND operation and the permission filter of the initial input are compared to determine if they are equal (i.e., whether bits set in one are also set in the other, and whether bits not set in one are not set in the other). If the comparison results in the output and the permission filter being equal, then the device or CPU associated with that filter has write permission to that page of memory.

[0043] For example, if Figure 3A Filter 2 ("_Y_DWP") and Figure 3B Entry 2 ("[ADDR]_Y_DWP") is an input to the filter logic circuit, so the output of the AND operation will be "_Y_DWP" because the "Y" bit is set in both, and the "DWP" bit is set in both. Therefore, the inputs to the "equal?" operation will be "_Y_DWP" (initial input / filter 1) and "_Y_DWP" (the output of the logic AND). Both inputs have the same bit set, and therefore the result will be write permission enabled.

[0044] In another example, if Figure 3A Filter 7 (“XYZDWP”) and Figure 3B Entry 1 (“[ADDR]X__DWP”) is the initial input to the filter logic circuit, so the output of the AND operation will be “X__DWP” because both the “X” bit and the “DWP” bit are set in both. However, the “Y” and “Z” bits are set in filter 7 but not in entry 1. Next, the input to the “equal?” operation will be the initial filter 7 “XYZDWP” and the output of the logical AND operation (“X__DWP”). The result of the “equal?” operation will cause the write request to fail because the inputs are not the same; the “Y” and “Z” bits are set in filter 7 but not in the output of the logical AND operation. Therefore, the result will be that write permission is not allowed.

[0045] Figure 4A This is an example flowchart of method 400 for using a permission filter to grant independent permissions to a device or CPU to memory using a shared page table. In block 402, logic circuitry may receive a memory access request for a first memory page from a first peripheral device associated with a first permission filter. The permission filter may include a first combination of bits defining the access permissions of the first peripheral device to the first memory page.

[0046] In block 404, the logic circuitry may apply a first permission filter to the set of permission bits of the first entry in the page table. The page table may be shared by one or more devices and / or CPUs, such as a first device and a second device. The entries in the page table provide a mapping to the physical address of a page of memory requested by the first peripheral device. The entries in the page table may also include one or more permission bits indicating the permissions granted to one or more devices or CPUs to access the pages of memory. The one or more permission bits may include a set of software bits for defining the access permissions of one or more devices and / or CPUs, and a set of hardware bits for granting access permissions to legacy devices, legacy CPUs, or legacy processors. A legacy device or CPU may ignore the software bits and only read the hardware bits to determine memory access permissions. Furthermore, a legacy processor may be a processor that has no knowledge of the permission filter, ignoring the software bits and only reading the hardware bits to determine access permissions.

[0047] In block 406, the logic circuitry can determine whether the set of permission bits of the first entry matches the combination of bits of the first permission filter. In one example, the logic circuitry compares a single corresponding bit of the set of permission bits of the first entry with the combination of bits of the first permission filter. As described below, if the bits match, access is permitted, but if the bits do not match, access is not permitted. In another example, the logic circuitry can compare the permission filter with a page table entry to provide an output consisting of corresponding bits set in both the permission filter and the page table entry (i.e., a logical AND operation for each corresponding bit). The output of the logical AND operation and the original permission filter can then be compared to determine whether they match, or in other words, whether they are equal. In an alternative embodiment, instead of comparing bits, the filter value can be compared with a list of values ​​to determine whether the device or CPU has access rights. Furthermore, software can be used as a filter to determine whether the device or CPU has access rights to a page of memory.

[0048] In block 408, if the set of permission bits of the first entry matches a first combination of bits of the first permission filter, the logic circuitry may grant the memory access request. If the memory access request is granted, the first peripheral device may access a page of memory according to the requested access (e.g., read or write). In block 410, if the set of permission bits of the first entry does not match a first combination of bits of the first permission filter, the logic circuitry may cause a page fault. The software may handle page faults to prevent access and track the cause of the page fault (i.e., inappropriate permissions).

[0049] Figure 4B This is an example flowchart of method 420, which uses a permission filter to grant independent permissions to devices and the CPU for memory using a shared page table. In block 422, the memory management unit (MMU) can receive direct memory access requests for pages of memory from peripheral devices or the CPU. The MMU can be an input / output MMU that controls memory access to peripheral devices or an MMU that controls CPU access to memory. The CPU or peripheral device can request direct memory access through the MMU or IOMMU.

[0050] In block 424, the IOMMU can retrieve the page table entry corresponding to a page of memory to be accessed by a peripheral device or CPU. Retrieving the page table entry may include a page walk, in which the IOMMU searches the page table to find the page table entry associated with a virtual address provided by a process executing on the peripheral device or CPU. Alternatively, if the page table entry is stored in a translation lookaside buffer (TLB), it can be retrieved from the TLB.

[0051] In block 426, the IOMMU can identify permission filters associated with a peripheral device or CPU. The permission filters associated with a device or CPU can be determined by consulting the context entries for the peripheral device or CPU in the IOMMU or MMU. The context entries map the peripheral device or CPU to one or more page tables to be used by the peripheral device or CPU. The context entries also associate the peripheral device or CPU with the permission filters that will be used to access memory via the page tables.

[0052] In block 428, the IOMMU may apply a permission filter to a page table entry. Applying a permission filter to a page table entry may include comparing the permission filter with the page table entry to provide an output consisting of bits set in both the permission filter and the page table entry (i.e., a logical AND operation on each corresponding bit). The output of the logical AND operation and the original permission filter may be compared to determine whether they match, or in other words, whether they are equal.

[0053] In block 430, the IOMMU determines whether the peripheral device or CPU has permission to write to a page in memory. The output of the comparison at block 408 and the initial permission filter are compared to determine if they are equal, as described above at block 428. If they are equal, the peripheral device or CPU has permission to write to a page in memory (or whatever access is requested). However, if they are not equal, the write will fail and a page fault may be triggered.

[0054] In block 432, the IOMMU can update page table entries to grant appropriate permissions to a peripheral device or CPU to allow it to write to pages in memory. This step can be optional and can be configured to occur for specific devices or CPUs under specified conditions. For example, it might be desirable to trigger a notification before allowing access. Page table entries can initially deny access to the page, but then be updated to grant access once a filter has been applied first. Notification before allowing a device or CPU to access pages in memory allows the system to perform any number of stewardship tasks, such as optimizations for media wear. In another example, it might be desirable to update the page table to deny access to certain devices or CPUs after the first device or CPU has accessed a page in memory.

[0055] Figure 5 is a block diagram illustrating the microarchitecture of a processor 500 that implements hardware support for unique page table permissions using a shared page table, according to one implementation. Specifically, the processor 500 depicts in-order architecture core and register renaming logic, and out-of-order issue / execution logic to be included in the processor according to at least one implementation of this disclosure.

[0056] Processor 500 includes a front-end unit 530 coupled to execution engine unit 550, and both are coupled to memory unit 570. Processor 500 may include a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. Alternatively, processor 500 may include dedicated cores, such as a network or communication core, a compression engine, a graphics core, etc. In one implementation, processor 500 may be a multi-core processor or part of a multi-processor system.

[0057] Front-end unit 530 includes branch prediction unit 532 coupled to instruction cache unit 534, instruction cache unit 534 coupled to translation lookaside buffer (TLB) 538, TLB 536 coupled to instruction fetch unit 538, instruction fetch unit 538 coupled to decoding unit 540. Decoding unit 540 (also called decoder) decodes instructions and generates one or more micro-operations, microcode entry points, micro-instructions, other instructions, or other control signals as outputs. These micro-operations, microcode entry points, micro-instructions, other instructions, or other control signals are decoded from, or otherwise reflect, or derived from, the original instructions. Decoder 540 can be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. Instruction cache unit 534 is also coupled to memory unit 570. The decoding unit 540 is coupled to the rename / allocator unit 552 in the execution engine unit 550.

[0058] The execution engine unit 550 includes a renaming / allocator unit 552 coupled to a retirement unit 554 and a group of one or more scheduler units 556. The scheduler units 556 represent any number of different scheduler circuits, including reservation stations (RS), central instruction windows, etc. The scheduler units 556 are coupled to one or more physical register set units 558. Each of the physical register set units 558 represents one or more physical register sets, which store one or more different data types, such as scalar integers, scalar floating-point numbers, compressed integers, compressed floating-point numbers, vector integers, vector floating-point numbers, etc., status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. One or more physical register set units 558 overlap with retirement units 554 to illustrate various ways that can be used to implement register renaming and out-of-order execution (e.g., using one or more reorder buffers and one or more retirement register sets, using one or more future files, one or more history buffers and one or more retirement register sets; using register maps and pools of registers; etc.).

[0059] Generally, architectural registers are visible from outside the processor or from the programmer's perspective. Registers are not limited to any known specific type of circuitry. Various types of registers are appropriate, as long as they can store and provide the data as described herein. Examples of appropriate registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers renamed using register renaming, combinations of dedicated and dynamically allocated physical registers, and so on. The retirement unit 554 and one or more physical register set units 558 are coupled to one or more execution clusters 560. The one or more execution clusters 560 include a set of one or more execution units 562 and a set of one or more memory access units 564. Execution units 562 can perform various operations (e.g., shift, addition, subtraction, multiplication) and operate on various types of data (e.g., scalar floating-point, compressed integer, compressed floating-point, vector integer, vector floating-point).

[0060] While some implementations may include several execution units dedicated to a specific function or set of functions, other implementations may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit (one or more) 556, the physical register set unit (one or more) 558, and the execution cluster (one or more) 560 are shown as potentially multiple because some implementations create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / compact integer / compact floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each with its own scheduler unit, physical register set unit, and / or execution cluster – and in the case of separate memory access pipelines, some implementations are implemented where only the execution cluster of this pipeline has one or more memory access units 564). It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be issued / executed out of order, while the rest are ordered.

[0061] The memory access unit 564 is coupled to memory unit 570, which may, for example, include a data prefetcher 580, a data TLB unit 572, a data cache unit (DCU) 574, and a Level 2 (L2) cache unit 576. In some implementations, DCU 574 is also referred to as the Level 1 data cache (L1 cache). DCU 574 can handle multiple pending cache misses and continue to serve incoming store and load operations. It also supports maintaining cache coherency. Data TLB unit 572 is a cache used to improve the speed of virtual address translation by mapping virtual and physical address spaces. In one exemplary implementation, memory access unit 564 may include a load unit, a store address unit, and a store data unit, each coupled to the data TLB unit 572 in memory unit 570. L2 cache unit 576 may be coupled to one or more other levels of cache and ultimately coupled to main memory.

[0062] In one implementation, the data prefetcher 580 speculatively loads / prefetches data into the DCU 574 by automatically predicting which data the program will consume. Prefetching can refer to transferring data stored in a memory cell (e.g., location) (e.g., a lower-level cache or memory) in the memory hierarchy to a higher-level memory cell closer to the processor (e.g., resulting in lower access latency) before the processor actually needs the data. More specifically, prefetching can refer to fetching data from one of the lower-level caches / memories back into the data cache and / or prefetch buffer before the processor issues a request for the return of specific data.

[0063] The processor 500 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with newer versions); the MIPS instruction set of Imagination Technologies, Kingslandley, Hertfordshire, UK; and the ARM instruction set of ARM Holdings, Sunnyvale, California (with optional additional extensions such as NEON).

[0064] It should be understood that the core can support multi-threaded processing (two or more parallel sets of operations or threads) and can support multi-threaded processing in a variety of ways, including time-sliced ​​multi-threaded processing, simultaneous multi-threaded processing (where a single physical core provides a logical core for each thread that performs multi-threaded processing simultaneously), or a combination of these (e.g., time-sliced ​​instruction fetching and decoding, followed by simultaneous multi-threaded processing, such as in Intel® Hyperthreading technology).

[0065] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in ordered architectures. While the illustrated implementation of the processor also includes separate instruction and data cache units and a shared L2 cache unit, alternative implementations may have a single internal cache for both instructions and data, such as a Level 1 (L1) internal cache, or multiple levels of internal caches. In some implementations, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0066] Figure 5B The diagram illustrates some implementation methods based on this disclosure. Figure 5A A block diagram of the ordered pipeline and register renaming stage, and the unordered issue / execute pipeline implemented in the processor 500. Figure 5B The solid box in the diagram illustrates the ordered pipeline 501, while the dashed box illustrates the register renaming, out-of-order issue / execute pipeline 503. Figure 5B In the pipeline, pipelines 501 and 503 include an instruction fetch phase 502, a length decoding phase 504, a decoding phase 506, an allocation phase 508, a renaming phase 510, a scheduling (also known as dispatching or issuing) phase 512, a register read / memory read phase 514, an execution phase 516, a write-back / memory write phase 518, an exception handling phase 522, and a commit phase 524. In some implementations, the order of stages 502-504 may differ from that shown in the diagram and is not limited to this. Figure 5B The specific sorting shown.

[0067] Figure 6A block diagram of the microarchitecture of processor 600 is illustrated according to an implementation of this disclosure. Processor 600 includes logic circuitry supporting hardware implementation of exclusive page table access for processors or integrated circuits using shared page tables. In some implementations, instructions according to one implementation can be implemented to operate on data elements having sizes of bytes, words, double words, quad words, etc., and data types such as single-precision and double-precision integer and floating-point data types. In one implementation, an ordered front-end 601 is a portion of processor 600 that fetches instructions to be executed and prepares them for later use in the processor pipeline. Implementations of page appending and content copying can be implemented in processor 600.

[0068] Front-end 601 may include several units. In one implementation, instruction prefetcher 616 fetches instructions from memory and feeds them to instruction decoder 618, which then decodes or interprets the instructions. For example, in one implementation, the decoder decodes the received instructions into one or more operations that the machine can execute, referred to as “microinstructions” or “microoperations” (also called micro-ops or uops). In other implementations, the decoder parses the instructions into opcodes and corresponding data and control fields, which are used by the microarchitecture to execute operations according to an implementation. In one implementation, trace cache 630 fetches the decoded uops and assembles them into a program ordering sequence or trace in uop queue 634 for execution. When trace cache 630 encounters complex instructions, microcode ROM (or RAM) 632 provides the uops needed to complete the operation.

[0069] Some instructions are converted into a single micro-op, while others require several micro-ops to complete the entire operation. In one implementation, if completing an instruction requires more than four micro-ops, the decoder 618 accesses the microcode ROM 632 to process the instruction. In one implementation, an instruction can be decoded into a small number of micro-ops for processing at the instruction decoder 618. In another implementation, if completing an operation requires several micro-ops, the instruction can be stored within the microcode ROM 632. The trace cache 630 references the entry point programmable logic array (PLA) to determine the correct micro-instruction pointer for reading the microcode sequence from the microcode ROM 632 to complete one or more instructions according to one implementation. After the microcode ROM 632 has completed the micro-op ordering for an instruction, the machine front end 601 continues to fetch micro-ops from the trace cache 630.

[0070] The out-of-order execution engine 603 is where instructions are prepared for execution. The out-of-order execution logic has several buffers to smooth and reorder the flow of instructions as they travel through the pipeline and are scheduled for execution to optimize performance. Allocator logic allocates the machine buffers and resources needed for each uop to execute. Register renaming logic renames logical registers to entries in the register set. The allocator also allocates entries for each uop in one of two uop queues preceding the instruction scheduler, one for memory operations and one for non-memory operations. These instruction schedulers are: the memory scheduler, the fast scheduler 602, the slow / general floating-point scheduler 604, and the simple floating-point scheduler 606. The uop schedulers 602, 604, and 606 determine when a uop is ready for execution based on the readiness of its dependent input register operand source and the availability of the execution resources required for the uop to complete its operation. One implementation of the fast scheduler 602 can schedule on every half of the master clock cycle, while the other schedulers can only schedule once per master clock cycle. The scheduler uses port arbitration to schedule uop for execution.

[0071] Register sets 608 and 610 are located between schedulers 602, 604, and 606 and execution units 612, 614, 616, 618, 620, 622, and 624 in execution block 611, with separate register sets 608 and 610 for integer and floating-point operations, respectively. In one implementation, each register set 608 and 610 also includes a bypass network that can bypass or forward recently completed results that have not yet been written to the register set to a new subordinate uop. Integer register set 608 and floating-point register set 610 can also communicate data with each other. In one implementation, integer register set 608 is divided into two separate register sets, one for the lower 32 bits of data and the second for the higher 32 bits. Floating-point register set 610 in one implementation has 128-bit wide entries, as floating-point instructions typically have operands with widths ranging from 64 to 128 bits.

[0072] Execution block 611 contains execution units 612, 614, 616, 618, 620, 622, and 624, where instructions are actually executed. This part includes register sets 608 and 610 storing integer and floating-point data operand values ​​required for microinstruction execution. One implementation of the processor 600 includes several execution units: address generation unit (AGU) 612, AGU 614, fast ALU 616, fast ALU 618, slow ALU 620, floating-point ALU 612, and floating-point move unit 614. In one implementation, floating-point execution blocks 612 and 614 perform floating-point, MMX, SIMD, and SSE operations, or other operations. One implementation's floating-point ALU 612 includes a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. For the implementations of this disclosure, floating-point hardware can be used to process instructions involving floating-point values.

[0073] In one implementation, ALU operations are handled by high-speed ALU execution units 616 and 618. The fast ALUs 616 and 618 in one implementation can perform fast operations with an effective delay of half a clock cycle. In another implementation, most complex integer operations are handled by the slow ALU 620, as it includes integer execution hardware for long-latency operations such as multipliers, shifters, flag logic, and branching. Memory load / store operations are performed by AGUs 622 and 624. In one implementation, the integer ALUs 616, 618, and 620 are described in the context of performing integer operations on 64-bit data operands. In alternative implementations, ALUs 616, 618, and 620 can be implemented to support various data bit widths, including 16, 32, 128, 256, etc. Similarly, floating-point units 622 and 624 can be implemented to support a range of bit operands with varying widths. In one implementation, floating-point units 622 and 624 can be combined with SIMD and multimedia instructions to operate on 128-bit wide compressed data manipulation objects.

[0074] In one implementation, the uop schedulers 602, 604, and 606 dispatch slave operations before the parent load completes execution. Since uops are speculatively scheduled and executed in processor 600, processor 600 also includes logic to handle memory errors. If data is missed in the data cache, there may be ongoing slave operations in the pipeline, leaving the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only slave operations need to be replayed, while independent operations are allowed to complete. In one implementation of the processor, the scheduler and replay mechanism are also designed to capture instruction sequences for text string comparison operations.

[0075] The term "register" can refer to an on-board processor storage location used as part of an instruction to identify the object of an operation. In other words, registers can be those available from outside the processor (from the programmer's perspective). However, the meaning of registers in an implementation should not be limited to a particular type of circuit. Rather, registers in an implementation can store and provide data and perform the functions described herein. The registers described herein can be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, and so on. In one implementation, an integer register stores 32 bits of integer data. The register set in one implementation also includes eight multimedia SIMD registers for compressing data.

[0076] In this paper, registers are understood to be data registers designed to hold compact data, such as the 64-bit wide MMX registers in microprocessors enabled by Intel's MMX technology from Santa Clara, California. TM Registers (also referred to in some contexts as "mm" registers). These MMX registers, available in both integer and floating-point forms, can be used in conjunction with compressed data elements operated on by SIMD and SSE instructions. Similarly, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, or later (collectively referred to as "SSEx") technologies can also be used to store such compressed data operation objects. In one implementation, registers do not need to distinguish between the two data types when storing compressed and integer data. In one implementation, integers and floating-point data may be contained in the same register set or different register sets. Furthermore, in one implementation, floating-point and integer data may be stored in different registers or in the same register.

[0077] This implementation can be implemented in many different system types. See now for reference. Figure 7 A block diagram of a hardware-supported multiprocessor system 700, illustrating an implementation method, is shown, demonstrating how unique page table permissions can be enforced on shared page tables. For example... Figure 7 As shown, the multiprocessor system 700 is a point-to-point interconnect system and includes a first processor 770 and a second processor 780 coupled via a point-to-point interconnect 750. Figure 7As shown, each of processors 770 and 780 can be a multi-core processor, including first and second processor cores (i.e., processor cores 774a and 774b and processor cores 784a and 784b), although there may be many more cores in the processor. Although shown as having two processors 770 and 780, it is to be understood that the scope of this disclosure is not limited thereto. In other implementations, one or more additional processors may exist in a given processor.

[0078] Processors 770 and 780 are shown to include integrated memory controller units 772 and 782, respectively. Processor 770 also includes point-to-point (PP) interfaces 776 and 788 as part of its bus controller unit; similarly, the second processor 780 includes PP interfaces 786 and 788. Processors 770 and 780 can exchange information via point-to-point (PP) interface 750 using PP interface circuits 778 and 788. Figure 7 As shown, IMC 772 and 782 couple the processor to their respective memories, namely memory 732 and memory 734, which may be part of the main memory locally attached to the respective processor.

[0079] Processors 770 and 780 can exchange information with chipset 790 via point-to-point interface circuits 776, 794, 786, and 798 through individual PP interfaces 752 and 754. Chipset 790 can also exchange information with high-performance graphics circuit 738 via high-performance graphics interface 739.

[0080] Chipset 790 may be coupled to first bus 716 via interface 796. In one implementation, first bus 716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a Fast PCI bus or interconnect bus, although the scope of this disclosure is not limited thereto.

[0081] Now for reference Figure 8 The present disclosure illustrates a block diagram of a third system 800 that enables hardware support by implementing unique page table permissions on a shared page table, according to an implementation of the present disclosure. Figure 7 and Figure 8 Similar elements in the text have similar labels, and Figure 8 Some aspects were from Figure 7 Omitted to avoid ambiguity Figure 7 Other aspects.

[0082] Figure 8The diagram illustrates that processors 870 and 880 may include integrated memory and I / O control logic (“CL”) 872 and 892, respectively. For at least one implementation, CL 872 and 882 may include, for example, the integrated memory controller unit described herein. Furthermore, CL 872 and 892 may also include I / O control logic. Figure 8 The diagram illustrates memories 832 and 834 coupled to CLs 872 and 892, and I / O device 814 also coupled to control logic 872 and 892. Legacy I / O device 815 is coupled to chipset 890. In one implementation, CLs 872 and 892 may include the filter logic circuitry described above to apply a permission filter associated with I / O device 814 to enforce unique page table permissions for I / O device 814. In another implementation, chipset 890 may include the filter logic circuitry described above.

[0083] Figure 9 This is an exemplary System-on-Chip (SoC) 900, which may include one or more of the cores 902A…902N that can implement hardware support by enforcing unique page table permissions on shared page tables. Other system designs and configurations known in the art for laptops, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In summary, many kinds of systems or electronic devices capable of incorporating the processors and / or other execution logic disclosed herein are generally suitable.

[0084] exist Figure 9Within the exemplary SoC 900, the dashed box represents a feature on a more advanced SoC. One or more interconnect units 902 may be coupled to: an application processor 917, which includes a set of one or more cores 902A-N and one or more shared cache units 906; a system proxy unit 910; one or more bus controller units 916; one or more integrated memory controller units 914; a set of one or more media processors 920, which may include integrated graphics logic 908, an image processor 924 for providing still and / or video camera functionality, an audio processor 926 for providing hardware audio acceleration, and a video processor 928 for providing video encoding / decoding acceleration; a static random access memory (SRAM) unit 930; a direct memory access (DMA) unit 932; and a display unit 940 for coupling to one or more external displays.

[0085] Next, turn to Figure 10 This document describes an implementation of a system-on-a-chip (SoC) design that enables hardware support for unique page table permissions on a shared page table, according to an implementation of the present disclosure. As an illustrative example, the SoC 1000 is included in user equipment (UE). In one implementation, UE refers to any device that will be used by an end user for communication, such as a mobile phone, smartphone, tablet, ultra-thin laptop, laptop with a broadband adapter, or any other similar communication device. The UE may connect to a base station or node, which in nature corresponds to a mobile station (MS) in a GSM network. Page addition and content copying implementations can be implemented in the SoC 1000.

[0086] Here, SoC 1000 includes two cores—1006 and 1007. Similar to the above discussion, cores 1006 and 1007 may conform to instruction set architectures such as processors with Intel® Core™ architecture, Advanced Micro Devices, Inc. (AMD) processors, MIPS-based processors, ARM-based processor designs, or their customers, licensees, or users. Cores 1006 and 1007 are coupled to cache control 1008 associated with bus interface unit 1009 and L2 cache 1010 to communicate with other parts of system 1000. Interconnect 1011 includes on-chip interconnects, such as IOSF, AMBA, or other interconnects discussed above, which implement one or more of the disclosed aspects described.

[0087] In one implementation, the SDRAM controller 1040 may be connected to the interconnect 1011 via cache 1010. The interconnect 1011 provides communication channels to other components, such as to a Subscriber Identity Module (SIM) 1030 for interfacing with a SIM card, to a boot ROM 1035 to store boot code for execution by cores 1006 and 1007 to initialize and boot the SoC 1000, to the SDRAM controller 1040 for interfacing with external memory (e.g., DRAM 1060), to a flash memory controller 1045 for interfacing with non-volatile memory (e.g., flash memory 1065), to a peripheral controller 1050 (e.g., a serial peripheral interface) for interfacing with peripherals, to a video codec 1020 and a video interface 1025 for displaying and receiving input (e.g., touch-enabled input), to a GPU 1015 for performing graphics-related calculations, and so on. Any of these interfaces may include aspects of the implementations described herein.

[0088] In addition, the system diagram illustrates peripherals used for communication, such as the Bluetooth® module 1070, the 3G modem 1075, the GPS 1080, and the Wi-Fi® 1085. Note that, as mentioned above, the UE includes radio devices for communication. Therefore, not all of these peripheral communication modules may be included. However, the UE should include some form of radio device for external communication.

[0089] Figure 11The illustration depicts a machine in an example form of computing system 1100, within which a set of instructions enables the machine to implement hardware support for unique page table permissions using a shared page table, according to any one or more methods discussed herein. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, or the Internet. The machine may operate as a server or client device in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying the actions to be taken by the machine. Furthermore, although only a single machine is illustrated, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform one or more methods discussed herein. The page addition and content copying methods can be implemented in the computing system 1100.

[0090] The computing system 1100 includes a processing device 1102, a main memory 1104 (e.g., flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or DRAM (RDRAM) etc.), a static memory 1106 (e.g., flash memory, static random access memory (SRAM) etc.), and a data storage device 1116, which communicate with each other via a bus 1108.

[0091] Processing device 1102 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computer (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 1102 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. In one implementation, processing device 1102 may include one or more processor cores. Processing device 1102 is configured to execute processing logic 1126 for performing the operations discussed herein.

[0092] In one implementation, processing device 1102 may be part of a processor or integrated circuit that includes a disclosed LLC cache architecture. Alternatively, computing system 1100 may include other components as described herein. It should be understood that the core may support multithreaded processing (two or more parallel sets of operations or threads performing operations) and may support multithreaded processing in a variety of ways, including time-sliced ​​multithreaded processing, simultaneous multithreaded processing (where a single physical core provides a logical core for each thread performing simultaneous multithreaded processing), or a combination of these (e.g., time-sliced ​​instruction fetching and decoding, followed by simultaneous multithreaded processing, such as in Intel® Hyperthreading technology).

[0093] The computing system 1100 may also include a network interface device 1118 communicatively coupled to the network 1119. The computing system 1100 may also include a video display device 1110 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1112 (e.g., a keyboard), a cursor control device 1114 (e.g., a mouse), a signal generation device 1120 (e.g., a speaker), or other peripheral devices. Furthermore, the computing system 1100 may include a graphics processing unit 1122, a video processing unit 1128, and an audio processing unit 1132. In another implementation, the computing system 1100 may include a chipset (not shown), which refers to a group of integrated circuits or chips designed to work with the processing device 1102 and control communication between the processing device 1102 and external devices. For example, a chipset can be a set of chips on a motherboard that links the processing device 1102 to high-speed devices, such as main memory 1104 and a graphics controller, and to lower-speed peripheral buses, such as USB, PCI, or ISA buses, that link the processing device 1102 to peripherals.

[0094] Data storage device 1116 may include computer-readable storage medium 1124 on which software 1126 implementing any one or more methods of the functions described herein is stored. The software 1126 may also exist entirely or at least partially as instructions 1126 in main memory 1104 and / or as processing logic in processing device 1102 during execution by computing system 1100; main memory 1104 and processing device 1102 also constitute computer-readable storage media.

[0095] Computer-readable storage medium 1124 may also be used to store instructions 1126 utilizing processing device 1102, and / or software libraries containing methods that call the aforementioned applications. Although computer-readable storage medium 1124 is shown as a single medium in the example implementation, the term "computer-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "computer-readable storage medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for machine execution and causing the machine to perform any one or more methods of the disclosed implementation. The term "computer-readable storage medium" should accordingly be understood to include, but is not limited to, solid-state memory, as well as optical and magnetic media.

[0096] The following examples represent further implementation methods.

[0097] Example 1 is a processor including: a processor core; a filter register for storing a first permission filter; and a memory management unit (MMU) coupled to the processor core, the filter register, and a first peripheral device associated with the first permission filter, wherein the MMU includes logic circuitry for managing a shared page table including entries corresponding to the processor core and the first peripheral device, wherein the logic circuitry is configured to: receive a memory access request for a first memory page from the first peripheral device; determine whether a set of permission bits of a first entry in the shared page table matches a first combination of bits of the first permission filter, wherein the first combination of bits of the first permission filter defines access permissions for the first peripheral device; grant the memory access request in response to the set of permission bits of the first entry matching the first combination of bits of the first permission filter; and cause a page fault in response to the set of permission bits of the first entry not matching the first combination of bits of the first permission filter.

[0098] In Example 2, as described in Example 1, the set of permission bits for the first entry includes one or more software bits that define access permissions for the first memory page.

[0099] In Example 3, the subject matter is as described in any of Examples 1-2, wherein the set of permission bits for the first entry comprises a first set of software bits and a second set of hardware bits, wherein the set of permission bits defines access permissions for the first memory page.

[0100] In Example 4, as described in any of Examples 1-3, wherein the filter register is used to store a second permission filter associated with a second peripheral device coupled to the MMU, wherein the logic circuitry is further configured to: receive a second memory access request from the second peripheral device for the first memory page; determine whether the set of permission bits of the first entry matches a second combination of bits of the second permission filter, wherein the second combination of bits defines access permissions for the second peripheral device, wherein the first combination of bits differs from the second combination of bits; in response to the set of permission bits of the first entry matching the second combination of bits of the second permission filter, the second memory access request is made; and in response to the set of permission bits of the first entry not matching the second combination of bits of the second permission filter, a page fault is caused.

[0101] In Example 5, the subject matter as described in any of Examples 1-4, wherein the logic circuitry is further configured to: receive a second memory access request for the first memory page from the processor core; determine whether the set of permission bits of the first entry indicates that the processor core has access rights to the first memory page; in response to the set of permission bits of the first entry indicating that the processor core has access rights to the first memory page, grant the second memory access request; and in response to the set of permission bits of the first entry indicating that the processor core does not have access rights to the memory page, cause a page fault.

[0102] In Example 6, the subject matter as described in any of Examples 1-5, wherein the logic circuitry includes: a first comparator for comparing a first combination of bits of the first permission filter with a set of permission bits of a first entry of the shared page table and providing an output including an intermediate set of bits, the intermediate set of bits being shared by the first combination of bits and the set of permission bits; and a second comparator for comparing the intermediate set of bits of the output of the first comparator with the first combination of bits of the first permission filter, wherein if the intermediate set of bits of the output of the first comparator matches the first combination of bits of the first permission filter, the memory access request is granted.

[0103] In Example 7, the subject matter as described in any of Examples 1-6, wherein the logic circuitry includes a comparator for comparing a first bit of a combination of bits of the first permission filter with a corresponding second bit of a set of permission bits of the first entry, wherein if the first bit matches the corresponding second bit, the first memory access request is granted.

[0104] In Example 8, the topic as described in any of Examples 1-7 further includes a root entry table, wherein the root entry table maps to a context table, wherein the context table includes a first context entry in which the first peripheral device is associated with the first permission filter.

[0105] In Example 9, the subject matter is as described in any of Examples 1-8, wherein the first peripheral device and the second peripheral device are both associated with the first permission filter in the first context entry.

[0106] Various implementations can have different combinations of the structural features described above. For example, all the optional features of the processor and methods described above can also be used in the system implementation described herein, and the specific details in the examples can be used anywhere in one or more implementations.

[0107] Example 10 is a system comprising: a memory for storing a shared page table; a first peripheral device coupled to the memory; a second peripheral device coupled to the memory; and a memory management unit (MMU) coupled to the memory, the first peripheral device, and the second peripheral device, wherein the MMU includes: a first permission filter, wherein the first permission filter includes a first combination of bits defining access permissions of the first peripheral device to a first memory page associated with a first entry in the shared page table; and a second permission filter, wherein the second permission filter includes a second combination of bits defining access permissions of the second peripheral device to the first memory page associated with a first entry in the shared page table, wherein the first combination of bits is different from the second combination of bits.

[0108] In Example 11, as described in Example 10, the MMU further includes logic circuitry for: receiving a memory access request from the first peripheral device for the first memory page, wherein the first memory page is associated with a first entry in the shared page table; determining whether a set of permission bits of the first entry matches a first combination of bits of the first permission filter; granting the memory access request in response to the set of permission bits of the first entry matching the first combination of bits of the first permission filter; and causing a page fault in response to the set of permission bits of the first entry not matching the first combination of bits of the first permission filter.

[0109] In Example 12, the subject matter as described in any of Examples 10-11, wherein the set of permission bits for the first entry includes a first set of software bits defining the access permissions of the first peripheral device to the first memory page and the access permissions of the second peripheral device to the first memory page, and a second set of hardware bits defining the access permissions of legacy devices to the first memory page.

[0110] In Example 13, as described in any of Examples 10-12, the logic circuitry is further configured to: receive a second memory access request for the first memory page from the second peripheral device; determine whether the set of permission bits of the first entry matches a second combination of bits of the second permission filter; grant the memory access request in response to the set of permission bits of the first entry matching the second combination of permission bits of the second permission filter; and cause a page fault in response to the set of permission bits of the first entry not matching the second combination of bits of the second permission filter.

[0111] In Example 14, the subject matter is as described in any of Examples 10-13, wherein the first software bit of the first entry indicates the first peripheral device's write permission to the first memory page, and the second software bit indicates the second peripheral device's write permission to the first memory page.

[0112] In Example 15, the subject matter as described in any of Examples 10-14, wherein the logic circuitry further includes logic to update the memory translation structure to indicate that the first permission filter has been applied to the first entry.

[0113] In Example 16, as described in any of Examples 10-15, the logic circuitry is further configured to: receive a second memory access request for the first memory page from a central processing unit (CPU); determine whether a second set of hardware bits of the first entry indicates that the CPU is permitted to access the first memory page; grant the second memory access request in response to the second set of hardware bits indicating that the CPU is permitted to access the first memory page; and cause a page fault in response to the second set of hardware bits indicating that the CPU is not permitted to access the first memory page.

[0114] Various implementations can have different combinations of the structural features described above. For example, all the optional features of the processor and methods described above can also be used in the system implementation described herein, and the specific details in the examples can be used anywhere in one or more implementations.

[0115] Example 17 is a method comprising: receiving a first memory access request for a first memory page from a first device associated with a first permission filter, wherein the first permission filter includes a first combination of bits defining access permissions of the first peripheral device to the first memory page; determining whether a set of permission bits of a first entry in a page table matches the first combination of bits of the first permission filter, wherein the page table is shared by the first device and a second device; granting the memory access request in response to the set of permission bits of the first entry matching the first combination of bits of the first permission filter; and causing a page fault in response to the set of permission bits of the first entry not matching the first combination of bits of the first permission filter.

[0116] In Example 18, the subject matter as described in Example 17 further includes: receiving a second memory access request for the first memory page from a second device associated with a second permission filter, wherein the second permission filter includes a second combination of bits defining the second device's access rights to the first memory page; determining whether the set of permission bits of the first entry matches the second combination of bits of the second permission filter; granting the memory access request in response to the set of permission bits of the first entry matching the second combination of bits of the second permission filter; and causing a page fault in response to the set of permission bits of the first entry not matching the second combination of bits of the second permission filter.

[0117] In Example 19, as described in any of Examples 17-18, applying the first permission filter to the set of permission bits of the first entry of the page table comprises: comparing a first combination of bits of the first permission filter with the set of permission bits of the first entry of the page table to provide an output comprising a set of bits that is shared by the first combination of bits of the permission filter and the set of permission bits of the first entry of the page table; comparing the set of bits of the output with the first combination of bits of the first permission filter to determine whether the set of bits of the output matches the first combination of bits of the first permission filter; and in response to determining that the output matches the permission filter, granting the memory access request to the first memory page.

[0118] In Example 20, the subject matter as described in any of Examples 17-19 further includes updating the first entry of the page table to indicate that the first permission filter has been applied to the first entry of the page table.

[0119] Example 21 is a system including means for performing the method described in any of Examples 17-20.

[0120] Example 22 is at least one non-transitory machine-readable storage medium comprising a plurality of instructions which, when executed, implement the method as described in any one of Examples 17-20 or the apparatus as described in any one of Examples 17-20.

[0121] Example 23 is an apparatus including a processor configured to perform the method described in any of Examples 17 to 20.

[0122] Although this disclosure has been described with respect to a limited number of implementations, those skilled in the art will appreciate the many modifications and variations from these implementations. It is intended that the appended claims cover all such modifications and variations falling within the true spirit and scope of this disclosure.

[0123] Throughout this description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware architectures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / heights, specific processor pipeline stages and operations, etc., to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that the implementation of this disclosure does not require the use of these specific details. In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuitry / code used for the described algorithm, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific code representations of the algorithm, specific power-down and gating techniques and logic, and other specific operational details of the computer system, have not been described in detail to avoid unnecessarily obscuring this disclosure.

[0124] The implementation is described with reference to determining the validity of data in cache lines of sector-based caches in a specific integrated circuit, such as a computing platform or microprocessor. The implementation can also be applied to other types of integrated circuits and programmable logic devices. For example, the disclosed implementation is not limited to desktop computer systems or portable computers, such as Intel® Ultrabooks™ computers. It can also be used in other devices, such as handheld devices, tablet devices, other thin and light notebooks, system-on-a-chip (SoC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), SoCs, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system capable of performing the functions and operations taught below. The system described can be any kind of computer or embedded system. The disclosed implementation is particularly applicable to low-end devices such as wearable devices (e.g., watches), electronic implants, sensing and control infrastructure devices, controllers, supervisory control and data acquisition (SCADA) systems, and so on. Furthermore, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also involve software optimizations for energy conservation and efficiency. As will become apparent in the following description, the implementation of the methods, apparatuses, and systems described herein (whether in terms of hardware, firmware, software, or a combination thereof) is crucial for the future of “green technology” that balances performance considerations.

[0125] While the implementations described herein are with reference to a processor, other implementations are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the implementations of this disclosure can be applied to other types of circuits or semiconductor devices that may benefit from higher pipeline throughput and improved performance. The teachings of the implementations of this disclosure are applicable to any processor or machine that performs data manipulation. However, this disclosure is not limited to processors or machines that perform 512-bit, 256-bit, 128-bit, 64-bit, 32-bit, or 16-bit data operations, but can be applied to any processor and machine in which data manipulation or management is performed. Furthermore, examples are provided in the description herein, and various examples are illustrated in the accompanying drawings for illustrative purposes. However, these examples should not be construed as limiting, as they are merely intended to provide examples of implementations of this disclosure and not an exhaustive list of all possible implementations of this disclosure.

[0126] While the foregoing examples describe instruction processing and distribution within the context of execution units and logic circuits, other implementations of this disclosure may be implemented using data or instructions stored on a machine-readable tangible medium that, when executed by a machine, causes the machine to perform functions conforming to at least one implementation of this disclosure. In one implementation, the functionality associated with an implementation of this disclosure is embodied in machine-executable instructions. These instructions can be used to cause a general-purpose or special-purpose processor programmed with these instructions to perform the steps of this disclosure. Implementations of this disclosure may be provided as a computer program product or software that may include a machine or computer-readable medium on which instructions are stored, which can be used to program a computer (or other electronic device) to perform one or more operations according to an implementation of this disclosure. Alternatively, the operations of implementations of this disclosure may be performed by a specific hardware component containing fixed-function logic for performing these operations, or by any combination of a programmed computer component and a fixed-function hardware component.

[0127] Instructions for programming logic to execute implementations of this disclosure may be stored in memory within the system, such as DRAM, cache, flash memory, or other storage devices. Furthermore, the instructions may be distributed via a network or by means of other computer-readable media. Thus, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form—but not limited to—floppy disks, optical disks, compact disc read-only memory (CD-ROM), magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage devices used when transmitting information via the Internet via electrical, optical, acoustic, or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.). Therefore, computer-readable media includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer) form.

[0128] Design can go through various stages, from creation to simulation to manufacturing. Data representing a design can be expressed in several ways. First, as useful in simulation, hardware can be represented using a hardware description language or another functional description language. Furthermore, at some stage of the design process, circuit-level models with logic and / or transistor gates can be generated. Additionally, most designs reach a level at some stage where data represents the physical placement of various devices within the hardware model. In the case of using conventional semiconductor fabrication techniques, data representing the hardware model can be data specifying the presence or absence of various features on different mask layers for the masks used to produce integrated circuits. In any representation of a design, data can be stored in any form of machine-readable medium. Memory or magnetic storage devices such as disks or optical storage devices can be machine-readable media used to store information transmitted via light or radio waves that are modulated or otherwise generated to transmit such information. When an electrical carrier carrying instructions or codes or designs is transmitted, a new copy is made in relation to copying, buffering, or retransmitting the electrical signals. Thus, a communications provider or network provider may store items, such as information encoded into a carrier wave, on a tangible machine-readable medium, at least temporarily, embodying the techniques of this disclosure.

[0129] As used herein, a module refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware, such as a microcontroller, associated with a non-transitory medium to store code suitable for execution by the microcontroller. Therefore, in one implementation, a module refers to hardware specifically configured to recognize and / or execute code to be stored on a non-transitory medium. Furthermore, in another implementation, the use of "module" refers to a non-transitory medium containing code specifically suitable for execution by a microcontroller to perform a predetermined operation. As can be inferred, in another implementation, the term "module" (in this example) could refer to a combination of a microcontroller and a non-transitory medium. Typically, the boundaries of modules illustrated as separate are generally variable and may overlap. For example, first and second modules may share hardware, software, firmware, or a combination thereof, while possibly retaining some independent hardware, software, or firmware. In one implementation, the use of the term "logic" includes hardware such as transistors, registers, or other hardware, such as programmable logic devices.

[0130] The use of the phrase "configured to" in one implementation refers to the arrangement, assembly, manufacture, offer for sale, import, and / or design of a device, hardware, logic, or element to perform a specified or defined task. In this example, a device or element that is not currently in operation is still "configured to" perform the specified task if it is designed, coupled, and / or interconnected to perform said specified task. As a purely illustrative example, a logic gate can provide 0 or 1 during operation. However, a logic gate "configured to" provide an enable signal to a clock does not include every possible logic gate that can provide 1 or 0. Instead, it is the kind of logic gate coupled in a way that enables the clock by outputting 1 or 0 during operation. Again, note that the use of the term "configured to" does not require operation but focuses on the potential state of a device, hardware, and / or element in which it is designed to perform a specific task when it is in operation.

[0131] Furthermore, in one implementation, the use of the phrases “used to,” “capable of,” and / or “operable to” refers to a device, logic, hardware, and / or element designed in a manner that enables the device, logic, hardware, and / or element to be used in the specified manner. As above, it should be noted that in one implementation, the use of “used to,” “capable of,” or “operable to” refers to a potential state of the device, logic, hardware, and / or element, wherein the device, logic, hardware, and / or element is not operational but is designed in a manner that enables the device to be used in the specified manner.

[0132] The values ​​used in this document include any known representation of numbers, states, logic states, or binary logic states. The use of logic levels, logic values, or logical values ​​is also commonly referred to as 1 and 0, which simply represent binary logic states. For example, 1 refers to a high logic level, and 0 refers to a low logic level. In one implementation, a storage unit, such as a transistor or flash memory unit, may be able to hold a single logic value or multiple logic values. However, other representations of values ​​in a computer system are used. For example, the decimal digit ten can also be represented as the binary value 1010 and the hexadecimal letter A. Therefore, values ​​include any representation of information that can be stored in a computer system.

[0133] Additionally, a state can be represented by a value or a portion of a value. As an example, a first value, such as logic one, can represent the default or initial state, while a second value, such as logic zero, can represent a non-default state. Furthermore, the terms reset and set in one implementation refer to the default and updated values ​​or states, respectively. For example, a default value might include a high logic value, i.e., reset, while an updated value might include a low logic value, i.e., set. Note that any combination of values ​​can be used to represent any number of states.

[0134] The methods, hardware, software, firmware, or code described above can be implemented via instructions or code executable by a processing element and stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium. Non-transitory machine-accessible / readable media include any mechanism that provides (i.e., stores and / or transmits) information in a machine-readable form (e.g., a computer or electronic system). For example, non-transitory machine-accessible media include random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for storing information received from transient (propagating) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from non-transitory media from which information can be received.

[0135] Instructions for programming logic to execute implementations of this disclosure may be stored in memory within the system, such as DRAM, cache, flash memory, or other storage devices. Furthermore, the instructions may be distributed via a network or by means of other computer-readable media. Thus, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form—but not limited to—floppy disks, optical disks, compact disc read-only memory (CD-ROM), magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage devices used when transmitting information via the Internet via electrical, optical, acoustic, or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.). Therefore, computer-readable media includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer) form.

[0136] Throughout this specification, the reference to "an implementation" or "a particular implementation" means that a specific feature, structure, or characteristic described in connection with that implementation is included in at least one implementation of this disclosure. Therefore, the phrase "in an implementation" or "in a particular implementation" appearing throughout this specification does not necessarily refer to the same implementation. Furthermore, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more implementations.

[0137] In the foregoing description, a detailed description has been given with reference to specific exemplary implementations. However, it will be apparent that various modifications and changes may be made therein without departing from the broader spirit and scope of this disclosure as set forth in the appended claims. Therefore, the description and drawings should be interpreted in an illustrative rather than a limiting sense. Furthermore, the foregoing use of implementations and other exemplary language does not necessarily refer to the same implementation or the same example, but may refer to different and distinct implementations, as well as potentially similar implementations.

[0138] Some parts of the detailed description are presented as algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, conceived as a self-consistent sequence of operations leading to a desired result. These operations are those that require physical manipulation of physical quantities. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for the sake of convention. The blocks described herein can be hardware, software, firmware, or a combination thereof.

[0139] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated clearly from the above discussion, it should be understood that throughout this specification, discussions using terms such as “definition,” “receive,” “determine,” “issue,” “link,” “associate,” “obtain,” “authenticate,” “prohibit,” “execute,” “request,” and “communicate” refer to the actions and processes of a computing system or similar electronic computing device that manipulate and transform data represented as physical (e.g., electronic) quantities within the registers and memory of a computing system into other data similarly represented as physical quantities within the computing system’s memory or registers or other such information storage, transmission, or display devices.

[0140] The terms “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as being more preferred or advantageous than other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to give a specific concept. For the purposes of this application, the term “or” is intended to mean inclusive “or” rather than exclusive “or.” That is, unless otherwise specified or clearly apparent from the context, “X comprises A or B” is intended to mean any natural inclusive substitution. That is, if X comprises A; X comprises B; or X comprises both A and B, then “X comprises A or B” is satisfied in any of the foregoing cases. Furthermore, the article “a” as used in this application and the appended claims should generally be interpreted as “one or more,” meaning that unless otherwise specified or clearly apparent from the context, it refers to the singular form. Additionally, the use of the terms “an implementation” or “one implementation” or “a method of implementation” throughout does not intend to refer to the same implementation or method of implementation unless so described. In addition, the terms “first,” “second,” “third,” “fourth,” etc., used in this article are intended to be used as labels to distinguish different elements and may not necessarily have an ordinal meaning based on their numerical designations.

Claims

1. An apparatus comprising: Logic circuits, used for: Receive a memory access request for the first memory page from the device; Identify a first permission filter among multiple permission filters, the first permission filter including a set of bits for defining the device's access permissions to the first memory page; Based on applying the set of bits of the first permission filter to the set of permission bits of the first entry in the shared page table, it is determined whether the memory access request to the first memory page is allowed, the shared page table including entries shared by the central processing unit (CPU) and the device. In response to determining that the memory access request to the first memory page is permitted, the memory access request is granted; as well as A page fault is triggered in response to the determination that the memory access request to the first memory page is not permitted.

2. The apparatus of claim 1, wherein, Applying the bit set of the first permission filter to the permission bit set of the first entry includes performing a logical AND operation on the bit set of the first permission filter and the permission bit set of the first entry.

3. The apparatus of claim 1, wherein, The multiple permission filters include seven permission filters.

4. The apparatus of claim 1, wherein, The first entry includes the set of permission bits.

5. The apparatus according to any one of claims 1 to 4, wherein, The device in question is a graphics device.

6. The apparatus according to any one of claims 1 to 4, wherein, The device is one that can perform direct memory access.

7. The apparatus according to any one of claims 1 to 4, wherein, The logic circuit is further configured to: identify a second permission filter among the plurality of permission filters, the second permission filter including a second set of bits for defining a second access permission of the second device to the first memory page, the second set of bits being different from the set of bits, and the second access permission being different from the access permission.

8. A system comprising: The apparatus as described in any one of claims 1 to 4; The CPU; as well as The device.

9. An apparatus comprising: Central Processing Unit (CPU); as well as An Input / Output Memory Management Unit (IOMMU) coupled to the CPU, the IOMMU including logic circuitry using a shared page table containing entries shared by the CPU and the device, the logic circuitry being used for: Receive a memory access request for a first memory page from the device; Identify a first permission filter among multiple permission filters, the first permission filter including a set of bits for defining the device's access permissions to the first memory page; Based on applying the set of bits of the first permission filter to the set of permission bits of the first entry in the shared page table, it is determined whether the memory access request to the first memory page is allowed. In response to determining that the memory access request to the first memory page is permitted, the memory access request is granted; as well as A page fault is triggered in response to the determination that the memory access request to the first memory page is not permitted.

10. The apparatus of claim 9, wherein, Applying the bit set of the first permission filter to the permission bit set of the first entry includes performing a logical AND operation on the bit set of the first permission filter and the permission bit set of the first entry.

11. The apparatus of claim 9, wherein, The multiple permission filters include seven permission filters.

12. The apparatus of claim 9, wherein, The first entry includes the set of permission bits.

13. The apparatus according to any one of claims 9 to 12, wherein, The device in question is a graphics device.

14. The apparatus according to any one of claims 9 to 12, wherein, The device is one that can perform direct memory access.

15. The apparatus according to any one of claims 9 to 12, wherein, The logic circuit is further configured to: identify a second permission filter among the plurality of permission filters, the second permission filter including a second set of bits for defining a second access permission of the second device to the first memory page, the second set of bits being different from the set of bits, and the second access permission being different from the access permission.

16. A system comprising: The apparatus as described in any one of claims 9 to 12; as well as The device.

17. An apparatus comprising: The apparatus for use is for using a shared page table, which includes entries shared by a central processing unit (CPU) and the device. A means for receiving, for receiving from the device a memory access request for a first memory page; The means for identification is used to identify a first permission filter among a plurality of permission filters, the first permission filter including a set of bits for defining the device’s access permissions to the first memory page; The means for determining whether the memory access request to the first memory page is permitted is based on the set of permission bits of the first permission filter applied to the set of permission bits of the first entry of the shared page table. A means for granting permission, for granting the memory access request in response to determining that the memory access request to the first memory page is permitted; as well as A means for triggering a page fault in response to determining that the memory access request to the first memory page is not permitted.

18. The apparatus of claim 17, wherein: The means for use includes logic circuitry for using the shared page table; The means for receiving includes logic circuitry for receiving the memory access request for the first memory page from the device. The device for identification includes logic circuitry for identifying the first permission filter; The means for determining includes logic circuitry for determining whether the memory access request to the first memory page is permitted based on applying the set of bits of the first permission filter to the set of permission bits of the first entry. The means for granting permission includes logic circuitry for granting the memory access request in response to determining that the memory access request to the first memory page is permitted. as well as The means for triggering includes logic circuitry for triggering a page fault in response to determining that the memory access request to the first memory page is not permitted.

19. The device as claimed in claim 17, wherein, Applying the bit set of the first permission filter to the permission bit set of the first entry includes performing a logical AND operation on the bit set of the first permission filter and the permission bit set of the first entry.

20. The device as claimed in claim 17, wherein, The multiple permission filters include seven permission filters.

21. The device as claimed in any one of claims 17 to 20, wherein, The first entry includes the set of permission bits.

22. The device as claimed in any one of claims 17 to 20, wherein, The identification device is also used to identify a second permission filter among the plurality of permission filters. The second permission filter includes a second set of bits for defining a second access permission of the second device to the first memory page. The second set of bits is different from the set of bits, and the second access permission is different from the access permission.

23. A method comprising: A shared page table is used, which includes entries shared by the central processing unit (CPU) and the device; Receive a memory access request for a first memory page from the device; Identify a first permission filter among multiple permission filters, the first permission filter including a set of bits for defining the device's access permissions to the first memory page; Based on applying the set of bits of the first permission filter to the set of permission bits of the first entry in the shared page table, it is determined whether the memory access request to the first memory page is allowed. In response to determining that the memory access request to the first memory page is permitted, the memory access request is granted; as well as A page fault is triggered in response to the determination that the memory access request to the first memory page is not permitted.

24. The method of claim 23, wherein, Applying the bit set of the first permission filter to the permission bit set of the first entry includes performing a logical AND operation on the bit set of the first permission filter and the permission bit set of the first entry.

25. The method of claim 23, wherein, Identifying the first permission filter includes identifying the first permission filter from seven permission filters, and wherein the first entry includes the permission bit set.

26. A machine-readable storage medium having a computer program product stored thereon, the computer program product including instructions that, when executed by one or more machines, cause the one or more machines to perform the method as described in any one of claims 23 to 25.

27. A system comprising: The system-on-a-chip (SoC) includes a central processing unit (CPU), a memory management unit (MMU), and an input / output memory management unit (IOMMU), wherein the IOMMU includes one or more context entries, filter registers, and filter logic circuits. One or more peripheral devices; and The main memory includes one or more page tables and addressable memory, wherein each page table may include multiple page table entries, and each page table entry corresponds to a mapping between virtual pages and physical pages of the memory. The system is configured to trigger a notification prior to the first write operation by the peripheral device or the CPU to a memory page.

28. The system according to claim 27, wherein, The filter logic circuit is also configured to: in response to determining that the first write request to a memory page from the peripheral device or the CPU fails due to a permission bit prohibiting write, update the corresponding permission bit in the page table entry to allow subsequent write requests.

29. The system according to claim 27, wherein, The context entry may include the root address of the page table to which the corresponding peripheral device and / or the CPU is mapped or assigned, and may be consulted to determine one or more permission filters for the corresponding peripheral device and / or the CPU.

30. The system of claim 27, wherein the filter logic circuit is configured to: after applying the filter and a write request fails, update the page table entry permission bits to grant the corresponding device or CPU write permission to the page.

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