Integrated circuit device and manufacturing method thereof

Abstract

The integrated circuit device includes: a first active region structure stack extending in a first direction including a lower active region structure and an upper active region structure stacked on each other; a front side power rail extending in the upper conductive layer over the lower and upper active region structures; a backside power rail extending in the lower conductive layer below the lower and upper active region structures; a plurality of vertical power line arrays, each vertical power line extending in a second direction perpendicular to the first direction in a conductive layer different from the upper conductive layer and the lower conductive layer; and a filling unit having a section of the first active region structure stack therein and having a power via connection extending in a third direction and conductively connecting the front-side power rail and the back-side power rail, and wherein the filling unit is located between two vertical power lines. The embodiment of the invention also relates to a method for manufacturing the integrated circuit device.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit devices and methods for manufacturing the same. Background Technology

[0002] Integrated circuit design is becoming increasingly complex, and there is a growing desire to increase the area density of circuit structures accordingly. One method to increase the area density of integrated circuits is to employ a three-dimensional device structure and place power and / or signal structures on the top and bottom of this three-dimensional device structure. Summary of the Invention

[0003] Some embodiments of this application provide an integrated circuit device, including: a first active region structure stack extending along a first direction parallel to a surface of a substrate, the first active region structure stack including a lower active region structure and an upper active region structure stacked on the substrate along a third direction perpendicular to the substrate; a front power rail extending along the first direction in an upper conductive layer above the lower and upper active region structures; a back power rail extending along the first direction in a lower conductive layer below the lower and upper active region structures; a vertical power line array, wherein each vertical power line in the vertical power line array extends along a second direction parallel to the surface of the substrate in a conductive layer different from the upper and lower conductive layers, the second direction being perpendicular to the first direction; and a filler unit having a segment of the first active region structure stack and having a power via connector extending along a third direction and conductively connecting the front power rail to the back power rail, wherein the filler unit is located between two of the vertical power lines.

[0004] Some other embodiments of this application provide an integrated circuit device, including: a plurality of active region structure stacks, each active region structure stack extending along a first direction parallel to the surface of a substrate, wherein the plurality of active region structure stacks includes a first active region structure stack extending along the first direction between a second active region structure stack and a third active region structure stack; a front power rail located in an upper conductive layer above the plurality of active region structure stacks; a back power rail located in a lower conductive layer below the plurality of active region structure stacks; and a filler unit having a segment of the first active region structure stack and a power via connector. The power via connector conductively connects the front power rail to the back power rail, wherein the power via connector extends along a third direction perpendicular to the surface of the substrate, and wherein the filling cell has no dynamic transistors, the dynamic transistors being configured to have channels whose states change over time; and a logic circuit cell adjacent to the filling cell, the logic circuit cell having a segment of the second active region structure stack, wherein the filling cell has vertical cell boundaries extending along a reference line in the second direction, the reference line being between two vertical cell boundaries of the logic circuit cell, the second direction being perpendicular to the first direction.

[0005] Some embodiments of this application provide a method for manufacturing an integrated circuit device, the method comprising: forming a first active region structure stack extending along a first direction parallel to the surface of a substrate, the formation of the first active region structure stack comprising: forming a lower active region structure; and forming an upper active region structure stacked with the lower active region structure along a third direction perpendicular to the substrate; forming a front power rail in an upper conductive layer above the lower active region structure and the upper active region structure; forming a back power rail in a lower conductive layer below the lower active region structure and the upper active region structure; and forming a filling cell having a segment of the first active region structure stack, the formation of the filling cell comprising: forming a power via connector extending along the third direction and conductively connecting the front power rail to the back power rail, wherein the filling cell is formed without any dynamic transistors, the dynamic transistors being configured to have channels whose states change over time. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1This is a layout diagram of an integrated circuit according to some embodiments.

[0008] Figure 2A This is a layout diagram of a logic circuit unit including an inverter circuit according to some embodiments.

[0009] Figures 2B-2D This is a cross-sectional view of a logic circuit unit including an inverter circuit according to some embodiments.

[0010] Figure 3A This is a layout diagram of logic circuit units according to some embodiments.

[0011] Figure 3B This is a cross-sectional view of a logic circuit unit according to some embodiments.

[0012] Figure 4A It is a layout diagram of logic circuit units according to some embodiments.

[0013] Figure 4B This is a cross-sectional view of a logic circuit unit according to some embodiments.

[0014] Figure 5A This is a layout diagram of the filling units according to some embodiments.

[0015] Figures 5B to 5D This is a cross-sectional view of the filling unit according to some embodiments.

[0016] Figure 6A This is a layout diagram of the filling units according to some embodiments.

[0017] Figures 6B to 6D This is a cross-sectional view of the filling unit according to some embodiments.

[0018] Figure 7A This is a layout diagram of the filling units according to some embodiments.

[0019] Figures 7B to 7D This is a cross-sectional view of the filling unit according to some embodiments.

[0020] Figures 8A to 8B This is a cross-sectional view of an integrated circuit according to some embodiments.

[0021] Figures 9A to 9D This is a schematic diagram of the layout formation stage according to some embodiments.

[0022] Figure 10 This is a flowchart of a layout formation method according to some embodiments.

[0023] Figure 11 This is a flowchart of a method for manufacturing an integrated circuit with filling cells according to some embodiments.

[0024] Figure 12 This is a flowchart of a method for manufacturing an IC device according to some embodiments.

[0025] Figure 13 This is a block diagram of an IC device design system according to some embodiments.

[0026] Figure 14 This is a block diagram of an IC manufacturing system and its related manufacturing processes according to some embodiments. Detailed Implementation

[0027] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0029] In integrated circuits with conductors (e.g., power conductors) located on the top and bottom sides of a three-dimensional device structure, it is sometimes necessary to provide conductors that pass through the three-dimensional structure to connect the top and bottom conductors. For example, in some cases, front and back power rails are connected to distribute a common power supply voltage to the front and back sides of the integrated circuit. Such connections occupy areas in the integrated circuit that would otherwise be available for functional circuitry (e.g., logic circuitry (or logic circuit cells)). Furthermore, although modern integrated circuit designs are extremely dense (i.e., efficiently utilizing substrate areas (e.g., wafer or die areas) to implement functional circuitry), the device area utilization of functional circuitry may be lower than the maximum available substrate area. Therefore, there may be areas on the substrate that are not used for functional circuitry (e.g., logic circuit cells).

[0030] An integrated circuit according to some embodiments includes one or more fill cells containing conductors connecting front-side power rails and rear-side power rails. In some embodiments, fill cells are disposed in areas not used for functional circuitry, such as spaces in a layout row not used for logic cells. In some embodiments, the size of the fill cells is adjusted based on the remaining space within the row after the logic cells are laid out. The location, number, and / or size of the fill cells can be adapted to unused layout areas (e.g., remaining areas after the logic cells are laid out) to achieve front and rear-side power connections without area loss or limiting the logic cell layout. In some embodiments, the fill cells provide sufficient front and rear-side power connections so that other front and rear-side power structures (e.g., regular arrangements placed in front of logic cells) are reduced in number and / or have increased layout spacing, thereby increasing the available area for the logic cell layout.

[0031] Figure 1 This is a schematic layout diagram of an integrated circuit 100 according to some embodiments.

[0032] Integrated circuit 100 includes multiple rows of cells. In Figure 1 As an example, three rows of cells (i.e., the first row 110A, the second row 110B, and the third row 110C) are explicitly shown, each extending along the X direction. The second row 110B is located between the first row 110A and the second row 110C relative to the Y direction. In other rows of the integrated circuit 100, such as in the regions adjacent to the first row 110A and / or the third row 110C, no [further details are needed]. Figure 1 As explicitly shown in the diagram. In some embodiments, each of the first row 110A, the second row 110B, and the third row 110C includes one or more active regions extending along the X direction on the substrate. In some embodiments, the active regions include nanosheets, such as nanosheets of silicon or other semiconductors. In some embodiments, the active regions include nanowires. In some embodiments, each of the rows 110A-110C includes a group of first-type active region structures 80F and second-type active region structures 80B stacked along the Z direction (perpendicular to the substrate). In some embodiments, one or both of the first-type active region structure 80F and the second-type active region structure 80B include nanosheets, nanowires, etc.

[0033] Integrated circuit 100 includes multiple power rails 20F / 20B and 40F / 40B extending along the X direction. Figure 1In this configuration, the first front power rail 20F overlaps with the first back power rail 20B, and the second front power rail 40F overlaps with the second back power rail 40B. The first and second front power rails 20F and 40F are located in the upper conductive layer. The first and second back power rails 20B and 40B are located in the lower conductive layer. In some embodiments, the first and second back power rails 20B and 40B are located on the same side of the substrate as the first and second front power rails 20F and 40F, for example, by forming the first and second back power rails 20B and 40B as buried power rails, and then forming an active region structure, a contact structure (MD structure), a gate structure, etc., above the buried power rails 20B and 40B. In other embodiments, the first and second back-side power rails 20B, 40B and the first and second front-side power rails 20F, 40F are located on opposite sides of the substrate, for example, by forming the first and second back-side power rails 20B, 40B on the side of the substrate opposite to the active region structure, contact structure (MD structure), gate structure, etc.

[0034] Power rails 20F / 20B and 40F / 40B are staggered relative to the Y direction. Each of power rails 20F / 20B and 40F / 40B overlaps with a boundary extending in the X direction between the two rows of cells. In some embodiments, each power rail 20F / 20B is configured to maintain a first power supply voltage (e.g., one of VDD or VSS), and each power rail 40F / 40B is configured to maintain a second power supply voltage different from the first power supply voltage (e.g., the other of VDD or VSS). In other embodiments, two or more adjacent rows of power rails are configured to maintain the same power supply voltage, i.e., the power supply voltages are not alternated row by row but arranged in different patterns. Furthermore, although Figure 1 The diagram shows a pair of first front and back power rails 20F / 20B and a second front and back power rail 40F / 40B, but in some embodiments, one of the first front or back power rails 20F or 20B is omitted in one or more rows, and / or one of the second front or back power rails 40F or 40B is omitted in one or more rows.

[0035] In integrated circuit 100, logic circuit units 101 and 104, and fill units 181-182 and 185 are disposed in the first row 110A. Logic circuit units 102 and 105-106, and fill units 183 and 186 are disposed in the second row 110B. Logic circuit units 103 and 107, and fill units 184 and 187 are disposed in the third row 110C. In other embodiments, the first, second, and / or third rows 110A, 110B, and / or 110C may contain more or fewer logic circuit units and / or more or fewer fill units. Examples of logic circuit units include inverter gate units, NAND gate units, NOR gate units, AND-OR-NOT (AOI) logic gate units, flip-flop circuit units, etc.

[0036] The filling unit includes a power via connector that electrically connects the front power rail to the back power rail. The power via connector extends along the Z-direction, i.e., perpendicular to the substrate surface. In some embodiments, the filling unit uses a conductor disposed between a first conductor of the conductive MO layer and a second conductor of the conductive BMO layer to connect the front and back power rails. In some embodiments, the filling unit uses a conductor disposed between the first conductor of the conductive MO layer and the second conductor of the conductive BMO layer to connect the front and back power rails, without using conductors above or below the MO layer to connect the front and back power rails.

[0037] Each fill cell does not perform any logic operation. In some embodiments, the fill cell does not have any dynamic transistors, while the logic circuit cell has at least one dynamic transistor. Here, a dynamic transistor refers to a transistor whose channel state is configured to change over time. That is, during the circuit operation of the logic circuit cell, the dynamic transistor is sometimes in a conducting state and sometimes in a non-conducting state. In some embodiments, no transistors are implemented inside the fill cell. In some embodiments, a transistor is implemented inside the fill cell, but the channel state of the transistor is configured not to change over time (such a transistor may be referred to as a non-dynamic transistor). In some embodiments, a transistor is implemented inside the fill cell, with its source and drain connected to the same constant voltage or power supply, and its gate connected to a constant voltage or power supply, etc. (such a transistor may also be referred to as a non-dynamic transistor). In some embodiments, the transistor included in the fill cell has one or more sources, drains, and gates that are not connected to a power supply or signal (e.g., in a floating state) (such a transistor may also be referred to as a non-dynamic transistor). In some embodiments, one or more fill cells include dynamic transistors and / or non-dynamic transistors that are logically decoupled from the logic circuit cell.

[0038] The following section will take filling unit 181 as an example to provide a detailed explanation of various aspects of filling units 181-187.

[0039] exist Figure 1 In the figure, integrated circuit 100 includes an array of vertical power lines extending along the Y direction. The figure illustrates a first vertical power line 70A, a second vertical power line 70B, and a third vertical power line 70C as examples. Each vertical power line in this array extends along the Y direction in a conductive layer different from the upper conductive layer (wherein it is used to implement the first and second front power rails 20F and 40F) and the lower conductive layer (wherein it is used to implement the first and second back power rails 20B and 40B). In some embodiments, the first vertical power line 70A is coupled to a first power supply voltage (e.g., one of VDD or VSS), the second vertical power line 70B is coupled to a second power supply voltage (e.g., the other of VDD or VSS), and the third vertical power line is coupled to the first power supply voltage.

[0040] The vertical power lines correspond to (e.g., vertically overlap with) power tap units that connect the power supply between the front and back sides of integrated circuit 100. A first vertical power line 70A corresponds to a first power tap structure region 75A, a second vertical power line 70B corresponds to a second power tap structure region 75B, and a third vertical power line 70C corresponds to a third power tap structure region 75C. In some embodiments, the vertical power lines and their corresponding power tap structure regions are alternately arranged in the X direction, such that the third vertical power line 70C and its corresponding third power tap structure region 75C are identical to the first vertical power line 70A and the first power tap structure region 75A, respectively. In some embodiments, all vertical power lines do not pass through or vertically overlap any filler unit.

[0041] In some embodiments, the first row 110A includes a first stack of a first type active region structure 80F and a second type active region structure 80B (extending along the row direction (X direction) in the first row 110A), the second row 110B includes a second stack of the first type active region structure 80F and the second type active region structure 80B (extending along the row direction (X direction) in the second row 110B), and the third row 110C includes a third stack of the first type active region structure 80F and the second type active region structure 80B (extending along the row direction (X direction) in the third row), and each of the first, second, and third vertical power lines 70A, 70B, and 70C extends across the first, second, and third stacks of the first and second type active region structures 80F and 80B. In some embodiments, for a fill cell located in the second row 110B, neither a first stack of active region structures nor a third stack of active region structures passes through the fill cell.

[0042] exist Figure 1In this embodiment, the first, second, and third power tap structure regions 75A, 75B, and 75C are arranged with a regular pitch along the X direction. In some embodiments, the first, second, and third power tap structure regions 75A, 75B, and 75C are arranged with gate pitch or contact polysilicon pitch (CPP) as integer multiples. In some embodiments, the power tap structure regions 75A, 75B, and 75C are contained within one or more power tap units aligned along the Y direction. In some embodiments, each of the first, second, and third power tap structure regions 75A, 75B, and 75C corresponds to a power tap unit of multiple rows in height. In other embodiments, each of the first, second, and third power tap structure regions 75A, 75B, and 75C corresponds to a plurality of power tap units aligned along the Y direction. Figure 1 In this embodiment, the first, second, and third power tap structure regions 75A, 75B, and 75C each extend beyond their respective row boundaries in the Y direction (i.e., beyond the upper boundary of the first row 110A and below the lower boundary of the third row 110C), indicating that the first, second, and third power tap structure regions 75A, 75B, and 75C simultaneously extend above the first row 110A and below the third row 110C in the Y direction. In other embodiments ( Figure 1 In some embodiments (not shown), the top and / or bottom of the power tap structure area are aligned with the row boundary. Figure 1 In the diagram (not shown), the height of the power tap structure area in the row height direction (Y direction) is equal to or less than one row.

[0043] In some embodiments, power tap units corresponding to the first, second, and third power tap structure regions 75A, 75B, and 75C are placed in the layout of the integrated circuit 100, prior to the arrangement of logic circuit units 101-107 and the arrangement of fill units 181-187. In some embodiments, units corresponding to the first, second, and third power tap structure regions 75A, 75B, and 75C are placed in the layout of the integrated circuit 100, prior to the arrangement of logic circuit units 101-107, and the arrangement of logic circuit units 101-107 precedes the arrangement of fill units 181-187.

[0044] In some embodiments, fill cells are placed in the layout of integrated circuit 100 after logic circuit cells are arranged. In some embodiments, the dimensions of fill cells 181-187 are designed to have: after placing cells (logic circuit cells 101-107) corresponding to the first, second, and third power tap structure regions 75A, 75B, and 75C, the cell width (along the X direction or the row extension direction) based on the remaining space in rows 110A-110C.

[0045] As previously described, fill cells include power via connectors that electrically connect the front power rail to the rear power rail. In some embodiments, wider fill cells (i.e., wider in the row extension direction X) include power via connectors that are wider than those of narrower fill cells (i.e., wider in the row extension direction X). In other embodiments, wider fill cells include a greater number of power via connectors than narrower fill cells. Including fill cells in the layout enhances the electrical connection between the front and rear power rails, helping to reduce the IR drop between the front and rear power networks. In some embodiments, fill cells improve the area utilization of the layout. For example, if logic circuit cells occupy 80 percent of the available cell area, some or all of the fill cells can be arranged in the remaining 20 percent of the available cell area to provide additional electrical connection between the front and rear power rails. In some embodiments, the enhanced electrical connectivity between the front and rear conductors by fill cells can reduce the number of other front and rear connection areas (such as power taps) and / or increase the spacing between them. In some embodiments, the area utilization of logic circuit cells can be improved by arranging one or more fill cells while simultaneously increasing the X-direction pitch of the power taps.

[0046] In some embodiments, one or more vertical boundaries (i.e., Y-direction boundaries) of the fill cell are offset relative to one or more vertical boundaries of the logic circuit cell in the row extension direction (i.e., offset in the X-direction). Figure 1 In this example, the offset is illustrated by reference line 109. Reference line 109 extends in the vertical direction (Y direction) and is parallel to the vertical cell boundaries of the fill cell and logic circuit cell. Fill cell 183, located in row 110B, has a vertical cell boundary 183bv extending vertically along reference line 109. The vertical cell boundary 183bv of fill cell 183 is located between two vertical cell boundaries of logic circuit cell 101, which is adjacent to fill cell 183 in the first row 110A.

[0047] In the example above, the filling unit 183 is located in the row (second row 110B) adjacent to the row (first row 110A) containing the logic circuit unit 101. In some embodiments, the filling unit 183 includes a first set of segments (in the second row 110B) of a first type of active region structure 80F and a second type of active region structure 80B, while the logic circuit unit 101 includes a second set of segments (in the first row 110A) of the first type of active region structure 80F and the second type of active region structure 80B.

[0048] Figure 2A This is a layout diagram of a logic circuit unit 101 including an inverter circuit according to some embodiments. In some embodiments, Figure 2A The logic circuit unit 101 corresponds to Figure 1Logic circuit unit 101. In some embodiments, Figure 2A The logic circuit unit 101 corresponds to Figure 1 One or more logic circuit units 102-107 are included. This inverter circuit is merely an example of a logic circuit, and in other embodiments, logic circuit unit 101 is implemented as other logic circuits.

[0049] Figures 2B-2D According to some embodiments, including Figure 2A A cross-sectional view of the logic circuit unit 101 in the inverter circuit. Specifically, the logic circuit unit 101 is composed of... Figure 2A The cross-sectional views in the cutting planes specified by lines A-A', B-B', and C-C' are respectively in Figure 2B , Figure 2C and Figure 2D Described in the text. Figure 2A The upper parts of the midlines A-A', B-B', and C-C' (i.e., A, B, and C) correspond to Figures 2B-2D On the right side of the middle.

[0050] Figure 2A The layout diagram includes an upper part (labeled "UPPER") and a lower part (labeled "LOWER"). Logic circuit cell 101 includes a first horizontal cell boundary 202 and a second horizontal cell boundary 208, which extend along the X direction and are spaced apart in the Y direction. Logic circuit cell 101 also includes a first vertical cell boundary 201 and a second vertical cell boundary 209, which extend along the Y direction and are spaced apart in the X direction.

[0051] The upper part of the layout diagram includes a layout pattern for specifying the first type of active region structure 80F, gate conductors 252F, 255F and 258F, terminal conductors 234F and 236F, upper layer conductor 222F, first front power rail 20F, second front power rail 40F, inter-terminal connector MDL1, dummy gate conductor g251F at the first vertical cell boundary 201, dummy gate conductor g259F at the second vertical cell boundary 209, and gate via connector VGF. Although Figure 2A A single upper-layer conductor 222F extending in the X direction is shown in the upper layer of logic circuit unit 101. However, in various embodiments, two or more conductors extend parallel to each other in the upper layer of logic circuit unit 101, while being spaced apart from each other in the Y direction, for example, with a regular pitch. Figure 2A In the middle, the upper layer conductor 222F, the first front power rail 20F, and the second front power rail 40F are in the same conductive layer, for example, in the first metallization layer M0.

[0052] The lower part of the layout diagram includes layout patterns for specifying the second type of active region structure 80B, gate conductors 252B, 255B and 258B, terminal conductors 234B and 236B, lower layer conductor 222B, first back-side power rail 20B, second back-side power rail 40B, terminal connector MDL1, dummy gate conductor g251B at the first vertical cell boundary 201, and dummy gate conductor g259B at the second vertical cell boundary 209, and various via connectors VDB. Although Figure 2A A lower-level conductor 222B extending in the X direction is shown in the lower layer of logic circuit unit 101, but in various embodiments, two or more conductors extend parallel in the lower layer of logic circuit unit 101 while being spaced apart from each other in the Y direction, for example with a regular pitch. Although Figure 2A A pair of conductors 222F / 222B is shown, but it should be understood that in some embodiments, this pair of conductors 222F / 222B is only one of a plurality of parallel-positioned wiring lines in the upper and lower conductive layers. The number of upper-layer conductors 222F and the number of lower-layer conductors 222B are the same in some embodiments and different in others. Figure 2A In the middle, the lower layer conductor 222B, the first back-side power rail 20B, and the second back-side power rail 40B are in the same conductive layer, for example, in the first back-side metallization layer BMO.

[0053] exist Figure 2A In the layout diagram, each of the first type active region structure 80F and the second type active region structure 80B extends along the X direction. Individual gate conductors (e.g., 252F, 255F, 258F, 252B, 255B, and 258B) and individual terminal conductors (e.g., 234F, 236F, 234B, and 236B) extend along the Y direction. In some embodiments, the first type active region structure 80F and the second type active region structure 80B are stacked on the front side of the substrate and offset relative to the second type active region structure along the Z direction, i.e., offset perpendicular to the substrate. The stacking of the first type active region structure 80F and the second type active region structure 80B along the Z direction also... Figures 2B-2D Depicted in a cross-sectional view. In Figure 2A and Figures 2B-2D In this system, the X, Y, and Z directions are orthogonal to each other and form an orthogonal coordinate system.

[0054] exist Figure 2AIn the layout diagram, the gate conductor 255F extending in the Y direction intersects with the first type active region structure 80F at the channel region of the first type transistor, and the gate conductor 255B extending in the Y direction intersects with the second type active region structure 80B at the channel region of the second type transistor. The terminal conductors 234F and 236F extending in the Y direction intersect with the first type active region structure 80F at one of the terminal regions of the first type transistor. The terminal conductors 234B and 236B extending in the Y direction intersect with the second type active region structure 80B at one of the terminal regions of the second type transistor. The terminal region of the transistor is either the source region or the drain region of the transistor.

[0055] In some embodiments, the first-type transistor with a first-type active region structure 80F is a PMOS transistor, and the second-type transistor with a second-type active region structure 80B is an NMOS transistor. In other embodiments, the first-type transistor with a first-type active region structure 80F is an NMOS transistor, and the second-type transistor with a second-type active region structure 80B is a PMOS transistor. The complementary field-effect transistor (CFET) device is formed by stacking the first-type transistor and the second-type transistor relative to the Z-direction.

[0056] In some embodiments, the first type active region structure 80F and the second type active region structure 80B each comprise one or more nanosheets. Figure 2A Both PMOS and NMOS transistors in this context can be referred to as nanosheet transistors. In some embodiments, the first type active region structure 80F and the second type active region structure 80B each contain one or more nanowires. Figure 2A Both PMOS and NMOS transistors in this context can be referred to as nanowire transistors.

[0057] exist Figure 2A In the layout diagram, the first and second front power rails 20F and 40F, extending along the X direction, are located in the upper conductor layer, while the back power rails 20B and 40B, extending along the X direction, are located in the lower conductor layer. For example... Figures 2B-2D As shown, the upper conductor layer is located above both the first type active region structure 80F and the second type active region structure 80B, while the lower conductor layer is located below both the first type active region structure 80F and the second type active region structure 80B. Furthermore, an upper conductor 222F extending along the X direction is implemented in the upper conductor layer, and a lower conductor 222B extending along the X direction is implemented in the lower conductor layer.

[0058] exist Figure 2A and Figures 2B-2DIn the example shown, a first-type transistor is coupled to a second-type transistor to form an inverter circuit configured to receive voltage supplies from power rails 20F / 20B and 40F / 40B.

[0059] exist Figure 2A and Figure 2D In this circuit, terminal conductor 236F (serving as the drain terminal of a first-type transistor) and terminal conductor 236B (serving as the drain terminal of a second-type transistor) are electrically connected together via an inter-terminal connector MDLI. Terminal conductors 236F and 236B form the output node of the inverter circuit. Terminal conductor 236B is connected to the lower conductor 222B via a through-hole connector VDB, thereby configuring the lower conductor 222B to receive the output signal of the inverter circuit from terminal conductor 236B.

[0060] exist Figure 2A and Figure 2C In this configuration, gate conductors 255F and 255B are connected to each other to form the input node of the inverter circuit. Gate conductor 255F is connected to the upper conductor 222F via a gate via connector VGF, thereby configuring gate conductor 255F (as the input node of the inverter circuit) to receive input signals from the upper conductor 222F. In other embodiments (not shown in...) Figures 2A-2B The gate conductor 255B is connected to the lower conductor 222B via a through-hole connector, thereby configuring the gate conductor 255B (as the input node of the inverter circuit) to receive input signals from the lower conductor 222B.

[0061] exist Figure 2A and Figure 2B In this configuration, the terminal conductor 234F of the source terminal of a first type of transistor is electrically connected to a first back-side power rail 20B via a via connector 280. The terminal conductor 234B of the source terminal of a second type of transistor is electrically connected to a second back-side power rail 40B via a lower via connector VDB. In some embodiments, the first type of transistor is a PMOS transistor and the second type of transistor is an NMOS transistor, the first back-side power rail 20B is configured to provide a first power supply voltage VDD, and the second back-side power rail 40B is configured to provide a second power supply voltage VSS. In other embodiments, the first type of transistor is an NMOS transistor and the second type of transistor is a PMOS transistor, the first back-side power rail 20B is configured to provide the second power supply voltage VSS, and the second back-side power rail 40B is configured to provide the first power supply voltage VDD.

[0062] exist Figure 2AIn this logic circuit unit 101, a first type of transistor with gate conductor 255F and a second type of transistor with gate conductor 255B are stacked to form a CFET device. The inverter circuit in the logic circuit unit 101 is implemented as a first CFET device with gate conductors 255F and 255B. Additional circuitry in the logic circuit unit 101 is implemented as other CFET devices, such as a second CFET device with gate conductors 252F and 252B, and a third CFET device with gate conductors 258F and 258B. Figure 2A The layout patterns for specifying the terminal conductors of the second and third CFET devices, as well as the layout patterns for specifying other components in the additional circuit (such as through-hole connectors and inter-terminal connectors), are not shown.

[0063] One side of the logic circuit cell 101 (at the first vertical cell boundary 201) is defined by dummy gate conductors g251F and g251B, and the opposite side (at the second vertical cell boundary 209) is defined by dummy gate conductors g259F and g259B. The first vertical cell boundary 201 of the logic circuit cell 101 is aligned with the dummy gate conductors g251F and g251B, and the second vertical cell boundary 209 is aligned with the dummy gate conductors g259F and g259B. In some embodiments, the cell width of the logic circuit cell 101, measured along the X direction, corresponds to the pitch between dummy gate conductors g251F and g259F, or the pitch between dummy gate conductors g251B and g259B.

[0064] The dummy gate conductor g251F corresponds to the boundary isolation region i251F. The dummy gate conductor g259F corresponds to the boundary isolation region i259F. Each of the boundary isolation regions i251F and i259F defines an isolation region in the first type active region structure 80F at the intersection of the corresponding dummy gate conductor and the first type active region structure 80F. The boundary isolation regions i251F and i259F in the first type active region structure 80F isolate the active regions (i.e., channel region, source region, and drain region) of the first type transistor in the logic circuit unit 101 from the active regions of other first type transistors in adjacent logic circuit units (in the first type active region structure 80F). The dummy gate conductor g251B corresponds to the boundary isolation region i251B. The dummy gate conductor g259B corresponds to the boundary isolation region i259B. Each of the boundary isolation regions i251B and i259B defines an isolation region in the second-type active region structure 80B at the intersection location between the corresponding dummy gate conductor and the second-type active region structure 80B. The boundary isolation regions i251B and i259B in the second-type active region structure 80B isolate the active regions of the second-type transistors in the logic circuit unit 101 from the active regions of other second-type transistors in adjacent logic circuit units (in the second-type active region structure 80B).

[0065] When viewed along a direction perpendicular to the substrate (i.e., in) Figure 2A When viewed in a plan view, the first horizontal cell boundary 202 of the logic circuit cell 101 extending along the X direction overlaps with the second front power rail 40F and the second back power rail 40B. In some embodiments, the first horizontal cell boundary 202 extends along the X direction at the centerline of the second front power rail 40F and / or the second back power rail 40B.

[0066] When viewed in a direction perpendicular to the substrate, i.e. Figure 2A When viewed in a plan view, the second horizontal cell boundary 208 of the logic circuit cell 101 extending along the X direction overlaps with the first front power rail 20F and the first back power rail 20B. In some embodiments, the second horizontal cell boundary 208 extends along the X direction at the centerline of the first front power rail 20F and / or the first back power rail 20B.

[0067] In some embodiments, the cell height of the logic circuit cell 101, measured along the Y direction, is determined by the pitch between the first front power rail 20F and the second front power rail 40F, or by the pitch between the first back power rail 20B and the second back power rail 40B. In other embodiments, the cell height of the logic circuit cell 101 is determined by other elements within the cell.

[0068] Figure 3A This is a layout diagram of logic circuit unit 301 according to some embodiments. In some embodiments, logic circuit unit 301 corresponds to Figure 1 The logic circuit unit 301. In some embodiments, the logic circuit unit 301 corresponds to the logic circuit unit 101. Figure 1 One or more logic circuit units 102-107.

[0069] Figure 3B This is a cross-sectional view of logic circuit unit 301 according to some embodiments. Specifically, Figure 3B It shows along Figure 3A A cross-sectional view of logic circuit unit 301 in the cutting plane defined by the center line A-A'. Figure 3A The upper part of the median A-A' (i.e., A) corresponds to Figure 3B On the right side of the middle.

[0070] The main reference and Figure 2A To describe the differences Figure 3A and will mainly refer to and Figure 2B To describe the differences Figure 3B .

[0071] exist Figure 3A In the upper part (marked "UPPER"), with Figure 2ACompared to the upper part, the logic circuit unit 301 also includes an upper through-hole connector VDF. (See reference) Figure 3A The upper part and reference Figure 3B The upper through-hole connector VDF electrically connects the first front-side power rail 20F to the terminal conductor 234F, which intersects with the first type of active region structure 80F. Therefore, the terminal conductor 234F (which serves as the source terminal of the first type of transistor) is connected not only to the first back-side power rail 20B (as shown in the image) via the through-hole connector 280. Figure 2A (as shown), and in Figure 3A It is also connected to the first front power rail 20F. Therefore, relative to Figures 2A-2B The logic circuit unit 301 is structured as follows: the logic circuit unit 301 also provides a front-to-back power connection between the first front power rail 20F and the first back power rail 20B.

[0072] Figure 4A This is a layout diagram of a logic circuit unit 401 according to some embodiments. In some embodiments, the logic circuit unit 401 corresponds to... Figure 1 The logic circuit unit 401. In some embodiments, the logic circuit unit 401 corresponds to Figure 1 One or more logic circuit units 102-107.

[0073] Figure 4B This is a cross-sectional view of the logic circuit unit 401 according to some embodiments. Specifically, Figure 4B Depicting Figure 4A A cross-sectional view of logic circuit unit 401 in the cutting plane defined by line A-A'. Figure 4A The upper part of the median A-A' (i.e., A) corresponds to Figure 4B On the right side of the middle.

[0074] The main reference is Figure 2A To describe the differences Figure 4A and mainly refer to Figure 2B To describe the differences Figure 4B .

[0075] exist Figure 4A In the upper part (labeled "upper"), with Figure 2A Compared to the upper portion, logic circuit unit 301 also includes an upper through-hole connector VDF. However, referring to... Figure 4A The upper and lower parts, relative to Figure 2A The through-hole connector 280 is omitted. (Refer to...) Figure 4A upper part and Figure 4B The upper through-hole connector VDF electrically connects the terminal conductor 234F, which intersects the first front power rail 20F with the first type of active area structure 80F. However, relative to... Figures 2A-2B Terminal conductor 234F (used as the source terminal of the first type of transistor) is not connected to the first back-side power rail 20B because the through-hole connector 280 is omitted.

[0076] Figure 5A This is a layout diagram of fill unit 581 according to some embodiments. In some embodiments, fill unit 581 corresponds to Figure 1 The filling unit 581. In some embodiments, the filling unit 581 corresponds to the filling unit 181. Figure 1 One or more filler units 182-187.

[0077] Figures 5B-5D This is a cross-sectional view of the filling unit 581 according to some embodiments. Specifically, Figure 5A The cross-sectional views of the filling element 581 of the cutting plane defined by lines A-A', B-B', and C-C' are respectively depicted on... Figure 5B , Figure 5C and Figure 5D middle. Figure 5A The upper portions of the midlines A-A', B-B', and C-C' (i.e., A, B, and C) correspond to respectively Figures 5B-5D On the right side.

[0078] Figures 5A-5D The main reference will be its relationship with Figures 2A-2D Explain the differences.

[0079] As discussed above regarding filler units 181-187, filler unit 581 includes a power through-hole connector that electrically connects the front power rail to the rear power rail.

[0080] exist Figures 5A-5D In the middle, the filling unit 581 is narrower than in the X-axis direction. Figures 2A-2D In the logic circuit unit 101, for example, relative to Figures 2A-2D The logic circuit unit 101 has a smaller gate pitch multiple for the fill unit 581. However, the embodiments are not limited to this. As mentioned above, in some embodiments, the dimensions of the fill units 181-187 are designed to have: after placing the units (logic circuit units 101-107) corresponding to the first, second, and third power tap structure regions 75A, 75B, and 75C, the unit width (along the X direction or the row extension direction) is based on the remaining space in rows 110A-110C. Therefore, in various embodiments, the width of the fill unit 581 may be the same as or wider than the logic circuit unit 101.

[0081] Fill cell 581 includes a power via connector 520, which conductively connects the first front power rail 20F and the first rear power rail 20B. Furthermore, fill cell 581 does not contain any dynamic transistors and does not form an active circuit, therefore relative to… Figures 2A-2D The logic circuit unit 101 omits the gate conductors 252F, 258F, 252B and 258B.

[0082] Fill cell 581 includes terminal conductors 534F and 534B (along line A-A') and terminal conductors 536F and 536B (along line C-C'), but fill cell 581 does not contain any dynamic transistors. Figures 5A-5D In one embodiment, the filling cell 581 includes a non-dynamic transistor whose source, drain, and gate are not connected to a power source or signal, for example, in a floating state.

[0083] Specifically, in filler unit 581, the following is omitted. Figures 2A-2D The gate via connector VGF and the lower via connector VDB of the middle logic circuit unit 101.

[0084] Furthermore, in filling unit 581, since the connection to power lines and signal lines is omitted, relative to... Figures 2A-2D In logic circuit unit 101, terminal conductors 534F and 536F are shortened in the Y direction (row height direction), and terminal conductors 534B and 536B are similarly shortened in the Y direction. However, it should be understood that in other embodiments, the terminal conductors 534F, 536F, 534B and / or 536B of fill unit 581 may have different lengths, and the terminal conductors 534F, 536F, 534B and / or 536B need not be shorter than the corresponding conductors in logic circuit unit 101. Further, in fill unit 581, given the omission of connections to signal lines, relative to... Figures 2A-2D In logic circuit unit 101, gate conductors 555F and 555B are shortened in the Y direction. In some embodiments, shortening the terminal conductors and / or gate conductors reduces overlap with front and / or back power lines and / or signal lines, thereby reducing parasitic capacitance and / or other undesirable coupling effects. However, it should be understood that in other embodiments, the gate conductors 555F and / or 555B of fill unit 581 may have different lengths, and the gate conductors 555F and / or 555B need not be shorter than the corresponding conductors in logic circuit unit 101. The advantage of shortening the terminal conductors and gate conductors is that it allows the terminal conductors and gate conductors to be spaced further away from the power via connector 520, thereby simplifying the manufacturing process and / or allowing the power via connector 520 to be correspondingly increased in the row height direction. Increasing the size of the power via connector 520 helps to reduce the resistance of the connection between the first front power rail 20F and the first back power rail 20B.

[0085] In some embodiments, the segments of the first type active region structure 80F and the second type active region structure 80B in the filling unit 581 have a cross-section that is smaller than the overall average cross-section of the first type and second type active region structures along the row, or a cross-section that is smaller than the cross-section of the segments of the first type and second type active region structures in the logic circuit unit. In some embodiments, the width of the segments of the first type and second type active region structures 80F and 80B in the filling unit 581 along the Y direction is smaller than the average width of the first type and second type active region structures 80F and 80B.

[0086] In fill cell 581, since connections to power and signal lines are omitted, gate conductors 555F and 555B are separated from each other in the Z direction (i.e., not connected together). Furthermore, relative to logic circuit cell 101, since connections to power and signal lines are omitted, the inter-terminal connector MDL1 is also omitted. Not connecting the gate conductors and omitting the inter-terminal connector MDL1 simplifies the manufacture of fill cell 581.

[0087] In filling unit 581, relative to Figures 2A-2D The logic circuit unit 101 has a power via connector 520 that is elongated in the X direction. Elongating the power via connector 520 helps reduce the connection resistance between the first front power rail 20F and the first back power rail 20B. As previously mentioned, the fill cell 581 can be made wider or narrower to fit the remaining space in the row; the power via connector 520 can be made wider or narrower in the X direction corresponding to the width of the fill cell 581.

[0088] Although a single power via connector 520 is shown in fill cell 581 with dimensions designed to match the width of fill cell 581 in the X direction, in other embodiments, multiple via connectors are used instead of changing the dimensions of the via connectors in the X direction, or a combination of multiple via connectors and changing the dimensions of the via connectors in the X direction is used. In some embodiments, multiple via connectors having the same XY footprint are arranged along the width direction of the cell; for example, as the width of the fill cell increases, the number of via connectors arranged in the fill cell increases.

[0089] In some embodiments, the filling unit 581 has a first vertical unit boundary 201 extending in the Y direction, which passes through a first isolation region i251B in the lower active region structure and a second isolation region i251F in the upper active region structure located at the first end of the segments of the first type and the second type active region structures 80F and 80B; and has a second vertical unit boundary 209 extending in the Y direction, which passes through a third isolation region i259B in the lower active region structure and a fourth isolation region i259F in the upper active region structure located at the second end of the segments of the first type and the second type active region structures 80F and 80B.

[0090] Figure 6A This is a layout diagram of the filling unit 681 according to some embodiments. In some embodiments, the filling unit 681 corresponds to Figure 1 The filling unit 681. In some embodiments, the filling unit 681 corresponds to the filling unit 181. Figure 1 One or more filler units 182-187.

[0091] Figures 6B-6D This is a cross-sectional view of the filling unit 681 according to some embodiments. Specifically, Figure 6B , Figure 6C and Figure 6D Correspondingly described along Figure 6A Sectional view of the filling element 681 of the cutting plane defined by centerlines A-A', B-B' and C-C'. Figure 6A The upper portions of the medians A-A', B-B', and C-C' (i.e., A, B, and C) correspond to Figures 6B-6D On the right side of the middle.

[0092] The following will mainly refer to Figures 6A-6D and Figures 2A-2D Explain the differences.

[0093] As discussed above regarding filler units 181-187, filler unit 681 includes a power through-hole connector that electrically connects the front power rail to the rear power rail.

[0094] exist Figures 6A-6D In the middle, the filling unit 681 is narrower than in the X-axis direction. Figures 2A-2DThe logic circuit unit 101 is used. However, the embodiments are not limited to this. As mentioned above, in some embodiments, the dimensions of the fill units 181-187 are designed to have: after placing the units (logic circuit units 101-107) corresponding to the first, second, and third power tap structure regions 75A, 75B, and 75C, the unit width (along the X direction or the row extension direction) based on the remaining space in rows 110A-110C. Therefore, in various embodiments, the width of the fill unit 681 may be the same as or wider than the logic circuit unit 101.

[0095] The filler unit 681 includes a through-hole connector 620 that electrically connects the first front power rail 20F to the first rear power rail 20B. Furthermore, the filler unit 681 does not have any dynamic transistors and does not form an active circuit, therefore relative to… Figures 2A-2D The logic circuit unit 101 omits the gate conductors 252F, 258F, 252B and 258B.

[0096] Fill cell 681 includes terminal conductors 634F and 634B (along line A-A') and terminal conductors 636F and 636B (along line C-C'). However, fill cell 681 does not have any dynamic transistors. Figures 6A-6D In one embodiment, the filling cell 681 includes a non-dynamic transistor whose source, drain, and gate are all coupled to a power source, for example, in a bound, non-floating state.

[0097] Specifically, in fill unit 681, terminal conductor 634F is electrically connected to power through-hole connector 620 via an additional upper through-hole connector VDF (relative to logic circuit unit 101), which is consistent with... Figure 3B The same method is described above. The upper through-hole connector VDF electrically connects the terminal conductor 634F, which intersects the first front-side power rail 20F with the first type of active region structure 80F. Therefore, the terminal conductor 634F (which serves as the source terminal of the first type of transistor) is connected not only to the first back-side power rail 20B (as described above) via the power through-hole connector 620. Figure 2A As shown), in Figure 6A It is also connected to the first front power rail 20F.

[0098] Furthermore, in filling unit 681, relative to Figures 2A-2DIn the logic circuit unit 101, the terminal conductor 636F is extended in the Y direction (unit height direction) to overlap with the first front power rail 20F, and is electrically connected to the power through-hole connector 620 through an additional upper through-hole connector VDF. This upper through-hole connector VDF electrically connects the terminal conductor 636F, where the first front power rail 20F intersects with the first type active region structure 80F. Thus, the terminal conductor 636F (which serves as the drain terminal of the first type transistor) is not only connected to the first back power rail 20B through the power through-hole connector 620, but also... Figure 6A The transistor is connected to the first front-side power rail 20F. Therefore, the source and drain terminals of this first type of transistor are both bonded to the same potential (first front-side power rail 20F).

[0099] Furthermore, in filling unit 681, relative to Figures 2A-2D The logic circuit unit 101 has a gate conductor 655F extended in the Y direction (unit height direction) to overlap with the first front power rail 20F, and electrically connected to the power via connector 620 via an additional upper via connector VDF. This upper via connector VDF electrically connects the gate conductor 655F, which intersects the first front power rail 20F with the first type active region structure 80F. Thus, the gate conductor 655F (which serves as the gate of the first type transistor) is not only connected to the first back power rail 20B via the power via connector 620, but also... Figure 6A The transistor is connected to the first front-side power rail 20F. Therefore, the source, drain, and gate terminals of this first type of transistor are all bonded to the same potential (first front-side power rail 20F).

[0100] Meanwhile, in the filling unit 681, the terminal conductor 634B is electrically connected to the second back-side power rail 40B through the lower through-hole connector VDB, which is in conjunction with... Figures 2A-2D The logic circuit unit 101 is configured in the same way. Therefore, terminal conductor 634B (which serves as the source terminal of the second type of transistor) is connected to... Figures 2A-2D The logic circuit unit 101 is connected to the second back-side power rail 40B in the same manner.

[0101] However, in filling unit 681, relative to Figures 2A-2D The logic circuit unit 101 has a terminal conductor 636B that is elongated in the Y direction (unit height direction) to overlap with the second back-side power rail 40B, and is conductively connected to the second back-side power rail 40B through the lower through-hole connector VDB. Relative to Figures 2A-2DIn logic circuit unit 101, terminal conductor 636B is not connected to lower layer conductor 222B. Lower through-hole connector VDB electrically connects terminal conductor 636B, which intersects the second back-side power rail 40B with the second type active region structure 80B. Therefore, terminal conductor 636B (which serves as the drain terminal of the second type transistor) is connected to the second back-side power rail 40B. Thus, the source and drain terminals of the second type transistor are both bonded to the same potential (second back-side power rail 40B).

[0102] Furthermore, in filling unit 681, relative to Figures 2A-2D In the logic circuit unit 101, the gate conductor 655B is extended in the Y direction (unit height direction) to overlap with the second back-side power rail 40B, and is electrically connected to the second back-side power rail 40B through an additional bottom through-hole connector VDB. This bottom through-hole connector VDB electrically connects the gate conductor 655B, which intersects the second back-side power rail 20B with the second type active region structure 80B. Thus, the gate conductor 655B (which serves as the gate of the second type transistor) is connected to the second back-side power rail 40B. Therefore, the source, drain, and gate terminals of this second type transistor are all bonded to the same potential (second back-side power rail 40B).

[0103] In fill cell 681, gate conductors 655F and 655B are separated from each other in the Z direction (i.e., not connected together). Furthermore, relative to... Figures 2A-2D The logic circuit unit 101 omits the inter-terminal connector MDL1. Eliminating the gate conductor and omitting the inter-terminal connector MDL1 simplifies the manufacturing process of the filling unit 681.

[0104] In filling unit 681, relative to Figures 2A-2D The logic circuit unit 101 has a power via connector 620 that is elongated in the X direction. Elongating the power via connector 620 helps reduce the connection resistance between the first front power rail 20F and the first back power rail 20B. As discussed earlier regarding the fill unit 581, the fill unit 681 can be made wider or narrower to accommodate the remaining space in the row; correspondingly, the power via connector 620 can be made wider or narrower in the X direction corresponding to the width of the fill unit 681.

[0105] Although the filling unit 681 is shown with a single power through-hole connector 620, which is designed to be the width of the filling unit 681 in the X direction, in other embodiments, multiple through-hole connectors are used instead of changing the size of the through-hole connectors in the X direction, or a combination of multiple through-hole connectors and changing the size of the through-hole connectors in the X direction is used. In some embodiments, multiple through-hole connectors having the same XY footprint are arranged along the width direction of the unit, for example, as the width of the filling unit increases, the number of through-hole connectors arranged in the filling unit increases.

[0106] In some embodiments, the filling unit 681 has a first vertical unit boundary 201 extending in the Y direction, which passes through a first isolation region i251B in the lower active region structure and a second isolation region i251F in the upper active region structure at the first end of the segments of the first and second type active region structures 80F and 80B; and has a second vertical unit boundary 209 extending in the Y direction, which passes through a third isolation region i259B in the lower active region structure and a fourth isolation region i259F in the upper active region structure at the second end of the segments of the first and second type active region structures 80F and 80B.

[0107] Figure 7A This is a layout diagram of the filling unit 781 according to some embodiments. In some embodiments, the filling unit 781 corresponds to Figure 1 The filling unit 781. In some embodiments, the filling unit 781 corresponds to the filling unit 181. Figure 1 One or more filler units 182-187.

[0108] Figures 7B-7D This is a cross-sectional view of the filling unit 781 according to some embodiments. Specifically, Figure 7B , Figure 7C and Figure 7D Correspondingly shown Figure 7A A cross-sectional view of the filling element 781 of the cutting plane defined by lines A-A', B-B' and C-C'. Figure 7A The upper portions of the medians A-A', B-B', and C-C' (i.e., A, B, and C) correspond to Figure 7B - The right side of the Journey 7D.

[0109] Main reference Figures 7A-7D and Figures 2A-2D Explain the differences.

[0110] As discussed above regarding filler units 181-187, filler unit 781 includes a power through-hole connector that electrically connects the front power rail to the rear power rail.

[0111] exist Figures 7A-7DIn the middle, the filling unit 781 is narrower than in the X-axis direction. Figures 2A-2D The logic circuit unit 101 is used. However, the embodiments are not limited to this. As mentioned above, in some embodiments, the filling units 181-187 are designed to have the following dimensions: after placing the units (logic circuit units 101-107) corresponding to the first, second, and third power tap structure regions 75A, 75B, and 75C, the unit width (along the X direction or the row extension direction) is based on the remaining space in rows 110A-110C. Therefore, in different embodiments, the width of the filling unit 781 may be the same as or wider than the logic circuit unit 101.

[0112] The filler unit 781 includes a power via connector 720 that electrically connects the first front power rail 20F to the first rear power rail 20B. Furthermore, the filler unit 781 does not have any dynamic transistors and does not form an active circuit, therefore compared to… Figures 2A-2D The logic circuit unit 101 omits the gate conductors 252F, 258F, 252B and 258B.

[0113] exist Figures 7A-7D In this embodiment, the filling unit 781 does not contain a transistor. Specifically, although the first type and the second type active region structures 80F and 80B exist in the filling unit 781, compared to Figures 2A-2D The logic circuit unit 101 omits the terminal conductors and gate conductors. In other embodiments (not shown in...) Figures 7A to 7D As shown in the figure, the first type and second type active region structures 80F and 80B are also omitted in the filling unit 781.

[0114] In the filling unit 781, the power through-hole connector 720 is relative to Figures 2A-2D The logic circuit unit 101 is elongated in the X direction. The elongated power via connector 720 helps reduce the connection resistance between the first front power rail 20F and the first rear power rail 20B. As described above, the fill unit 781 can be made wider or narrower to fit the remaining space in the row; the power via connector 720 can be made wider or narrower in the X direction corresponding to the width of the fill unit 781.

[0115] Although the illustrated filling unit 781 employs a single power via connector 720, which is designed to be the width of the filling unit 781 in the X direction, in other embodiments, multiple via connectors are used instead of changing the dimensions of the via connectors in the X direction, or a combination of multiple via connectors and changing the dimensions of the via connectors in the X direction is used. In some embodiments, multiple via connectors having the same XY footprint are arranged along the width direction of the unit; for example, as the width of the filling unit increases, the number of via connectors arranged in the filling unit increases.

[0116] In some embodiments, the filling unit 781 has a first vertical unit boundary 201 extending in the Y direction, which passes through the first isolation region i251B of the lower active region structure and the second isolation region i251F of the upper active region structure at the first end of the segments of the first and second type active region structures 80F and 80B; and a second vertical unit boundary 209 extending in the Y direction, which passes through the third isolation region i259B of the lower active region structure and the fourth isolation region i259F of the upper active region structure at the second end of the segments of the first and second type active region structures 80F and 80B.

[0117] Figures 8A-8B This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Specifically, the integrated circuit 100 is composed of... Figure 1 The cross-sectional views in the cutting planes specified by lines P-P' and Q-Q' are respectively in Figure 8A and Figure 8B The corresponding description is in the text. Figure 1 The upper portions (i.e., P and Q) of lines P-P' and Q-Q' correspond to Figures 8A-8B On the right side of the middle.

[0118] refer to Figure 1 , Figure 8A and Figure 8B The integrated circuit 100 includes power rails 20F / 20B and 40F / 40B extending in the X direction. A first front power rail 20F perpendicularly overlaps with a first back power rail 20B (i.e., overlaps relative to the Z direction), and a second front power rail 40F perpendicularly overlaps with a second back power rail 40B. The first and second front power rails 20F and 40F are located in an upper conductive layer. The first and second back power rails 20B and 40B are located in a lower conductive layer. Power rails 20F / 20B are staggered with respect to power rails 40F / 40B in the Y direction.

[0119] The first type of active region structure 80F and the second type of active region structure 80B overlap each other in the vertical direction and extend in the X direction, and intersect with power rails 20F / 20B and 40F / 40B relative to the Y direction.

[0120] In the first power tap structure region 75A, the first vertical power line 70A is coupled to the first front power rail 20F of the first, second, and third rows 110, 110B, and 110C via a corresponding upper via connector VDF passing through the interlayer dielectric layer. In the second power tap structure region 75B, the second vertical power line 70B is coupled to the second front power rail 40F of the first, second, and third rows 110, 110B, and 110C via a corresponding upper via connector VDF passing through the interlayer dielectric layer. In some embodiments, the vertical power line is located in the second metallization layer or the M1 metallization layer, the front power rail is located in the first metallization layer or the M0 metallization layer, and the via conductor VDF is located in the first via layer or the VIA0 via layer.

[0121] In the first power tap structure region 75A and the second power tap structure region 75B, conductor 641 extends in a direction perpendicular to the substrate (Z direction) to conductively connect the first front power rail 20F to the first back power rail 20B, and conductor 642 extends in the Z direction to conductively connect the second front power rail 40F to the second back power rail 40B.

[0122] exist Figures 8A-8B In the first and second power tap structures 75A and 75B, there are no transistors. Therefore, conductors 641 and / or 642 can be made larger in the X and / or Y directions, relative to... Figures 8A-8B As shown. For example, in some embodiments, the dimensions of conductors 641 and 642 in the row height direction (Y direction) are the same as those of power rails 20F / 20B and 40F / 40B. Increasing the dimensions of conductors 641 and 642 (i.e., the XY plane footprint) can reduce the resistance between the front and back power rails.

[0123] In other embodiments, the number and / or size of conductors 641 and 642 are reduced, and / or the row pitch of conductors 641 and 642 is increased, thereby providing additional logic circuit cell layout area; additional front-to-back connections are provided by fill cells to fully or partially compensate for the reduced front-to-back conductivity caused by the reduction in the number and / or size of conductors 641 and 642, and / or the increase in the row pitch of conductors 641 and 642.

[0124] Figures 9A-9D These are the various stages of forming the layout according to some embodiments. Figure 10 Based on some embodiments, and Figures 9A-9D The flowchart for the corresponding layout formation method 1000. It should be understood that, in Figure 10 Additional operations may be performed before, during, and / or after Method 1000, and some of these additional operations may only be briefly described herein.

[0125] exist Figure 9A In operation 1010 of method 1000, power rails 20F / 20B and 40F / 40B are arranged in a layout extending along the X direction. The first front power rail 20F is arranged to perpendicularly overlap with the first back power rail 20B (i.e., overlap relative to the Z direction), and the second front power rail 40F is arranged to perpendicularly overlap with the second back power rail 40B. The first and second front power rails 20F and 40F are disposed in an upper conductive layer, and the first and second back power rails 20B and 40B are disposed in a lower conductive layer. Power rails 20F / 20B and power rails 40F / 40B are arranged alternately relative to the Y direction.

[0126] exist Figure 9B In operation 1020 of method 1000, the first, second, and third power tap structures 75A, 75B, and 75C are arranged to be sequentially spaced apart in the X direction, and each of the first, second, and third power tap structures 75A, 75B, and 75C extends in the Y direction to cross the first and second front power rails 20F and 40F. Furthermore, the first, second, and third vertical power lines 70A, 70B, and 70C are arranged to be sequentially spaced apart in the X direction, and each of the first, second, and third vertical power lines 70A, 70B, and 70C extends in the Y direction and vertically overlaps one of the corresponding first, second, and third power tap structures 75A, 75B, and 75C.

[0127] exist Figure 9C In operation 1030 of method 1000, logic circuit units 101-107 are arranged in the first, second, and third rows 110A, 110B, and 110C within the space between the first, second, and third power supply tap structure areas 75A, 75B, and 75C.

[0128] exist Figure 9D In operation 1040 of method 1000, filling units 181-187 are arranged in the first, second, and third rows 110A, 110B, and 110C within the space between logic circuit units 101-107. Figure 9D In this embodiment, the dimensions of fill cells 181-187 are based on the remaining space in rows 110A-110C after the arrangement of logic circuit cells 101-107, meaning that fill cells 181-187 have different dimensions. In other embodiments, the fill cells are all of the same size, and / or multiple smaller fill cells are arranged in a single space.

[0129] Figure 11 This is a flowchart of a method 1100 for manufacturing an integrated circuit with filled cells according to some embodiments. It should be understood that, in Figure 11 Additional operations may be performed before, during, and / or after method 1100, and this document only briefly describes some of these other operations.

[0130] In operation 1102 of method 1100, a lower active region structure extending along the X direction is fabricated on a substrate. For example, refer to... Figures 5B-5D In some embodiments, the second type of active region structure 80B is fabricated on a substrate.

[0131] In operation 1104 of method 1100, a lower gate conductor is formed that intersects with the lower active region structure. For example, refer to Figures 5B-5D This forms a gate conductor 555B that intersects with the second type of active region structure 80B.

[0132] In operation 1106 of method 1100, a lower terminal conductor is formed that intersects with the second type of active region structure 80B. For example, refer to Figures 5B-5D Terminal conductors 534B and 536B are formed that intersect with the second type of active region structure 80B.

[0133] In operation 1108 of method 1100, an upper active region structure extending along the X direction is fabricated to stack with a lower active region structure. For example, refer to... Figures 5B-5D The first type of active region structure 80F is manufactured to be stacked with the second type of active region structure 80B.

[0134] In operation 1110 of method 1100, an upper gate conductor is formed that intersects with the upper active region structure. For example, refer to Figures 5B-5D This forms a gate conductor 555F that intersects with the first type of active region structure 80F.

[0135] In operation 1112 of method 1100, an upper terminal conductor is formed that intersects with the upper active region structure. For example, refer to... Figures 5B-5D Terminal conductors 534F and 534B are formed that intersect with the first type of active region structure 80F.

[0136] In operation 1114 of method 1100, a power via conductor is formed in the filled cell, offset in the Y direction from the lower and upper active region structures. For example, refer to Figures 5B-5D The power through-hole connector 520 is formed to be offset in the Y direction from the first and second type active area structures 80F and 80B.

[0137] In operation 1116 of method 1100, a front power rail and a back power rail are formed to extend along the X direction and are connected together through power via conductors in the fill cell. For example, refer to Figures 5B-5D The first front power rail 20F and the first rear power rail 20B are formed to extend along the X direction and are connected together by a power through hole connector 520.

[0138] In some embodiments, method 1100 is used to manufacture an integrated circuit having fill cells 581. It should be understood that method 1100 is not limited to... Figure 11 The order of operations described above. Furthermore, various operations may be omitted or replaced in other embodiments; for example, operations 1104, 1106, 1110, and 1112 may be omitted when manufacturing an integrated circuit with filling unit 781.

[0139] Figure 12 This is a flowchart of a semiconductor device manufacturing method 1200 according to some embodiments.

[0140] According to some embodiments, method 1200 may, for example, use EDA system 1300 (see...). Figure 13 (discussed below) and integrated circuit (IC) manufacturing system 1400 (see below) Figure 14 (Discussed below) to be implemented. Examples of semiconductor devices that can be manufactured according to method 1200 include one or more integrated circuits described above.

[0141] exist Figure 12 In method 1200, blocks 1202 through 1204 are included. In operation 1202, a layout diagram is generated, which in particular includes one or more layout diagrams disclosed herein, or similar layout diagrams.

[0142] Operation 1202 may be implemented using, for example, EDA system 1300 (…) Figure 13 (Discussed below) to implement this. In some embodiments, operation 1202 includes generating a shape corresponding to the structure to be represented in the semiconductor diagram.

[0143] At operation 1204, based on the layout diagram, at least one of the following is performed: (A) performing one or more photolithographic exposures, or (B) fabricating one or more semiconductor masks, or (C) fabricating one or more components in a layer of an integrated circuit (IC) device (e.g., a semiconductor device).

[0144] Figure 13 This is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments. The EDA system 1300 can be used to design one or more of the aforementioned integrated circuits.

[0145] In some embodiments, the EDA system 1300 includes an Automatic Placement and Routing (APR) system. In some embodiments, the EDA system 1300 is or includes a general-purpose computing device including a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. The computer-readable storage medium 1304 is encoded with (i.e. stores) computer program code 1306 (i.e., a set of executable instructions). The instructions 1306, executed by the processor 1302, represent (at least partially) an EDA tool that implements some or all of the methods described herein (hereinafter referred to as the process and / or method) according to one or more embodiments.

[0146] In some embodiments, the layout diagram design method for representing wiring arrangements described herein can be implemented using an EDA system 1300.

[0147] In some embodiments, processor 1302 executes instructions 1306 (at least in part) representing an IC device design system that implements part or all of the processes and / or methods described.

[0148] In some embodiments, the computer program product includes a non-transitory computer-readable storage medium 1304 storing instructions that, when executed by a processor 1302, cause the processor 1302 to perform unit layout operations.

[0149] Processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Processor 1302 is also electrically coupled to input / output (I / O) interface 1310 via bus 1308. Network interface 1312 is also electrically connected to processor 1302 via bus 1308. Network interface 1312 is connected to network 1314, enabling processor 1302 and computer-readable storage medium 1304 to be connected to external components via network 1314. Processor 1302 is configured to execute computer program code 1306 encoded in computer-readable storage medium 1304 to enable EDA system 1300 to perform some or all of the process and / or method. In some embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0150] In some embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). In some embodiments, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disk, the computer-readable storage medium 1304 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0151] In some embodiments, computer-readable storage medium 1304 stores computer program code 1306 (instructions) configured to enable EDA system 1300 (wherein the execution representation (at least partially) EDA tool) to perform part or all of the process and / or method. In some embodiments, computer-readable storage medium 1304 also stores information that facilitates the execution of part or all of the process and / or method. In some embodiments, computer-readable storage medium 1304 stores a standard cell library 1307, including such standard cells disclosed herein. In some embodiments, computer-readable storage medium 1304 stores one or more layout figures 1309 corresponding to one or more layouts disclosed herein.

[0152] EDA system 1300 includes an I / O interface 1310. The I / O interface 1310 is coupled to external circuitry. In some embodiments, the I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1302.

[0153] EDA system 1300 also includes a network interface 1312 coupled to processor 1302. Network interface 1312 allows EDA system 1300 to communicate with network 1314, to which one or more other computer systems are connected. Network interface 1312 includes: a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In some embodiments, some or all of the processes and / or methods are implemented in two or more EDA systems 1300.

[0154] EDA system 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1302. This information is transmitted to processor 1302 via bus 1308. EDA system 1300 is also configured to receive information related to the user interface (UI) via I / O interface 1310. This information is stored in computer-readable storage medium 1304 as UI 1342.

[0155] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by EDA system 1300. In some embodiments, the layout diagram containing standard cells is provided using a solution such as CADENCE DESIGN SYSTEMS. This layout is generated using tools or other suitable layout generation tools.

[0156] In some embodiments, the process is implemented as program functionality stored in a non-transient computer-readable recording medium. Examples of non-transient computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or storage cells, such as one or more of the following: optical discs of a DVD, disks such as hard disks, ROM, RAM, memory cards, etc.

[0157] Figure 14 This is a block diagram of an IC manufacturing system 1400 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the IC manufacturing system 1400 is used to manufacture at least one of the following: (A) one or more semiconductor masks; or (B) at least one component in a semiconductor integrated circuit layer.

[0158] exist Figure 14In this IC manufacturing system 1400, entities such as design company 1420, mask factory 1430, and IC manufacturer / fab 1450 collaborate with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC device 1460. The entities in IC manufacturing system 1400 are connected via a communication network. In some embodiments, this communication network is a single network. In other embodiments, the communication network includes multiple different networks, such as intranets and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design company 1420, mask factory 1430, and IC manufacturing plant 1450 belong to the same large company. In other embodiments, two or more of design company 1420, mask factory 1430, and IC manufacturing plant 1450 coexist in the same facility and share resources.

[0159] Design company (or design team) 1420 generates IC design layout 1422 based on the processes and / or methods described above. This IC design layout 1422 includes various geometric patterns corresponding to metal layers, oxide layers, or semiconductor layers, which constitute various components of the IC device 1460 to be manufactured. The layers are combined to form various IC components. For example, a portion of the IC design layout 1422 includes various IC components to be formed on a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads. Design company 1420 implements appropriate design procedures to form the IC design layout 1422. Design procedures include one or more of logic design, physical design, or place-and-route. The IC design layout 1422 is presented in one or more data files containing geometric pattern information. For example, the IC design layout 1422 can be expressed in GDSII or DFII file format.

[0160] Mask fabrication plant 1430 includes mask data preparation 1432 and mask fabrication 1444. Mask fabrication plant 1430 uses an IC design layout 1422 to fabricate one or more masks 1445 for manufacturing various layers of an IC device 1460 according to the IC design layout 1422. Mask fabrication plant 1430 performs mask data preparation 1432, in which the IC design layout 1422 is converted into a representative data file (RDF). Mask data preparation 1432 provides the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1445 or a substrate 1453 (e.g., a semiconductor wafer). The IC design layout 1422 is manipulated by mask data preparation 1432 to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication plant 1450. Figure 14 In this embodiment, mask data preparation 1432 and mask manufacturing 1444 are shown as separate elements. In some embodiments, mask data preparation 1432 and mask manufacturing 1444 may be collectively referred to as mask data preparation.

[0161] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 1422. In some embodiments, mask data preparation 1432 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also employed, which treats OPC as a reverse imaging problem.

[0162] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that examines the IC design layout 1422, which has undergone optical proximity correction (OPC), using a set of mask creation rules. These mask creation rules include specific geometric and / or connectivity constraints to ensure sufficient margin and accommodate variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for constraints during mask fabrication 1444, which may undo some modifications performed by the OPC to satisfy the mask creation rules.

[0163] In some embodiments, mask data preparation 1432 includes a lithography process inspection (LPC), which simulates the process to be performed by an IC manufacturing plant 1450 to manufacture an IC device 1460. The LPC simulates this process based on an integrated circuit design layout 1422 to create a simulated manufactured device (e.g., integrated circuit device 1460). Process parameters in the LPC simulation may include parameters related to each process in the integrated circuit manufacturing cycle, parameters related to the tools used to manufacture the integrated circuit, and / or other aspects of the manufacturing process. The LPC considers a variety of factors, including spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other applicable factors, and combinations thereof. In some embodiments, after the LPC generates a simulated manufactured device, if the shape of the simulated device is not close enough to the design rule requirements, OPC and / or MRC are repeated to further optimize the integrated circuit design layout 1422.

[0164] It should be understood that, for clarity, the description of mask data preparation 1432 above has been simplified. In some embodiments, mask data preparation 1432 includes additional features, such as logic operations (LOPs) for modifying the integrated circuit design layout 1422 according to manufacturing rules. Furthermore, the processes applied to the integrated circuit design layout 1422 during mask data preparation 1432 may be performed in a variety of different sequences.

[0165] Following mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or mask set 1445 is fabricated based on a modified integrated circuit design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more photolithographic exposures based on the integrated circuit design layout 1422. In some embodiments, an electron beam or multi-electron beam mechanism is employed to pattern the mask (photomask or intermediate mask) 1445 based on the modified integrated circuit design layout 1422. The mask 1445 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1445. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (such as ultraviolet (UV) beams) used to expose a photosensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and propagate through the transparent regions. Exemplarily, a binary mask version of mask 1445 comprises a transparent substrate (such as fused silica) and an opaque material (such as chromium) coated on the opaque regions of the binary mask. In another example, mask 1445 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1445, features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various instances, the phase-shifting mask may be an attenuation-type PSM or an alternating-type PSM. The mask generated by mask fabrication 1444 can be used in a variety of processes. For example, in some embodiments, the mask is used in an ion implantation process to form various doped regions in substrate 1453, in an etching process to form various etched regions in substrate 1453, and / or in other suitable processes.

[0166] The integrated circuit manufacturing plant 1450 is an integrated circuit manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different integrated circuit products. In some embodiments, the integrated circuit manufacturing plant 1450 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple integrated circuit products, a second manufacturing facility that can provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging of the integrated circuit products, and a third manufacturing facility that can provide other services for the foundry business.

[0167] The integrated circuit manufacturing plant 1450 includes a wafer fabrication tool 1452 configured to perform various manufacturing operations on a substrate 1453, such that an integrated circuit device 1460 is manufactured according to a mask (e.g., mask 1445). In some embodiments, the wafer fabrication tool 1452 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a chemical vapor deposition chamber or a low-pressure chemical vapor deposition furnace), a chemical mechanical polishing (CMP) system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0168] The integrated circuit manufacturing plant 1450 uses a mask 1445 manufactured by a mask factory 1430 to manufacture an integrated circuit device 1460. Therefore, the integrated circuit manufacturing plant 1450 uses at least indirectly an integrated circuit design layout 1422 to manufacture the integrated circuit device 1460. In some embodiments, the substrate 1453 is manufactured by the integrated circuit manufacturing plant 1450 using mask 1445 to form the integrated circuit device 1460. In some embodiments, the integrated circuit manufacturing includes performing one or more photolithographic exposures based at least indirectly on the integrated circuit design layout 1422. In some embodiments, the substrate 1453 includes a silicon substrate or other suitable substrate having a material layer formed thereon. In some embodiments, the substrate 1453 also includes one or more of various doped regions, dielectric components, multilayer interconnect structures, etc. (formed in subsequent manufacturing steps).

[0169] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 14 Details of the IC manufacturing system 1400 and its related manufacturing processes can be found in, for example, U.S. Patent No. 9,256,709 (Granted February 9, 2016), U.S. Patent Application Publication No. 2015 / 0278429A1 (Granted October 1, 2015), U.S. Patent Application Publication No. 2014 / 0040838A1 (Granted February 6, 2014), and U.S. Patent No. 7,260,442 (Granted August 21, 2007), the entire contents of which are incorporated herein by reference.

[0170] In some embodiments, the integrated circuit device includes: a first type of active semiconductor structure extending along a first direction parallel to a substrate surface; a second type of active semiconductor structure extending along the first direction, stacked with the first type of active semiconductor structure, and offset from the first type of active semiconductor structure along a normal direction perpendicular to the substrate surface; a front power rail in a front conductive layer above the first type of active semiconductor structure and the second type of active semiconductor structure; a back power rail in a back conductive layer below the first type of active semiconductor structure and the second type of active semiconductor structure; and a filler unit having a via connector extending along a third direction, the via connector electrically connecting the front power rail and the back power rail. In some embodiments, the filler unit has one or more transistors, and the channel state of each transistor is configured to remain static and fixed over time. In some embodiments, the filler unit does not have transistors, i.e., there are no transistors or no transistors present.

[0171] In some embodiments, a complementary field-effect transistor (CFET) device includes: a top device disposed on the front side and configured to operate according to a power signal; a bottom device disposed on the back side and configured to operate according to the power signal; a first power rail disposed on the front side; a second power rail disposed on the back side; and a power via configured to transmit the power signal from the second power rail to the first power rail, wherein the power via is separated from both the top device and the bottom device in a cross-sectional view.

[0172] In some embodiments, the integrated circuit device includes: a first active region structure stack extending along a first direction parallel to a substrate surface, the first active region structure stack including a lower active region structure and an upper active region structure stacked on the substrate along a third direction perpendicular to the substrate; a front power rail extending along the first direction in an upper conductive layer above the lower active region structure and the upper active region structure; a back power rail extending along the first direction in a lower conductive layer below the lower active region structure and the upper active region structure; a vertical power line array, wherein each vertical power line in the vertical power line array extends along a second direction parallel to the substrate surface in a conductive layer different from the upper conductive layer and the lower conductive layer, the second direction being perpendicular to the first direction; and a filling unit having a segment of the first active region structure stack therein and having a power via connector extending along the third direction, the power via connector electrically connecting the front power rail and the back power rail, and the filling unit being located between two of the vertical power lines.

[0173] In some embodiments, the width of a segment of the first active region structure stack in the filling cell along the second direction is less than the average width of the first active region structure stack. In some embodiments, the front power rail or the back power rail is connected to the vertical power lines in the vertical power line array via vias passing through the interlayer dielectric layer. In some embodiments, no vertical power lines pass through the filling cell. In some embodiments, the filling cell contains no transistors. In some embodiments, the filling cell contains one or more transistors, and each transistor in the filling cell is configured to have a channel configured in a static state that remains constant over time. In some embodiments, the filling cell contains one or more transistors, and the gate terminal of each transistor in the filling cell is configured as a floating node or a voltage node with a constant voltage. In some embodiments, the integrated circuit device further includes a plurality of logic circuit units, and the filling cell is logically decoupled from each logic circuit unit. In some embodiments, the filling unit further includes: a first vertical unit boundary extending along a second direction and passing through a first isolation region in the lower active region structure and a second isolation region in the upper active region structure at a first end of a segment of the first active region structure stack; and a second vertical unit boundary extending along the second direction and passing through a third isolation region in the lower active region structure and a fourth isolation region in the upper active region structure at a second end of a segment of the first active region structure stack. In some embodiments, the integrated circuit device further includes: a second active region structure stack extending along a first direction; and a third active region structure stack extending along the first direction; wherein the first active region structure stack extends along the first direction between the second active region structure stack and the third active region structure stack, and wherein each vertical power line in the vertical power line array traverses each of the first active region structure stack, the second active region structure stack, and the third active region structure stack. In some embodiments, neither the second active region structure stack nor the third active region structure stack passes through the filling unit. In some embodiments, the integrated circuit device further includes a logic circuit cell adjacent to a filling cell, the logic circuit cell having a segment of a second active region structure stack, and the filling cell having a vertical cell boundary extending along a second direction, the boundary being along a reference line between two vertical cell boundaries of the logic circuit cell. In some embodiments, both the lower active region structure and the upper active region structure have a plurality of nanosheets extending along a first direction. In some embodiments, both the lower active region structure and the upper active region structure have a plurality of nanowires extending along a first direction. In some embodiments, the integrated circuit includes: a first type of transistor with a channel located in the lower active region structure; and a second type of transistor with a channel located in the upper active region structure.In some embodiments, the first type of transistor is a PMOS transistor, and the second type of transistor is an NMOS transistor. In some embodiments, the first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor.

[0174] In some embodiments, the integrated circuit device includes: a plurality of active region structure stacks, each active region structure stack extending along a first direction parallel to a substrate surface, wherein the plurality of active region structure stacks includes a first active region structure stack extending along the first direction between a second active region structure stack and a third active region structure stack; a front power rail in an upper conductive layer above the plurality of active region structure stacks; a back power rail in a lower conductive layer below the plurality of active region structure stacks; and a filling unit comprising a segment of the first active region structure stack and a power via connector, wherein the power via... A connector electrically connects the front power rail to the back power rail, wherein the power via connector extends along a third direction perpendicular to the substrate surface, and wherein the fill cell does not contain any dynamic transistors, the dynamic transistor being a transistor whose channel state changes over time; and a logic circuit cell adjacent to the fill cell, the logic circuit cell containing a segment of the second active region structure stack, wherein the fill cell has a vertical cell boundary extending along a reference line in a second direction, the reference line being located between two vertical cell boundaries of the logic circuit cell, the second direction being perpendicular to the first direction.

[0175] In some embodiments, the filling cell contains no transistors. In some embodiments, the second and third active region structure stacks are both adjacent to the first active region structure stack, and neither the second nor the third active region structure stack penetrates the filling cell. In some embodiments, each of the plurality of active region structure stacks includes a lower active region structure and an upper active region structure stacked on the substrate along a third direction perpendicular to the substrate, the lower active region structure having a channel for a first type of transistor, and the upper active region structure having a channel for a second type of transistor. In some embodiments, a segment of the first active region structure stack is defined between a first vertical cell boundary and a second vertical cell boundary of the filling cell, and both the first and second vertical cell boundaries extend along a second direction and intersect the first active region structure stack. In some embodiments, the filling cell is defined between a first horizontal cell boundary extending along a first direction and a second horizontal cell boundary extending along a first direction.

[0176] In some embodiments, the integrated circuit device includes: a first active region structure stack extending along a first direction parallel to a substrate surface, the first active region structure stack including a lower active region structure and an upper active region structure stacked on the substrate along a third direction perpendicular to the substrate, wherein a channel of a first type of transistor is formed in the lower active region structure, and a channel of a second type of transistor is formed in the upper active region structure; a front power rail in an upper conductive layer above the lower and upper active region structures; a back power rail in a lower conductive layer below the lower and upper active region structures; and a filler unit having a segment of the first active region structure stack and a power via connector extending along a third direction, the connector electrically connecting the front power rail and the back power rail, wherein the filler unit does not contain any dynamic transistors, a dynamic transistor being a transistor configured such that its channel state changes over time. In some embodiments, the filler unit does not contain any transistors. In some embodiments, the segment of the first active region structure stack is defined between the first vertical cell boundary and the second vertical cell boundary of the filling cell, and the first vertical cell boundary and the second vertical cell boundary each extend along a second direction, intersecting with the first active region structure stack and passing through the isolation area in the lower active region structure and the isolation area in the upper active region structure.

[0177] In some embodiments, a method of manufacturing an integrated circuit device includes: forming a first active region structure stack extending along a first direction parallel to a substrate surface, the formation of the first active region structure stack including: forming a lower active region structure; and forming an upper active region structure stacked with the lower active region structure along a third direction perpendicular to the substrate; forming a front power rail in an upper conductive layer located above the lower and upper active region structures; forming a back power rail in a lower conductive layer located below the lower and upper active region structures; and forming a filler cell having a segment of the first active region structure stack, the formation of the filler cell including: forming a via connector extending along a third direction and conductively connecting the front power rail and the back power rail, wherein the filler cell is formed without any dynamic transistors, the dynamic transistors being transistors whose channel states change over time.

[0178] In some embodiments, the fill cell is formed without any transistors. In some embodiments, forming the fill cell includes: forming a segment of the first active region structure stack defined between a first vertical cell boundary and a second vertical cell boundary of the fill cell, both the first and second vertical cell boundaries extending along a second direction. In some embodiments, forming the fill cell includes: forming a first lower isolation region and a second lower isolation region in the lower active region structure; and forming a first upper isolation region and a second upper isolation region in the upper active region structure. In some embodiments, forming the first lower isolation region and the second lower isolation region includes: forming a first lower isolation region in the lower active region structure at a position aligned with the first vertical cell boundary, and forming a second lower isolation region in the lower active region structure at a position aligned with the second vertical cell boundary; and forming the first upper isolation region and the second upper isolation region includes: forming a first upper isolation region in the upper active region structure at a position aligned with the first vertical cell boundary, and forming a second upper isolation region in the upper active region structure at a position aligned with the second vertical cell boundary.

[0179] Some embodiments of this application provide an integrated circuit device, including:

[0180] A first active region structure stack extends along a first direction parallel to the surface of the substrate. The first active region structure stack includes a lower active region structure and an upper active region structure stacked on the substrate along a third direction perpendicular to the substrate.

[0181] The front power rail extends along a first direction in the upper conductive layer above the lower active region structure and the upper active region structure.

[0182] The back-side power rail extends along a first direction in the lower conductive layer below the lower active region structure and the upper active region structure.

[0183] A vertical power line array, wherein each vertical power line in the vertical power line array extends in a conductive layer different from the upper and lower conductive layers, along a second direction parallel to the surface of the substrate, the second direction being perpendicular to the first direction; and

[0184] A filling unit having a section of the first active area structure stack and a power via connector extending in a third direction and conductively connecting the front power rail to the rear power rail, wherein the filling unit is located between the two vertical power lines.

[0185] In some embodiments, the width of a segment of the first active region structure stack in the filling unit along the second direction is smaller than the average width of the first active region structure stack.

[0186] In some embodiments, the front power rail or the back power rail is connected to the vertical power lines in the vertical power line array via a through-hole connector that passes through the interlayer dielectric layer.

[0187] In some embodiments, the filling cell contains no transistors.

[0188] In some embodiments, the filling cell has one or more transistors, and each transistor in the filling cell has a channel configured to a static state that remains unchanged over time.

[0189] In some embodiments, the filling cell has one or more transistors, and the gate terminal of each transistor in the filling cell is configured as a floating node or a voltage node with a constant voltage.

[0190] In some embodiments, the filling unit further includes:

[0191] The first vertical unit boundary extends along the second direction and passes through the first end of the segment of the first active region structure stack, encompassing the first isolation region in the lower active region structure and the second isolation region in the upper active region structure; and

[0192] The second vertical unit boundary extends along the second direction and passes through the third isolation area in the lower active region structure and the fourth isolation area in the upper active region structure at the second end of the section of the first active region structure stack.

[0193] In some embodiments, the integrated circuit device further includes:

[0194] A second active region structure stack extends along the first direction; and

[0195] A third active region structure stack extends along the first direction, wherein the first active region structure stack extends along the first direction between the second active region structure stack and the third active region structure stack, and each vertical power line in the vertical power line array extends across the first active region structure stack, the second active region structure stack and the third active region structure stack.

[0196] In some embodiments, neither the second active region structure stack nor the third active region structure stack passes through the filling unit.

[0197] In some embodiments, the integrated circuit device further includes:

[0198] A logic circuit unit, adjacent to the filling unit, having a segment of the second active region structure stack, wherein the filling unit has a vertical cell boundary extending along a reference line in the second direction, the reference line being between two vertical cell boundaries of the logic circuit unit.

[0199] Other embodiments of this application provide an integrated circuit device, including:

[0200] Multiple active region structure stacks, each active region structure stack extending along a first direction parallel to the surface of the substrate, wherein the multiple active region structure stacks include a first active region structure stack extending along the first direction between a second active region structure stack and a third active region structure stack.

[0201] The front power rail is located in the upper conductive layer above the stack of multiple active area structures;

[0202] The back-side power rail is located in the lower conductive layer below the stack of multiple active area structures;

[0203] A filling unit, wherein the filling unit has a segment of the first active region structure stack and a power via connector, the power via connector electrically connecting the front power rail to the back power rail, wherein the power via connector extends in a third direction perpendicular to the surface of the substrate, and wherein the filling unit has no dynamic transistors, the dynamic transistors being configured to have channels whose states change over time; and

[0204] A logic circuit unit, adjacent to the filling unit, has a segment of the second active region structure stack, wherein the filling unit has a vertical unit boundary extending along a reference line in a second direction, the reference line being between two vertical unit boundaries of the logic circuit unit, and the second direction being perpendicular to the first direction.

[0205] In some embodiments, the filling cell contains no transistors.

[0206] In some embodiments, the second active region structure stack and the third active region structure stack are both adjacent to the first active region structure stack, and neither the second active region structure stack nor the third active region structure stack passes through the filling unit.

[0207] In some embodiments, a segment of the first active region structure stack is defined between a first vertical cell boundary and a second vertical cell boundary of the filling cell, wherein each of the first vertical cell boundary and the second vertical cell boundary extends along the second direction and intersects the first active region structure stack.

[0208] In some embodiments, the filling unit is defined between a first horizontal unit boundary extending along the first direction and a second horizontal unit boundary extending along the first direction.

[0209] Further embodiments of this application provide a method for manufacturing an integrated circuit device, the method comprising:

[0210] Forming a first active region structure stack extending along a first direction parallel to the surface of the substrate, the formation of the first active region structure stack comprising:

[0211] Forming a lower active region structure; and

[0212] An upper active region structure is formed by stacking with the lower active region structure along a third direction perpendicular to the substrate;

[0213] A front power rail is formed in the upper conductive layer above the lower active region structure and the upper active region structure.

[0214] A back-side power rail is formed in the lower conductive layer below the lower active region structure and the upper active region structure; and

[0215] Forming a filling unit for a segment having the first active region structure stack, the filling unit comprising:

[0216] A power via connector is formed, the power via connector extending along the third direction and electrically connecting the front power rail to the rear power rail, wherein the filler cell is formed without any dynamic transistors, the dynamic transistors being configured to have channels whose states change over time.

[0217] In some embodiments, the filling cell is formed without any transistors.

[0218] In some embodiments, forming the filling unit includes:

[0219] The segment of the first active region structure stack is defined between the first vertical cell boundary and the second vertical cell boundary of the filling cell, each of the first vertical cell boundary and the second vertical cell boundary extending along a second direction.

[0220] In some embodiments, forming the filling unit includes:

[0221] A first lower isolation region and a second lower isolation region are formed in the lower active region structure; and

[0222] A first upper isolation region and a second upper isolation region are formed in the upper active region structure.

[0223] In some embodiments, forming the first lower isolation zone and the second lower isolation zone includes:

[0224] The first lower isolation region is formed at a position aligned with the boundary of the first vertical unit in the lower active region structure, and

[0225] A second lower isolation region is formed at a position aligned with the boundary of the second vertical unit in the lower active region structure; and

[0226] The formation of the first upper isolation zone and the second upper isolation zone includes:

[0227] The first upper isolation region is formed at a position aligned with the boundary of the first vertical unit in the upper active region structure, and

[0228] The second upper isolation region is formed at a position aligned with the boundary of the second vertical unit in the upper active region structure.

[0229] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An integrated circuit device, comprising: A first active region structure stack extends along a first direction parallel to the surface of the substrate. The first active region structure stack includes a lower active region structure and an upper active region structure stacked on the substrate along a third direction perpendicular to the substrate. The front power rail extends along a first direction in the upper conductive layer above the lower active region structure and the upper active region structure. The back-side power rail extends along a first direction in the lower conductive layer below the lower active region structure and the upper active region structure. A vertical power line array, wherein each vertical power line in the vertical power line array extends in a conductive layer different from the upper conductive layer and the lower conductive layer, along a second direction parallel to the surface of the substrate, the second direction being perpendicular to the first direction; as well as A filling unit having a section of the first active area structure stack and a power via connector extending in a third direction and conductively connecting the front power rail to the rear power rail, wherein the filling unit is located between the two vertical power lines.

2. The integrated circuit device according to claim 1, wherein, The width of the segment of the first active region structure stack in the filling unit along the second direction is smaller than the average width of the first active region structure stack.

3. The integrated circuit device according to claim 1, wherein, The front power rail or the back power rail is connected to the vertical power lines in the vertical power line array via a through-hole connector that passes through the interlayer dielectric layer.

4. The integrated circuit device according to claim 1, wherein, The filling cell contains no transistors.

5. The integrated circuit device according to claim 1, wherein, The filling cell has one or more transistors, and each transistor in the filling cell has a channel configured in a static state that remains unchanged over time.

6. The integrated circuit device according to claim 5, wherein, The filling cell has one or more transistors, and the gate terminal of each transistor in the filling cell is configured as a floating node or a voltage node with a constant voltage.

7. The integrated circuit device according to claim 1, wherein, The filling unit further includes: The first vertical unit boundary extends along the second direction and passes through the first end of the segment of the first active region structure stack, encompassing the first isolation region in the lower active region structure and the second isolation region in the upper active region structure; and The second vertical unit boundary extends along the second direction and passes through the third isolation area in the lower active region structure and the fourth isolation area in the upper active region structure at the second end of the section of the first active region structure stack.

8. The integrated circuit device according to claim 1, further comprising: The second active region structure stack extends along the first direction; as well as A third active region structure stack extends along the first direction, wherein the first active region structure stack extends along the first direction between the second active region structure stack and the third active region structure stack, and each vertical power line in the vertical power line array extends across the first active region structure stack, the second active region structure stack and the third active region structure stack.

9. An integrated circuit device, comprising: Multiple active region structure stacks, each active region structure stack extending along a first direction parallel to the surface of the substrate, wherein the multiple active region structure stacks include a first active region structure stack extending along the first direction between a second active region structure stack and a third active region structure stack. The front power rail is located in the upper conductive layer above the stack of multiple active area structures; The back-side power rail is located in the lower conductive layer below the stack of multiple active area structures; A filling unit, wherein the filling unit has a segment of the first active region structure stack and a power via connector, the power via connector electrically connecting the front power rail to the back power rail, wherein the power via connector extends in a third direction perpendicular to the surface of the substrate, and wherein the filling unit has no dynamic transistors, the dynamic transistors being configured to have channels whose states change over time; and A logic circuit unit, adjacent to the filling unit, has a segment of the second active region structure stack, wherein the filling unit has a vertical unit boundary extending along a reference line in a second direction, the reference line being between two vertical unit boundaries of the logic circuit unit, and the second direction being perpendicular to the first direction.

10. A method for manufacturing an integrated circuit device, the method comprising: Forming a first active region structure stack extending along a first direction parallel to the surface of the substrate, the formation of the first active region structure stack comprising: Forming a lower active region structure; and An upper active region structure is formed by stacking with the lower active region structure along a third direction perpendicular to the substrate; A front power rail is formed in the upper conductive layer above the lower active region structure and the upper active region structure. A back-side power rail is formed in the lower conductive layer below the lower active region structure and the upper active region structure; and Forming a filling unit for a segment having the first active region structure stack, the filling unit comprising: A power via connector is formed, the power via connector extending along the third direction and electrically connecting the front power rail to the rear power rail, wherein the filler cell is formed without any dynamic transistors, the dynamic transistors being configured to have channels whose states change over time.

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