Method and apparatus for reducing accumulation in analog-to-digital converters

Abstract

The invention relates to a method and apparatus for reducing accumulation in an analog-to-digital converter. An example apparatus includes combining circuitry (220) having a first input, a second input, and an output; analog-to-digital converter (ADC) circuitry (225) having an input and an output, the input of the ADC circuitry coupled to the output of the combinatorial circuitry; a digital-to-analog converter (DAC) circuitry (230) having an input and an output, the input of the DAC circuitry being coupled to the output of the ADC circuitry; a resistor (210) having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first input of the combinatorial circuitry; amplifier circuitry (235) having an input coupled to the output of the DAC circuitry and the second terminal of the resistor.

Description

Technical Field

[0001] This specification generally relates to analog-to-digital conversion, and more specifically, to methods and apparatus for reducing accumulations in analog-to-digital converters. Background Technology

[0002] As electronics continue to advance, systems have become capable of operating safely under increasingly complex conditions, such as higher speeds and greater accuracy. In analog-to-digital converter (ADC) circuitry, increasingly sophisticated circuitry implements advanced techniques to support increased conversion speeds and higher resolution outputs. Regardless of the complexity of the operating conditions, such circuitry allows ADC circuitry to generate accurate outputs at higher resolutions. Summary of the Invention

[0003] For methods and apparatus for reducing accumulations in an analog-to-digital converter, one example apparatus includes: a combinational circuit system having a first input, a second input, and an output; an analog-to-digital converter (ADC) circuit system having an input and an output, the input of the ADC circuit system being coupled to the output of the combinational circuit system; a digital-to-analog converter (DAC) circuit system having an input and an output, the input of the DAC circuit system being coupled to the output of the ADC circuit system; a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first input of the combinational circuit system; and an amplifier circuit system having an input coupled to the output of the DAC circuit system and the second terminal of the resistor. Other examples are described.

[0004] For methods and apparatus for reducing accumulation in analog-to-digital converters, one example apparatus includes: a combinational circuit system having an input and an output; an analog-to-digital converter (ADC) circuit system having an input and an output, the input of the ADC circuit system being coupled to the output of the combinational circuit system; a digital-to-analog converter (DAC) circuit system having an input and an output, the input of the DAC circuit system being coupled to the output of the ADC circuit system; a first amplifier circuit system having an input and an output, the input of the first amplifier circuit system being coupled to the output of the DAC circuit system; and a second amplifier circuit system having an input and an output, the input of the second amplifier circuit system being coupled to the output of the first amplifier circuit system, and the output of the second amplifier circuit system being coupled to the input of the combinational circuit system. Other examples are described.

[0005] For methods and apparatus for reducing accumulations in analog-to-digital converters, one example apparatus includes: a combinational circuit system having an input and an output; an analog-to-digital converter (ADC) circuit system having an input, a first output, and a second output, the input of the ADC circuit system being coupled to the output of the combinational circuit system; a first digital-to-analog converter (DAC) circuit system having an input and an output, the input of the first DAC circuit system being coupled to the first output of the ADC circuit system; an amplifier circuit system having an input coupled to the output of the DAC circuit system; and a second DAC circuit system having an input and an output, the input of the second DAC circuit system being coupled to the second output of the ADC circuit system, the output of the second DAC circuit system being coupled to the input of the combinational circuit system. Other examples are described.

[0006] For methods and apparatus for reducing accumulation in analog-to-digital converters, one example apparatus includes: a first interstage gain circuit system comprising: a combinational circuit system having an input and an output; an analog-to-digital converter (ADC) circuit system having an input and an output, the input of the ADC circuit system being coupled to the output of the combinational circuit system; a digital-to-analog converter (DAC) circuit system having an input and an output, the input of the DAC circuit system being coupled to the output of the ADC circuit system; and an amplifier circuit system having an input and an output, the input of the amplifier circuit system being coupled to the output of the DAC circuit system; and a second interstage gain circuit system having an input coupled to the output of the amplifier circuit system. Other examples are described. Attached Figure Description

[0007] Figure 1 This is a block diagram of an example continuous-time pipelined ADC that includes an example interstage gain circuit system.

[0008] Figure 2 It includes an example feedback circuit system. Figure 1 A schematic diagram of an example of an interstage gain circuit system.

[0009] Figure 3 It includes Figure 2 Feedback circuit system Figure 1 and 2 A schematic diagram of another example of an interstage gain circuit system.

[0010] Figure 4 It includes Figure 2 and 3 Example feedback circuit system Figure 1 , 2A schematic diagram of another example of an interstage gain circuit system of 3.

[0011] Figure 5 This indicates that it can be used. Figure 1 , 2 A flowchart illustrating example operations of at least one of the example implementations, instantiations, or executions of the interstage gain circuit system of 3.

[0012] Figure 6 It includes an example feedback circuit system. Figure 1 A schematic diagram of an example of an interstage gain circuit system.

[0013] Figure 7 It includes Figure 6 Another example of a feedback circuit system Figure 1 and 6 A schematic diagram of another example of an interstage gain circuit system.

[0014] Figure 8 This indicates that it can be used. Figure 1 , 6 Example implementation of the 7-stage interstage gain circuit system uses Figure 6 and 7 A flowchart of a feedback circuit system for implementing, instantiating, or executing at least one of the example operations.

[0015] Figure 9 It includes Figure 2 , 3 Feedback circuit systems of 6 and 7 Figure 1 , 2 Timing diagrams for example operation of the interstage gain circuit systems of stages 3, 6, and 7.

[0016] The figures are not necessarily drawn to scale. Generally, the same reference numerals in the figures and in this specification refer to features and / or parts that are (functionally and / or structurally) the same or similar. Although the figures show areas with clearly defined lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries or lines may be unobservable, mixed, or irregular. Detailed Implementation

[0017] As electronics continue to advance, systems have become capable of operating safely under increasingly complex conditions, such as higher speeds and greater accuracy. In analog-to-digital converter (ADC) circuitry, increasingly sophisticated circuitry implements advanced techniques to support increased conversion speeds and higher resolution outputs. Regardless of the complexity of the operating conditions, such circuitry allows ADC circuitry to generate accurate outputs at higher resolutions.

[0018] In some designs, ADC circuitry needs to convert analog values ​​into digital bits at relatively high speeds to accurately represent analog input signals. Continuous-time pipelined (CTP) ADC circuitry uses multiple series-coupled stages to convert analog values ​​into digital bits. Each stage of a CTP ADC corresponds to the resolution of the digital output. For example, the first stage of a CTP ADC produces one or more most significant bits (LSBs) of the digital output, and a second stage following the first stage produces one or more next LSBs after the output of the first stage. Each stage contains an interstage gain circuitry and one or more latches. The latches in each stage sequence the supply of one or more bits from the interstage gain circuitry to an output latch, which supplies a digital output as a combination of bits from each stage.

[0019] Each instance of the interstage gain circuitry is coupled to either the circuitry supplying the analog input signal or the output of the preceding instance of the interstage gain circuitry. The interstage gain circuitry includes a delay circuitry, a sub-ADC circuitry, a digital-to-analog converter (DAC) circuitry, an amplifier circuitry, and a filter circuitry. The sub-ADC circuitry samples the analog input signal to determine the analog input voltage to be converted to digital. Compared to the resolution of the CTP ADC circuitry's output, the sub-ADC circuitry performs a relatively low-resolution analog-to-digital conversion of the analog input voltage. The sub-ADC circuitry supplies one or more bits from the relatively low-resolution conversion to the DAC circuitry and a latch. The latch supplies one or more bits to the output latch of the CTP ADC circuitry.

[0020] A DAC circuit system uses one or more bits to generate an approximation of the analog input voltage. A delay circuit system delays the analog input signal by a certain duration, providing time for the sub-ADC and DAC circuit systems to convert the analog input voltage. An amplifier circuit system generates an output voltage proportional to the difference between the approximation and the actual analog input voltage. This difference is called the residual or quantization error. The amplifier circuit system amplifies the residual by a gain and supplies the amplified residual to subsequent instances of the interstage gain circuit system. These subsequent instances of the interstage gain circuit system use the amplified residual to determine higher resolution bits.

[0021] The filter circuitry is coupled between the input and output of the amplifier circuitry. It provides a feedback path for the current from the amplifier's output. The filter circuitry stabilizes the interstage gain circuitry by reducing the amplifier's response time to voltage at the input. It also removes high-frequency noise from the amplifier's output. However, the capacitor and inductor components of the filter circuitry accumulate charge from residuals from previous samples. This accumulation affects the signal-to-noise ratio (SNR) of the CTP ADC circuitry. Furthermore, it affects the accuracy of subsequent instances of the interstage gain circuitry. Increasing the resolution of the sub-ADC and DAC circuitry can reduce accumulation by decreasing the residuals. However, increasing the resolution of the sub-ADC and DAC circuitry increases the conversion time of each stage of the CTP ADC and increases power consumption.

[0022] The examples described herein include methods and apparatus for using feedback circuitry systems to compensate for residual accumulation in an analog input to reduce accumulation in an ADC. In some of the described examples, the interstage gain circuitry system comprises a combination circuitry system and a feedback circuitry system located between the input of the interstage gain circuitry system and the sub-ADC circuitry system. The combination circuitry system uses a voltage from the feedback circuitry system to compensate for residual accumulation in the analog input signal. In some examples, the feedback circuitry system is an amplifier circuitry system coupled to the outputs of both the combination circuitry system and the interstage gain circuitry system. In such examples, the amplifier circuitry system multiplies the voltage at the output of the interstage gain circuitry system by the feedback gain to generate a compensation voltage proportional to the residual. Alternatively, a transfer function can be used to determine the feedback gain.

[0023] In other examples, the feedback circuitry is an additional DAC circuitry coupled to both the sub-ADC circuitry and the combinational circuitry. The additional DAC circuitry receives the least significant bit (LSB) of the output from the sub-ADC circuitry. The DAC circuitry uses the LSB to generate an analog error voltage. The combinational circuitry applies this analog error voltage to the analog input signal to compensate for the accumulation of previous residuals. Advantageously, the combinational and feedback circuitry compensates for the accumulation of previous residuals in the filter circuitry. Advantageously, the combinational and feedback circuitry improves the signal-to-noise ratio of the CTP ADC circuitry.

[0024] Figure 1 This is a block diagram of an example continuous-time pipelined (CTP) ADC circuit system 100. Figure 1In the example, the CTP ADC circuit system 100 includes a first interstage gain circuit system 105, a second interstage gain circuit system 110, a third interstage gain circuit system 115, a first latch 120, a second latch 125, a third latch 130, a fourth latch 135, a fifth latch 140, a sixth latch 145, and a seventh latch 150. The CTP ADC circuit system 100 has input terminals and output terminals. The input terminals of the CTP ADC circuit system 100 are configured to couple to an external circuit system that supplies analog input signals. The output terminals of the CTP ADC circuit system 100 are configured to couple to an external circuit system that receives digital output signals. In some examples, the CTP ADC circuit system 100 receives analog input signals from sensors, analog devices, instrumentation systems, imaging systems, etc. In some such examples, the CTP ADC circuit system 100 supplies digital output signals to programmable circuit systems, such as processing units, signal processing circuit systems, etc.

[0025] Interstage gain circuit system 105 has an input terminal, a first output terminal, and a second output terminal. The input terminal of interstage gain circuit system 105 is coupled to the input terminal of CTP ADC circuit system 100, which supplies the analog input signal. The first output terminal of interstage gain circuit system 105 is coupled to interstage gain circuit system 110. The second output terminal of interstage gain circuit system 105 is coupled to latch 120. Interstage gain circuit system 110 has an input terminal, a first output terminal, and a second output terminal. The input terminal of interstage gain circuit system 110 is coupled to interstage gain circuit system 105. The first output terminal of interstage gain circuit system 110 is coupled to interstage gain circuit system 115. The second output terminal of interstage gain circuit system 110 is coupled to latch 130. Interstage gain circuit system 115 has an input terminal, a first output terminal, and a second output terminal. The input terminal of interstage gain circuit system 115 is coupled to interstage gain circuit system 110. The first output terminal of the interstage gain circuitry 115 may be coupled to additional instances of the interstage gain circuitry 105, 110, 115. In some examples, additional instances of the interstage gain circuitry 105, 110, 115 increase the resolution of the CTP ADC circuitry 100. The second output terminal of the interstage gain circuitry 115 is coupled to latch 140.

[0026] Latch 120 has input terminals and output terminals. The input terminals of latch 120 are coupled to interstage gain circuitry 105. The output terminals of latch 120 are coupled to latch 125. Latch 125 has input terminals and output terminals. The input terminals of latch 125 are coupled to latch 120. The output terminals of latch 125 are coupled to latch 150. In some examples, CTP ADC circuitry 100 includes one or more additional latches coupled between latches 120 and 125. In such examples, the number of additional latches corresponds to the number of additional interstage gain circuitry systems 105, 110, and 115 following interstage gain circuitry system 105.

[0027] Latch 130 has input and output terminals. The input terminals of latch 130 are coupled to interstage gain circuitry 110. The output terminals of latch 130 are coupled to latch 135. Latch 135 has input and output terminals. The input terminals of latch 135 are coupled to latch 130. The output terminals of latch 135 are coupled to latch 150. In some examples, CTP ADC circuitry 100 includes one or more additional latches coupled between latches 130 and 135. In such examples, the number of additional latches corresponds to the number of additional interstage gain circuitry systems 105, 110, and 115 following interstage gain circuitry system 110.

[0028] Latch 140 has input terminals and output terminals. The input terminals of latch 140 are coupled to interstage gain circuitry 115. The output terminals of latch 140 are coupled to latch 145. Latch 145 has input terminals and output terminals. The input terminals of latch 145 are coupled to latch 140. The output terminals of latch 145 are coupled to latch 150. In some examples, CTP ADC circuitry 100 includes one or more additional latches coupled between latches 140 and 145, or one or more fewer latches coupled between interstage gain circuitry 115 and latch 150. In such examples, the number of latches corresponds to the number of additional interstage gain circuitry systems 105, 110, 115 following interstage gain circuitry system 115.

[0029] Latch 150 (also called an output latch) has input terminals and output terminals. The input terminals of latch 150 are coupled to latches 125, 135, and 145. The output terminals of latch 150 are coupled to the output terminals of the CTP ADC circuit system 100 that supply digital output signals to external circuit systems.

[0030] In the example operation, the interstage gain circuitry 105 receives an analog input signal at the input terminal of the CTP ADC circuitry 100. The interstage gain circuitry 105 determines the analog value to be converted by sampling the analog input signal at a first time. The interstage gain circuitry 105 generates one or more digital bits representing the sampled analog value at a first resolution. A latch 120 latches one or more digital bits. The interstage gain circuitry 105 amplifies the difference between the sampled analog value and the analog representation of the one or more digital bits.

[0031] In this example operation, the interstage gain circuitry 110 generates one or more digital bits representing the amplified difference of the analog value at a second time. Also at a second time, latch 125 latches the digital bits of latch 120, and latch 130 latches one or more digital bits from the interstage gain circuitry 110. The interstage gain circuitry 110 amplifies the difference between the remaining portion of the sampled analog value and the analog representation of the one or more digital bits.

[0032] In this example operation, the interstage gain circuitry 115 generates one or more digital bits representing the amplified difference of the analog value at a third time. Also at the third time, latch 135 latches the digital bits of latch 130, and latch 140 latches one or more digital bits from the interstage gain circuitry 115. At the third time, the digital bits of latches 125, 135, and 140 form a digital representation of the sampled analog value. At the fourth time, latch 150 supplies the determined digital bits to the external circuitry. Additionally, during the second and third times, the interstage gain circuitry 105 and 110 continue to sample and convert subsequent analog values ​​of the analog input signal.

[0033] Combination Figure 2 , 3 Sections 6 and 7 illustrate and describe examples of interstage gain circuit systems 105, 110, and 115. (In conjunction with...) Figure 4 and 7 Further explanation and description of example operation of interstage gain circuit systems 105, 110, and 115.

[0034] Figure 2 Is as Figure 1 A schematic diagram of an example interstage gain circuit system 200, showing examples of interstage gain circuit systems 105, 110, and 115. Figure 2 In the example, the interstage gain circuit system 200 includes a delay circuit system 205, a first resistor 210, an interconnect circuit system 215, a combination circuit system 220, an ADC circuit system 225, a DAC circuit system 230, a first amplifier circuit system 235, a filter circuit system 240, and a second amplifier circuit system 245. Figure 2The example filter circuit system 240 includes an example capacitor 250 and a second example resistor 255.

[0035] Interstage gain circuitry system 200 has an input terminal, a first output terminal, and a second output terminal. The input terminal of interstage gain circuitry system 200 is configured to couple to an output terminal of a previous instance of interstage gain circuitry system 200 or to an external circuit system that supplies an analog input signal (Vin). In both examples, interstage gain circuitry system 200 receives an analog input signal at the input terminal. The first output terminal of interstage gain circuitry system 200 is configured to couple to a subsequent instance of interstage gain circuitry system 200. The second output terminal of interstage gain circuitry system 200 is configured to couple to a latch (e.g., ...). Figure 1 (Latches 120, 130, 140). In some examples, the interstage gain circuitry 200 has multiple output terminals configured to supply multiple digital bits (DOUT) to the latches or external circuitry.

[0036] The delay circuit system 205 has a first terminal and a second terminal. The first terminal of the delay circuit system 205 is coupled to the input terminal of the interconnect circuit system 215 and the interstage gain circuit system 200, which supplies the analog input signal. The second terminal of the delay circuit system 205 is coupled to a resistor 210. In some examples, the delay circuit system 205 is a discrete component constructed to delay the propagation of the analog input signal. In other examples, the delay circuit system 205 is a passive component, such as a trace, which reduces the propagation speed of the analog input signal.

[0037] Resistor 210 has a first terminal and a second terminal. The first terminal of resistor 210 is coupled to delay circuit system 205. The second terminal of resistor 210 is coupled to DAC circuit system 230, amplifier circuit system 235, and filter circuit system 240. Figure 2 In the example, resistor 210 is configured to isolate the voltage of amplifier circuitry 235 from the voltage of the analog input signal. Figure 2 In the example, resistor 210 is illustrated and described as a discrete component separate from the delay circuit system 205. Alternatively, in some examples, such as when the delay circuit system 205 is a transmission line, resistor 210 may be illustrated or described as part of the delay circuit system 205. For example, resistor 210 may be illustrated or described as the equivalent resistance of a component of the delay circuit system 205.

[0038] Interconnect circuit system 215 has a first terminal and a second terminal. The first terminal of interconnect circuit system 215 is coupled to the input terminals of the delay circuit system 205 and the interstage gain circuit system 200 for supplying analog input signals. The second terminal of interconnect circuit system 215 is coupled to the combinational circuit system 220. In some examples, the interstage gain circuit system 200 may be illustrated and described without interconnect circuit system 215. For example, when the interstage gain circuit system 200 is configured for single-ended signals, such as... Figure 2 As shown, the interconnecting circuitry 215 can be removed. In such examples, the combinational circuitry 220 is directly coupled to the input terminals of the interstage gain circuitry 200 and the delay circuitry 205. However, when the interstage gain circuitry 200 is configured for differential signals, as... Figure 3 The diagram shows an interconnect circuit system 215. The interconnect circuit system 215 is a circuit system constructed to exchange signals on the p-side and m-side. The following section combines... Figure 3 Further description and explanation of the interconnection circuit system 215.

[0039] The combinational circuit system 220 has a first terminal, a second terminal, and a third terminal. The first terminal (also referred to as the first input terminal) of the combinational circuit system 220 is coupled to the interconnect circuit system 215. The second terminal (also referred to as the second input terminal) of the combinational circuit system 220 is coupled to the amplifier circuit system 245. The third terminal (also referred to as the output terminal) of the combinational circuit system 220 is coupled to the ADC circuit system 225. Figure 2 In the example, the combinational circuit system 220 is constructed as a subtraction circuit system that subtracts the second input from the first input.

[0040] ADC circuit system 225 has input terminals and output terminals. The input terminals of ADC circuit system 225 are coupled to combinational circuit system 220. The output terminals of ADC circuit system 225 are coupled to the output terminals of DAC circuit system 230 and interstage gain circuit system 200. In some examples, ADC circuit system 225 is illustrated and described as a flash memory constructed for analog-to-digital conversion. Additionally, one or more output terminals of ADC circuit system 225 may be individually coupled to one of the output terminals of DAC circuit system 230 or interstage gain circuit system 200. For example, the output terminal of interstage gain circuit system 200 may be coupled to the most significant bit of the output of ADC circuit system 225.

[0041] The DAC circuit system 230 has input terminals and output terminals. The input terminals of the DAC circuit system 230 are coupled to the ADC circuit system 225 and can be coupled to the output terminals of the interstage gain circuit system 200. The output terminals of the DAC circuit system 230 are coupled to resistor 210, amplifier circuit system 235 and filter circuit system 240.

[0042] Amplifier circuit system 235 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of amplifier circuit system 235 (also referred to as the non-inverting input terminal) is coupled to resistor 210, DAC circuit system 230, and filter circuit system 240. The second input terminal of amplifier circuit system 235 (also referred to as the inverting input terminal) is coupled to a common terminal that provides a common potential (e.g., ground, AVSS, etc.). The output terminal of amplifier circuit system 235 is coupled to the first output terminal of filter circuit system 240, amplifier circuit system 245, and interstage gain circuit system 200, which may be coupled to another instance of interstage gain circuit system 200.

[0043] The filter circuit system 240 has a first terminal and a second terminal. The first terminal of the filter circuit system 240 is coupled to the resistor 210, the DAC circuit system 230, and the amplifier circuit system 235. The second terminal of the filter circuit system 240 is coupled to the amplifier circuit systems 235 and 245 and the first output terminal of the interstage gain circuit system 200, the first output terminal of which may be coupled to another instance of the interstage gain circuit system 200.

[0044] Amplifier circuit system 245 (also referred to as feedback circuit system) has input terminals and output terminals. The input terminals of amplifier circuit system 245 are coupled to a first output terminal of amplifier circuit system 235 and interstage gain circuit system 200, the first output terminal being coupled to another instance of interstage gain circuit system 200. The output terminals of amplifier circuit system 245 are coupled to combinational circuit system 220.

[0045] Capacitor 250 has a first terminal and a second terminal. The first terminal of capacitor 250 is coupled to resistor 210, DAC circuit system 230, amplifier circuit system 235, and resistor 255. The second terminal of capacitor 250 is coupled to amplifier circuit systems 235, 245, resistor 255, and a first output terminal of interstage gain circuit system 200, the first output terminal of which may be coupled to another instance of interstage gain circuit system 200. Resistor 255 has a first terminal and a second terminal. The first terminal of resistor 255 is coupled to resistor 210, DAC circuit system 230, amplifier circuit system 235, and capacitor 250. The second terminal of resistor 255 is coupled to amplifier circuit systems 235, 245, capacitor 250, and a first output terminal of interstage gain circuit system 200, the first output terminal of which may be coupled to another instance of interstage gain circuit system 200. Figure 2 In the example, capacitor 250 and resistor 255 form a low-pass filter circuit system. Alternatively, capacitor 250 and resistor 255 can be replaced with alternative circuit systems to form another low-pass filter or another type of filter.

[0046] The following text combines Figure 5 An example operation of the interstage gain circuitry system 200 is illustrated and described. Advantageously, the combinational circuitry system 220 and the amplifier circuitry system 245 form a feedback path to compensate the analog input signal for the accumulation of the filter circuitry system 240. Advantageously, compensating the analog input signal for the accumulation increases the signal-to-noise ratio.

[0047] Figure 3 This is a schematic diagram of an example interstage gain circuit system 300, which is... Figure 1 and 2 Another example of interstage gain circuit systems 105, 110, 115, and 200. In Figure 3 In the example, the interstage gain circuit system 300 includes Figure 2 Delay circuit system 205 Figure 2 Resistor 210, Figure 2 Interconnection circuit system 215, Figure 2 Combinatorial circuit system 220, Figure 2 ADC circuit system 225 Figure 2 DAC circuit system 230 Figure 2 Amplifier circuit system 235 Figure 2 Filter circuit system 240 Figure 2 The amplifier circuit system 245, the second delay circuit system 305, and the third resistor 310. Figure 3 Example filter circuit system 240 includes Figure 2 250 capacitors Figure 2The resistor is 255, the second capacitor is 315, and the fourth resistor is 320. Figure 3 In the example, the interstage gain circuit system 300 is a fully differential representation of the interstage gain circuit system 200.

[0048] The interstage gain circuit system 300 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the interstage gain circuit system 300 is configured to couple to an output terminal of a previous instance of the interstage gain circuit system 300 or to an external circuit system, which supplies a p-side analog input signal (Vinp). The second input terminal of the interstage gain circuit system 300 is configured to couple to an output terminal of a previous instance of the interstage gain circuit system 300 or to an external circuit system, which supplies an m-side analog input signal (Vinm). Figure 3 In the example, the difference between the p-side analog input signal and the m-side analog input signal represents the analog input signal. The first output terminal of the interstage gain circuit system 300 is configured to couple to a subsequent instance of the interstage gain circuit system 300. The second output terminal of the interstage gain circuit system 300 is configured to couple to a latch (e.g., Figure 1 (Latches 120, 130, 140).

[0049] The delay circuit system 305 has a first terminal and a second terminal. The first terminal of the delay circuit system 305 is coupled to a second input terminal of the interconnect circuit system 215 and the interstage gain circuit system 300, the second input terminal supplying a p-side analog input signal. The second terminal of the delay circuit system 305 is coupled to a resistor 310. In some examples, the delay circuit system 305 is a discrete component constructed to delay the propagation of the analog input signal. In other examples, the delay circuit system 305 is a passive component, such as a trace, which reduces the propagation speed of the analog input signal.

[0050] Resistor 310 has a first terminal and a second terminal. The first terminal of resistor 310 is coupled to delay circuit system 305. The second terminal of resistor 310 is coupled to DAC circuit system 230, amplifier circuit system 235, and filter circuit system 240. Figure 3 In the example, resistor 310 is configured to isolate the voltage of amplifier circuit system 235 from the voltage of analog input signal.

[0051] Capacitor 315 has a first terminal and a second terminal. The first terminal of capacitor 315 is coupled to DAC circuit system 230, amplifier circuit system 235, and resistors 310 and 320. The second terminal of capacitor 315 is coupled to one of the first output terminals of amplifier circuit systems 235 and 245, resistor 320, and interstage gain circuit system 300, one of which may be coupled to another instance of interstage gain circuit system 300. Resistor 320 has a first terminal and a second terminal. The first terminal of resistor 255 is coupled to DAC circuit system 230, amplifier circuit system 235, resistor 310, and capacitor 315. The second terminal of resistor 320 is coupled to a first of the first output terminals of amplifier circuit systems 235 and 245, capacitor 315, and interstage gain circuit system 300, the first of which may be coupled to another instance of interstage gain circuit system 300. Figure 3 In the example, capacitor 315 and resistor 320 form a low-pass filter circuit system. Alternatively, capacitor 315 and resistor 320 can be replaced with alternative circuit systems to form another low-pass filter or another type of filter.

[0052] exist Figure 3 In the example, interconnect circuitry 215 switches the p-side and m-side analog input signals. Alternatively, interstage gain circuitry 300 can be modified to remove or replace interconnect circuitry 215 with alternative circuitry. Figure 5 An example operation of the interstage gain circuitry system 300 is illustrated and described. Advantageously, the combinational circuitry system 220 and the amplifier circuitry system 245 are capable of compensating for cumulative differential signals.

[0053] Figure 4 This is a schematic diagram of an example interstage gain circuit system 400, which is... Figure 1 , 2 Another example of interstage gain circuit systems 105, 110, 115, 200, and 300. In Figure 4 In the example, the interstage gain circuit system 400 includes Figure 2 and 3 Delay circuit system 205 Figure 2 and 3 Resistor 210, Figure 2 and 3 Interconnection circuit system 215, Figure 2 and 3 ADC circuit system 225 Figure 2 and 3 DAC circuit system 230 Figure 2 and 3 Amplifier circuit system 235 Figure 2 and3 The filter circuit system 240, the first example resistor 405, the first example capacitor 410, the second example resistor 415, the second example capacitor 420, the third example resistor 425, and the third example capacitor 430. Figure 4 Example filter circuit system 240 includes Figure 2 and 3 250 capacitors and Figure 2 and 3 The resistor is 255.

[0054] Resistor 405 has a first terminal and a second terminal. The first terminal of resistor 405 is coupled to interconnect circuit system 215 and capacitor 410. The second terminal of resistor 405 is coupled to ADC circuit system 225, capacitors 410, 420, and 430, and resistors 415 and 425.

[0055] Capacitor 410 has a first terminal and a second terminal. The first terminal of capacitor 410 is coupled to interconnect circuit system 215 and resistor 405. The second terminal of capacitor 410 is coupled to ADC circuit system 225, resistors 405, 415, 425 and capacitors 420, 430.

[0056] Resistor 415 has a first terminal and a second terminal. The first terminal of resistor 415 is coupled to ADC circuit system 225, resistors 405, 425 and capacitors 410, 420, 430. The second terminal of resistor 415 is coupled to amplifier circuit system 235, filter circuit system 240 and capacitor 420.

[0057] Capacitor 420 has a first terminal and a second terminal. The first terminal of capacitor 420 is coupled to ADC circuit system 225, resistors 405, 415, 425 and capacitors 410, 430. The second terminal of capacitor 420 is coupled to amplifier circuit system 235, filter circuit system 240 and resistor 415.

[0058] Resistor 425 has a first terminal and a second terminal. The first terminal of resistor 425 is coupled to ADC circuit system 225, resistors 405, 415 and capacitors 410, 420, 430. The second terminal of resistor 425 is coupled to a common terminal supplying a common potential.

[0059] Capacitor 430 has a first terminal and a second terminal. The first terminal of capacitor 430 is coupled to ADC circuit system 225, resistors 405, 415, 425 and capacitors 410, 420. The second terminal of capacitor 430 is coupled to a common terminal supplying a common potential.

[0060] exist Figure 4In the example, resistors 405, 415, 425 and capacitors 410, 420, 430 have resistance and capacitance that provide gain to the input of ADC circuitry 225. Resistors 405, 425 and capacitors 410, 430 set the gain of the signal from interconnect circuitry 215. Resistors 415, 425 and capacitors 420, 430 set the gain of the signal from amplifier circuitry 235. In the example operation, resistors 405, 415, 425 are also configured as a summing circuitry that combines the currents from interconnect circuitry 215 and amplifier circuitry 235. Alternatively, as... Figure 2 and 3 As shown, resistors 405, 415, 425 and capacitors 410, 420, 430 can be used in amplifiers and combinational circuit systems (e.g. Figure 2 and 3 Combined circuit system 220 and Figure 2 and 3 The amplifier circuit system 245) is used to replace or describe it.

[0061] Figure 5 This indicates that it can be used. Figure 1 , 2 The flowchart illustrates an example implementation of at least one of the example operations 500 of the interstage gain circuit systems 105, 110, 115, 200, 300, and 400, which are implemented, instantiated, or executed. Figure 5 Example operation 500 begins at box 505, where the interstage gain circuitry systems 105, 110, 115, 200, and 300 receive analog signals (box 505). In some examples, for example... Figure 2 and 4 The interstage gain circuitry systems 200 and 400 receive single-ended analog input signals. In other examples, such as... Figure 3 The interstage gain circuit system 300 receives analog input signals from the p-side and m-side as a differential signal pair representing the analog input signals.

[0062] Figure 2 , 3 Delay circuit systems 205 and 305 delay the analog signal (Box 510). In some examples, delay circuit systems 205 and 305 use passive components such as traces to reduce the propagation speed of the analog signal. In other examples, delay circuit systems 205 and 305 are discrete components that delay the propagation delay of the analog signal. In both examples, the delay of delay circuit systems 205 and 305 is caused by… Figure 2 and 3The timing of the ADC circuit system 225 and the DAC circuit system 230 is determined. For example, when the ADC circuit system 225 and the DAC circuit system 230 have a propagation delay of ten milliseconds, the delay circuit systems 205 and 305 are constructed to have a delay of approximately ten milliseconds.

[0063] The ADC circuitry 225 samples the analog signal at the sampling time to determine the analog input voltage (box 515). In some examples, the ADC circuitry 225 samples and holds the analog signal to determine the analog input voltage to be converted to digital. In some such examples, the ADC circuitry 225 periodically samples the analog signal in response to a clock signal that determines the sampling timing. In some example operations, Figure 4 Resistors 405 and 425 have the function of amplifying the analog signal by a gain value. In some such examples, Figure 4 Capacitors 410 and 430 have capacitance relative to the source Figure 4 Resistor 415 and Figure 4 The feedback from capacitor 420 is used to stabilize the timing of the analog signal.

[0064] The ADC circuit system 225 converts the analog input voltage into digital bits (box 520). In some examples, the ADC circuit system 225 implements analog-to-digital conversion techniques to determine the digital bits representing the analog input voltage. In such examples, compared to the input voltage from... Figure 1 The digital output of latch 150 allows ADC circuitry 225 to generate a relatively low-resolution representation of the analog input voltage. For example, ADC circuitry 225 generates a three-bit representation of the analog input voltage, and latch 150 provides a sixteen-bit representation. In such examples, additional instances of interstage gain circuitry 105, 110, 115, 200, and 300 supply additional digital bits. Alternatively, in some examples, only the most significant bit (MSB) of ADC circuitry 225 is supplied to latch 150. Advantageously, implementing relatively low-resolution analog-to-digital conversion increases conversion speed and reduces the complexity of ADC circuitry 225.

[0065] DAC circuitry 230 uses digital bits to generate an approximate analog voltage (Box 525). In some examples, DAC circuitry 230 implements digital-to-analog conversion techniques to generate an analog voltage using digital bits from ADC circuitry 225. However, since digital bits are a relatively low-resolution representation of the analog input voltage, the analog voltage of DAC circuitry 230 is an approximation of the analog input voltage. Additionally, DAC circuitry 230 may receive the most significant bit from ADC circuitry 225 to further reduce conversion time.

[0066] Figure 2 and3 The amplifier circuit system 235 amplifies the difference between the approximate analog voltage and the delayed analog input signal by a certain gain (box 530). In some examples, the amplifier circuit system 235 amplifies the difference between the approximate analog voltage and the delayed analog input signal by a certain gain. Figure 2 Resistor 210 receives an analog signal and an approximate analog voltage from DAC circuitry 230. In such an example, amplifier circuitry 235 generates an output based on the difference between the analog input voltage from delay circuitry 205 and the approximate analog voltage from DAC circuitry 230. This difference between the approximate analog voltage and the analog input voltage is called a residual or quantization error. The residual represents the difference between a relatively low-resolution digital approximation of the analog input voltage and the actual analog input voltage. Furthermore, amplifier circuitry 235 amplifies the residual by a gain, referred to as interstage gain. Interstage gain allows subsequent interstage gain circuitry systems (e.g., interstage gain circuitry systems 110, 115) to use ADC and DAC circuitry systems with the same resolution as the preceding ADC circuitry system 225 and DAC circuitry system 230. Advantageously, such interstage gain reduces complexity when determining relatively high-precision bits of the analog input voltage.

[0067] Figure 2 and 3 The filter circuit system 240 filters the difference between the approximate analog voltage and the delayed analog input signal (box 535). In some examples, the filter circuit system 240 is coupled to provide a feedback path between the non-inverting input and output of the amplifier circuit system 235. In such examples, the filter circuit system 240 improves the stability of the interstage gain circuit system 200 by limiting the response time of the amplifier circuit system 235 to changes at the input. Additionally, the filter circuit system 240 improves the output of the amplifier circuit system 235 by preventing the amplifier circuit system 235 from amplifying relatively high-frequency noise.

[0068] Figure 2 and 3 The amplifier circuit system 245 or resistors 415, 425 determine the residual after amplification (box 540). In some examples, the filter circuit system 240 includes capacitor or inductor components, such as... Figure 2 and 3Capacitors 250 and 315. In such examples, filter circuitry 240 accumulates excess charge from previous residuals. The excess charge from previous residuals depends on the frequency of interstage gain circuitry 200 and 300 and the voltage (V(t)) at the output of amplifier circuitry 235. Amplifier circuitry 245 can use Equation (1) below to predict the voltage at the output of amplifier circuitry 235 based on the current voltage at the output of amplifier circuitry 235 for the next analog input voltage V(t+ΔT) from ADC circuitry 225. In such examples, amplifier circuitry 245 can use Equation (1) below to determine the gain of the residuals taking into account subsequent samples at subsequent times (t+ΔT). In some examples, resistors 415 and 425 have resistances that set the gain of the feedback from amplifier circuitry 235 using Equation (1) below.

[0069]

[0070] In other examples, amplifier circuitry 235 uses the complex domain (also known as the frequency domain or time domain) to predict the subsequent residual V. res (t+ΔT). In such examples, the Laplace transformation of equation (1) above can be used to determine the subsequent residuals. This type of Laplace transformation is described by equation (2) below. Advantageously, in the s-domain, the zeros and poles characterize the gain of the filter circuit system 240. Determining the transfer function (H(s)) of equation (2) below simplifies the determination of the poles and zeros. Equation (3) below describes the relationship between the interstage gain (G) a The transfer functions of the interstage gain circuit systems 200 and 300. However, the capacitor or inductor components of the filter circuit system 240 discharge between the samples of the ADC circuit system 225. Multiplying equation (3) by the attenuation value (d) f The residual at the next sampling time is taken into account, plus the delay of the delay circuit system 205. The amplifier circuit system 235 can use Equation (4) below to determine the residual at a subsequent time. Advantageously, Equation (4) allows the amplifier circuit system 235 to determine the residual of the filter circuit system 240 at a future time without integrating or deriving the output of the amplifier circuit system 235.

[0071] Laplace(V res (t+ΔT))=V(s)+sV(s)k Equation (2)

[0072]

[0073]

[0074] Figure 2 and 3 The combined circuit system 220 is designed for residual compensation of the analog signal (box 545). In some examples, the combined circuit system 220 subtracts the determined residual from the amplifier circuit system 245 from the analog input signal. In such examples, the combined circuit system 220 adjusts the analog input signal to account for the accumulation of charge from the previous residual in the filter circuit system 240. Advantageously, the amplifier circuit system 245 reduces the error caused by the previous residual. Advantageously, resistors 415, 425 reduce the error caused by the previous residual. Additionally, capacitors 410, 420, 430 allow the interstage gain circuit system 400 to have a gain equal to zero.

[0075] The ADC circuitry 225 samples the compensated analog signal at another sampling time to determine the analog input voltage (box 550). In some examples, the ADC circuitry 225 samples and holds the compensated analog signal to determine the analog input voltage to be converted to digital. In some such examples, the ADC circuitry 225 periodically samples the compensated analog signal to generate subsequent digital values.

[0076] Advantageously, the ADC circuit system 225 uses a compensated analog signal to generate digital bits. Advantageously, the DAC circuit system 230 uses the compensated digital bits to generate a compensated approximate analog voltage. Advantageously, the compensated approximate analog voltage increases the accuracy of the amplifier circuit system 235 by taking into account the accumulated charge from the previous residual in the filter circuit system 240.

[0077] Although reference Figure 5 The flowcharts described illustrate the example method, but implementations may also be used in this specification. Figure 1 , 2 Interstage gain circuit systems of 105, 110, 115, 200, 300 and 3 Figure 2 and 3 Many other methods exist for the amplifier circuit system 245. For example, the execution order of the blocks can be changed, or some of the blocks described can be altered, eliminated, or combined. Similarly, in the manufacturing process, additional operations may be included before, between, or after the blocks shown in the illustrated example.

[0078] Figure 6 This is a schematic diagram of an example interstage gain circuit system 600, which is... Figure 1 , 2 Another example of interstage gain circuit systems 105, 110, 115, 200, and 300. In Figure 6 In the example, the interstage gain circuit system 600 includes Figure 2 and 3Delay circuit system 205 Figure 2 and 3 Resistor 210, Figure 2 and 3 Interconnection circuit system 215, Figure 2 and 3 ADC circuit system 225 Figure 2 and 3 DAC circuit system 230 Figure 2 and 3 Amplifier circuit system 235 Figure 2 and 3 The filter circuit system 240, the combination circuit system 610, and the second DAC circuit system 620. Figure 6 Example filter circuit system 240 includes Figure 2 and 3 250 capacitors and Figure 2 and 3 The resistor is 255.

[0079] Interstage gain circuitry system 600 has an input terminal, a first output terminal, and a second output terminal. The input terminal of interstage gain circuitry system 600 is configured to couple to an output terminal of a previous instance of interstage gain circuitry system 600 or to an external circuitry system that supplies an analog input signal (Vin). In both examples, interstage gain circuitry system 600 receives an analog input signal at the input terminal. The first output terminal of interstage gain circuitry system 600 is configured to couple to a subsequent instance of interstage gain circuitry system 600. The second output terminal of interstage gain circuitry system 600 is configured to couple to a latch (e.g., ...). Figure 1 (Latches 120, 130, 140). In some examples, the interstage gain circuitry 600 has multiple output terminals configured to supply multiple digital bits to the latches or external circuitry.

[0080] The combinational circuit system 610 has a first terminal, a second terminal, and a third terminal. The first terminal (also called the first input terminal) of the combinational circuit system 610 is coupled to the interconnect circuit system 215. The second terminal (also called the second input terminal) of the combinational circuit system 610 is coupled to the DAC circuit system 620. The third terminal (also called the output terminal) of the combinational circuit system 610 is coupled to the ADC circuit system 225. Figure 6 In the example, the combinational circuit system 610 is constructed as an adder circuit system, which generates an output voltage by adding the input voltages.

[0081] The DAC circuit system 620 (also known as the feedback circuit system) has input terminals and output terminals. The input terminals of the DAC circuit system 620 are coupled to the ADC circuit system 225. The output terminals of the DAC circuit system 620 are coupled to the combinational circuit system 610. Figure 6 In the example, DAC circuitry 620 is configured to receive one or more least significant bits (LSBs) of the output of ADC circuitry 225. For instance, when ADC circuitry 225 performs a six-bit analog-to-digital conversion, ADC circuitry 225 supplies three most significant bits to DAC circuitry 230 and three least significant bits to DAC circuitry 620. Advantageously, the three least significant bits represent the quantization error between the approximate analog voltage from DAC circuitry 230 and the actual value of the analog input voltage. The following is in conjunction with... Figure 8 This section describes an example operation of the interstage gain circuit system 600.

[0082] Figure 7 This is a schematic diagram of an example interstage gain circuit system 700, which is... Figure 1 , 2 Another example of interstage gain circuit systems 105, 110, 115, 200, 300, and 600. In Figure 7 In the example, the interstage gain circuit system 700 includes Figure 2 , 3 The delay circuit system 205 and 4 Figure 2 , 3 And 4 resistor 210, Figure 2 , 3 Interconnection circuit system 215 with 4 Figure 2 , 3 The ADC circuit system of 225 and 4 Figure 2 , 3 The DAC circuit system of 230 and 4 Figure 2 , 3 The amplifier circuit system 235, the combination circuit system 705, the second DAC circuit system 710, the second delay circuit system 715, the third DAC circuit system 720, and the filter circuit system 725 are all included. Figure 7 The example filter circuit system 725 includes a first example capacitor 730, a second example resistor 735, a third example resistor 740, a second example capacitor 745, a fourth example resistor 750, a third example amplifier circuit system 755, a fifth example resistor 760, and a third example capacitor 765.

[0083] Interstage gain circuitry system 700 has an input terminal, a first output terminal, and a second output terminal. The input terminal of interstage gain circuitry system 700 is configured to couple to an output terminal of a previous instance of interstage gain circuitry system 700 or to an external circuit system that supplies an analog input signal (Vin). In both examples, interstage gain circuitry system 700 receives an analog input signal at the input terminal. The first output terminal of interstage gain circuitry system 700 is configured to couple to a subsequent instance of interstage gain circuitry system 700. The second output terminal of interstage gain circuitry system 700 is configured to couple to a latch (e.g., ...). Figure 1 (Latches 120, 130, 140). In some examples, the interstage gain circuitry 700 has multiple output terminals configured to supply multiple digital bits to the latches or external circuitry.

[0084] The combinational circuit system 705 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the combinational circuit system 705 (also referred to as the first input terminal) is coupled to the interconnect circuit system 215. The second terminal of the combinational circuit system 705 (also referred to as the second input terminal) is coupled to the DAC circuit system 710. The third terminal of the combinational circuit system 705 (also referred to as the third input terminal) is coupled to the DAC circuit system 720. The fourth terminal of the combinational circuit system 705 (also referred to as the output terminal) is coupled to the ADC circuit system 225. Figure 7 In the example, the combinational circuit system 705 is constructed as an adder circuit system, which generates an output voltage by adding the input voltages.

[0085] DAC circuit system 710 has input terminals and output terminals. The input terminals of DAC circuit system 710 are coupled to ADC circuit system 225. The output terminals of DAC circuit system 710 are coupled to combinational circuit system 705. Delay circuit system 715 has input terminals and output terminals. The input terminals of delay circuit system 715 are coupled to ADC circuit system 225 and DAC circuit system 710. The output terminals of delay circuit system 715 are coupled to DAC circuit system 720. DAC circuit system 720 has input terminals and output terminals. The input terminals of DAC circuit system 720 are coupled to delay circuit system 715. The output terminals of DAC circuit system 720 are coupled to combinational circuit system 705. DAC circuit systems 710, 720 and delay circuit system 715 may be referred to as a feedback circuit system.

[0086] exist Figure 7In the example, DAC circuitry 710 and delay circuitry 715 are configured to receive one or more least significant bits (LSBs) of the output of ADC circuitry 225. For instance, when ADC circuitry 225 performs a six-bit analog-to-digital conversion, it supplies three most significant bits to DAC circuitry 230 and three least significant bits to DAC circuitry 710 and delay circuitry 715. Advantageously, the three least significant bits represent the quantization error between the approximate analog voltage from DAC circuitry 230 and the actual value of the analog input voltage.

[0087] The filter circuit system 725 has a first terminal, a second terminal, and a third terminal. The first terminal of the filter circuit system 725 is coupled to resistor 210, DAC circuit system 230, and amplifier circuit system 235. The second terminal of the filter circuit system 725 is coupled to amplifier circuit system 235. The third terminal of the filter circuit system 725 is coupled to a first output terminal of interstage gain circuit system 700, which may be coupled to another instance of interstage gain circuit system 700.

[0088] Capacitor 730 has a first terminal and a second terminal. The first terminal of capacitor 730 is coupled to resistors 210 and 735, DAC circuit system 230, and amplifier circuit system 235. The second terminal of capacitor 730 is coupled to amplifier circuit system 235 and resistors 735 and 740. Resistor 735 has a first terminal and a second terminal. The first terminal of resistor 735 is coupled to resistor 210, DAC circuit system 230, amplifier circuit system 235, and capacitor 730. The second terminal of resistor 735 is coupled to amplifier circuit system 235, capacitor 730, and resistor 740.

[0089] Resistor 740 has a first terminal and a second terminal. The first terminal of resistor 740 is coupled to amplifier circuit system 235, capacitor 730, and resistor 735. The second terminal of resistor 740 is coupled to capacitor 745 and resistor 750. Capacitor 745 has a first terminal and a second terminal. The first terminal of capacitor 745 is coupled to resistors 740 and 750. The second terminal of capacitor 745 is coupled to a common terminal supplying a common potential. Resistor 750 has a first terminal and a second terminal. The first terminal of resistor 750 is coupled to resistor 740 and capacitor 745. The second terminal of resistor 750 is coupled to amplifier circuit system 755, resistor 760, and capacitor 765.

[0090] Amplifier circuit system 755 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of amplifier circuit system 755 (also referred to as the inverting input) is coupled to resistors 750 and 760 and capacitor 765. The second input terminal of amplifier circuit system 755 (also referred to as the non-inverting input terminal) is coupled to a common terminal supplying a common potential. The output terminal of amplifier circuit system 755 is coupled to resistor 760, capacitor 765, and the first output terminal of interstage gain circuit system 700, which may be coupled to subsequent embodiments of interstage gain circuit system 700.

[0091] Resistor 760 has a first terminal and a second terminal. The first terminal of resistor 760 is coupled to resistor 750, amplifier circuit system 755, and capacitor 765. The second terminal of resistor 760 is coupled to amplifier circuit system 755, capacitor 765, and a first output terminal of interstage gain circuit system 700, the first output terminal being coupled to a subsequent embodiment of interstage gain circuit system 700. Capacitor 765 has a first terminal and a second terminal. The first terminal of capacitor 765 is coupled to resistors 750 and 760 and amplifier circuit system 755. The second terminal of capacitor 765 is coupled to amplifier circuit system 755, resistor 760, and a first output terminal of interstage gain circuit system 700, the first output terminal being coupled to a subsequent embodiment of interstage gain circuit system 700.

[0092] exist Figure 7 In the example, filter circuit system 725 is a relatively high-order filter compared to filter circuit system 240. Alternatively, filter circuit system 725 can be replaced by alternative circuit systems to form filters of different orders or another type of filter. Advantageously, higher-order filters reduce errors at the output of interstage gain circuit system 700. The following is in conjunction with... Figure 8 This section describes an example operation of the interstage gain circuit system 700.

[0093] Figure 8 This indicates that it can be used. Figure 1 , 6 The flowchart of example operation 800 of example implementation, instantiation or execution of at least one of the example implementations of the interstage gain circuit systems 105, 110, 115, 600, and 700. Figure 8 Example operation 800 begins at box 805, where interstage gain circuitry systems 105, 110, 115, 600, and 700 receive analog signals (box 805). In some examples, interstage gain circuitry systems 600 and 700 receive single-ended analog input signals. Alternatively, similar to... Figure 3With modifications, the interstage gain circuit systems 600 and 700 can be modified to receive analog input signals from the p-side and m-side as differential signal pairs representing the analog input signals.

[0094] Figure 2 , 3 Delay circuit system 205 of 6 and 7 delays the analog signal (Box 810). In some examples, delay circuit system 205 uses passive components such as traces to reduce the propagation speed of the analog signal. In other examples, delay circuit system 205 is a discrete component that delays the propagation delay of the analog signal. In both examples, the delay of delay circuit system 205 is caused by... Figure 2 , 3 The timing of the ADC circuit system 225 and DAC circuit system 230 in 6 and 7 is determined. For example, when the ADC circuit system 225 and DAC circuit system 230 have a propagation delay of ten milliseconds, the delay circuit system 205 is constructed to have a delay of approximately ten milliseconds.

[0095] The ADC circuitry 225 samples the analog signal at the sampling time to determine the analog input voltage (Box 815). In some examples, the ADC circuitry 225 samples and holds the analog signal to determine the analog input voltage to be converted to digital. In some such examples, the ADC circuitry 225 periodically samples the analog signal in response to a clock signal that determines the sampling timing.

[0096] The ADC circuit system 225 converts the analog input voltage into digital bits (box 820). In some examples, the ADC circuit system 225 implements analog-to-digital conversion techniques to determine the digital bits representing the analog input voltage. In such examples, compared to the input voltage from... Figure 1 The digital output of latch 150 enables ADC circuitry 225 to generate a low-resolution representation of the analog input voltage. For example, ADC circuitry 225 generates a three-bit representation of the analog input voltage, and latch 150 provides a sixteen-bit representation. In such examples, additional instances of interstage gain circuitry systems 105, 110, 115, 600, and 700 supply additional digital bits. Alternatively, in some examples, only the most significant bit (MSB) of ADC circuitry 225 is supplied to latch 150. Advantageously, implementing low-resolution analog-to-digital conversion increases conversion speed and reduces the complexity of ADC circuitry 225.

[0097] DAC circuitry 230 uses the most significant bit of the digital bits to generate an approximate analog voltage (Box 825). In some examples, DAC circuitry 230 implements digital-to-analog conversion techniques to generate an analog voltage using digital bits from ADC circuitry 225. However, since digital bits are a low-resolution representation of the analog input voltage, the analog voltage of DAC circuitry 230 is an approximation of the analog input voltage. In some such examples, DAC circuitry 230 may use one or more of the most significant bits of the digital bits to generate an approximate analog voltage. Advantageously, reducing the number of bits that DAC circuitry 230 converts to analog increases the speed of digital-to-analog conversion.

[0098] Figure 2 and 3 The amplifier circuit system 235 amplifies the difference between the approximate analog voltage and the delayed analog input signal by a certain gain (box 830). In some examples, the amplifier circuit system 235 amplifies the difference between the approximate analog voltage and the delayed analog input signal by a certain gain. Figure 2 , 3 Resistors 210 (6 and 7) receive an analog signal and an approximate analog voltage from DAC circuitry 230. In such examples, amplifier circuitry 235 generates an output based on the difference between the analog input voltage from delay circuitry 205 and the approximate analog voltage from DAC circuitry 230. This difference between the approximate analog voltage and the analog input voltage is called a residual. The residual represents the difference between a low-resolution digital approximation of the analog input voltage and the actual analog input voltage. In some examples, the residual is referenced or described in relation to quantization error. Additionally, amplifier circuitry 235 amplifies the residual by a gain, referred to as interstage gain. Interstage gain allows subsequent interstage gain circuitry (e.g., interstage gain circuitry 110, 115) to use ADC and DAC circuitry with the same resolution as the preceding ADC circuitry 225 and DAC circuitry 230. Advantageously, such interstage gain reduces complexity when determining higher precision bits of the analog input voltage.

[0099] Figure 2 , 3The filter circuit systems 240 and 725 of 6 and 7 filter the difference between the approximate analog voltage and the delayed analog input signal (Box 835). In some examples, the filter circuit systems 240 and 725 are coupled to provide a feedback path between the non-inverting input and output of the amplifier circuit system 235. In such examples, the filter circuit systems 240 and 725 improve the stability of the interstage gain circuit systems 600 and 700 by limiting the response time of the amplifier circuit system 235 to changes at the input. Additionally, the filter circuit systems 240 and 725 improve the output of the amplifier circuit system 235 by preventing the amplifier circuit system 235 from amplifying high-frequency noise.

[0100] Figure 6 and 7 The DAC circuit systems 620, 710, and 720 determine the error voltage based on the least significant bit of the digital bits (Box 840). In some examples, the DAC circuit systems 620 and 710 use the least significant bit of the output of the ADC circuit system 225 to generate the error voltage. For example, when the ADC circuit system 225 is a six-bit converter, the DAC circuit systems 620 and 710 may receive three least significant bits. The DAC circuit systems 620 and 710 generate the error voltage as an analog value representing the digital bits. Advantageously, not using the least significant bit to generate an approximate analog voltage sets the error voltage to be proportional to the residual.

[0101] In addition, Figure 7 In the example, DAC circuitry 720 uses the least significant bit of the previous output of ADC circuitry 225 to generate a second error voltage. In such examples, delay circuitry 715 stores the previous least significant bit or delays the supply of the previous least significant bit to DAC circuitry 720. Advantageously, delay circuitry 715 and DAC circuitry 720 allow interstage gain circuitry 700 to consider residual errors across multiple samples. Advantageously, delay circuitry 715 and DAC circuitry 720 allow interstage gain circuitry 700 to consider residuals relative to higher-order filters, such as filter circuitry 725. Advantageously, the least significant bit of the digital bits is an approximate representation of the difference between the approximate analog voltage and the analog input voltage, its approximate residual.

[0102] Figure 6 and 7 The combinational circuit systems 610 and 705 compensate for the error voltage of the analog signal (Box 845). In some examples, the combinational circuit systems 610 and 705 apply the error voltage from the DAC circuit systems 620, 710, and 720 to the analog signal. In such examples, the combinational circuit systems 610 and 705 compensate for the residual of the previous sample by applying the error voltage to the analog input signal.

[0103] The ADC circuitry 225 samples the compensated analog signal at another sampling time to determine the analog input voltage (box 850). In some examples, the ADC circuitry 225 samples and holds the compensated analog signal to determine the analog input voltage to be converted to digital. In some such examples, the ADC circuitry 225 periodically samples the compensated analog signal to generate subsequent digital values.

[0104] Advantageously, the ADC circuit system 225 uses the compensated analog signal to generate digital bits. Advantageously, the DAC circuit system 230 uses the compensated digital bits to generate a compensated approximate analog voltage. Advantageously, the compensated approximate analog voltage increases the accuracy of the amplifier circuit system 235 by taking into account the charge accumulation from the previous residual in the filter circuit systems 240, 725.

[0105] Although reference Figure 9 The flowcharts described herein illustrate example methods, but implementations may also be used in this specification. Figure 1 , 6 Interstage gain circuit systems 105, 110, 115, 600, 700 and 7 Figure 6 and 7 Many other methods exist for the DAC circuit systems 620, 710, and 720. For example, the execution order of the boxes can be changed, or some of the described boxes can be altered, eliminated, or combined. Similarly, additional operations may be included before, between, or after the boxes shown in the illustrated examples during the manufacturing process.

[0106] Figure 9 yes Figure 1 , 2 Interstage gain circuit systems of 105, 110, 115, 200, 300, 600, 700 or more generally, 3, 6 and 7. Figure 1 Timing diagram 900 for example operation of CTP ADC circuit system 100. In Figure 9 In the example, timing diagram 900 includes a reference output voltage 910 and a compensated output voltage 920. The reference output voltage 910 illustrates the time transition when... Figure 2 and 3 Amplifier circuit system 245 and Figure 6 and 7 When the DAC circuit systems 620, 710, and 720 are not enabled (e.g., off, not operating, etc.), Figure 2 , 3The outputs of amplifier circuit systems 235, 6, and 7, are described. A reference output voltage 910 has an amplitude ranging from a first voltage 930 to a second voltage 940. A compensated output voltage 920 describes the output of amplifier circuit system 235 over time when amplifier circuit system 245 or DAC circuit systems 620, 710, 720 are enabled (e.g., switched on, operated, etc.). The compensated output voltage 920 has an amplitude ranging from a third voltage 950 to a fourth voltage 960. Advantageously, using feedback from amplifier circuit system 245 or DAC circuit systems 620, 710, 720 to compensate for variations in the analog input signal at the outputs of interstage gain circuit systems 105, 110, 115, 200, 300, 600, 700 is beneficial.

[0107] "Comprising" and "including" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of "comprising" or "including" (e.g., includes, encompassing, including, having, etc.) as a preamble or within any type of claim reference, additional elements, items, etc., may be present without exceeding the scope of the corresponding claim or reference. As used herein, the phrase "at least" is open-ended when used as a transitional term, for example, in the preamble of a claim, in the same way as the terms "comprising" and "including". The term "and / or", when used, for example, in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, C, such as: (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A and B” means an implementation that includes any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A or B” means an implementation that includes any one of: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the conduct or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” means an implementation that includes any one of: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the conduct or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation that includes any one of: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0108] As used herein, singular references (e.g., “a(a)”, “a(an)”, “first”, “second”, etc.) do not exclude plurals. As used herein, the term “a(a)” or “a(an)” refers to one or more of the objects mentioned. The terms “a(a)” (or “a(an)”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be performed by, for example, the same entity or object. Additionally, while individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible or advantageous.

[0109] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the earth. The first part is above the second part if at least one portion of the second part lies between the earth and the first part. Similarly, as used herein, the first part is "below" the second part when the first part is closer to the earth than the second part. As mentioned above, the first part may be above or below the second part, with one or more of the following conditions: there are other parts between them; there are no other parts between them; the first and second parts are in contact; or the first and second parts are not in direct contact with each other.

[0110] As used herein, a statement that any part (e.g., layer, film, region, area, or plate) is located on another part in any way (e.g., on it, situated on it, placed on it, or formed thereon, etc.) indicates that the referenced part is in contact with said other part, or that the referenced part is above said other part, with one or more intermediate parts positioned therebetween.

[0111] As used herein, unless otherwise indicated, a connection reference (e.g., attachment, coupling, connection, and engagement) may include an intermediate member between the elements referenced by the connection reference or the elements in relative movement. Thus, a connection reference does not necessarily imply that two elements are directly connected to each other or are fixedly related. As used herein, the statement that any part is in "contact" with another part is defined to mean that there is no intermediate part between the two parts.

[0112] Unless otherwise specifically stated, descriptive terms such as “first,” “second,” and “third” are used herein not to indicate, or otherwise suggest, priority, physical order, arrangement, or any sorting in the list, but merely as markers or at least one of any name to distinguish elements in order to facilitate understanding of the described examples. In some examples, the descriptive term “first” may be used to refer to an element in a particular embodiment, while the same element may be referred to in the claims by different descriptive terms such as “second” or “third.” In such cases, such descriptive terms are used only to clearly identify those elements within the context of the discussion (e.g., within the technical solution), in which elements may otherwise share the same name.

[0113] As used herein, “approximately” and “about” modify their objects / values ​​to identify the potential for variation that may occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may be imprecise due to at least one of manufacturing tolerances or other real-world defects. For example, unless otherwise specified herein, “approximately” and “about” may indicate that such dimensions are within a tolerance of + / - 10%.

[0114] As used herein, the phrase “communication”, including its variations, covers one or a combination of direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at at least one of periodic intervals, predetermined intervals, non-periodic intervals or one-off events.

[0115] As used herein, a “programmable circuit system” is defined as comprising at least one of the following: (i) one or more special-purpose circuits (e.g., special-purpose circuits (ASICs)) configured to perform a particular operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits programmable by instructions to perform one or more particular functions or operations and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as: a central processing unit (CPU) that can execute first instructions to perform one or more operations or functions; a field-programmable gate array (FPGA) that can be programmed with second instructions to configure or construct at least one of the following to instantiate one or more operations or functions corresponding to the first instructions; a graphics processing unit (GPU) that can execute first instructions to perform one or more operations or functions; a digital signal processor (DSP) that can execute first instructions to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers that can execute first instructions to perform one or more operations or functions; or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU can be implemented by a heterogeneous computing system that includes a variety of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and configuration technologies (e.g., application programming interfaces (APIs) that can assign computing tasks to any (or more) of the various types of programmable circuit systems that are suitable and available to perform the computing tasks).

[0116] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0117] In this description, the term "coupling" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in the first example, device A is coupled to device B via a direct connection; or (b) in the second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0118] A device “configured to” perform a task or function may be configured at the time of manufacture (e.g., by programming or hardwiring) to perform at least one of the following: perform the function, or be user-configurable (or reconfigurable) after manufacture to perform the function or other additional or alternative functions. The configuration may be achieved through at least one of firmware or software programming of the device, through at least one of the construction or layout of the device's hardware components and interconnects, or a combination thereof.

[0119] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0120] In this specification and claims, the described "circuit system" may include one or more circuits. A circuit or device described herein as including certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or an integrated circuit (IC) package) and may be adapted to be coupled, during or after manufacturing, for example by at least one of an end user or a third party, to at least some of the passive elements or sources to form the described structure.

[0121] The circuits described herein can be reconfigured to include replacement components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in at least one of series or parallel to provide the amount of impedance represented by the illustrated resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. While some elements in the described examples are included in the integrated circuit and others are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features described as being outside the integrated circuit may be included in said integrated circuit, and some features described as being inside the integrated circuit may be incorporated outside said integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of the following: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; or (iv) incorporated in / on the same printed circuit board.

[0122] The use of the phrase “ground” in the foregoing description includes at least one of chassis ground, wire ground, floating ground, virtual ground, digital ground, common ground, or any other form of grounding connection applicable to or suited to the teachings of this specification. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value indicates + / - 10% of said value, or, if the value is zero, a reasonable range of values ​​near zero.

[0123] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. An apparatus comprising: A combinational circuit system having a first input, a second input, and an output; An analog-to-digital converter (ADC) circuit system having an input and an output, wherein the input of the ADC circuit system is coupled to the output of the combined circuit system; A digital-to-analog converter (DAC) circuit system having an input and an output, wherein the input of the DAC circuit system is coupled to the output of the ADC circuit system; A resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first input of the combined circuit system; An amplifier circuit system having the output coupled to the DAC circuit system and the input to the second terminal of the resistor.

2. The device of claim 1, wherein the amplifier circuit system is a first amplifier circuit system having an output, and the device further includes a second amplifier circuit system having an input and an output, wherein the input of the second amplifier circuit system is coupled to the output of the first amplifier circuit system, and the output of the second amplifier circuit system is coupled to the second input of the combined circuit system.

3. The device of claim 1, wherein the DAC circuit system is a first DAC circuit system, the output of the ADC circuit system is a first output, the ADC circuit system further has a second output, and the device further includes a second DAC circuit system having an input and an output, the input of the second DAC circuit system being coupled to the second output of the ADC circuit system, and the output of the second DAC circuit system being coupled to the second input of the combined circuit system.

4. The device of claim 1, wherein the amplifier circuit system further has an output, and the device further includes an interstage gain circuit system having an input coupled to the output of the amplifier circuit system.

5. The device of claim 1, wherein the amplifier circuitry further has an output, and the device further comprises: A delay circuit system having a first terminal and a second terminal, the first terminal of the delay circuit system being coupled to a first input of the combined circuit system, and the second terminal of the delay circuit system being coupled to the first terminal of the resistor; as well as A filter circuit system having a first terminal and a second terminal, wherein the first terminal of the filter circuit system is coupled to the output of the DAC circuit system, the second terminal of the resistor and the input of the amplifier circuit system, and the second terminal of the filter circuit system is coupled to the output of the amplifier circuit system.

6. An apparatus comprising: A combinational circuit system that has inputs and outputs; An analog-to-digital converter (ADC) circuit system having an input and an output, wherein the input of the ADC circuit system is coupled to the output of the combined circuit system; A digital-to-analog converter (DAC) circuit system having an input and an output, wherein the input of the DAC circuit system is coupled to the output of the ADC circuit system; A first amplifier circuit system having an input and an output, wherein the input of the first amplifier circuit system is coupled to the output of the DAC circuit system; as well as A second amplifier circuit system has an input and an output, the input of the second amplifier circuit system being coupled to the output of the first amplifier circuit system, and the output of the second amplifier circuit system being coupled to the input of the combined circuit system.

7. The device of claim 6, wherein the input of the combined circuit system is a first input, the combined circuit system further has a second input, and the device further comprises: A delay circuit system having a first terminal and a second terminal, wherein the first terminal of the delay circuit system is coupled to the second input of the combined circuit system; as well as A resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the second terminal of the delay circuit system, and the second terminal of the resistor being coupled to the output of the DAC circuit system and the input of the first amplifier circuit system.

8. The device according to claim 6, wherein the combined circuit system is a subtraction circuit system.

9. The device according to claim 6, further comprising: An interstage gain circuit system having an input coupled to the output of the first amplifier circuit system and the input of the second amplifier circuit system; as well as A latch having an input coupled to the output of the ADC circuit system and the input of the DAC circuit system.

10. The device of claim 6, further comprising a filter circuit system, the filter circuit system comprising: A capacitor having a first terminal and a second terminal; and A resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the output of the DAC circuit system, the input of the first amplifier circuit system and the first terminal of the capacitor, and the second terminal of the resistor being coupled to the output of the first amplifier circuit system, the input of the second amplifier circuit system and the second terminal of the capacitor.

11. An apparatus comprising: A combinational circuit system that has inputs and outputs; An analog-to-digital converter (ADC) circuit system having an input, a first output, and a second output, wherein the input of the ADC circuit system is coupled to the output of the combined circuit system; A first digital-to-analog converter (DAC) circuit system has an input and an output, wherein the input of the first DAC circuit system is coupled to the first output of the ADC circuit system; An amplifier circuit system having an input coupled to the output of the DAC circuit system; as well as A second DAC circuit system has an input and an output, wherein the input of the second DAC circuit system is coupled to the second output of the ADC circuit system, and the output of the second DAC circuit system is coupled to the input of the combined circuit system.

12. The device of claim 11, wherein the input of the combined circuit system is a first input, the combined circuit system further has a second input, and the device further comprises: A delay circuit system having a first terminal and a second terminal, wherein the first terminal of the delay circuit system is coupled to the second input of the combined circuit system; as well as A resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the second terminal of the delay circuit system, and the second terminal of the resistor being coupled to the output of the first DAC circuit system and the input of the amplifier circuit system.

13. The device of claim 11, wherein the combined circuit system is an additive circuit system.

14. The device of claim 11, wherein the amplifier circuitry further has an output terminal, and the device further comprises: An interstage gain circuit system having an input coupled to the output of the amplifier circuit system; as well as A latch having an input coupled to the output of the ADC circuit system and the input of the first DAC circuit system.

15. The device of claim 11, wherein the amplifier circuitry further has an output terminal, and the device further includes a filter circuitry comprising: A capacitor having a first terminal and a second terminal; and A resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the output of the DAC circuit system, the input of the amplifier circuit system and the first terminal of the capacitor, and the second terminal of the resistor being coupled to the output of the amplifier circuit system and the second terminal of the capacitor.

16. An apparatus comprising: The first-stage interstage gain circuit system includes: A combinational circuit system that has inputs and outputs; An analog-to-digital converter (ADC) circuit system having an input and an output, wherein the input of the ADC circuit system is coupled to the output of the combined circuit system; A digital-to-analog converter (DAC) circuit system having an input and an output, wherein the input of the DAC circuit system is coupled to the output of the ADC circuit system; and An amplifier circuit system having an input and an output, wherein the input of the amplifier circuit system is coupled to the output of the DAC circuit system; as well as The second-stage interstage gain circuit system has an input coupled to the output of the amplifier circuit system.

17. The device of claim 16, wherein the amplifier circuit system is a first amplifier circuit system having an output, and the device further includes a second amplifier circuit system having an input coupled to the output of the first amplifier circuit system and the input of the second interstage gain circuit system.

18. The device of claim 16, wherein the DAC circuit system is a first DAC circuit system, the output of the ADC circuit system is a first output, the ADC circuit system further has a second output, and the device further includes a second DAC circuit system having an input coupled to the second output of the ADC circuit system.

19. The device of claim 16, wherein the input of the combined circuit system is a first input, the combined circuit system further has a second input, and the device further comprises: A delay circuit system having a first terminal and a second terminal, wherein the first terminal of the delay circuit system is coupled to the second input of the combined circuit system; as well as A resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the second terminal of the delay circuit system, and the second terminal of the resistor being coupled to the output of the DAC circuit system and the input of the amplifier circuit system.

20. The device of claim 16, further comprising a filter circuit system, the filter circuit system comprising: A capacitor having a first terminal and a second terminal; and A resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the output of the DAC circuit system, the input of the amplifier circuit system and the first terminal of the capacitor, and the second terminal of the resistor being coupled to the output of the amplifier circuit system, the input of the second interstage gain circuit system and the second terminal of the capacitor.

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