A communication method, an electronic device, a communication apparatus, and a storage medium

Abstract

The embodiment provides a communication method, an electronic device, a communication device and a storage medium, which are applied to the technical field of signal processing and are used for improving the precision of signal rate measurement. The communication method comprises the following steps: obtaining the pulse width of a first clock signal based on the pulse width sequence of an input signal; determining the reference signal pulse width corresponding to each input signal pulse width based on each input signal pulse width and the pulse width of the first clock signal; determining the clock deviation corresponding to each input signal pulse width based on each input signal pulse width and the corresponding reference signal pulse width, and obtaining a clock deviation sequence; performing a sliding window operation on the clock deviation sequence based on a window width to obtain an updated clock deviation sequence; and obtaining the signal rate of the input signal based on the corrected input signal pulse width sequence in the case that all the clock deviations in the updated clock deviation sequence are smaller than a deviation threshold.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, in particular to a communication method, an electronic device, a communication apparatus and a storage medium. BACKGROUND

[0002] In the field of digital communication and high-speed signal testing, accurate clock recovery is crucial, which is the basis for accurate jitter analysis, eye diagram drawing and other operations. In oscilloscopes and other instruments, accurate measurement of the rate of the signal is required to achieve clock recovery, and then accurate clock information is extracted. Therefore, high-precision signal rate measurement is a technical indicator that the industry is concerned about. SUMMARY

[0003] The present application discloses a communication method, an electronic device, a communication apparatus and a storage medium, which are used to improve the accuracy of signal rate measurement.

[0004] In a first aspect, the present application provides a communication method, comprising: obtaining a pulse width of a first clock signal based on a pulse width sequence of an input signal, the pulse width sequence of the input signal comprising a plurality of input signal pulse widths arranged in time sequence, and the pulse width of the first clock signal being the smallest input signal pulse width in the pulse width sequence of the input signal; determining a reference signal pulse width corresponding to each input signal pulse width based on each input signal pulse width and the pulse width of the first clock signal, the reference signal pulse width being a pulse width corresponding to an integer multiple with the smallest difference from the input signal pulse width in a plurality of integer multiples of the pulse width of the first clock signal; determining a clock deviation corresponding to each input signal pulse width based on each input signal pulse width and the corresponding reference signal pulse width to obtain a clock deviation sequence, the clock deviation being a difference between each input signal pulse width and the corresponding reference signal pulse width; performing a sliding window operation on the clock deviation sequence based on a window width to obtain an updated clock deviation sequence, the sliding window operation comprising a plurality of sliding window processes, a step length between windows corresponding to each sliding window process being a sliding window step length, and each sliding window process comprising: in a case where a change value of the clock deviation in the window is greater than a change threshold, correcting an input signal pulse width corresponding to the clock deviation in the window and updating the clock deviation sequence in the window. Wherein, the window width is a preset time distance, and the change value is a difference between a maximum value of the clock deviation in the window and a minimum value of the clock deviation in the window. In a case where all clock deviations in the updated clock deviation sequence are less than a deviation threshold, obtaining a signal rate of the input signal based on the corrected pulse width sequence of the input signal.

[0005] In the embodiments of the present application, by introducing a correction mechanism based on a sliding window, on the one hand, the problem of inaccurate signal rate measurement caused by signal jitter is effectively improved, and on the other hand, the efficiency of signal rate measurement is improved on the basis of ensuring the accuracy of signal rate measurement, thereby realizing high-precision and high-efficiency signal rate recovery. Specifically, by using the smallest one of the plurality of input signal pulse widths to establish an initial reference clock signal (i.e., a first clock signal), and calculating the deviation between each input signal pulse width and the closest integer multiple of the pulse width of the first clock signal (i.e., a reference signal pulse width), a clock deviation sequence is formed. In theory, under ideal non-jitter conditions, the values of each input signal pulse width are accurate, at this time, the signal rate is the reciprocal of the pulse width of the first clock signal, and each input signal pulse width should be an integer multiple of the pulse width of the first clock signal, that is, all deviations should be 0. However, the present application notes that due to signal jitter, the values of the input signal pulse widths are not completely accurate, so the reciprocal of the pulse width of the first clock signal as the signal rate is also likely to be inaccurate. The present application uses the property that the input signal pulse widths should be integer multiples of the pulse width of the first clock signal in theory, and the clock deviation sequence formed can reflect the clock deviation distribution of the input signal pulse widths. Then, in the correction phase, a sliding window mechanism is used to traverse the clock deviation sequence, and when the deviation change value (the difference between the maximum clock deviation in the window and the minimum clock deviation in the window) in the window exceeds the preset threshold, the pulse width corresponding to the steepest change (i.e., the point where signal jitter is most likely to occur) in the window is corrected, avoiding the defect that the inaccurate values of individual input signal pulse widths (caused by severe jitter) lead to inaccurate rate calculation.

[0006] In addition, compared with the global optimization algorithm which needs to perform complex fitting or adjustment on each data point, the sliding window strategy of the present embodiment significantly reduces the computational complexity. It does not need to process all subtle jitter, but focuses on significant abnormal mutation points caused by cumulative effects that exceed the threshold, achieving a good balance between accurate correction and computational efficiency. The pulse width sequence after sliding window correction can more truly reflect the ideal periodic characteristics of the signal, thereby improving the accuracy of calculating the signal rate.

[0007] In a possible implementation, the method for correcting the input signal pulse width corresponding to the clock deviation comprises: in the case that the change value of the clock deviation in the window is greater than the change threshold and the clock deviation jumps downward, the corrected input signal pulse width is more than the uncorrected input signal pulse width by one pulse width corresponding to the first clock signal; and in the case that the change value of the clock deviation in the window is greater than the change threshold and the clock deviation jumps upward, the corrected input signal pulse width is less than the uncorrected input signal pulse width by one pulse width corresponding to the first clock signal.

[0008] In the embodiments of the present application, when the deviation change is detected to exceed the threshold by using the sliding window, the jump direction of the deviation is further analyzed to perform targeted correction: when the clock deviation jumps downward, it indicates that the current pulse width is "short" compared to the nearest ideal integer multiple reference pulse width, which usually means that the pulse width may have "missed" one complete clock period (the pulse width corresponding to the first clock signal) in reality, and at this time, the modified pulse width is increased by one pulse width corresponding to the first clock signal, which is beneficial to make up for the missing period count and make the pulse width estimation return to the vicinity of the correct integer multiple reference. When the clock deviation jumps upward, it indicates that the current pulse width is "long", and it is likely to have "overestimated" one pulse width corresponding to the first clock signal, and at this time, the modified pulse width is reduced by one pulse width corresponding to the first clock signal, which is beneficial to eliminate the redundant period count and correct the overestimation error.

[0009] In a possible implementation, the method further includes: increasing the window width when all clock deviations in the updated clock deviation sequence have a clock deviation greater than or equal to the deviation threshold; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain the updated clock deviation sequence.

[0010] In the embodiments of the present application, the initial fixed window width may not be able to effectively capture all the integer period misjudgments caused by severe jitter or complex noise patterns. By setting the closed-loop feedback rule "if there is still a clock deviation exceeding the deviation threshold after completing the scanning, increase the window width and re-execute the sliding window operation", the algorithm can intelligently judge the current correction effect. If it has not completely converged (i.e. there is still a large deviation), the detection field of view is automatically widened (the window is increased), so that global and cumulative errors that are hidden or not accurately located under a smaller window can be found and corrected. This self-adjusting mechanism ensures that the correction process can proceed towards the direction of completely eliminating significant deviations.

[0011] In a possible implementation, increasing the window width includes: increasing the width of the sliding window from X times the pulse width of the first clock signal to (X+1) times the pulse width of the first clock signal, X being a positive integer, and continuing to scan the subsequent clock deviations.

[0012] In the embodiments of the present application, the "pulse width of the first clock signal" (i.e. the minimum pulse width) is used as the adjustment reference unit, which ensures that the expansion of the window is strictly aligned with the clock period characteristics of the signal itself. This avoids the uncertainty that may be caused by using an arbitrary or unitless step for adjustment, so that each window increase corresponds to accurately covering one more potential clock period position on the time axis, thereby being more conducive to systematically and structurally capturing and correcting the deviation patterns caused by integer period misjudgments, and enhancing the reliability of the entire adjustment process and the consistency of the results.

[0013] In a possible implementation, X is greater than or equal to 3 and less than or equal to 10.

[0014] In the embodiment of the present application, the lower limit of the window width is set to be not less than the pulse width of three first clock signals (X≥3), which ensures that the window has basic signal observation capability. A window with a width covering at least the pulse width of three first clock signals can effectively accommodate at least one complete signal transition period and necessary context information, so that it can reliably distinguish random small jitter from systematic and sudden deviation caused by integer period misjudgment. This avoids misjudgment (for example, mistaking normal jitter for mutation) or missing judgment of continuous errors due to insufficient field of view when the window is too narrow, and ensures the stability and accuracy of initial detection. In addition, the upper limit is set to be not more than the pulse width of ten first clock signals (X≤10), which effectively controls the calculation complexity and prevents over-smoothing.

[0015] In a possible implementation, the variation threshold is the pulse width of the first clock signal.

[0016] In the embodiment of the present application, by directly associating the variation threshold with the characteristic of the signal itself, that is, the pulse width of the first clock signal, it means that the standard for judging whether there is a mutation in a window is based on the ideal period length of the signal itself. When the difference between the maximum and minimum clock deviation in the window exceeds the pulse width of one first clock signal, it is physically clear that at least one cumulative misjudgment of an integer number of clock periods has occurred in the window (for example, a certain pulse width is less or more than one complete pulse width of the first clock signal). This threshold based on the intrinsic scale of the signal is more reasonable and universal than arbitrarily setting a fixed numerical threshold (such as a certain voltage or time value), and can adapt to signals of different rates, effectively avoiding missed detection (threshold too high) or false detection (threshold too low) caused by improper threshold setting, and ensuring that only significant deviation caused by integer period error triggers the correction mechanism.

[0017] In a possible implementation, the signal rate of the input signal is obtained based on the corrected input signal pulse width sequence, including: obtaining the signal rate of the input signal based on the corrected input signal pulse width sequence by using the least square method.

[0018] In the embodiment of the present application, the least square method is used to calculate the signal rate based on the corrected pulse width sequence, which combines the advantages of front-end sliding window correction eliminating integer errors with the theory of back-end mathematical optimization, and improves the accuracy of signal rate measurement.

[0019] In a possible implementation, the signal rate of the input signal is obtained based on the modified input signal pulse width sequence by using a least square method, including: a second clock signal is obtained based on the modified input signal pulse width sequence, and the pulse width of the second clock signal corresponds to the minimum signal pulse width in the modified input signal pulse width sequence. The number of clock pulses contained in each modified input signal pulse width is obtained based on the second clock signal, and the number of clock pulses is the ratio of the corresponding modified input signal pulse width and the pulse width of the second clock signal. The signal rate of the input signal is obtained by using the least square method based on the number of clock pulses corresponding to each modified input signal pulse width. The least square method is used to adjust the signal rate and the phase to minimize the square sum of the deviation of the clock edge obtained according to the product of the reciprocal of the signal rate and the number of clock pulses corresponding to each modified input signal pulse width and the target phase corresponding to each modified input signal pulse width and the edge of the corresponding output signal.

[0020] In the embodiments of the present application, the modified data is not directly used for final calculation, but an updated clock reference, the second clock signal (whose pulse width is the minimum value in the modified sequence), is extracted therefrom. The pulse width corresponding to the second clock signal is a more accurate reference than the initial "first clock signal pulse width", which is generated based on the modified data of higher quality and closer to the ideal. On this basis, the number of accurate clock periods (which can be a non-integer multiple) contained in each modified pulse width is calculated based on this better reference. This is equivalent to performing a data preprocessing and parameter pre-calibration before entering the final least square optimization, which provides a significantly improved initial starting point for subsequent mathematical optimization, thereby achieving higher final accuracy as a whole. In addition, the least square method is used in the embodiments of the present application, which minimizes the overall deviation (sum of squares of errors) between the ideal clock edges generated according to the estimated clock parameters (reciprocal of signal rate, i.e., corresponding to the minimum signal pulse width, i.e., clock signal pulse width, and phase) and the actual data edges of the original input signal. Since the position of the finally recovered ideal clock edge is directly determined by the two parameters of signal rate and phase, the joint adjustment and optimization of these two parameters by the least square method can systematically eliminate residual random errors and small systematic deviations. This makes the signal rate and phase values solved finally be the optimal estimation in a statistical sense, and are closer to the true values, thereby ensuring that the clock recovery result has high theoretical accuracy.

[0021] In a possible implementation, the communication method is applied to a communication system, and the communication system comprises a signal generation apparatus and a clock recovery apparatus. The signal generation apparatus is configured to perform any of the communication methods described above. The clock recovery apparatus comprises a phase discriminator and a voltage-controlled oscillator. After obtaining the signal rate of the input signal, the communication method further comprises: the signal generation apparatus inputs the signal rate to the voltage-controlled oscillator to obtain a recovered clock signal output by the voltage-controlled oscillator, and the recovered clock signal is used for clock recovery. The phase discriminator outputs a control signal based on the recovered clock signal and a mapping relationship table. The mapping relationship table is used to represent a mapping relationship between the control signal and a level of the input signal corresponding to a transition edge of the recovered clock signal. The control signal is used to control the voltage-controlled oscillator to adjust the oscillation frequency and phase, so that the recovered clock signal is consistent with the input signal edge.

[0022] In the embodiments of the present application, the accurate signal rate calculated is input to the voltage-controlled oscillator, and a recovered clock signal with a highly matched frequency can be directly generated. More importantly, by introducing a feedback control loop based on the mapping relationship table (a control signal is output by table lookup according to the input signal level corresponding to the transition edge time of the recovered clock), the control strategy of the phase discriminator based on the mapping relationship table provides an efficient and robust phase synchronization mechanism. Compared with the way of calculating the control signal by setting adders, comparators and other hardware circuits, the present application does not need to set complex hardware circuits, but can quickly obtain the result by table lookup, greatly reduces the calculation complexity, and significantly improves the phase discrimination speed.

[0023] In a possible implementation, in the mapping relationship table, when the level of the input signal corresponding to a transition edge of the recovered clock signal is high and the level of the input signal corresponding to a previous transition edge of the recovered clock signal is high, the control signal is low. When the level of the input signal corresponding to a transition edge of the recovered clock signal is high and the level of the input signal corresponding to a previous transition edge of the recovered clock signal is low, the control signal is high. When the level of the input signal corresponding to a transition edge of the recovered clock signal is low and the level of the input signal corresponding to a previous transition edge of the recovered clock signal is high, the control signal is high. When the level of the input signal corresponding to a transition edge of the recovered clock signal is low and the level of the input signal corresponding to a previous transition edge of the recovered clock signal is low, the control signal is low.

[0024] In the embodiments of the present application, by only investigating the input signal level (high or low) at the moment of the recovery clock jump edge and the moment before it, it can be determined whether the current phase relationship is "leading" or "lagging", and the corresponding binary control signal (high or low level) is output to instruct the voltage-controlled oscillation unit to "speed up" or "slow down". For example, when the recovery clock edge captures the input signal from "high" to "low" (corresponding to the third case in the embodiments), it indicates that the recovery clock may be ahead of the valid data window of the input signal, at this time, the "high" level control signal is output to make the voltage-controlled oscillation unit slow down appropriately to align the phase. The complex analog voltage comparison or digital calculation is avoided, the decision speed is fast, the hardware implementation area is small, the power consumption is low, and it is suitable for application in the clock data recovery circuit of high-speed serial interface.

[0025] In a second aspect, the present application provides an electronic device, comprising: a communication interface and a processor. The processor is coupled to the communication interface and is configured to perform any of the communication methods in the first aspect.

[0026] In a third aspect, the present application provides a communication device, comprising: a minimum pulse width calculation module, configured to obtain a pulse width of a first clock signal based on a pulse width sequence of an input signal, the pulse width sequence of the input signal comprising a plurality of input signal pulse widths arranged in time sequence, and the pulse width of the first clock signal being the minimum one of the input signal pulse widths in the pulse width sequence of the input signal; a reference pulse width calculation module, configured to determine a reference signal pulse width corresponding to each input signal pulse width based on the input signal pulse width and the pulse width of the first clock signal, the reference signal pulse width being a pulse width corresponding to the minimum difference between the input signal pulse width and a plurality of integer multiples of the pulse width of the first clock signal; a clock deviation calculation module, configured to determine a clock deviation corresponding to each input signal pulse width based on the input signal pulse width and the corresponding reference signal pulse width, to obtain a clock deviation sequence, the clock deviation being the difference between each input signal pulse width and the corresponding reference signal pulse width; a pulse width correction module, configured to perform a sliding window operation on the clock deviation sequence based on a window width to obtain an updated clock deviation sequence, the sliding window operation comprising a plurality of sliding window processes, a step length between the windows corresponding to each sliding window process being a sliding window step length, and each sliding window process comprising: in the case that a change value of the clock deviation in the window is greater than a change threshold, correcting the input signal pulse width corresponding to the clock deviation in the window and updating the clock deviation sequence in the window. Wherein, the window width is a preset time distance, and the change value is the difference between the maximum value of the clock deviation in the window and the minimum value of the clock deviation in the window. A judgment module, configured to obtain a signal rate of the input signal based on the corrected pulse width sequence of the input signal in the case that all the clock deviations in the updated clock deviation sequence are less than a deviation threshold.

[0027] In a fourth aspect, the present application provides a computer readable storage medium, which comprises instructions. When the instructions are run on a processor, the processor is caused to perform the communication method according to any one of the first aspect.

[0028] The technical principles and advantages of the second aspect, the third aspect and the fourth aspect can refer to the above description of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0030] Figure 1 A flowchart of a communication method provided by an embodiment of the present application is shown Figure 1 ;

[0031] Figure 2 A pulse width sequence diagram of an input signal provided by an embodiment of the present application is shown

[0032] Figure 3 A schematic diagram of a sliding window operation provided by an embodiment of the present application is shown

[0033] Figure 4 A flowchart of a communication method provided by an embodiment of the present application is shown Figure 2 ;

[0034] Figure 5 A flowchart of a communication method provided by an embodiment of the present application is shown Figure 3 ;

[0035] Figure 6 A flowchart of a communication method provided by an embodiment of the present application is shown Figure 4 ;

[0036] Figure 7 A structural schematic diagram of a clock recovery circuit provided by an embodiment of the present application is shown

[0037] Figure 8 A structural schematic diagram of a half-speed phase detector provided by an embodiment of the present application is shown

[0038] Figure 9 An output waveform diagram of a half-speed phase detector provided by an embodiment of the present application is shown

[0039] Figure 10This paper shows a schematic diagram of the structure of a clock recovery device provided in an embodiment of this application;

[0040] Figure 11 The diagram shows the output waveform of a half-speed phase detector model provided in an embodiment of this application.

[0041] Figure 12 A schematic diagram of the structure of a communication system provided in an embodiment of this application is shown;

[0042] Figure 13 This application provides a flowchart illustrating a communication method according to an embodiment. Figure 5 ;

[0043] Figure 14 This paper shows a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0044] Figure 15 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1- Clock recovery circuit;

[0047] 10-Phase-locked loop structure;

[0048] 101-Phase detector; 102-Loop filter; 103-Voltage controlled oscillator;

[0049] 100-half-speed phase detector;

[0050] 1001 - First D flip-flop; 1002 - Second D flip-flop; 1003 - XOR circuit;

[0051] 3-Communication system;

[0052] 31 - Signal generating device;

[0053] 4- Clock recovery device;

[0054] 41-Phase detection unit; 42-Judgment unit; 43-Loop filter unit; 44-Voltage controlled oscillator unit;

[0055] 6-communication device;

[0056] 61 - Minimum pulse width calculation module; 62 - Reference pulse width calculation module; 63 - Clock deviation calculation module; 64 - Pulse width correction module; 65 - Judgment module;

[0057] 8-Electronic devices;

[0058] 81-Processor; 82-Memory; 83-Communication interface. Detailed Implementation

[0059] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of distinguishing the same type of features, and should not be understood as indicating relative importance, quantity, order, etc.

[0060] The terms "exemplary" or "for example" and the like used in the present application are used to indicate that an embodiment or design scheme described as "exemplary" or "for example" is not necessarily preferred or advantageous over other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present relevant concepts in a concrete manner.

[0061] The terms "coupled", "coupling", "connected", "connecting" involved in the embodiments of the present application should be interpreted in a broad sense, for example, can refer to physical direct connection or indirect connection through electronic devices.

[0062] With the current high-speed digital design developing towards faster speed and larger data throughput, higher and higher requirements are put forward for the transmission speed of communication systems, and the transmission bandwidth of communication interface technology as an important part of it is also constantly improving with the times.

[0063] Serial communication technology gradually replaces the traditional parallel scheme and becomes the mainstream technology for realizing high-speed communication interface due to its advantages of high transmission rate, strong anti-interference ability and less occupied channel and pin number. Specifically, the serial communication technology can include but is not limited to peripheral component interconnect express (PICE) protocol, universal serial bus (USB) and serializer / deserializer (SerDes) interface technology.

[0064] In high-speed serial transmission, in order to avoid the clock offset problem in parallel transmission, in the transmission process, the data encoding will embed the clock signal (CLK) into the data stream, and the receiving end needs to extract the clock information through the clock data recovery (CDR) technology, and sample the data according to the recovered clock, to ensure the accuracy and reliability of signal transmission and reception.

[0065] Embodiment one:

[0066] The clock recovery method of high-speed serial interfaces such as Serdes, PCIE, USB, etc. usually adopts a simple algorithm based on the minimum pulse width of the signal to estimate the signal rate. However, in the case of severe jitter, noise or complex code type of the signal, these methods are easily disturbed and may lead to misjudgment of the integer multiple of the basic clock unit, thereby generating a basic error. This error will be passed to the entire recovered link, causing the recovered clock information (which can include clock frequency or phase) to deviate from the true value, and then significantly affecting the reliability of the measurement results of the downstream analysis module such as jitter and eye diagram. How to achieve high-precision and high-robust clock recovery in a high-jitter environment has become a key technical challenge to improve the performance of test instruments.

[0067] To implement clock recovery, the signal rate needs to be accurately measured first, and then the accurate clock information can be extracted. Therefore, high-precision signal rate measurement is a technical indicator that the industry is concerned about. In order to improve the accuracy of signal rate measurement, the present disclosure provides a communication method, which effectively improves the problem of misjudgment of integer clock periods caused by signal jitter by introducing a sliding window-based correction mechanism, thereby achieving high-precision and high-efficiency signal rate measurement. As shown in Figure 1 , Figure 1 A flowchart of a communication method provided by an embodiment of the present application is shown, which specifically includes steps S110-S150:

[0068] S110, based on the pulse width sequence of the input signal, obtaining the pulse width of the first clock signal.

[0069] In some possible implementations, the input signal can be a non-return-to-zero (NRZ) and pulse amplitude modulation n-level (PAMn) signal. As shown in Figure 2 , Figure 2 A pulse width sequence diagram of an input signal provided by an embodiment of the present application is shown, which includes a plurality of input signal pulse widths arranged in time order (such as t1, t2, t3, t4,..., tn-1, tn). By performing edge detection (for example, the time point at which the voltage crosses the preset threshold) on the input signal waveform, a series of time intervals of adjacent edges, i.e. the pulse width sequence, is calculated. The pulse width of the first clock signal is the smallest input signal pulse width in the pulse width sequence of the input signal.

[0070] As shown in Figure 2 , the pulse width sequence can include: the first pulse width = t2-t1, the second pulse width = t3-t2, the third pulse width = t4-t3,..., the (n-1)th pulse width = tn-tn-1.

[0071] In some embodiments, an edge detection module can be configured in a detection device, such as a digital signal processor (DSP), to record the precise sampling time stamps (e.g., t1, t2, t3, t4,..., tn-1, tn) when the sampled input signal voltage changes from below a threshold value to above the threshold value (or vice versa). The difference between consecutive time stamps is calculated to obtain a pulse number array or a pulse width sequence. A comparator is used to find the minimum value in the array or sequence, and the minimum input signal pulse width is output as the pulse width of the first clock signal.

[0072] S120, based on each input signal pulse width and the pulse width of the first clock signal, determine the reference signal pulse width corresponding to each input signal pulse width.

[0073] In some possible embodiments, the reference signal pulse width is the pulse width of the first clock signal multiplied by an integer, and the integer corresponds to the minimum difference between the input signal pulse width and the pulse width of the first clock signal.

[0074] In theory, each actual pulse width in the pulse width sequence of the input signal should include an integer number of pulse widths of the first clock signal. The ratio or quotient of each actual pulse width, such as the first pulse width = t2-t1, the second pulse width = t3-t2, the third pulse width = t4-t3,..., the n-1 pulse width = tn-tn-1, to the pulse width of the first clock signal is calculated, and the ratio or quotient is rounded to the nearest integer. The pulse width corresponding to the integer value closest to the actual value is selected as the "reference signal pulse width".

[0075] In some embodiments, the input signal edge time stamps are taken as t1=0.98ns, t2=2.93ns, t3=3.91ns, t4=6.86ns, t5=8.81ns.

[0076] The pulse width sequence is: the first pulse width = 1.95ns, the second pulse width = 0.98ns, the third pulse width = 2.95ns, and the fourth pulse width = 1.95ns. The minimum pulse width is the second pulse width = 0.98ns, which is taken as the pulse width of the first clock signal.

[0077] The reference signal pulse width of the first pulse width = 1.95ns is denoted as the first reference signal pulse width, and the first pulse width / second pulse width = 1.95ns / 0.98ns ≈ 1.99, which is rounded to 2, and the first reference signal pulse width = 2x0.98 = 1.96ns.

[0078] The reference signal pulse width of the second pulse width = 0.98ns is denoted as the second reference signal pulse width, and the second pulse width / second pulse width = 0.98ns / 0.98ns = 1, and the second reference signal pulse width = 0.98ns.

[0079] The reference signal pulse width with a third pulse width of 2.95ns is denoted as the third reference signal pulse width. Then, the third pulse width / the second pulse width = 2.95ns / 0.98ns ≈ 3.01. 3.01 is rounded to 3. Therefore, the third reference signal pulse width = 3 × 0.98 = 2.94ns.

[0080] The fourth pulse width is 1.95ns. The reference signal pulse width is denoted as the fourth reference signal pulse width. Then, the fourth pulse width / the second pulse width = 1.95ns / 0.98ns ≈ 1.99. 1.99 is rounded to 2. The fourth reference signal pulse width = 2 × 0.98 = 1.96ns.

[0081] S130. Based on the pulse width of each input signal and the corresponding pulse width of the reference signal, determine the clock deviation corresponding to each input signal pulse width to obtain the clock deviation sequence.

[0082] In some possible implementations, clock skew is the difference between each input signal pulse width and its corresponding reference signal pulse width, i.e., clock skew = input signal pulse width - reference signal pulse width. This sequence of differences is called the "clock skew sequence," and it quantifies how much each pulse width deviates from its ideal integer multiple of its period; ideally, without jitter, all deviations should be zero. Figure 3 As shown, Figure 3 The diagram illustrates a sliding window operation according to an embodiment of this application, where the horizontal axis represents time and the vertical axis represents clock deviation.

[0083] In some implementations, the example corresponding to step S120 will continue to be used.

[0084] The clock deviation with a first pulse width of 1.95ns is denoted as the first clock deviation. Then, the first clock deviation = first pulse width - first reference signal pulse width = 1.95ns - 1.96ns = -0.01ns.

[0085] The clock deviation of the second pulse width = 0.98ns is denoted as the second clock deviation. Then: Second clock deviation = Second pulse width - Second reference signal pulse width = 0.98ns - 0.98ns = 0.00ns.

[0086] The clock deviation with a third pulse width of 2.95ns is denoted as the third clock deviation. Then, the third clock deviation = third pulse width - third reference signal pulse width = 2.95 - 2.94 = 0.01ns.

[0087] The clock deviation of the fourth pulse width = 1.95ns is denoted as the fourth clock deviation. Then: Fourth clock deviation = fourth pulse width - fourth reference signal pulse width = 1.95ns - 1.96ns = -0.01ns.

[0088] S140, performing a sliding window operation on the clock deviation sequence based on the window width to obtain an updated clock deviation sequence.

[0089] In some possible embodiments, the window width is a preset time distance, and one window width can be X times of the pulse width of the first clock signal, X can be a positive integer greater than or equal to 3 and less than or equal to 10. For example, as shown in FIG. 2, one window width can be 3 times of the pulse width of the first clock signal, that is, one window width can cover 3 consecutive clock deviation values. Figure 3

[0090] Setting the lower limit of the window width to be no less than 3 pulse widths of the first clock signal (X≥3) ensures that the window has basic signal observation capability. A window with a width of at least 3 pulse widths of the first clock signal can effectively accommodate at least one complete signal transition period and the necessary context information, so that it can reliably distinguish between random small jitter and systematic and sudden deviation caused by integer period misjudgment. Avoiding misjudgment (e.g., mistaking normal jitter as mutation) or missing judgment of consecutive errors due to insufficient field of view when the window is too narrow, ensures the stability and accuracy of the initial detection. In addition, setting the upper limit to be no more than 10 pulse widths of the first clock signal (X≤10) effectively controls the computational complexity and prevents over-smoothing. This upper limit ensures that the sliding window operation is always performed within a limited and manageable range, avoiding the problem of rapid increase in computational resources and decrease in real-time performance caused by unlimited increase in the window. More importantly, a too wide window (e.g., much wider than 10 pulse widths of the first clock signal) will over-smooth the details of the clock deviation sequence, which may mask those discrete and local integer period misjudgment points, thereby weakening the pertinence and accuracy of the correction algorithm. Setting the upper limit within 10 pulse widths of the first clock signal allows the algorithm to moderately expand the field of view to handle more complex error patterns while maintaining sufficient attention to local mutations, achieving the best balance between correction ability and computational efficiency.

[0091] The sliding window operation includes multiple sliding window processes, and the step length between the windows corresponding to each sliding window process is a sliding window step length, which can be smaller than the window width to avoid missing detection. The sliding window operation slides along the deviation sequence with the sliding window step length.

[0092] In some scenarios, when the signal has severe jitter, the rounding in step S120 can cause integer multiple misjudgment, for example, mistaking 2 pulse widths of the first clock signal as 3 pulse widths of the first clock signal. This will generate a mutation point close to one pulse width of the first clock signal in the deviation sequence.

[0093] ​In view of this, in some embodiments, each sliding window process includes: if the change in clock offset within the window is greater than a threshold, correcting the pulse width of the input signal corresponding to the clock offset within the window and updating the clock offset sequence within the window. If the change in clock offset within the window is less than the threshold, no correction is made, and the sliding window operation continues.

[0094] The change in clock skew within the window can be the difference between the maximum and minimum clock skew values ​​within the window, i.e., the change in clock skew = maximum clock skew - minimum clock skew. The change threshold can be the pulse width of the first clock signal. This step detects and corrects such errors by scanning the skew sequence through a sliding window.

[0095] By directly linking the change threshold to a characteristic of the signal itself—the pulse width of the first clock signal—it means that the standard for judging whether a "sudden change" exists within a window is based on the ideal period length of the signal itself. When the difference between the maximum and minimum values ​​of the clock deviation within the window exceeds the pulse width of a first clock signal, it physically indicates that at least one cumulative misjudgment of an integer number of clock cycles has occurred within that window (e.g., a pulse width is under- or over-counted by a complete first clock signal pulse width). This threshold based on the intrinsic scale of the signal is more reasonable and universal than arbitrarily setting a fixed threshold value (such as a voltage or time value). It can adapt to signals of different rates, effectively avoiding missed detections (threshold too high) or false detections (threshold too low) caused by improper threshold settings, and ensuring that only significant deviations truly caused by integer period errors will trigger the correction mechanism.

[0096] In other scenarios, when correcting the pulse width of the input signal corresponding to the clock deviation within the correction window, the position with the steepest change in adjacent deviations within the abrupt change window is found. The pulse width corresponding to this position is most likely to be misjudged as an integer, and can be corrected according to the direction of the deviation jump.

[0097] Specifically, in some implementations, such as Figure 4 As shown, Figure 4 This paper illustrates a flowchart of a communication method provided in an embodiment of this application. The correction of the input signal pulse width corresponding to the clock deviation specifically includes steps a1-a2:

[0098] Step a1: When the change value of the clock deviation within the window is greater than the change threshold and the clock deviation jumps downward, the pulse width of the corrected input signal is greater than the pulse width of the input signal before correction by the pulse width corresponding to the first clock signal.

[0099] Step a2, in the case that the change value of the clock bias within the window is greater than the change threshold value, and the clock bias jumps upward, the modified input signal pulse width is less than the pulse width corresponding to one first clock signal of the unmodified input signal pulse width.

[0100] In some examples, when performing the sliding window processing, the bias sequence is traversed, and the change value of the clock bias within the window is calculated each time iteration = max of the clock bias - min of the clock bias. If the change value of the clock bias is greater than the change threshold value, the index i with the maximum absolute value | clock bias [i+1] - clock bias [i] | within the window is found, then the integer multiple of the i-th pulse width is modified by ±1, and all subsequent related calculations are updated.

[0101] In a specific embodiment, the pulse width of the first clock signal is = 1.0 ns, the change threshold value is the pulse width of the first clock signal = 1.0 ns, and the window width is 3 pulse widths of the first clock signal.

[0102] The measured pulse width of a certain input signal is = 3.07 ns, and the calculated measured pulse width / pulse width of the first clock signal = 3.27 / 1.0 ≈ 3.27. The reference signal pulse width is = 3.0 ns, and the clock bias is = 3.27 - 3.0 = +0.27 ns. If the subsequent clock bias sequence is mutated as follows: [..., +0.27, -0.82, -0.72...]. For the window [+0.27, -0.82, -0.72], the change value within the window is = 0.27 - (-0.82) = 1.09 ns, which is greater than the change threshold value = the pulse width of the first clock signal = 1.0 ns.

[0103] And it is determined that +0.27 -> -0.82 is a downward jump, so the integer multiple value corresponding to the pulse width of a certain input signal is modified from 3 to 4. The modified reference pulse width is = 4.0 ns, and the new bias is = 3.27 - 4.0 = -0.73 ns. At this time, the bias sequence becomes [..., -0.73, -0.82, -0.72...], which is more continuous with the surrounding bias.

[0104] In the embodiments of the present application, when the deviation change is detected to exceed the threshold by the sliding window, the jump direction of the deviation is further analyzed to perform targeted correction: when the clock deviation jumps downward, it indicates that the current pulse width is "short" compared to the nearest ideal integer multiple reference pulse width, which usually means that the pulse width may have "missed" one complete clock period (the pulse width corresponding to the first clock signal) in practice, and the modified pulse width is increased by one pulse width corresponding to the first clock signal at this time, which is beneficial to make up for the missing period count and make the pulse width estimate return to the correct integer multiple reference. When the clock deviation jumps upward, it indicates that the current pulse width is "long", and it is likely to have "overestimated" one pulse width corresponding to the first clock signal, and the modified pulse width is reduced by one pulse width corresponding to the first clock signal at this time, which is beneficial to eliminate the redundant period count and correct the overestimation error.

[0105] S150, in the case that all clock deviations in the updated clock deviation sequence are less than the deviation threshold, obtaining the signal rate of the input signal based on the modified input signal pulse width sequence.

[0106] In some possible implementations, when the sliding window correction is completed and all values in the entire deviation sequence are less than the deviation threshold, it is considered that the pulse width sequence has been sufficiently modified. At this time, the final signal rate is calculated based on the modified and more accurate pulse width sequence.

[0107] The deviation threshold can be determined according to the pulse width of the first clock signal, such as the deviation threshold can be equal to the product of a preset coefficient and the pulse width of the first clock signal, for example, the deviation threshold = 0.1 x the pulse width of the first clock signal.

[0108] In some implementations, the signal rate corresponding to the minimum input signal pulse width in the modified input signal pulse width sequence can be taken as the signal rate of the input signal.

[0109] In other implementations, the signal rate of the input signal can be obtained based on the modified input signal pulse width sequence by using the least square method. Using the least square method to calculate the signal rate based on the modified pulse width sequence combines the advantages of front-end sliding window correction to eliminate integer errors with the theory of back-end mathematical optimization, thereby improving the accuracy of signal rate measurement. As shown in Figure 5 Figure 5 Fig. 1 shows a flow diagram of a communication method provided by an embodiment of the present application, which obtains the signal rate of the input signal based on the modified input signal pulse width sequence by using the least square method and specifically includes steps S151-S153:

[0110] S151, obtaining the second clock signal based on the modified input signal pulse width sequence.

[0111] ​In some examples, the second clock signal corresponds to a pulse width that is the smallest pulse width in the sequence of modified input signal pulse widths.

[0112] After the sliding window processing in step S140, the sequence of input signal pulse widths has been as much as possible freed from false positives of integer clock periods. At this point, the minimum value is sought again from this higher quality "sequence of modified input signal pulse widths". This new minimum value (the pulse width of the second clock signal) is closer to the true pulse width of the clock signal than the pulse width of the first clock signal, because it is based on more reliable data. This "pulse width of the second clock signal" is used as a more accurate reference for the subsequent fine calculation.

[0113] S152, based on the second clock signal, obtaining a number of clock periods contained in each modified input signal pulse width.

[0114] In some examples, the number of clock periods is a ratio of the corresponding modified input signal pulse width to the pulse width of the second clock signal.

[0115] Using the more accurate reference pulse width of the second clock signal obtained in the previous step, it is re-evaluated how many of such reference periods are contained in each modified pulse width. Since the pulse widths have been modified, the result of the division here (the number of clock periods) will be very close to an integer, but it is allowed to be a fraction (e.g. 3.01, 1.98), which preserves more fine-grained period information than rounding to the nearest integer in step S120, providing high-precision input for the subsequent least squares fitting.

[0116] S153, based on the number of clock periods corresponding to each modified input signal pulse width, obtaining a signal rate of the input signal using least squares method.

[0117] In some examples, the least squares method is used to adjust the signal rate and the phase to minimize a sum of squares of deviations of clock edges obtained from a sum of products of an inverse of the signal rate and the number of clock periods corresponding to each modified input signal pulse width and a sum of target phases corresponding to each modified input signal pulse width from edges of the corresponding output signal.

[0118] In an example, the least squares method aims to find an optimal clock period T (inverse of the signal rate) and a target phase φ such that the total error between all ideal clock edges generated from them and the actual signal modified edges is minimized.

[0119] Objective function of the least squares method: minimize Σ(((N_i x T + φ) - t_i)^2).

[0120] Where T represents the clock period, or the inverse of the signal rate. t_i represents the time stamp of the i-th actual signal edge in the input signal. N_i represents the number of clock periods corresponding to the i-th modified input signal pulse width. φ represents the target phase, which can be 0.

[0121] The goal of the least square method is to adjust T and φ so that the sum of the fitting errors ((N_i*T+φ)-t_i)^2 of all edges is minimized. The T and φ thus solved are the optimal estimates of the true clock parameters in a statistical sense.

[0122] In the embodiment shown in steps S151-S153, the modified data is not directly used for the final calculation, but an updated clock reference, the second clock signal (whose pulse width is the minimum in the modified sequence), is first extracted therefrom. The pulse width corresponding to the second clock signal is generated based on the modified data of higher quality and closer to the ideal, and is a more accurate reference than the initial "first clock signal pulse width". Based on this, the number of accurate clock periods (which can be a non-integer multiple) contained in each modified pulse width is calculated using this more optimal reference. This is equivalent to performing a data preprocessing and parameter pre-calibration before entering the final least square optimization, providing a significantly improved initial starting point for the subsequent mathematical optimization, thereby achieving higher final accuracy overall. In addition, in this embodiment, the least square method is used to minimize the overall deviation (sum of squared errors) between the ideal clock edges generated according to the estimated clock parameters (inverse of the signal rate, corresponding to the minimum signal pulse width, i.e. clock signal pulse width, and phase) and the actual data edges of the original input signal. Since the final recovered ideal clock edge positions are directly determined by the two parameters of signal rate and phase, joint adjustment and optimization of these two parameters through the least square method can systematically eliminate residual random errors and small systematic deviations. This makes the finally solved signal rate and phase values optimal estimates in a statistical sense, closer to the true values, thereby ensuring that the clock recovery result has theoretically high accuracy.

[0123] In the embodiment shown in steps S110-S150, by introducing a sliding window-based correction mechanism, on the one hand, the problem of inaccurate signal rate measurement caused by signal jitter is effectively improved, and on the other hand, the efficiency of signal rate measurement is improved on the basis of ensuring the accuracy of signal rate measurement, thereby realizing high-precision and high-efficiency signal rate recovery. Specifically, by using the minimum one of the plurality of input signal pulse widths to establish an initial reference clock signal (i.e., a first clock signal), and calculating the deviation between each input signal pulse width and the integer multiple (i.e., a reference signal pulse width) of the pulse width of the closest first clock signal, a clock deviation sequence is formed. In theory, in the ideal non-jitter case, the values of each input signal pulse width are accurate, at this time, the signal rate is the inverse of the pulse width of the first clock signal, and each input signal pulse width should be an integer multiple of the pulse width of the first clock signal, that is, all deviations should be 0. However, the present application notes that due to signal jitter, the values of the input signal pulse widths are not completely accurate, so the inverse of the pulse width of the first clock signal as the signal rate is also likely to be inaccurate. The present application utilizes the property that the input signal pulse widths should be integer multiples of the pulse width of the first clock signal in theory, and the clock deviation sequence formed can reflect the clock deviation distribution of the input signal pulse widths. Then, in the correction phase, a sliding window mechanism is used to traverse the clock deviation sequence, and when the deviation change value (the difference between the maximum clock deviation in the window and the minimum clock deviation in the window) in the window exceeds the preset threshold, the pulse width corresponding to the steepest change (i.e., the point where signal jitter is most likely to occur) in the window is corrected, avoiding the defect that the inaccurate value of the individual input signal pulse width (caused by misjudgment due to severe jitter) causes the rate calculation to be inaccurate.

[0124] In addition, compared with the global optimization algorithm which needs to perform complex fitting or adjustment on each data point, the sliding window strategy of the embodiment significantly reduces the computational complexity. It does not need to process all the subtle jitter, but focuses on the significant abnormal mutation points caused by the cumulative effect and exceeding the threshold, achieving a good balance between accurate correction and computational efficiency. The pulse width sequence after sliding window correction can more truly reflect the ideal periodic characteristics of the signal, thereby improving the accuracy of calculating the signal rate.

[0125] In other possible embodiments, as shown in Figure 6 , the present application provides a communication method, and the method comprises steps S110-S150: Figure 6 The method for correcting the input signal pulse width corresponding to the clock deviation comprises steps S160-S170:

[0126] S160, in the case that all clock deviations in the updated clock deviation sequence have a clock deviation greater than or equal to the deviation threshold, the window width is increased.

[0127] In some embodiments, the width of the sliding window can be increased from X times the pulse width of the first clock signal to (X+1) times the pulse width of the first clock signal, and continue to slide the subsequent clock skew, X being a positive integer.

[0128] Taking the pulse width of the first clock signal (i.e. the minimum pulse width) as the adjustment reference unit ensures that the expansion of the window is strictly aligned with the clock period characteristics of the signal itself. Avoiding the uncertainty that may be caused by adjusting using an arbitrary or unitless step size, each window increase corresponds to accurately covering one more potential clock period position on the time axis, thereby more conducive to systematically and structurally capturing and correcting the deviation pattern caused by integer period misjudgment, enhancing the reliability of the entire adjustment process and the consistency of the results. In addition, the present embodiment gradually increases the window width in small steps and discretely (e.g. from 3 times the pulse width of the first clock signal to 4 times the pulse width of the first clock signal), and the algorithm can maintain high sensitivity to local sharp mutations in the initial small window while gradually and gently expanding the detection field of view. If the smaller window fails to completely solve all deviations, a slightly larger window (e.g. 4 times the pulse width of the first clock signal) can better observe the deviation accumulation trend across the period or identify complex error patterns that are "split" under a smaller window. This gradual adjustment method, compared to jumping to an excessively large window at once, can avoid smoothing out or masking local details that should be corrected due to the excessively wide window, and can also avoid oscillation or over-adjustment due to improper step size, making the entire adaptive process smoother and more controllable, and optimizing the correction effect.

[0129] S170, performing a sliding window operation on the clock skew sequence based on the increased window width to obtain an updated clock skew sequence.

[0130] The specific implementation of step S170 is similar to that of step S140, and can be referred to the specific implementation of step S140, which will not be repeated here.

[0131] In this embodiment, by introducing a dynamic adjustment mechanism for the window width, the adaptive capability and reliability of the final correction result of the sliding window correction algorithm are further enhanced. Specifically, this embodiment enables the communication method to have the ability of adaptive iterative optimization. An initial fixed window width may not be able to effectively capture all integer period misjudgments caused by severe jitter or complex noise patterns. By setting a closed-loop feedback rule of "if there is still a clock deviation exceeding the deviation threshold after the scan is completed, increase the window width and re-execute the sliding window operation", the algorithm can intelligently judge the current correction effect. If it has not fully converged (i.e., there is still a large deviation), it automatically widens the detection field of view (increases the window), thereby potentially discovering and correcting global and cumulative errors that are masked or not accurately located under a smaller window. This self-adjustment mechanism ensures that the correction process can move towards completely eliminating significant deviations. In addition, this embodiment can also achieve an optimized balance between correction accuracy and computational efficiency. The algorithm does not use a large window for global calculation from the beginning (that would bring unnecessary computation and may reduce the sensitivity to local mutations), but adopts a gradual strategy of "from fine to broad". Local mutation points are processed efficiently with a smaller window first. If discrepancies still exist after processing, the window width is increased for a more comprehensive analysis. This strategy can correct these discrepancies with minimal computational cost in most cases, increasing complexity only when necessary, thus achieving higher overall processing efficiency.

[0132] Example 2:

[0133] Clock recovery methods for high-speed serial interfaces such as SERDES, PCIe, and USB can also be implemented based on a phase-locked loop (PLL) structure. A PLL is a phase error control system that adjusts the output signal (clock signal) by comparing the phase between the input and output signals to achieve synchronization between the output and input signals.

[0134] like Figure 7 As shown, Figure 7 A schematic diagram of a clock recovery circuit provided in an embodiment of this application is shown.

[0135] Figure 7 A clock recovery circuit based on a phase-locked loop (PLL) is shown. The clock recovery circuit 1 includes a PLL structure 10, which comprises a phase detector (PD) 101, a loop filter (LF) 102, and a voltage-controlled oscillator (VCO) 103. This device tracks the embedded clock in the input data by adjusting the phase of the oscillating clock through the loop, thereby recovering the clock signal from the data signal.

[0136] The phase detector 101 can include, but is not limited to, a Hogge phase detector, an Alexander phase detector, and a half-rate phase detector. The phase detector 101 is used to compare the phase of the input signal with the phase of the output signal (clock signal) of the voltage-controlled oscillator 103, and detect the phase difference therebetween. The phase difference is converted into a voltage signal, and the magnitude and polarity of the voltage signal reflect the magnitude and direction of the phase difference. For example, if the input signal phase leads the voltage-controlled oscillator 103 output signal phase, the phase detector 101 outputs a positive voltage. Conversely, a negative voltage is output.

[0137] In a specific embodiment, taking a simple half-rate phase detector as an example, as shown in FIG. 1, Figure 8 a structure diagram of a half-rate phase detector is shown, and the half-rate phase detector 100 includes a first D flip-flop 1001, a second D flip-flop 1002, and an XOR gate 1003. Figure 8 The output signal Q1 represents the output signal of the first D flip-flop 1001, and the output signal Q2 represents the output signal of the second D flip-flop 1002. Figure 8

[0138] The relationship among the input signal, the clock signal, and the output signal of the D flip-flop (including the first D flip-flop 1001 and the second D flip-flop 1002, taking the rising edge trigger as an example) is shown in Table 1:

[0139] Table 1

[0140]

[0141] The half-rate phase detector 100 outputs, according to the input signal and the clock signal, as shown in FIG. 2, Figure 9 a structure diagram of a half-rate phase detector is shown, and the half-rate phase detector 100 includes a first D flip-flop 1001, a second D flip-flop 1002, and an XOR gate 1003. Figure 9 An output waveform diagram of a half-rate phase detector provided by an embodiment of the present application is shown, wherein the input signal is modulated by two levels of high / low as an example. Figure 9 The output signal Q1 represents the output signal of the first D flip-flop 1001, the output signal Q2 represents the output signal of the second D flip-flop 1002, and the phase detection result represents the control signal of the output of the XOR gate 1003, which can be expressed as a voltage signal.

[0142] The loop filter 102 performs filtering processing on the signal output by the phase detector, for removing high-frequency noise and interference, and making the signal smoother. The filtered signal will be used to control the voltage-controlled oscillator 103. The loop filter 102 usually adopts the form of a low-pass filter, which can allow low-frequency signals to pass through while suppressing high-frequency noise, thereby improving the stability and accuracy of clock recovery.

[0143] ​The voltage-controlled oscillator 103 adjusts its oscillation frequency according to the control voltage output by the loop filter 102. When the control voltage changes, the output frequency of the voltage-controlled oscillator 103 also changes accordingly. During clock recovery, the output signal of the voltage-controlled oscillator 103 serves as the recovered clock signal (recovered clock signal) for sampling the input high-speed serial data. By continuously adjusting the frequency of the voltage-controlled oscillator 103, the phase of its output recovered clock signal gradually synchronizes with the phase of the input signal, thereby achieving clock recovery and outputting the clock signal.

[0144] exist Figure 7 In the phase-locked loop-based clock recovery scheme shown, the phase detector 101, as the main module, is responsible for comparing the phase of the input signal with the feedback clock. Its performance directly affects the accuracy and efficiency of clock recovery. However, the phase detector consists of multiple adders and comparators, which consumes a lot of hardware resources and has high computational complexity, leading to increased signal processing delay.

[0145] by Figure 8 Taking the half-speed phase detector shown as an example, its internal logic units, such as D flip-flops and XOR circuits, need to be constructed sequentially. A point-by-point traversal method is used to sample and compare the phase of the input signal and the feedback clock, and then output the phase detection result. For scenarios with more complex flip-flop combinations and more varied signal characteristics (such as signals containing complex modulation patterns, mixed clocks, or large clock jitter), the computational burden of the phase detector will increase dramatically, and its processing efficiency will decrease significantly.

[0146] Furthermore, the 10-loop throughput of the phase-locked loop (PLL) structure is limited by the computational efficiency of the phase detector, becoming a key bottleneck restricting the overall data bandwidth. In high-speed communication or real-time processing systems, low-bandwidth loop throughput will lead to the accumulation of signal phase errors, increased clock recovery delay, and even the inability to track changes in signal frequency and phase in a timely manner. This severely affects the overall efficiency and reliability of clock signal recovery, reducing the transmission performance and stability of the communication system.

[0147] In order to solve such Figure 7 Due to the high computational complexity of the phase detector 101 in the clock recovery scheme shown, this application provides a clock recovery device, such as... Figure 10 As shown, Figure 10 A schematic diagram of a clock recovery device provided in an embodiment of this application is shown.

[0148] like Figure 10 As shown, the clock recovery device 4 includes a phase detection unit 41, a judgment unit 42, a loop filtering unit 43, and a voltage-controlled oscillator unit 44. It achieves dynamic recovery and phase synchronization of the clock signal through a closed-loop feedback mechanism. The specific working process is as follows:

[0149] The phase discrimination unit 41 receives the input signal and the feedback recovery clock signal (the feedback recovery clock signal as the reference clock signal) of the voltage-controlled oscillation unit 44 at the same time, and directly determines the phase discrimination result through a pre-constructed mapping relationship table (or state transition table). The mapping relationship table is used to represent the mapping relationship between the phase discrimination result and the level of the input signal corresponding to the jump edge of the feedback recovery clock signal of the voltage-controlled oscillation unit 44. Compared with the phase discriminator based on the adder and the comparator (such as the phase discriminator 101 shown in Figure 7 or the half-speed phase discriminator 100 shown in Figure 8 , the embodiment directly obtains the phase difference information by searching the mapping relationship table, avoids the complex point-by-point operation process, significantly reduces the calculation complexity, and improves the phase discrimination speed.

[0150] The phase discrimination result is input to the judgment unit 42 as the control signal. The judgment unit 42 is used to judge whether the phase discrimination result converges. If the phase discrimination result does not converge, the phase discrimination result is input to the loop filter unit 43. The loop filter unit 43 performs low-pass filtering on the phase discrimination result and outputs a smooth voltage signal. The voltage signal is input to the voltage-controlled oscillation unit 44 again, and the oscillation frequency and phase are dynamically adjusted. If the phase discrimination result converges, a control instruction is output to the voltage-controlled oscillation unit 44. The control instruction is used to instruct the voltage-controlled oscillation unit 44 to output the clock signal currently fed back to the phase discrimination unit 41 as the clock signal recovered from the input signal.

[0151] The clock signal output by the voltage-controlled oscillation unit 44 is fed back to the phase discrimination unit 41 to form a closed-loop feedback system. Through multiple iterations, the phase difference between the clock signal and the input signal is continuously reduced until the preset convergence condition (such as the phase difference being less than a threshold value or the continuous multiple iteration results being stable) is met, and finally a stable and accurate clock signal is output.

[0152] In a specific embodiment, taking the half-speed phase discriminator 100 shown in Figure 8 as an example, the expression of the phase discrimination result Vout can be derived by constructing a model of the D flip-flop and the XOR gate. For example, the state transition table of the D flip-flop (including the first D flip-flop 1001 and the second D flip-flop 1002) can be equivalent to formula (1):

[0153] Formula (1).

[0154] Wherein, represents the state of the output end of the D flip-flop after the rising edge of the clock signal CLK triggers, represents the data value of the input end of the D flip-flop at the previous sampling point of the rising edge of the clock signal CLK.

[0155] The XOR gate 1003 transition table can be equivalent to:

[0156] .

[0157] wherein m represents the output of the XOR gate, p and q represent the output signal of the first D flip-flop 1001 and the output signal of the second D flip-flop 1002 respectively, represents the negation of q, represents the negation of .

[0158] In summary, the half-speed phase detector 100 can be equivalent to formula (2):

[0159] Formula (2).

[0160] wherein, represents the state of the D flip-flop output end after the clock signal CLK falling edge trigger, represents the data value of the D flip-flop input end at the previous sampling point of the clock signal CLK falling edge, represents the negation of , represents the negation of , represents the negation of , represents the negation of , represents the negation of , represents the negation of , represents the negation of .

[0161] For the data model of the half-speed phase detector 100, according to the input signal and the clock signal, outputs such as Figure 11 are output at different positions, Figure 11 Fig. 6 shows an output waveform diagram of a half-speed phase detector model provided by the embodiment of the present application.

[0162] As shown in Figure 11 , all initial states are set to 0 by default, the input signal corresponding to the first clock rising edge (R1) is low, and the input signal corresponding to the first falling edge F1 is high. Therefore, the phase detection result Vout in the period of R1~F1 can be calculated by the above formula (1) and formula (2):

[0163] .

[0164] .

[0165] .

[0166] Similarly, the phase detection result Vout in the period of F1~R2 can be calculated by the above formula (1) and formula (2):

[0167] .

[0168] .

[0169] .

[0170] Similarly, all the above states can be correspondingly output, such as F1~R2, R2~F2, F2~R3, R3~F3, F3~R4, R4~F4, F4~R5 and R5~F5, and a mapping relationship table is obtained, as shown in Table 2:

[0171] Table 2

[0172]

[0173] In Table 2, represents the level of the corresponding input signal when the clock signal is at the rising edge, represents the level of the corresponding input signal when the clock signal is at the falling edge.

[0174] Specifically, according to Table 2, in the case that the level of the corresponding input signal at one transition edge of the recovered clock signal is high, and the level of the corresponding input signal at the previous transition edge of the recovered clock signal is high, the control signal (the phase discrimination result can be used as the control signal) is low.

[0175] In the case that the level of the corresponding input signal at one transition edge of the recovered clock signal is high, and the level of the corresponding input signal at the previous transition edge of the recovered clock signal is low, the control signal is high.

[0176] In the case that the level of the corresponding input signal at one transition edge of the recovered clock signal is low, and the level of the corresponding input signal at the previous transition edge of the recovered clock signal is high, the control signal is high.

[0177] In the case that the level of the corresponding input signal at one transition edge of the recovered clock signal is low, and the level of the corresponding input signal at the previous transition edge of the recovered clock signal is low, the control signal is low.

[0178] After the above processing, the phase discrimination operation (flip-flop calculation, XOR calculation) does not need to be performed point by point, only the recording of the rising and falling edges ,and the output of the corresponding phase discrimination result Vout, and the subsequent non-edge positions all keep the previous output value Voutpre.

[0179] In the embodiment, by only investigating the input signal level (high or low) at the moment of the recovery clock jump edge and the previous moment, it can be determined whether the current phase relationship is "leading" or "lagging", and the corresponding binary control signal (high or low level) is output to instruct the voltage-controlled oscillator to "speed up" or "slow down". For example, when the recovery clock edge captures the input signal from "high" to "low" (corresponding to the third case in the embodiment), it indicates that the recovery clock may be ahead of the valid data window of the input signal, at this time, outputting a "high" level control signal makes the voltage-controlled oscillator slow down appropriately to align the phase, avoiding complex analog voltage comparison or digital calculation, the decision speed is fast, the hardware implementation area is small, and the power consumption is low, which is suitable for application in the clock data recovery circuit of high-speed serial interface.

[0180] In addition, the embodiment further establishes the mapping relationship among the input signal, the recovery clock signal and the control signal, directly obtains the control signal representing the phase difference based on the level state of the signal jump edge, and recovers the clock signal of the input signal based on the control signal. Compared with the hardware phase detection circuit scheme, the embodiment eliminates the complex adder and comparator operation circuit, simplifies the phase detection process to a signal state query operation, significantly reduces the calculation complexity, significantly improves the phase detection processing speed, and realizes efficient and low complexity clock recovery.

[0181] Embodiment three:

[0182] As shown in Figure 12 , Figure 12 A structure schematic diagram of a communication system provided by an embodiment of the present application is shown. The communication system 3 includes a signal generation device 31 and a clock recovery device 4 as shown in Figure 10 To realize faster and more accurate locking of the clock information of the input signal and effective clock recovery, the signal generation device 31 can input a generated signal rate to the voltage-controlled oscillation unit 44 as the initial oscillation frequency of the voltage-controlled oscillation unit 44. Because different signal rates correspond to different data transmission rhythms, the initial frequency of the voltage-controlled oscillation unit 44 needs to be matched with the signal rate, so as to faster and more accurately lock the clock information of the input signal and realize effective clock recovery. For example, for a high-rate signal, the initial frequency of the voltage-controlled oscillation unit 44 needs to be set relatively high to adapt to the fast data transmission.

[0183] In some embodiments, as shown in Figure 12 , the signal rate obtained in the embodiment one can be used as the initial oscillation frequency. The operation mode of the clock recovery device 4 for clock recovery based on the signal rate is shown in Figure 13 , Figure 13 A flowchart of a communication method provided by an embodiment of the present application is shown, which specifically includes steps S210-S220:

[0184] S210, inputting a signal rate to the voltage-controlled oscillation unit to obtain a recovered clock signal output by the voltage-controlled oscillation unit.

[0185] In some examples, the voltage-controlled oscillation unit 44 generates a recovered clock signal based on the signal rate and feeds back the clock signal to the phase discriminator 41, which is used for clock recovery.

[0186] S220, outputting a control signal by the phase discriminator based on the recovered clock signal and a mapping relationship table.

[0187] In some examples, the mapping relationship table is used to represent a mapping relationship between the control signal and a level of the input signal corresponding to a jump edge of the recovered clock signal, as shown in Table 2.

[0188] The control signal is used to control the voltage-controlled oscillation unit 44 to adjust the oscillation frequency and phase, so that the recovered clock signal is consistent with the input signal edge.

[0189] In the embodiments of the present application, the accurate signal rate calculated is input to the voltage-controlled oscillation unit, which can directly generate a recovered clock signal with a highly matched frequency. More importantly, by introducing a feedback control loop based on the mapping relationship table (according to the input signal level corresponding to the jump edge time of the recovered clock, the control signal is output by table lookup to fine-tune the frequency and phase of the voltage-controlled oscillation unit), the control strategy of the phase discriminator based on the mapping relationship table provides an efficient and robust phase synchronization mechanism. Compared with the way of calculating the control signal by setting adder, comparator and other hardware circuits, the present application does not need to set complex hardware circuits, but can quickly obtain the result by table lookup, greatly reducing the calculation complexity and significantly improving the phase discrimination speed.

[0190] The "mapping relationship table" explicitly defines the corresponding relationship between the input signal level (such as high, low, rising edge, falling edge) observed at the edge of the recovered clock and the control instruction (such as acceleration, deceleration, and maintenance) applied to the voltage-controlled oscillation unit. Compared with complex real-time calculation, this table lookup method has fast response speed, definite logic, and simple implementation, and is particularly suitable for implementation in high-speed hardware circuits. It enables the system to quickly respond to the phase error between the input signal and the recovered clock, and drives the voltage-controlled oscillation unit to make accurate compensation, ultimately achieving and maintaining phase locking, and ensuring the long-term stability of the recovered clock.

[0191] Embodiment Four

[0192] Based on the above embodiments, the present embodiment provides a communication device, which comprises Figure 14As shown, the communication device 6 can be a signal generation device 31, which comprises a minimum pulse width calculation module 61, a reference pulse width calculation module 62, a clock deviation calculation module 63, a pulse width correction module 64 and a judgment module 65.

[0193] The minimum pulse width calculation module 61 is configured to obtain a pulse width of a first clock signal based on a pulse width sequence of an input signal, the pulse width sequence of the input signal comprising a plurality of input signal pulse widths arranged in time sequence, and the pulse width of the first clock signal being the minimum one of the input signal pulse widths in the pulse width sequence of the input signal.

[0194] The reference pulse width calculation module 62 is configured to determine a reference signal pulse width corresponding to each input signal pulse width based on each input signal pulse width and the pulse width of the first clock signal, the reference signal pulse width being the pulse width corresponding to the minimum difference between the input signal pulse width and the plurality of integer multiples of the pulse width of the first clock signal.

[0195] The clock deviation calculation module 63 is configured to determine a clock deviation corresponding to each input signal pulse width based on each input signal pulse width and the corresponding reference signal pulse width, to obtain a clock deviation sequence, and the clock deviation being the difference between each input signal pulse width and the corresponding reference signal pulse width.

[0196] The pulse width correction module 64 is configured to perform a sliding window operation on the clock deviation sequence based on a window width to obtain an updated clock deviation sequence, the sliding window operation comprising a plurality of sliding window processes, a step length between the windows corresponding to each sliding window process being a sliding window step length, and each sliding window process comprising: in a case where a change value of the clock deviation in the window is greater than a change threshold, correcting the input signal pulse width corresponding to the clock deviation in the window and updating the clock deviation sequence in the window. Wherein the window width is a preset time distance, and the change value is the difference between the maximum value of the clock deviation in the window and the minimum value of the clock deviation in the window.

[0197] The judgment module 65 is configured to obtain a signal rate of the input signal based on the corrected input signal pulse width sequence in a case where all the clock deviations in the updated clock deviation sequence are less than a deviation threshold.

[0198] In some embodiments, the pulse width correction module 64 is further configured to, in a case where the change value of the clock deviation in the window is greater than the change threshold and the clock deviation jumps downward, the corrected input signal pulse width being one pulse width corresponding to the first clock signal more than the uncorrected input signal pulse width. And in a case where the change value of the clock deviation in the window is greater than the change threshold and the clock deviation jumps upward, the corrected input signal pulse width being one pulse width corresponding to the first clock signal less than the uncorrected input signal pulse width.

[0199] In some embodiments, the communication device 6 further comprises a window adjusting module and an obtaining module.

[0200] The window adjusting module is configured to increase the window width when all clock skews in the updated clock skew sequence have a clock skew greater than or equal to the skew threshold.

[0201] The obtaining module is configured to perform a sliding window operation on the clock skew sequence based on the increased window width to obtain the updated clock skew sequence.

[0202] In some embodiments, the window adjusting module is further configured to increase the width of the sliding window from X times of the pulse width of the first clock signal to (X+1) times of the pulse width of the first clock signal, and continue to slide and scan the subsequent clock skews, where X is a positive integer.

[0203] In some embodiments, X in the window adjusting module is greater than or equal to 3 and less than or equal to 10.

[0204] In some embodiments, the judging module 65 is further configured to obtain the signal rate of the input signal based on the corrected input signal pulse width sequence by using the least square method.

[0205] In some embodiments, the judging module 65 is further configured to obtain a second clock signal based on the corrected input signal pulse width sequence, the second clock signal corresponding to the smallest signal pulse width in the corrected input signal pulse width sequence. Based on the second clock signal, the number of clock pulses contained in each corrected input signal pulse width is obtained, the number of clock pulses being the ratio of the corresponding corrected input signal pulse width and the pulse width of the second clock signal. Based on the number of clock pulses corresponding to each corrected input signal pulse width, the signal rate of the input signal is obtained by using the least square method. The least square method is used to adjust the signal rate and the phase to minimize the sum of squares of deviations between the clock edges obtained according to the product of the inverse of the signal rate and the number of clock pulses corresponding to each corrected input signal pulse width and the sum of target phases corresponding to each corrected input signal pulse width and the edges of the corresponding output signal.

[0206] Based on the above embodiments, the present embodiment further provides a communication system, as shown in Figure 12 .

[0207] The signal generating device 31 or the communication device 6 is configured to input the signal rate to the voltage-controlled oscillating unit to obtain the recovered clock signal output by the voltage-controlled oscillator, the recovered clock signal being used for clock recovery.

[0208] The phase discrimination unit is configured to output a control signal based on the recovered clock signal and a mapping relationship table. The mapping relationship table is configured to represent a mapping relationship between the control signal and a level of the input signal corresponding to a transition edge of the recovered clock signal. The control signal is configured to control the voltage-controlled oscillator to adjust the oscillation frequency and the phase, so that the recovered clock signal is consistent with the input signal in edge. In some embodiments, in the mapping relationship table in the phase discrimination unit, when a level of the input signal corresponding to a transition edge of the recovered clock signal is high and a level of the input signal corresponding to a previous transition edge of the recovered clock signal is high, the control signal is low. When a level of the input signal corresponding to a transition edge of the recovered clock signal is high and a level of the input signal corresponding to a previous transition edge of the recovered clock signal is low, the control signal is high. When a level of the input signal corresponding to a transition edge of the recovered clock signal is low and a level of the input signal corresponding to a previous transition edge of the recovered clock signal is high, the control signal is high. When a level of the input signal corresponding to a transition edge of the recovered clock signal is low and a level of the input signal corresponding to a previous transition edge of the recovered clock signal is low, the control signal is low.

[0209] Embodiment five

[0210] The embodiment further provides a computer readable storage medium, and a person skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware, and the program can be stored in a computer readable storage medium. When the program is executed, the program can include the processes of the above-mentioned embodiment methods. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM) and the like.

[0211] Embodiment six

[0212] The embodiment further provides a computer readable storage medium, and a person skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware, and the program can be stored in a computer readable storage medium. When the program is executed, the program can include the processes of the above-mentioned embodiment methods. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM) and the like. Figure 15 As shown in FIG. 8, a schematic diagram of an electronic device provided by an embodiment of the present application is shown. The electronic device 8 includes one or more processors 81, a memory 82, and an interface for connecting various components, including a high-speed interface and a low-speed interface. Various components are communicatively connected to each other by using different buses, and can be installed on a common mainboard or in other ways as needed. The processor can process instructions executed in the electronic device 8, including instructions stored in the memory or the memory to display graphical information on a GUI on an external input / output device, such as a display device coupled to the interface.

[0213] In some alternative embodiments, multiple processors and / or buses can be used with multiple memories and multiple storages, if desired. Also, multiple electronic devices 8 can be connected, each providing part of the necessary operations (e.g., as a server array, a set of blade servers, or a multi-processor system).

[0214] The processor 81 can be a central processing unit, a network processing unit, or a combination thereof. The processor 81 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or any combination thereof.

[0215] The memory 82 stores instructions executable by the at least one processor 81 to cause the at least one processor 81 to perform the methods illustrated in the above embodiments.

[0216] The memory 82 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs required by at least one function. The data storage area can store data created by the use of the electronic device 8 according to the presentation of the applet landing page, and the like. In addition, the memory 82 can include a high-speed random access memory, and can further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device.

[0217] The memory 82 can include a volatile memory, such as a random access memory. The memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state disk. The memory 82 can further include a combination of the above-mentioned types of memory.

[0218] The electronic device 8 further includes a communication interface 83 for communication of the electronic device 8 with other devices or communication networks.

[0219] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, can include the processes of the above-mentioned embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0220] Each of the above-mentioned modules or units can be implemented by software, for example, the clock recovery device 4, the phase detection unit 41, the determination unit 42, the loop filter unit 43, and the voltage-controlled oscillation unit 44 can be implemented based on software.

[0221] In the present application, "implemented by software" means that the processor reads and executes program instructions stored in the memory to implement the functions corresponding to the above-mentioned modules or units, wherein the processor refers to a processing circuit having a program instruction execution function, including but not limited to at least one of the following: a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a micro controller unit (MCU), or various types of processing circuits capable of running program instructions, etc. In other embodiments, the processor can also include other processing function circuits (such as hardware circuits for hardware acceleration, bus and interface circuits, etc.). The processor can be in the form of an integrated chip, for example, in the form of an integrated chip whose processing function only includes the function of executing software instructions, or it can also be in the form of SoC (system on a chip), that is, on one chip, in addition to including processing circuits (usually referred to as "nuclei") capable of running program instructions, it also includes other hardware circuits for implementing specific functions (of course, these hardware circuits can also be implemented based on ASIC, FPGA), accordingly, the processing function, in addition to including the function of executing software instructions, can also include various hardware acceleration functions (such as AI calculation, coding and decoding, compression and decompression, etc.).

[0222] It should be noted that when the present application is implemented by software, different software can be used, and it is not limited to using only one kind of software. For example, one module or unit can be implemented using a CPU, and another module or unit can be implemented using a DSP. Of course, it is not limited that part or all of the modules or units are implemented using the same software (such as all through the CPU).

[0223] The above preferred embodiments further illustrate the purpose, technical solutions and advantages of the present application. It should be understood that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A communication method characterized by comprising: The method comprises: obtaining a pulse width of a first clock signal based on a pulse width sequence of an input signal, the pulse width sequence of the input signal comprising a plurality of input signal pulse widths arranged in time sequence, the pulse width of the first clock signal being the smallest one of the input signal pulse widths in the pulse width sequence of the input signal; determining a reference signal pulse width corresponding to each input signal pulse width based on each input signal pulse width and the pulse width of the first clock signal, the reference signal pulse width being a pulse width corresponding to an integer multiple of the pulse width of the first clock signal, the integer multiple being the one with the smallest difference from the input signal pulse width; determining a clock deviation corresponding to each input signal pulse width based on each input signal pulse width and the corresponding reference signal pulse width, to obtain a clock deviation sequence, the clock deviation being a difference between each input signal pulse width and the corresponding reference signal pulse width; performing a sliding window operation on the clock deviation sequence based on a window width to obtain an updated clock deviation sequence, the sliding window operation comprising a plurality of sliding window processes, a step length between windows corresponding to each sliding window process being a sliding window step length, each sliding window process comprising: in a case where a change value of the clock deviation in the window is greater than a change threshold, correcting the input signal pulse width corresponding to the clock deviation in the window and updating the clock deviation sequence in the window; wherein the window width is a preset time distance, and the change value is a difference between a maximum value of the clock deviation in the window and a minimum value of the clock deviation in the window; in a case where all clock deviations in the updated clock deviation sequence are less than a deviation threshold, obtaining a signal rate of the input signal based on a corrected input signal pulse width sequence.

2. The communication method according to claim 1, characterized by, The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence.

3. The communication method according to claim 1, wherein, The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence.

4. The communication method according to claim 3, wherein, The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and 5. The communication method according to claim 4, wherein, performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence.

6. The communication method of claim 1, wherein, The method further comprises:

7. The communication method according to any one of claims 1 to 6, characterized by, in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on the clock deviation sequence based on the increased window width to obtain an updated clock deviation sequence. The method further comprises: in a case where all clock deviations in the updated clock deviation sequence are greater than or equal to the deviation threshold, increasing the window width; and performing the sliding window operation on Based on the corrected input signal pulse width sequence, the signal rate of the input signal is obtained by using a least square method.

8. The communication method according to claim 7, wherein, The signal rate of the input signal is obtained by using a least square method based on the corrected input signal pulse width sequence, including: Based on the corrected input signal pulse width sequence, a second clock signal is obtained, and a pulse width corresponding to the second clock signal is the smallest signal pulse width in the corrected input signal pulse width sequence. Based on the second clock signal, the number of clock pulses contained in each corrected input signal pulse width is obtained, and the number of clock pulses is the ratio of the corresponding corrected input signal pulse width to the pulse width of the second clock signal. Based on the number of clock pulses corresponding to each corrected input signal pulse width, the signal rate of the input signal is obtained by using a least square method. The least square method is used to adjust the signal rate and the phase to minimize the sum of squares of deviations of clock edges obtained according to the product of the reciprocal of the signal rate and the number of clock pulses corresponding to each corrected input signal pulse width and the sum of target phases corresponding to each corrected input signal pulse width from edges of the corresponding output signal.

9. The communication method of claim 1, wherein, The application is applied to a communication system, and the communication system includes: A signal generation device is used to perform the communication method in any one of claims 1-8; A clock recovery device includes a phase detection unit and a voltage-controlled oscillation unit. After the signal rate of the input signal is obtained, the communication method further includes: The signal generation device inputs the signal rate to the voltage-controlled oscillation unit to obtain a recovery clock signal output by the voltage-controlled oscillation unit, and the recovery clock signal is used for clock recovery. The phase detection unit outputs a control signal based on the recovery clock signal and a mapping relationship table, and the mapping relationship table is used to represent the mapping relationship between the control signal and the transition edge of the recovery clock signal corresponding to the level of the input signal. The control signal is used to control the voltage-controlled oscillation unit to adjust the oscillation frequency and the phase, so that the recovery clock signal is consistent with the edge of the input signal.

10. The communication method according to claim 9, wherein, In the mapping relationship table, In the case that the level of the input signal corresponding to one transition edge of the recovery clock signal is high, and the level of the input signal corresponding to the previous transition edge of the recovery clock signal is high, the control signal is low; In the case that the level of the input signal corresponding to one transition edge of the recovery clock signal is high, and the level of the input signal corresponding to the previous transition edge of the recovery clock signal is low, the control signal is high; In the case that the level of the input signal corresponding to one transition edge of the recovery clock signal is low, and the level of the input signal corresponding to the previous transition edge of the recovery clock signal is high, the control signal is high; In the case that the level of the input signal corresponding to one transition edge of the recovery clock signal is low, and the level of the input signal corresponding to the previous transition edge of the recovery clock signal is low, the control signal is low.

11. An electronic device, comprising: It includes: A communication interface; A processor coupled to the communication interface and configured to perform the communication method of any one of claims 1-10.

12. A communications device, characterized by Comprise: a minimum pulse width calculation module configured to obtain a pulse width of a first clock signal based on a pulse width sequence of an input signal, the pulse width sequence of the input signal comprising a plurality of input signal pulse widths arranged in time sequence, the pulse width of the first clock signal being a minimum input signal pulse width in the pulse width sequence of the input signal; a reference pulse width calculation module configured to determine a reference signal pulse width corresponding to each input signal pulse width based on each input signal pulse width and the pulse width of the first clock signal, the reference signal pulse width being a pulse width corresponding to a minimum difference between the input signal pulse width and a plurality of integer multiples of the pulse width of the first clock signal; a clock deviation calculation module configured to determine a clock deviation corresponding to each input signal pulse width based on each input signal pulse width and the corresponding reference signal pulse width, to obtain a clock deviation sequence, the clock deviation being a difference between each input signal pulse width and the corresponding reference signal pulse width; a pulse width correction module configured to perform a sliding window operation on the clock deviation sequence based on a window width to obtain an updated clock deviation sequence, the sliding window operation comprising a plurality of sliding window processes, a step length between windows corresponding to each sliding window process being a sliding window step length, each sliding window process comprising: in a case where a change value of the clock deviation in the window is greater than a change threshold, correcting the input signal pulse width corresponding to the clock deviation in the window and updating the clock deviation sequence in the window; wherein the window width is a preset time distance, and the change value is a difference between a maximum value of the clock deviation in the window and a minimum value of the clock deviation in the window; a determination module configured to obtain a signal rate of the input signal based on a corrected input signal pulse width sequence in a case where all clock deviations in the updated clock deviation sequence are less than a deviation threshold.

13. A computer-readable storage medium, characterized in that, The computer readable storage medium comprises instructions; when the instructions run on the processor, the processor performs the communication method of any one of claims 1-10.

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