A back contact solar cell manufacturing method with a set combination mask layer and the cell thereof

Abstract

The present application belongs to the technical field of back contact solar cell, and particularly relates to a back contact solar cell manufacturing method with a combined mask layer and a cell thereof, comprising the following steps: S2, forming a tunneling oxide layer, an intrinsic polysilicon layer, a first silicon oxide mask layer and a second polysilicon mask layer on the back of a silicon wafer in sequence; S3, forming a tunneling oxide layer, an N-type polysilicon layer, a first phosphorus-doped silicon oxide mask layer, a second phosphorus-doped polysilicon mask layer and a third PSG mask layer on the back; S4, forming a second semiconductor opening area; S5, etching and cleaning; then cleaning to remove the third PSG mask layer; S6, forming a third semiconductor layer and an anti-reflection layer on the front; S7, removing the anti-reflection layer and the wrap-around layer by using an acid solution; then removing the third semiconductor layer and the wrap-around layer by using an alkali solution; and finally cleaning. The present application can completely protect the first semiconductor structure of the tunneling oxide layer and the N-type polysilicon layer on the back, and does not need to increase new process equipment, thereby ensuring a high passivation level and improving the conversion efficiency of the cell.

Description

Technical Field

[0001] This invention belongs to the field of back-contact solar cell technology, specifically relating to a method for manufacturing a back-contact solar cell with a combined mask layer and the cell thereof. Background Technology

[0002] In the field of back-contact solar cells, silicon nitride mask layers are usually used as protective layers for wet cleaning on the back side. With the optimization of back-contact solar cell process routes, the new generation of back-contact solar cells with lower cost is the post-texturing process, which requires repeated cleaning processes of alkaline solution-acid solution-alkaline solution-acid solution. Therefore, the conventional single mask layer method can no longer meet the current cleaning process of back-contact solar cells.

[0003] Specifically, the main process flow of the existing post-texturing process for co-passivated back contact solar cells is as follows: 1) Deposition of a tunneling polycrystalline layer on the back side; 2) Using the PSG and silicon nitride mask layer on the surface of the polycrystalline layer as mask layers for subsequent alkaline texturing and hydrofluoric acid cleaning; 3) Deposition of the third semiconductor layer and antireflection layer on the front side; 4) Sequential cleaning of the back surface using hydrofluoric acid and alkaline solution. However, the conventional silicon nitride mask layer will be removed during hydrofluoric acid cleaning after texturing. Therefore, during the subsequent hydrofluoric acid and alkaline cleaning steps, the back tunneling polycrystalline layer will be completely exposed to the solution and severely corroded, affecting the cell conversion efficiency.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or known technology. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies where the post-texturing manufacturing process of back-contact solar cells has insufficient efficiency for further improvement. This invention provides a method for manufacturing back-contact solar cells with a combined mask layer and the cell itself. This invention can completely protect the first semiconductor structure, including the back tunneling oxide layer and the N-type polycrystalline silicon layer, without requiring additional process equipment, ensuring a high passivation level and improving cell conversion efficiency.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a method for manufacturing a back-contact solar cell with a combined mask layer, comprising the following steps:

[0007] S1. Provides double-sided polished silicon wafers;

[0008] S2. A tunneling oxide layer, an intrinsic polysilicon layer, a first silicon oxide mask layer, and a second polysilicon mask layer are sequentially formed on the back side of the silicon wafer.

[0009] S3. Phosphorus diffusion and high-temperature annealing are performed on the back side film to form a tunneling oxide layer, an N-type polycrystalline silicon layer, a first phosphorus-doped silicon oxide mask layer, a second phosphorus-doped polycrystalline silicon mask layer, and a third PSG mask layer. During this process, the annealing temperature T (in °C) and the thickness L1 (in nm) of the first silicon oxide mask layer and the thickness L2 (in nm) of the second polycrystalline silicon mask layer satisfy the following relationship: T = 10L1 + 2L2 + 920.

[0010] S4. First etching openings are made on each film layer on the back side obtained in S3 to form a second semiconductor opening region arranged at intervals.

[0011] S5. By texturing and cleaning, the residual tunneling oxide layer and N-type polysilicon layer in the second semiconductor opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the second semiconductor opening area. Then, the third PSG mask layer is removed by cleaning. The texturing solution used in the texturing process contains PSG protective additives.

[0012] S6. A third semiconductor layer and an anti-reflection layer are formed on the front side of the silicon wafer, while a corresponding wrap-around plating layer is formed on the back side.

[0013] S7. First, use acid to remove the antireflection layer coating; then use alkaline solution to remove the third semiconductor layer coating, while the second phosphorus-doped polysilicon mask layer is removed; then clean, while the first phosphorus-doped silicon oxide mask layer is removed.

[0014] S8. Deposit a second semiconductor layer on the back side.

[0015] In some preferred embodiments of the present invention, in S3, L1 is 2-3 nm, L2 is 25-35 nm; and / or, T is 990-1020 °C.

[0016] In some preferred embodiments of the present invention, in S3, the phosphorus doping concentration of the third PSG mask layer is controlled to be 5e21cm. -3 -8e21cm -3 The phosphorus doping concentration of the second phosphorus-doped polycrystalline silicon mask layer is 1e21cm. -3 -3e21cm -3 The phosphorus doping concentration of the first phosphorus-doped silicon oxide mask layer is 5e20cm. -3 -8e20cm -3 ; and / or, the phosphorus doping concentration of the N-type polycrystalline silicon layer is 1e20cm⁻¹. -3 -5e20cm -3 .

[0017] In some preferred embodiments of the present invention, the thickness of the N-type polysilicon layer is 100-150 nm, the thickness of the tunneling oxide layer is 1.2-1.8 nm, and / or the thickness of the third PSG mask layer is 15-25 nm.

[0018] In some preferred embodiments of the present invention, at least one of the following conditions is also satisfied in S3:

[0019] Condition 1: The conditions for phosphorus diffusion include: process temperature of 810-830℃ and process time of 25-30min;

[0020] Condition 2: During the phosphorus diffusion process, phosphorus oxychloride, oxygen, and nitrogen are introduced. The oxygen flow rate is 500-1000 sccm, and the flow rate of the mixed gas carrying phosphorus oxychloride is 150-250 sccm.

[0021] Condition 3: The conditions for high-temperature annealing include: annealing pressure of 300-500 mbar, and / or, high-temperature annealing time of 4-6 min;

[0022] Condition 4: Oxygen is introduced during the high-temperature annealing process, with an oxygen flow rate of 2000-4000 sccm.

[0023] In some preferred embodiments of the present invention, in S2, the process of forming the tunneling oxide layer, the intrinsic polysilicon layer, the first silicon oxide mask layer, and the second polysilicon mask layer includes: in the first stage, oxygen is introduced and then oxygen is trapped to form the tunneling oxide layer; in the second stage, silane is introduced to form the intrinsic polysilicon layer; in the third stage, oxygen is introduced and then oxygen is trapped to form the first silicon oxide mask layer; and in the fourth stage, silane is introduced to form the second polysilicon mask layer; wherein the process conditions of each stage satisfy at least one of the following processes:

[0024] The conditions for the first stage of process 1 include: oxygen flow rate of 8000-10000 sccm, oxygen supply time of 3-5 min, oxygen saturation pressure of 500-800 mbar, oxygen saturation temperature of 600-610℃, and oxygen saturation time of 15-25 min.

[0025] The conditions for the second stage of process 2 include: silane flow rate of 300-800 sccm, process pressure of 20-30 Pa, process temperature of 605-615℃, and process time of 20-30 min.

[0026] The conditions for the third stage of process 3 include: oxygen flow rate of 8000-10000 sccm, oxygen supply time of 3-5 min, oxygen saturation pressure of 500-800 mbar, oxygen saturation temperature of 610-630℃, and oxygen saturation time of 5-10 min.

[0027] The conditions for the fourth stage of process include: silane flow rate of 100-200 sccm, process pressure of 10-20 Pa, process temperature of 610-630℃, and process time of 4-8 min.

[0028] In some preferred embodiments of the present invention, in S5, the mass concentration of the PSG protective additive in the texturing solution is 0.5%-3%, and / or, in S5, the cleaning to remove the third PSG mask layer uses a hydrofluoric acid solution with a mass concentration of 1%-5%.

[0029] In some preferred embodiments of the present invention, in S7, the acid solution is a hydrofluoric acid solution with a mass concentration of 5%-10%, and the alkali solution is a sodium hydroxide solution or potassium hydroxide solution with a mass concentration of 1%-2%.

[0030] In some preferred embodiments of the present invention, in S7, the acid cleaning time is 4-6 min and the alkali cleaning time is 1.5-3 min.

[0031] In some preferred embodiments of the present invention, the method for manufacturing a back-contact solar cell further includes at least one of the following methods:

[0032] In Method 1, S6, the third semiconductor layer includes oxygen-doped amorphous silicon, and the antireflection layer includes silicon nitride.

[0033] Method 2, in S6, the thickness of the third semiconductor layer is 6-10 nm, and the thickness of the antireflection layer is 80-110 nm;

[0034] Method 3, S8, the second semiconductor layer includes an intrinsic amorphous silicon layer and a P-type doped silicon layer disposed sequentially;

[0035] Method 4, the manufacturing method also includes the following steps:

[0036] S9. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region, and then cleaned.

[0037] S10. Deposit a conductive film layer on the back side obtained in S9;

[0038] S11. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0039] S12. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0040] In a second aspect, the present invention provides a back-contact solar cell, which is manufactured by the back-contact solar cell manufacturing method described in the first aspect, which provides a combined mask layer.

[0041] Beneficial effects:

[0042] The present invention, through the above-mentioned technical solution, especially the combined mask layer structure of a first phosphorus-doped silicon oxide mask layer, a second phosphorus-doped polycrystalline silicon mask layer and a third PSG mask layer on the back side in S2-S3, and the annealing temperature T controlled to advance the high-temperature annealing process to satisfy the above-mentioned specific relationship with the thickness of the first silicon oxide mask layer and the thickness of the second polycrystalline silicon mask layer, and the texturing solution used in S5 containing PSG protective additives and step S7, can completely protect the first semiconductor structure of the back tunneling oxide layer and the N-type polycrystalline silicon layer, without the need to add new process equipment, ensuring a high passivation level and improving battery conversion efficiency. The specific combination of a first phosphorus-doped silicon oxide mask layer, a second phosphorus-doped polysilicon mask layer, and a third PSG mask layer creates a mask structure that protects the tunnel oxide layer, N-type polysilicon layer, first phosphorus-doped silicon oxide mask layer, and second phosphorus-doped polysilicon mask layer during texturing in S5. The third PSG mask layer is then removed during cleaning. Furthermore, the second phosphorus-doped polysilicon mask layer protects the tunnel oxide layer, N-type polysilicon layer, and first phosphorus-doped silicon oxide mask layer from damage during the acid removal of the anti-reflection layer and the plating process in S7. Subsequently, the second phosphorus-doped polysilicon mask layer is removed in an alkaline solution, while the first phosphorus-doped silicon oxide mask layer blocks alkaline erosion, protecting the underlying tunnel oxide layer and N-type polysilicon layer from damage. After removing the back-side wrapping, cleaning removes the first phosphorus-doped silicon oxide mask layer on the back side. This achieves a first semiconductor structure that completely protects the back-side tunnel oxide layer and N-type polysilicon layer without requiring additional process equipment.

[0043] Furthermore, the applicant's research found that when S3 is performed after forming the tunneling oxide layer, intrinsic polysilicon layer, first silicon oxide mask layer, and second polysilicon mask layer in S2, the first silicon oxide mask layer has a significant blocking effect on phosphorus diffusion, which easily leads to excessively high phosphorus doping concentration in the third PSG mask layer and excessively low doping solubility in the N-type polysilicon layer. This makes the third PSG mask layer easily corroded during the subsequent S5 texturing and cleaning process, thus failing to provide protection. The N-type polysilicon layer also suffers from poor conductivity and field passivation due to low doping solubility. To address this, the present invention specifically controls the annealing temperature T during the high-temperature annealing process to satisfy the aforementioned specific relationship with the thicknesses of the first silicon oxide mask layer and the second polycrystalline silicon mask layer. This optimizes the high-temperature diffusion process, allowing phosphorus to quickly pass through the first silicon oxide mask layer without damaging the tunneling oxide layer (while, under the same mask layer combination, the high-temperature annealing process of the traditional diffusion process requires a temperature of approximately 850-900°C and a relatively long time of about 30 minutes, at which temperature phosphorus is difficult to pass through the second tunneling layer). This effectively controls the doping concentrations of the N-type polycrystalline silicon layer, the second phosphorus-doped polycrystalline silicon mask layer, and the third PSG mask layer, enabling them to provide optimal protection during subsequent cleaning, thereby ensuring a high passivation level and improving battery conversion efficiency. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the structure of a silicon wafer after polishing and cleaning, according to a specific embodiment of the present invention.

[0046] Figure 2 This is a schematic diagram of the structure of a combined mask layer formed after diffusion on a silicon wafer, according to a specific embodiment of the present invention.

[0047] Figure 3 This is a schematic diagram of the structure after texturing and cleaning following the formation of the second semiconductor opening region in a specific embodiment of the present invention.

[0048] Figure 4 This is a schematic diagram of the structure of forming a third semiconductor layer and an anti-reflection layer on the front side of a silicon wafer according to a specific embodiment of the present invention.

[0049] Figure 5 This is a schematic diagram of the structure of a silicon wafer after RCA cleaning, according to a specific embodiment of the present invention.

[0050] Figure 6 This is a schematic diagram of a structure in which a first semiconductor opening region is formed on the back side of a silicon wafer according to a specific embodiment of the present invention.

[0051] Figure 7 This is a schematic diagram of a transparent conductive film layer deposited on the back of a silicon wafer according to a specific embodiment of the present invention.

[0052] Figure 8 This is a schematic diagram of a structure in which a metal electrode is formed on the back side of a silicon wafer according to a specific embodiment of the present invention.

[0053] Explanation of reference numerals in the attached figures

[0054] 1. Silicon wafer, 2. Tunneling oxide layer, 3. N-type polycrystalline silicon layer, 4. First phosphorus-doped silicon oxide mask layer, 5. Second phosphorus-doped polycrystalline silicon mask layer, 6. Third PSG mask layer, 7. Third semiconductor layer, 8. Anti-reflection layer, 9. Intrinsic amorphous silicon layer, 10. P-type doped amorphous silicon layer, 11. Transparent conductive film layer, 12. First semiconductor opening region S101, 13. Second semiconductor opening region S102. Detailed Implementation

[0055] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0056] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0057] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "optional" mean that they may or may not be included (or may or may not be present).

[0058] In this invention, the area closer to the silicon wafer is considered the inside, and the area farther from the silicon wafer is considered the outside.

[0059] In a first aspect, the present invention provides a method for manufacturing a back-contact solar cell with a combined mask layer, comprising the following steps:

[0060] S1. Provides double-sided polished silicon wafers;

[0061] S2. A tunneling oxide layer, an intrinsic polysilicon layer, a first silicon oxide mask layer, and a second polysilicon mask layer are sequentially formed on the back side of the silicon wafer.

[0062] S3. Phosphorus diffusion and high-temperature annealing are performed on the back film layer to form a tunneling oxide layer, an N-type polycrystalline silicon layer, a first phosphorus-doped silicon oxide mask layer, a second phosphorus-doped polycrystalline silicon mask layer, and a third PSG mask layer. During this process, the annealing temperature T (in °C) and the thickness L1 (in nm) of the first silicon oxide mask layer and the thickness L2 (in nm) of the second polycrystalline silicon mask layer satisfy the following relationship: T = 10L1 + 2L2 + 920.

[0063] S4. First etching openings are made on each film layer on the back side obtained in S3 to form a second semiconductor opening region arranged at intervals.

[0064] S5. By texturing and cleaning, the residual tunneling oxide layer and N-type polysilicon layer in the second semiconductor opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the second semiconductor opening area. Then, the third PSG mask layer is removed by cleaning. The texturing solution used in the texturing process contains PSG protective additives.

[0065] S6. A third semiconductor layer and an anti-reflection layer are formed on the front side of the silicon wafer, while a corresponding wrap-around plating layer is formed on the back side.

[0066] S7. First, use acid to remove the antireflection layer coating; then use alkaline solution to remove the third semiconductor layer coating, while the second phosphorus-doped polysilicon mask layer is removed; then clean, while the first phosphorus-doped silicon oxide mask layer is removed.

[0067] S8. Deposit a second semiconductor layer on the back side.

[0068] In the manufacturing method of this invention, a specific combination mask layer structure comprising a first phosphorus-doped silicon oxide mask layer, a second phosphorus-doped polysilicon mask layer, and a third PSG mask layer protects the tunneling oxide layer, the N-type polysilicon layer, the first phosphorus-doped silicon oxide mask layer, and the second phosphorus-doped polysilicon mask layer during texturing in S5, and removes the third PSG mask layer in the subsequent cleaning process; and protects the tunneling oxide layer and the N-type polysilicon layer during the acid removal of the antireflection layer and the plating process in S7, using the second phosphorus-doped polysilicon mask layer. The crystalline silicon layer and the first phosphorus-doped silicon oxide mask layer remain undamaged. Subsequently, the second phosphorus-doped polycrystalline silicon mask layer is removed in an alkaline solution. At the same time, the first phosphorus-doped silicon oxide mask layer blocks the erosion of the alkaline solution, protecting the underlying tunneling oxide layer and N-type polycrystalline silicon layer from damage. After removing the back-side wrapping, the first phosphorus-doped silicon oxide mask layer on the back side is removed by cleaning. This achieves a first semiconductor structure that can completely protect the back-side tunneling oxide layer and N-type polycrystalline silicon layer without the need for additional process equipment, thereby improving the battery conversion efficiency.

[0069] In some preferred embodiments of the present invention, in S3, L1 is 2-3 nm, specifically 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, or 3 nm, or any range between two values; and / or, L2 is 25-35 nm, specifically 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, or 35 nm, or any range between two values. The present invention employs a first phosphorus-doped silicon oxide mask layer and a second phosphorus-doped polycrystalline silicon mask layer of suitable thickness, which is more conducive to more completely protecting the tunneling oxide layer and the first semiconductor layer of the N-type polycrystalline silicon layer in subsequent cleaning steps while ensuring sufficient phosphorus doping.

[0070] In some preferred embodiments of the present invention, T is 990-1020℃, specifically 990℃, 995℃, 998℃, 1000℃, 1001℃, 1002℃, 1005℃, 1007℃, 1009℃, 1010℃, 1012℃, 1015℃, 1018℃, 1019℃, or 1020℃, or any range between two points. The present invention employs a suitable high-temperature annealing advance temperature, coupled with a specific relationship between this temperature and the thickness of the first phosphorus-doped silicon oxide mask layer and the second phosphorus-doped polycrystalline silicon mask layer. This better ensures the alkali resistance of the third PSG mask layer while increasing the doping concentration of the N-type polycrystalline silicon layer, improving the conductivity of the N-type polycrystalline silicon layer, further increasing the battery fill factor, and improving the battery conversion efficiency.

[0071] In S2 of this invention, the tunneling oxide layer, the intrinsic polysilicon layer, the first silicon oxide mask layer, and the second polysilicon mask layer can be deposited by tubular PECVD, LPCVD, or PVD processes, with tubular LPCVD process being preferred.

[0072] In some preferred embodiments of the present invention, in step S2, the process of forming the tunneling oxide layer, the intrinsic polysilicon layer, the first silicon oxide mask layer, and the second polysilicon mask layer includes: in the first stage, oxygen is introduced followed by oxygen saturation to form the tunneling oxide layer; in the second stage, silane is introduced to form the intrinsic polysilicon layer; in the third stage, oxygen is introduced followed by oxygen saturation to form the first silicon oxide mask layer; and in the fourth stage, silane is introduced to form the second polysilicon mask layer. This preferred approach facilitates the formation of a dense oxide layer and polysilicon layer, ensuring passivation while improving the corrosion resistance of each mask layer.

[0073] In some preferred embodiments of the present invention, the conditions of the first stage include: an oxygen flow rate of 8000-10000 sccm, an oxygen supply time of 3-5 min, an oxygenation pressure of 500-800 mbar, an oxygenation temperature of 600-610℃, and an oxygenation time of 15-25 min.

[0074] In some preferred embodiments of the present invention, the conditions of the second stage include: silane flow rate of 300-800 sccm, process pressure of 20-30 Pa, process temperature of 605-615 °C, and process time of 20-30 min.

[0075] In some preferred embodiments of the present invention, the conditions of the third stage include: an oxygen flow rate of 8000-10000 sccm, an oxygen supply time of 3-5 min, an oxygenation pressure of 500-800 mbar, an oxygenation temperature of 610-630°C, and an oxygenation time of 5-10 min.

[0076] In some preferred embodiments of the present invention, the conditions for the fourth stage include: silane flow rate of 100-200 sccm, process pressure of 10-20 Pa, process temperature of 610-630 °C, and process time of 4-8 min.

[0077] In some preferred embodiments of the present invention, in S3, the phosphorus doping concentration of the third PSG mask layer is controlled to be 5e21cm. -3 -8e21cm -3 The phosphorus doping concentration of the second phosphorus-doped polycrystalline silicon mask layer is 1e21cm. -3 -3e21cm -3 The phosphorus doping concentration of the first phosphorus-doped silicon oxide mask layer is 5e20cm. -3 -8e20cm -3 This preferred approach better ensures the alkali resistance of the third PSG mask layer while improving the conductivity of the N-type polysilicon layer.

[0078] In some preferred embodiments of the present invention, the phosphorus doping concentration of the N-type polycrystalline silicon layer is 1e20cm⁻¹. -3 -5e20cm -3 This preferred approach is more conducive to improving the passivation performance and conductivity of the N-type polycrystalline silicon layer.

[0079] In some preferred embodiments of the present invention, the thickness of the N-type polycrystalline silicon layer is 100-150 nm.

[0080] Preferably, the thickness of the tunneling oxide layer is 1.2-1.8 nm.

[0081] In some preferred embodiments of the present invention, the thickness of the third PSG mask layer is 15-25 nm, specifically, it can be 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, or 25 nm, or any range between two values. Using a suitable thickness for the third PSG mask layer is more conducive to protecting the underlying film layer from alkaline corrosion during the texturing step.

[0082] In this invention, phosphorus diffusion and high-temperature annealing in S3 can be carried out using a tubular high-temperature diffusion furnace.

[0083] In some preferred embodiments of the present invention, the conditions for phosphorus diffusion include: a process temperature of 810-830°C and a process time of 25-30 minutes. This preferred approach facilitates a more complete reaction of phosphorus oxychloride.

[0084] In some preferred embodiments of the present invention, during the phosphorus diffusion process, phosphorus oxychloride, oxygen, and nitrogen are introduced. The oxygen flow rate is 500-1000 sccm, and the flow rate of the nitrogen-carrying phosphorus oxychloride mixture is 150-250 sccm. Preferably, phosphorus oxychloride is introduced by nitrogen bubbling, and the flow rate of phosphorus oxychloride is sufficient to achieve the target phosphorus doping concentration.

[0085] In some preferred embodiments of the present invention, the conditions for high-temperature annealing include: an annealing pressure of 300-500 mbar, and / or a high-temperature annealing time of 4-6 min. The present invention employs a shorter high-temperature annealing time, which is more conducive to ensuring uniform diffusion of phosphorus impurities into the N-type polycrystalline silicon layer without damaging the tunneling oxide layer.

[0086] In some preferred embodiments of the present invention, oxygen is introduced during the high-temperature annealing process, which is more conducive to the formation of a dense third PSG mask layer. A further preferred oxygen flow rate is 2000-4000 sccm.

[0087] In S5 of this invention, the PSG protective additive in the texturing solution can be obtained commercially, as long as it can protect the third PSG mask layer during the texturing process; furthermore, other components in the texturing solution, such as texturing additives, can be processed in accordance with the prior art, as long as they facilitate the removal of the residual tunneling oxide layer and N-type polysilicon layer in the second semiconductor opening region, and simultaneously form a textured surface on the front side of the silicon wafer and the second semiconductor opening region.

[0088] In some preferred embodiments of the present invention, in step S5, the mass concentration of the PSG protective additive in the texturing solution is 0.5%-3%. The PSG protective additive is a commercially available product and will not be described in detail here.

[0089] In some more preferred embodiments of the present invention, in S5, the cleaning and removal of the third PSG mask layer uses a hydrofluoric acid solution with a mass concentration of 1%-5%.

[0090] In some preferred embodiments of the present invention, in step S7, the acid solution is a hydrofluoric acid solution with a mass concentration of 5%-10%, and the alkaline solution is a sodium hydroxide solution or potassium hydroxide solution with a mass concentration of 1%-2%. This preferred approach better ensures cleaning capability while reducing damage to the membrane layer from the solution.

[0091] In some preferred embodiments of the present invention, in step S7, the acid cleaning time is 4-6 minutes, and the alkaline cleaning time is 1.5-3 minutes. This preferred approach better ensures cleaning capability while reducing damage to the membrane layer from the solution.

[0092] The solution used to remove the first phosphorus-doped silicon oxide mask layer in S7 of this invention can be obtained using a conventional RCA cleaning process, as long as the target film layer can be removed.

[0093] In some preferred embodiments of the present invention, in S6, the third semiconductor layer comprises oxygen-doped amorphous silicon, and the antireflection layer comprises silicon nitride. This preferred approach better ensures passivation while reducing parasitic absorption in the front-side film, thereby increasing current.

[0094] In some preferred embodiments of the present invention, in S6, the thickness of the third semiconductor layer is 6-10 nm, and the thickness of the antireflection layer is 80-110 nm.

[0095] More preferably, the refractive index of the antireflective layer is 2.2-2.5, which is more conducive to improving the short-circuit current of the battery.

[0096] In S7 of this invention, acid is first used to remove the antireflection layer coating; then, alkaline solution is used to remove the third semiconductor layer coating, which can be carried out using a chain-type water-floating device.

[0097] In some preferred embodiments of the present invention, in step S8, the second semiconductor layer comprises an intrinsic amorphous silicon layer and a P-type doped silicon layer sequentially disposed. The P-type doped silicon layer may be, for example, P-type doped amorphous silicon or P-type doped microcrystalline silicon. The thicknesses and corresponding doping concentrations of the intrinsic amorphous silicon layer and the P-type doped silicon layer described in the present invention can refer to the ranges in the prior art, and all can be used in the present invention. For example, the thickness of the intrinsic amorphous silicon layer is 5-15 nm, the thickness of the P-type doped silicon layer is 10-35 nm, and the boron doping concentration is 1e19 cm⁻¹. -3 -4e20 cm -3 .

[0098] In some preferred embodiments of the present invention, the manufacturing method further includes the following steps:

[0099] S9. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region, and then cleaned.

[0100] S10. Deposit a conductive film layer on the back side obtained in S9;

[0101] S11. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0102] S12. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0103] The corresponding etching methods for the first and second semiconductor opening regions of this invention can each employ laser etching or mask etching. More preferably, the laser is an ultraviolet or green laser with a pulse width of less than 100 ns.

[0104] The widths of the first semiconductor opening region, the second semiconductor opening region, and the isolation trench of the present invention can refer to the range of the prior art. For example, the width of the second semiconductor opening region is 0.3-0.6 mm, the width of the first semiconductor opening region is 0.1-0.3 mm, and the width of the isolation trench is 30-200 µm.

[0105] In a second aspect, the present invention provides a back-contact solar cell, which is manufactured by the back-contact solar cell manufacturing method described in the first aspect, which provides a combined mask layer.

[0106] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0107] Example 1

[0108] A back-contact solar cell is manufactured by the following method:

[0109] S1, such as Figure 1 As shown, silicon wafer 1 (N-type monocrystalline silicon wafer) is polished and cleaned on both sides.

[0110] S2, such as Figure 2As shown, a tunneling oxide layer 2, an intrinsic polysilicon layer, a first silicon oxide mask layer, and a second polysilicon mask layer are sequentially formed on the back side of silicon wafer 1 using a tubular LPCVD process. Specifically, in the first stage, oxygen is introduced followed by oxygen annealing to form the tunneling oxide layer 2. The oxygen flow rate is 9000 sccm, the oxygen introduction time is 4 min, the oxygen annealing pressure is 600 mbar, the oxygen annealing temperature is 600℃, the oxygen annealing time is 20 min, and the thickness of the tunneling oxide layer 2 is 1.4 nm. In the second stage, silane is introduced to form the intrinsic polysilicon layer. The silane flow rate is 500 sccm, the process pressure is 25 Pa, the process temperature is 610℃, the process time is 25 min, and the thickness of the intrinsic polysilicon layer is 120 nm. After the third stage, oxygen is introduced and oxygen is allowed to condense to form the first silicon oxide mask layer. The oxygen flow rate is 9000 sccm, the oxygen introduction time is 5 min, the oxygen condensation pressure is 600 mbar, the process temperature is 620℃, and the oxygen condensation time is 6 min. The thickness L1 of the first silicon oxide mask layer is 2.5 nm. In the fourth stage, silane is introduced to form the second polycrystalline silicon mask layer. The silane flow rate is 150 sccm, the process pressure is 15 Pa, the process temperature is 610℃, and the process time is 6 min. The thickness L2 of the second polycrystalline silicon mask layer is 30 nm.

[0111] S3, such as Figure 2 As shown, a tubular high-temperature diffusion furnace was used to perform high-temperature phosphorus diffusion on the tunneling oxide layer 2, the intrinsic polycrystalline silicon layer, the first silicon oxide mask layer, and the second polycrystalline silicon mask layer to form the tunneling oxide layer 2, the N-type polycrystalline silicon layer 3, the first phosphorus-doped silicon oxide mask layer 4, the second phosphorus-doped polycrystalline silicon mask layer 5, and the third PSG mask layer 6. The high-temperature phosphorus diffusion process included: the first stage, phosphorus oxychloride and oxygen were introduced for phosphorus diffusion, with phosphorus oxychloride carried by nitrogen bubbling. The process temperature was 820℃, the oxygen flow rate was 700 sccm, and the flow rate of the mixed gas carrying phosphorus oxychloride was 200 sccm. The process time was 25 min. The second stage was a high-temperature annealing and propagation stage. The annealing temperature T was 1005℃, and oxygen was introduced during annealing at a flow rate of 3000 sccm. The annealing pressure was 400 mbar, and the annealing time was 5 min. After diffusion, the third PSG mask layer 6 was naturally formed with a thickness of 20 nm. The phosphorus doping concentration of the third PSG mask layer 6 is 6.5e21cm. -3 The phosphorus doping concentration of the second phosphorus-doped polycrystalline silicon mask layer is 1.5e21cm. -3 The phosphorus doping concentration of the first phosphorus-doped silicon oxide mask layer is 6.5e20cm. -3 The phosphorus doping concentration of the N-type polycrystalline silicon layer is 3e20cm. -3 .

[0112] S4, such as Figure 3As shown, an opening is etched on the back side of silicon wafer 1 using a laser to form a second semiconductor opening region S102. The second semiconductor opening region S102 has a width of 0.5 mm, and the tunneling oxide layer 2, N-type polysilicon layer 3, first phosphorus-doped silicon oxide mask layer 4, second phosphorus-doped polysilicon mask layer 5, and third PSG mask layer 6 within the second semiconductor opening region S102 are etched away. The laser used is an ultraviolet laser with a pulse width of 50 ns.

[0113] S5, such as Figure 3 As shown, texturing and cleaning are performed using a texturing solution with a mass concentration of 1.5% PSG protective additive (commercially available). This removes the residual tunneling oxide layer 2 and N-type polysilicon layer 3 within the second semiconductor opening region S102, simultaneously forming a textured surface on the front side of the silicon wafer 1 and the second semiconductor opening region S102. During texturing, a third PSG mask layer 6 protects the tunneling oxide layer 2, N-type polysilicon layer 3, first phosphorus-doped silicon oxide mask layer 4, and second phosphorus-doped polysilicon mask layer 5. Afterwards, cleaning with a mass concentration of 2% hydrofluoric acid solution removes the third PSG mask layer 6 outside the second semiconductor opening region S102 on the back side of the silicon wafer 1.

[0114] S6, such as Figure 4 As shown, a third semiconductor layer 7 and an antireflection layer 8 are formed on the front side of silicon wafer 1, while a third semiconductor layer and an antireflection layer are formed around the back side. The third semiconductor layer 7 is oxygen-doped amorphous silicon with a thickness of 6 nm, and the antireflection layer 8 is silicon nitride with a thickness of 90 nm and a refractive index of 2.3.

[0115] S7, such as Figure 5 As shown, a chain-type floating device is used to remove the back-side third semiconductor layer and anti-reflection layer coatings. Specifically, firstly, a 7% hydrofluoric acid solution is used to remove the anti-reflection layer coating for 5 minutes, protecting the tunneling oxide layer 2, N-type polysilicon layer 3, and first phosphorus-doped silicon oxide mask layer 4 from damage through the second phosphorus-doped polysilicon mask layer 5. Next, a 1.5% potassium hydroxide solution is used to remove the back-side third semiconductor layer coating for 2 minutes, during which the second phosphorus-doped polysilicon mask layer 5 is removed, while the first phosphorus-doped silicon oxide mask layer 4 blocks alkaline corrosion, protecting the underlying tunneling oxide layer 2 and N-type polysilicon layer 3 from damage. After removing the back-side coating, a conventional RCA cleaning process is used to remove the first phosphorus-doped silicon oxide mask layer 4.

[0116] S8, such as Figure 6 As shown, a second semiconductor layer is deposited on the back side of a silicon wafer using plasma-enhanced chemical vapor deposition (PECVD). This second semiconductor layer comprises an intrinsic amorphous silicon layer 9 with a thickness of 10 nm and a p-type doped amorphous silicon layer 10. The p-type doped amorphous silicon layer 10 has a thickness of 20 nm and a boron doping concentration of 1e20 cm⁻¹.-3 .

[0117] S9, such as Figure 6 As shown, an opening is etched on the back side of silicon wafer 1 using a laser to form a first semiconductor opening region S101 spaced apart from the second semiconductor opening region S102, followed by cleaning. The first semiconductor opening region S101 has a width of 0.2 mm, and the second semiconductor layer within the first semiconductor opening region S101 is etched and cleaned. The laser used is an ultraviolet laser with a pulse width of 20 ns.

[0118] S10, such as Figure 7 As shown, a transparent conductive film layer 11 is deposited on the back side of silicon wafer 1.

[0119] S11, such as Figure 7 As shown, an isolation trench with a width of 100µm is formed between the first semiconductor opening region S101 and the second semiconductor opening region S102 by means of laser.

[0120] S12, such as Figure 8 As shown, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers of the first semiconductor opening region S101 and the second semiconductor opening region S102.

[0121] Example 2

[0122] The procedure was carried out in accordance with Example 1, except that the thickness L2 of the second polysilicon mask layer was adjusted to 25 nm, and the annealing temperature T for the high-temperature annealing process was correspondingly adjusted to 995 °C. The resulting phosphorus doping concentration of the third PSG mask layer was 7e21 cm⁻¹. -3 The phosphorus doping concentration of the second phosphorus-doped polycrystalline silicon mask layer is 2.3e21cm. -3 The phosphorus doping concentration of the first phosphorus-doped silicon oxide mask layer is 6 e20 cm⁻¹. -3 The phosphorus doping concentration of the N-type polycrystalline silicon layer is 2 e20 cm⁻¹. -3 The thickness of the resulting third PSG mask layer is 18 nm.

[0123] Example 3

[0124] The procedure was carried out in accordance with Example 1, except that the thickness L1 of the first silicon oxide mask layer was adjusted to 2 nm, and the annealing temperature T for the high-temperature annealing process was correspondingly adjusted to 1000 °C. The resulting phosphorus doping concentration of the third PSG mask layer was 6.8 e21 cm⁻¹. -3 The phosphorus doping concentration of the second phosphorus-doped polycrystalline silicon mask layer is 1.8e21cm. -3 The phosphorus doping concentration of the first phosphorus-doped silicon oxide mask layer is 6.3e20cm. -3 The phosphorus doping concentration of the N-type polycrystalline silicon layer is 2.5 e20cm. -3The thickness of the resulting third PSG mask layer is 19 nm.

[0125] Example 4

[0126] The procedure was carried out in accordance with Example 1, except that in S5, the mass concentration of the PSG protective additive in the texturing solution was 0.5%.

[0127] Comparative Example 1

[0128] The existing conventional back-contact solar cell manufacturing method differs from Example 1 in that S2-S3 are replaced with: depositing a tunneling oxide layer and an N-type polycrystalline silicon layer on the back side, using a PSG and silicon nitride mask layer on the surface of the N-type polycrystalline silicon layer as a protective mask layer; and S5 does not contain the PSG protective additive. The conventional PSG and silicon nitride mask layers are removed during the hydrofluoric acid cleaning in S5 after texturing. Therefore, during the subsequent hydrofluoric acid and alkaline cleaning steps in S7, the back-contact tunneling oxide layer and the N-type polycrystalline silicon layer will be completely exposed to the solution and severely corroded, affecting the cell's conversion efficiency.

[0129] Comparative Example 2

[0130] The process was carried out in accordance with Example 1, except that the annealing temperature T for the high-temperature annealing was 900°C. The resulting phosphorus doping concentration in the third PSG mask layer was 3e22cm⁻¹. -3 The phosphorus doping concentration of the second phosphorus-doped polycrystalline silicon mask layer is 8e21cm. -3 The phosphorus doping concentration of the first phosphorus-doped silicon oxide mask layer is 1e20cm. -3 The phosphorus doping concentration of the N-type polycrystalline silicon layer is 5e18cm. -3 .

[0131] Comparative Example 3

[0132] The procedure was carried out in accordance with Example 1, except that the condition T = 10L1 + 2L2 + 920 was not met. Therefore, the thickness L2 of the second polysilicon mask layer was adjusted to 50 nm. The corresponding phosphorus doping concentration of the resulting third PSG mask layer was 6.5e21 cm⁻¹. -3 The phosphorus doping concentration of the second phosphorus-doped polycrystalline silicon mask layer is 2e21cm. -3 The phosphorus doping concentration of the first phosphorus-doped silicon oxide mask layer is 3e20cm. -3 The phosphorus doping concentration of the N-type polycrystalline silicon layer is 2e19cm. -3 .

[0133] Test case

[0134] The back-contact solar cells obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0135] Table 1

[0136]

[0137] The results above show that, compared with the comparative example, the embodiment of the present invention has a higher open-circuit voltage and fill factor, which can completely protect the first semiconductor structure of the back tunneling oxide layer and the N-type polycrystalline silicon layer, and does not require the addition of new process equipment, thus ensuring a higher passivation level and improving the battery conversion efficiency.

[0138] Furthermore, as can be seen from Examples 1 and 2-4, the preferred scheme of the present invention is more conducive to ensuring a higher passivation level and improving battery conversion efficiency.

[0139] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A method for manufacturing a back-contact solar cell with a combined mask layer, characterized in that, Includes the following steps: S1. Provides double-sided polished silicon wafers; S2. A tunneling oxide layer, an intrinsic polysilicon layer, a first silicon oxide mask layer, and a second polysilicon mask layer are sequentially formed on the back side of the silicon wafer. S3. Phosphorus diffusion and high-temperature annealing are performed on the back film layer to form a tunneling oxide layer, an N-type polycrystalline silicon layer, a first phosphorus-doped silicon oxide mask layer, a second phosphorus-doped polycrystalline silicon mask layer, and a third PSG mask layer. During this process, the annealing temperature T (in °C) and the thickness L1 (in nm) of the first silicon oxide mask layer and the thickness L2 (in nm) of the second polycrystalline silicon mask layer satisfy the following relationship: T = 10L1 + 2L2 + 920. The phosphorus doping concentration of the third PSG mask layer was controlled to be 5e21cm. -3 -8e21cm -3 The phosphorus doping concentration of the second phosphorus-doped polycrystalline silicon mask layer is 1e21cm. -3 -3e21cm -3 The phosphorus doping concentration of the first phosphorus-doped silicon oxide mask layer is 5e20cm. -3 -8e20cm -3 ; And / or, the phosphorus doping concentration of the N-type polycrystalline silicon layer is 1e20cm. -3 -5e20cm -3 ; S4. First etching openings are made on each film layer on the back side obtained in S3 to form a second semiconductor opening region arranged at intervals. S5. By texturing and cleaning, the residual tunneling oxide layer and N-type polysilicon layer in the second semiconductor opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the second semiconductor opening area. Then, the third PSG mask layer is removed by cleaning. The texturing solution used in the texturing process contains PSG protective additives. S6. A third semiconductor layer and an anti-reflection layer are formed on the front side of the silicon wafer, while a corresponding wrap-around plating layer is formed on the back side. S7. First, use acid to remove the antireflection layer coating; then use alkaline solution to remove the third semiconductor layer coating, while the second phosphorus-doped polysilicon mask layer is removed; then clean, while the first phosphorus-doped silicon oxide mask layer is removed. S8. Deposit a second semiconductor layer on the back side.

2. The method for manufacturing a back contact solar cell with a combined mask layer according to claim 1, characterized in that, In S3, L1 is 2-3 nm, L2 is 25-35 nm; and / or, T is 990-1020 °C.

3. The method for manufacturing a back contact solar cell with a combined mask layer according to claim 1, characterized in that, The thickness of the N-type polysilicon layer is 100-150 nm, the thickness of the tunneling oxide layer is 1.2-1.8 nm, and / or the thickness of the third PSG mask layer is 15-25 nm.

4. The method for manufacturing a back contact solar cell with a combined mask layer according to claim 1, characterized in that, S3 also satisfies at least one of the following conditions: Condition 1: The conditions for phosphorus diffusion include: process temperature of 810-830℃ and process time of 25-30min; Condition 2: During the phosphorus diffusion process, phosphorus oxychloride, oxygen, and nitrogen are introduced. The oxygen flow rate is 500-1000 sccm, and the flow rate of the mixed gas carrying phosphorus oxychloride is 150-250 sccm. Condition 3: The conditions for high-temperature annealing include: annealing pressure of 300-500 mbar, and / or, high-temperature annealing time of 4-6 min; Condition 4: Oxygen is introduced during the high-temperature annealing process, with an oxygen flow rate of 2000-4000 sccm.

5. The method for manufacturing a back contact solar cell with a combined mask layer according to claim 1, characterized in that, In S2, the process of forming the tunneling oxide layer, the intrinsic polysilicon layer, the first silicon oxide mask layer, and the second polysilicon mask layer includes: in the first stage, oxygen is introduced and then silane is introduced to form the tunneling oxide layer; in the second stage, silane is introduced to form the intrinsic polysilicon layer; in the third stage, oxygen is introduced and then silane is introduced to form the first silicon oxide mask layer; and in the fourth stage, silane is introduced to form the second polysilicon mask layer. The process conditions for each stage satisfy at least one of the following: The conditions for the first stage of process 1 include: oxygen flow rate of 8000-10000 sccm, oxygen supply time of 3-5 min, oxygen saturation pressure of 500-800 mbar, oxygen saturation temperature of 600-610℃, and oxygen saturation time of 15-25 min. The conditions for the second stage of process 2 include: silane flow rate of 300-800 sccm, process pressure of 20-30 Pa, process temperature of 605-615℃, and process time of 20-30 min. The conditions for the third stage of process 3 include: oxygen flow rate of 8000-10000 sccm, oxygen supply time of 3-5 min, oxygen saturation pressure of 500-800 mbar, oxygen saturation temperature of 610-630℃, and oxygen saturation time of 5-10 min. The conditions for the fourth stage of process include: silane flow rate of 100-200 sccm, process pressure of 10-20 Pa, process temperature of 610-630℃, and process time of 4-8 min.

6. The method for manufacturing a back contact solar cell with a combined mask layer according to claim 1, characterized in that, In S5, the mass concentration of the PSG protective additive in the texturing solution is 0.5%-3%, and / or, in S5, the cleaning to remove the third PSG mask layer uses a hydrofluoric acid solution with a mass concentration of 1%-5%.

7. The method for manufacturing a back contact solar cell with a combined mask layer according to claim 1, characterized in that, In S7, the acid solution is a hydrofluoric acid solution with a mass concentration of 5%-10%, and the alkaline solution is a sodium hydroxide solution or potassium hydroxide solution with a mass concentration of 1%-2%. And / or, In S7, the acid cleaning time is 4-6 minutes, and the alkaline cleaning time is 1.5-3 minutes.

8. The method for manufacturing a back contact solar cell with a combined mask layer according to claim 1, characterized in that, The manufacturing method of back contact solar cells also includes at least one of the following methods: In Method 1, S6, the third semiconductor layer includes oxygen-doped amorphous silicon, and the antireflection layer includes silicon nitride. Method 2, in S6, the thickness of the third semiconductor layer is 6-10 nm, and the thickness of the antireflection layer is 80-110 nm; Method 3, S8, the second semiconductor layer includes an intrinsic amorphous silicon layer and a P-type doped silicon layer disposed sequentially; Method 4, the manufacturing method also includes the following steps: S9. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region, and then cleaned. S10. Deposit a conductive film layer on the back side obtained in S9; S11. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench. S12. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

9. A back-contact solar cell, characterized in that, It is manufactured by the back contact solar cell manufacturing method of any one of claims 1-8, which provides a combined mask layer.

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