Silicon optical integrated chip containing silicon nitride waveguide and preparation method thereof
Monolithic integration of silicon nitride devices and silicon photonic active devices was achieved through a low-temperature SiO2-SiO2 bonding process, which solved the impact of high-temperature annealing on silicon photonic active devices and achieved ultra-low loss and high-performance integration with good process compatibility.
Patent Information
- Application Number
- CN202411026708.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-30
- Publication Date
- 2026-02-03
AI Technical Summary
In existing technologies, when integrating silicon nitride waveguides onto silicon photonic active devices, the high-temperature annealing process severely impacts the performance of the silicon photonic active devices, making it difficult to achieve compatible integration of high-performance silicon nitride devices and silicon photonic active devices.
A low-temperature SiO2-SiO2 bonding process is used to fabricate silicon nitride devices and silicon photonic active devices separately and then bond them together. The low-temperature process avoids the impact of high-temperature annealing on silicon photonic active devices. Contact hole etching and metallization processes are then performed to achieve monolithic integration.
It effectively avoids the impact of high-temperature annealing on silicon photonic active devices, and realizes the integration of ultra-low loss silicon nitride and high-performance silicon photonic active devices. The process has low complexity and is compatible with existing silicon photonic integration processes.
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Figure CN121463620A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optoelectronic integration technology, and in particular to a silicon photonic integrated chip containing silicon nitride waveguide and its fabrication method. Background Technology
[0002] Silicon-based optoelectronic integration technology, with its advantages of high integration, low power consumption, and low cost, has become one of the mainstream technologies for future data communication. It is widely used in fields such as artificial intelligence, optical communication, data centers, and supercomputers, and has enormous market application prospects. Silicon nitride (SiN) materials possess low optical loss, wide spectral transparency (400-2350nm), compatibility with CMOS processes, compatibility with high-power optical systems, versatility in device fabrication, and integration potential with other materials, making them widely used in telecommunications, sensing, spectroscopy, imaging, and quantum technology. How to integrate SiN materials onto silicon-based optoelectronic platforms to fully leverage the advantages of both silicon and SiN platforms has become a key research focus in the industry. In existing technologies, achieving ultra-low SiN waveguide loss requires multiple, long-duration high-temperature annealing processes, which severely impacts the performance of silicon active optical devices such as silicon modulators and germanium detectors. Therefore, to simultaneously achieve the integration of high-performance SiN devices and silicon active optical devices, a comprehensive consideration of device performance, process thermal budget, and process complexity is necessary, posing a challenge to the integration process. Summary of the Invention
[0003] The purpose of this invention is to provide a silicon photonic integrated chip containing silicon nitride waveguides and its fabrication method, so that the key processes of silicon nitride devices and silicon photonic active devices do not affect each other, thereby effectively avoiding the serious impact of high-temperature annealing process on silicon photonic active devices when integrating silicon nitride waveguides on silicon photonic active devices in the prior art.
[0004] To address the aforementioned technical problems, this invention provides a silicon photonic integrated chip containing a silicon nitride waveguide and its fabrication method. The technical solution adopted by this invention is as follows:
[0005] This invention provides a method for fabricating a silicon optical integrated chip containing a silicon nitride waveguide, comprising:
[0006] Step 1: Provide a silicon photonics wafer, wherein the silicon photonics wafer sequentially comprises a first substrate, a BOX layer, a silicon-based passive device, an active device, and a first SiO2 coating layer;
[0007] Step 2: Provide a silicon nitride wafer, wherein the silicon nitride wafer sequentially comprises a second substrate, a first thermally oxidized SiO2 layer, a silicon nitride waveguide, and a second SiO2 cladding layer;
[0008] Step 3: Low-temperature bonding of the first SiO2 coating layer of the silicon photonics wafer and the second SiO2 coating layer of the silicon nitride wafer to form a composite wafer;
[0009] Step 4: Perform subsequent processes on the composite wafer to form a silicon photonic integrated chip containing silicon nitride waveguide.
[0010] The silicon-based passive device in step one includes one or more of the following: grating coupler, beam splitter, and polarization controller; the active device includes one or more of the following: silicon optical modulator and silicon-based germanium detector.
[0011] The silicon-based passive device includes a grating coupler, a beam splitter, and a polarization controller. The active device includes a silicon optical modulator and a silicon-based germanium detector. The method for forming the silicon-based passive device and the active device includes: a first step of silicon etching to form a vertical grating structure corresponding to the grating coupler; a second step of silicon etching to form a ridge waveguide corresponding to the silicon optical modulator; and a third step of silicon etching to form strip waveguides corresponding to the beam splitter, the polarization controller, and the silicon-based germanium detector, respectively.
[0012] Ion implantation is performed on the regions requiring doping in the ridge waveguide and the strip waveguide, followed by rapid thermal annealing to activate the implanted ions. The regions in the strip waveguide requiring germanium growth are etched, and a germanium layer is epitaxially grown to fabricate a silicon-based germanium detector. A certain thickness of SiO2 is deposited on the active device to form the first SiO2 cladding layer. The surface of the first SiO2 cladding layer is polished and flattened using CMP technology to form a silicon photonic wafer to be bonded. At this point, the key front-end processes of the silicon photonic active device have been basically completed.
[0013] In step two, the silicon nitride waveguide is formed on the first thermally oxidized SiO2 layer using low-pressure chemical vapor deposition.
[0014] In steps two and three, the first SiO2 coating layer or the second SiO2 coating layer is formed by combining plasma-enhanced chemical vapor deposition with high-density plasma-enhanced chemical vapor deposition. The first SiO2 coating layer or the second SiO2 coating layer is then bonded at low temperature to form a composite wafer, thereby realizing the integration of silicon photonic active devices and silicon nitride devices.
[0015] In step four, the subsequent processing includes removing the second substrate on the composite wafer and thinning the first thermally oxidized SiO2 layer to a required thickness for subsequent contact hole etching and metallization processes.
[0016] In step four, the subsequent processing technology also includes contact hole etching and metallization processes on the composite wafer to achieve the connection between the components on the wafer and the power supply and other components.
[0017] The present invention also provides a silicon photonic integrated chip containing a silicon nitride waveguide, comprising: a first substrate, a deep silicon etched scribe groove on one side of the first substrate, a BOX layer on the first substrate, a silicon-based passive device and an active device on the BOX layer, the silicon-based passive device comprising: a grating coupler, a beam splitter and a polarization controller, the active device comprising: a silicon photonic modulator and a silicon-based germanium detector, a first SiO2 cladding layer on the silicon-based passive device and the active device, a second SiO2 cladding layer on the first SiO2 cladding layer, a silicon nitride waveguide in the second SiO2 cladding layer, a first thermally oxidized SiO2 layer on the second SiO2 cladding layer, and a heater and a metal electrode on the first thermally oxidized SiO2 layer.
[0018] The beneficial effects of this invention are as follows: This invention provides a silicon photonic integrated chip containing a silicon nitride waveguide and its fabrication method. First, the key processes for fabricating the silicon nitride device and the silicon photonic active device are prepared separately. Then, a low-temperature SiO2-SiO2 bonding process is introduced to bond the two wafers. After removing the silicon substrate and thinning the SiO2, contact hole etching and subsequent metallization processes are performed. Through this approach, the key processes of the silicon nitride device and the silicon photonic active device do not interfere with each other, effectively avoiding the severe impact of the high-temperature annealing process on the silicon photonic active device when integrating the silicon nitride waveguide on the silicon photonic active device in the prior art. Simultaneously, it achieves monolithic integration of ultra-low-loss silicon nitride and high-performance silicon photonic active devices. Furthermore, this approach is compatible with existing silicon photonic integration processes and has the advantage of low process complexity. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a flowchart of a method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide according to the present invention;
[0021] Figure 2 and Figure 3 This is a schematic diagram of the silicon photonics wafer of the present invention;
[0022] Figure 4 This is a schematic diagram of the silicon nitride wafer of the present invention;
[0023] Figure 5 This is a schematic diagram of the composite wafer formed by bonding silicon photonics wafer and silicon nitride wafer according to the present invention;
[0024] Figure 6 This is a schematic diagram of the composite wafer of the present invention after substrate removal and SiO2 thinning treatment;
[0025] Figure 7 This is a schematic diagram of the composite wafer of the present invention after contact hole etching and metallization.
[0026] 1. First substrate; 2. BOX layer; 3. Silicon-based passive device; 4. Active device; 5. First SiO2 cladding layer; 6. Second substrate; 7. First thermally oxidized SiO2 layer; 8. Silicon nitride waveguide; 9. Second SiO2 cladding layer; 10. Composite wafer; A. Grating coupler; B. Beam splitter; C. Polarization controller; D. Silicon photonic modulator; E. Silicon-based germanium detector; A1. Vertical grating structure; B1. Strip waveguide; C1. Strip waveguide; D1. Ridge waveguide; E1. Strip waveguide; E2. Germanium layer; 11. Deep silicon etched scribe groove; 12. Heater; 13. Metal electrode; 14. Second thermally oxidized SiO2 layer. Detailed Implementation
[0027] The following description and accompanying drawings fully illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Some portions and features of some embodiments may be included in or replace portions and features of other embodiments.
[0028] Example 1
[0029] like Figure 1 As shown, the present invention provides a method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide, comprising the following steps:
[0030] Step 1, such as Figure 2 and Figure 3 As shown, a silicon photonics wafer is provided, which sequentially includes a first substrate 1, a BOX layer (buried oxide layer) 2, a silicon-based passive device 3, an active device 4, and a first SiO2 coating layer 5. The specific fabrication method includes:
[0031] First, silicon-based passive device 3 and active device 4 structures are fabricated on the SOI wafer, i.e., the top silicon layer is etched to form silicon waveguides, resulting in silicon waveguide structures corresponding to devices such as grating coupler A, beam splitter B, polarization controller C, silicon optical modulator D, and silicon-based germanium detector E. Specifically, the first step of silicon etching forms the vertical grating structure A1 corresponding to grating coupler A; the second step of silicon etching forms the ridge waveguide D1 corresponding to silicon optical modulator D; and the third step of silicon etching forms the strip waveguide B1 corresponding to beam splitter B, the strip waveguide C1 corresponding to polarization controller C, and the strip waveguide E1 corresponding to silicon-based germanium detector E.
[0032] In other embodiments, the silicon-based passive device 3 may be one or more of a grating coupler A, a beam splitter B, and a polarization controller C, and the active device 4 may be one or more of a silicon optical modulator D and a silicon-based germanium detector E.
[0033] Then, ion implantation was performed on the regions requiring doping in the ridge waveguide D1 corresponding to the silicon photonic modulator D and the strip waveguide E1 corresponding to the silicon-based germanium detector E, respectively, to form P-regions and N-regions of different concentrations. Rapid thermal annealing was then performed to activate the implanted ions. Specifically, ion implantation was performed on the silicon photonic modulator D to form P-regions and N-regions with light, medium, and heavy doping concentrations, while ion implantation was performed on the silicon-based germanium detector E to form P-regions and N-regions with medium and heavy doping concentrations. The regions requiring germanium growth were etched into the strip waveguide E1 corresponding to the silicon-based germanium detector E, and a germanium layer E2 was epitaxially generated for fabricating the silicon-based germanium detector E.
[0034] Finally, a first SiO2 coating layer 5, with a thickness of 600–800 nm, is deposited on the active device using a combination of plasma-enhanced chemical vapor deposition (PECVD) and high-density plasma-enhanced chemical vapor deposition (HDPCVD). The surface of the first SiO2 coating layer 5 is then polished and smoothed using CMP (Chemical Mechanical Polishing) to form a silicon photonic wafer ready for bonding. At this point, the key processes for the silicon photonic active device are essentially complete.
[0035] PECVD utilizes low-temperature plasma generated by gas glow discharge to enhance the chemical activity of reactants and promote chemical reactions between gases, thereby forming a new solid film on a substrate at low temperatures. PECVD requires relatively low temperatures, typically between 200 and 400°C.
[0036] CMP (Chemical Motion Process) is a key process for achieving wafer surface planarization in integrated circuit manufacturing. Unlike traditional purely mechanical or purely chemical polishing methods, CMP combines surface chemical action and mechanical grinding techniques to remove different materials at the micron / nano scale from the wafer surface, thereby achieving nanoscale planarization of the wafer surface. This allows the polished wafer surface to meet the requirements of high planarization, low surface roughness, and low defects.
[0037] Step 2, as follows Figure 4 As shown, a silicon nitride wafer is provided, which sequentially includes a second substrate 6, a first thermally oxidized SiO2 layer 7, a silicon nitride waveguide 8, and a second SiO2 cladding layer 9. The specific fabrication method includes:
[0038] First, a first thermally oxidized SiO2 layer 7 and a second thermally oxidized SiO2 layer 14 are formed on the upper and lower surfaces of the second substrate 6 using a thermal oxidation process. The first thermally oxidized SiO2 layer 7 forms the lower cladding layer of the silicon nitride waveguide, avoiding losses caused by the leakage of optical signals in the silicon nitride waveguide into the silicon substrate.
[0039] Then, silicon nitride is deposited on the first thermally oxidized SiO2 layer 7 using low-pressure chemical vapor deposition (LPCVD) at a deposition temperature of 600–800℃ and a deposition thickness of 300–600 nm. Unwanted portions of the silicon nitride layer are removed using dry etching to form a silicon nitride waveguide 8 with a specific structure or pattern. The silicon nitride waveguide 8 is then subjected to high-temperature annealing to improve the optical properties of the silicon nitride layer.
[0040] Finally, a second SiO2 cladding layer 9, with a thickness of 600–800 nm, is deposited on the silicon nitride waveguide 8 using a combination of plasma-enhanced chemical vapor deposition (PECVD) and high-density plasma-enhanced chemical vapor deposition (HDPCVD). This silicon dioxide layer is used for bonding with the first SiO2 cladding layer 5. A second annealing and chemical mechanical polishing process is then performed.
[0041] Step 3, as follows Figure 5 As shown, the first SiO2 coating layer 5 of the silicon photonics wafer and the second SiO2 coating layer 9 of the silicon nitride wafer are bonded at low temperature to form a composite wafer 10.
[0042] Step 4: As shown in the figure, the composite wafer 10 undergoes silicon substrate removal and SiO2 thinning processes to complete contact hole etching and subsequent metallization processes, forming a silicon photonic integrated chip containing a silicon nitride waveguide. The specific process includes:
[0043] First, the second thermally oxidized SiO2 layer 14 on the second substrate 6 is removed by chemical etching using hydrofluoric acid solution. Then, the second substrate 6 is thinned to a remaining silicon thickness of 100-200 μm using a thinning process. Next, the remaining silicon substrate is removed by a dry etching process. Then, the first thermally oxidized SiO2 layer 7 is thinned to ensure that the thickness of the first thermally oxidized SiO2 layer 7 meets the requirements of subsequent processes.
[0044] After SiO2 thinning, contact hole etching and metallization are performed on composite wafer 10. Contact holes are key channels connecting different material layers, used to allow current to flow. The etching process typically uses photolithography to precisely form contact holes at specific locations, followed by dry etching to etch the contact holes.
[0045] Finally, the composite wafer 10 after the contact hole etching is completed is metallized by depositing a metal layer on the contact hole and wafer surface and forming a metal electrode 13 by etching the metal to form a circuit connection. The selection of multilayer metallization process and parameter settings depend on different device designs and process requirements.
[0046] The deep silicon etched dicing groove 11 is formed by photolithography, dry etching of the oxide layer, and dry etching of the silicon substrate.
[0047] The heater 12 is formed by depositing a layer of metallic TiN and then by photolithography and dry etching.
[0048] The method for removing the second substrate 6 is not limited to chemical etching, but can also be mechanical polishing. The solution used for chemical etching is KOH or TMAH solution.
[0049] The thinning process of the SiO2 layer is not limited to chemical etching, but can also be physical polishing, plasma etching, etc.
[0050] The first substrate 1 and / or the second substrate 6 are silicon substrates.
[0051] Example 2
[0052] The present invention also provides a silicon photonic integrated chip containing a silicon nitride waveguide, comprising: a first substrate 1, a deep silicon etched scribe groove 11 on one side of the first substrate 1, a BOX layer 2 on the first substrate, a silicon-based passive device 3 and an active device 4 on the BOX layer 2, the silicon-based passive device 3 comprising: a grating coupler A, a beam splitter B and a polarization controller C, the active device 4 comprising: a silicon photonic modulator D and a silicon-based germanium detector E, a first SiO2 cladding layer 5 on the silicon-based passive device 3 and the active device 4, a second SiO2 cladding layer 9 on the first SiO2 cladding layer 5, a silicon nitride waveguide 8 in the second SiO2 cladding layer 9, a first thermally oxidized SiO2 layer 7 on the second SiO2 cladding layer 9, a heater 12 and a metal electrode 13 on the first thermally oxidized SiO2 layer 7.
[0053] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide, characterized in that, include: Step 1: Provide a silicon photonics wafer, the silicon photonics wafer including a first substrate (1), a BOX layer (2), a silicon-based passive device (3), an active device (4), and a first SiO2 coating layer (5); Step 2: Provide a silicon nitride wafer, wherein the silicon nitride wafer comprises, in sequence, a second substrate (6), a first thermally oxidized SiO2 layer (7), a silicon nitride waveguide (8), and a second SiO2 cladding layer (9); Step 3: Low-temperature bonding of the first SiO2 coating layer (5) of the silicon photonics wafer and the second SiO2 coating layer (9) of the silicon nitride wafer to form a composite wafer (10); Step 4: Perform subsequent processes on the composite wafer to form a silicon photonic integrated chip containing silicon nitride waveguide.
2. The method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide according to claim 1, characterized in that, In step one, the silicon-based passive device (3) includes one or more of the following: grating coupler (A), beam splitter (B), and polarization controller (C).
3. The method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide according to claim 1, characterized in that, In step one, the active device (4) includes one or more of the following: a silicon photonic modulator (D) and a silicon-based germanium detector (E).
4. A method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide according to claim 2 or 3, characterized in that, The silicon-based passive device (3) includes: a grating coupler (A), a beam splitter (B), and a polarization controller (C). The active device (4) includes: a silicon optical modulator (D) and a silicon-based germanium detector (E). The method for forming the silicon-based passive device (3) and the active device (4) includes: a first step of silicon etching to form a vertical grating structure (A1) corresponding to the grating coupler (A); a second step of silicon etching to form a ridge waveguide (D1) corresponding to the silicon optical modulator (D); and a third step of silicon etching to form strip waveguides (B1), (C1), and (E1) corresponding to the beam splitter (B), the polarization controller (C), and the silicon-based germanium detector (E), respectively.
5. The method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide according to claim 4, characterized in that, Ion implantation is performed on the regions in the ridge waveguide (D1) and the strip waveguide (E1) that need to be doped, and rapid thermal annealing is performed to activate the implanted ions. The regions in the strip waveguide (E1) that need to grow germanium are etched to generate a germanium layer (E2). A certain thickness of SiO2 is deposited to form the first SiO2 cladding layer (5). The surface of the first SiO2 cladding layer (5) is polished and smoothed using CMP process.
6. The method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide according to claim 1, characterized in that, In step two, the silicon nitride waveguide (8) is formed on the first thermally oxidized SiO2 layer (7) using low-pressure chemical vapor deposition.
7. The method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide according to claim 1, characterized in that, In steps two and three, the first SiO2 coating layer (5) or the second SiO2 coating layer (9) is formed by combining plasma-enhanced chemical vapor deposition with high-density plasma-enhanced chemical vapor deposition.
8. The method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide according to claim 1, characterized in that, In step four, the subsequent processing includes removing the second substrate (6) on the composite wafer (10) and thinning the first thermally oxidized SiO2 layer (7).
9. The method for fabricating a silicon photonic integrated chip containing a silicon nitride waveguide according to claim 8, characterized in that, In step four, the subsequent processing technology also includes etching the contact holes and metallizing the composite wafer (10).
10. A silicon photonic integrated chip containing a silicon nitride waveguide, characterized in that, The silicon-optical integrated chip with a silicon nitride waveguide, fabricated using any one of claims 1-9, comprises: a first substrate (1), a deep silicon etched scribe groove (11) on one side of the first substrate (1), a BOX layer (2) on the first substrate, a silicon-based passive device (3) and an active device (4) on the BOX layer (2), wherein the silicon-based passive device (3) comprises: a grating coupler (A), a beam splitter (B), and a polarization controller (C), and the active device (4) comprises: silicon... Optical modulator (D), silicon-based germanium detector (E), first SiO2 cladding layer (5) on the silicon-based passive device (3) and the active device (4), second SiO2 cladding layer (9) on the first SiO2 cladding layer (5), silicon nitride waveguide (8) in the second SiO2 cladding layer (9), first thermally oxidized SiO2 layer (7) on the second SiO2 cladding layer (9), heater (12) and metal electrode (13) on the first thermally oxidized SiO2 layer (7).