Epitaxial silicon wafer and preparation method thereof
By monitoring the temperature difference between the back and front sides of the epitaxial silicon wafer and controlling it to -5℃≤△W≤5℃ during the cooling stage, the problem of high edge stress in epitaxial silicon wafers was solved, improving temperature uniformity and product quality, and extending service life.
Patent Information
- Application Number
- CN202511372934.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-24
- Publication Date
- 2026-02-06
Smart Images
Figure CN121472986A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for preparing an epitaxial silicon wafer and the epitaxial silicon wafer obtained by the method. Background Technology
[0002] The semiconductor industry is developing rapidly, with chips becoming increasingly integrated and smaller in size. Consequently, the requirements for the quality and performance of epitaxial silicon wafers are rising. Epitaxial silicon wafers are the foundation of chip manufacturing, and their quality directly affects the performance and reliability of the final product. During wafer manufacturing and subsequent chip processing, edge stress issues on epitaxial silicon wafers are becoming increasingly prominent, becoming a significant factor influencing the development of the semiconductor industry.
[0003] High edge stress in epitaxial silicon wafers poses numerous risks. From a crystal structure perspective, stress causes silicon lattice distortion, generating defects such as dislocations. These defects become carrier scattering centers, significantly impacting the electrical performance of semiconductor devices, slowing transistor switching speeds, and increasing resistance. The quality of the epitaxial layer is also affected; stress leads to poor thickness uniformity, irregular atomic arrangement, and defects such as stacking faults and twins, reducing the crystal quality of the epitaxial layer and consequently affecting device reliability. In chip manufacturing, stress-concentrated wafer edges are susceptible to cracking or even breakage during photolithography, etching, and packaging processes, causing chip failure. This also results in inconsistent device performance between the wafer edge and center regions, increasing process control difficulty and reducing product yield and production efficiency. Furthermore, during long-term product use, stress-induced stress migration and material aging seriously threaten product reliability and stability, shortening product lifespan. Therefore, the edge stress problem of epitaxial silicon wafers has become a key challenge that needs to be addressed for the further development of the semiconductor industry. Summary of the Invention
[0004] To address the problem of high edge stress in epitaxial silicon wafers, this invention provides a method for fabricating epitaxial silicon wafers and the epitaxial silicon wafers obtained by this method. The method for fabricating epitaxial silicon wafers of this invention can reduce the edge stress of the fabricated epitaxial silicon wafers, improve the yield of epitaxial silicon wafers, and extend the service life of epitaxial silicon wafers.
[0005] To achieve the above objectives, a first aspect of the present invention provides a method for preparing an epitaxial silicon wafer, comprising: S1: The silicon wafer is heat-treated in a reaction chamber at a temperature of W1 to obtain a silicon wafer epitaxial substrate; S2: The silicon wafer epitaxial substrate is brought into contact with a film-forming gas to grow an epitaxial layer on the surface of the silicon wafer epitaxial substrate, thereby obtaining an epitaxial silicon wafer; S3: Monitor temperature difference: Cool the epitaxial silicon wafer to reduce the temperature of the reaction chamber to the target cooling temperature W2, monitor the temperature difference ΔW between the back side temperature and the front side temperature of the epitaxial silicon wafer, and remove the epitaxial silicon wafer from the reaction chamber when -5℃≤ΔW≤5℃. Among them, W1 is 1100℃-1200℃, and W2 is 750℃-900℃.
[0006] A second aspect of the present invention provides an epitaxial silicon wafer, which is prepared by the method described in the first aspect of the present invention.
[0007] By employing the above technical solution, the present invention has at least the following advantages compared with the prior art: Research has revealed that the primary reason for the high edge stress in epitaxial silicon wafers is the cooling stage during wafer fabrication. This stage involves purging the front side of the wafer with a purge gas, while the back side contacts the substrate. The thermal conductivity of the purge gas differs from that of the substrate, resulting in a significant temperature difference between the front and back sides. This leads to poor temperature uniformity and consequently, high edge stress, making the wafer prone to warping and affecting its quality. In conventional epitaxial silicon wafer fabrication methods, the wafer is removed from the reaction chamber once the target cooling temperature is reached. At this point, the temperature difference between the front and back sides is also significant, resulting in poor temperature uniformity.
[0008] To improve the temperature uniformity of epitaxial silicon wafers, in the epitaxial silicon wafer fabrication method of the present invention, the temperature difference ΔW between the back side and the front side of the epitaxial silicon wafer during the cooling process is monitored. When the temperature of the reaction chamber reaches the target temperature, the epitaxial silicon wafer is left to stand for a certain period of time so that the temperature difference ΔW between the back side and the front side of the epitaxial silicon wafer satisfies -5℃≤ΔW≤5℃. At this time, the temperature difference between the back side and the front side of the epitaxial silicon wafer is small, the temperature uniformity of the epitaxial silicon wafer is good, and the edge stress of the epitaxial silicon wafer is small, which meets the timing for removing the epitaxial silicon wafer from the reaction chamber. Removing the epitaxial silicon wafer from the reaction chamber at this time can improve the temperature uniformity of the epitaxial silicon wafer, reduce the edge stress of the epitaxial silicon wafer, reduce the edge warping of the epitaxial silicon wafer, improve the quality of the epitaxial silicon wafer, and extend the service life of the epitaxial silicon wafer.
[0009] Other features and advantages of the present invention will be described in detail in the following detailed description section.
[0010] The endpoints and any values of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges or values. For numerical ranges, the endpoint values of the various ranges, the endpoint values of the various ranges and individual point values, and individual point values can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Attached Figure Description
[0011] Figure 1 The diagram shows the location of the edge stress test. Detailed Implementation
[0012] The following provides a detailed description of specific embodiments of the present invention. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the invention. Unless otherwise specified herein, data ranges include endpoints.
[0013] It should be noted that the numerical designations such as "first" and "second" in this disclosure are only used to distinguish different substances or methods of use, and do not represent a difference in order.
[0014] The first aspect of this invention provides a method for preparing an epitaxial silicon wafer, comprising: S1: The silicon wafer is heat-treated in a reaction chamber at a temperature of W1 to obtain a silicon wafer epitaxial substrate; S2: The silicon wafer epitaxial substrate is brought into contact with a film-forming gas to grow an epitaxial layer on the surface of the silicon wafer epitaxial substrate, thereby obtaining an epitaxial silicon wafer; S3: Monitor temperature difference: Perform a cooling process on the epitaxial silicon wafer to reduce the temperature of the reaction chamber to the target cooling temperature W2, and monitor the temperature difference ΔW between the back side temperature and the front side temperature of the epitaxial silicon wafer. When -5℃≤ΔW≤5℃ (e.g., 5℃, 4.5℃, 4℃, 3.5℃, 3℃, 2.5℃, 2℃, 1.5℃, 1℃, 0.5℃, 0.1℃, 0℃, -0.1℃, -0.5℃, -1℃, -1.5℃, -2℃, -2.5℃, -3℃, -3.5℃, -4℃, -4.5℃ or -5℃), remove the epitaxial silicon wafer from the reaction chamber. Wherein, W1 is 1100℃-1200℃ (e.g., 1100℃, 1110℃, 1120℃, 1130℃, 1140℃, 1150℃, 1160℃, 1170℃, 1180℃, 1190℃ or 1200℃), and W2 is 750℃-900℃ (e.g., 750℃, 780℃, 800℃, 830℃, 850℃, 880℃ or 900℃).
[0015] Research has found that during the fabrication of epitaxial silicon wafers, both the heat treatment and cooling stages affect the edge stress of the silicon wafers. However, after heat treatment, the edge stress generated by the heat treatment is released during the film formation stage, i.e., the growth of the epitaxial layer. Therefore, the impact of heat treatment on the edge stress of epitaxial silicon wafers is relatively small. The main reason affecting the edge stress of epitaxial silicon wafers is the poor temperature uniformity of the epitaxial silicon wafers during the cooling stage.
[0016] To improve the temperature uniformity of epitaxial silicon wafers, this invention monitors the temperature difference ΔW between the back side and front side of the epitaxial silicon wafer during the cooling process. This controls the timing of removing the epitaxial silicon wafer from the reaction chamber. When the temperature of the reaction chamber drops to the target temperature W2, the epitaxial silicon wafer is not immediately removed from the reaction chamber. Instead, it is left to stand for a certain period of time, extending its time in the reaction chamber, thereby reducing the temperature difference between the back side and front side of the epitaxial silicon wafer. The epitaxial silicon wafer is then removed from the reaction chamber when -5℃≤ΔW≤5℃. The above method, by extending the time the epitaxial silicon wafer spends in the reaction chamber and reducing the temperature difference between the back and front sides of the epitaxial silicon wafer, can effectively improve the temperature uniformity of the epitaxial silicon wafer, reduce warping deformation caused by the temperature difference between the back and front sides, reduce edge defects, reduce edge stress, improve the quality of the epitaxial silicon wafer, and extend its service life.
[0017] Furthermore, even in conventional fabrication methods, there is a time deviation in removing the epitaxial silicon wafer from the reaction chamber. This time deviation is insufficient to ensure that the temperature difference between the back side and the front side of the epitaxial silicon wafer satisfies -5℃ ≤ ΔW ≤ 5℃. However, to improve the temperature uniformity of the epitaxial silicon wafer, this invention specifically controls the timing of removing the epitaxial silicon wafer from the reaction chamber. It is understood that during the fabrication of the epitaxial silicon wafer, ΔW can be preset to a certain value within the range of -5℃ to 5℃. The epitaxial silicon wafer is then removed from the reaction chamber only when ΔW reaches this preset value.
[0018] In this invention, the heat treatment is a front-side purging process for the silicon wafer. The cooling process is a front-side purging process for the epitaxial silicon wafer. In the reaction chamber, the silicon wafer is located on a substrate. The back side of the epitaxial silicon wafer refers to the side that contacts the substrate in the reaction chamber. The front side of the epitaxial silicon wafer refers to the side opposite the back side.
[0019] In this invention, by controlling the cooling stage during the fabrication of epitaxial silicon wafers, the temperature difference between the front and back sides of the epitaxial silicon wafer can be reduced compared to existing technologies, thereby reducing edge stress, improving wafer quality, and extending wafer lifespan. To further enhance the effect, one or more of the technical features can be further optimized.
[0020] In one example, -3℃ ≤ ΔW ≤ 3℃. Controlling ΔW within this range can further improve the temperature uniformity of the epitaxial silicon wafer and further reduce the edge stress of the epitaxial silicon wafer while maintaining high efficiency.
[0021] In one example, the atmosphere of the heat treatment includes hydrogen, and the duration of the heat treatment is 10s-60s (e.g., 10s, 15s, 20s, 25s, 30s, 35s, 40s, 45s, 50s, 55s or 60s).
[0022] In one example, the film-forming gas includes a silicon source gas and a dopant gas. The silicon source gas includes one or more of dichlorosilane, trichlorosilane, silane, and silicon chloride. The dopant gas includes diborane and / or phosphine (PH3). The volume ratio of the silicon source gas to the dopant gas is (15-100):1 (e.g., 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, 45:1, 50:1, 55:1, 60:1, 65:1, 70:1, 75:1, 80:1, 85:1, 90:1, or 100:1).
[0023] In one example, the volume ratio of the silicon source gas to the dopant gas is (30-80):1.
[0024] In one example, the starting time t1 is the time point when W2 is reached, and the ending time t2 is the time point when the epitaxial silicon wafer is removed from the reaction chamber. The difference between the ending time t2 and the starting time t1 is Δt ≥ 5s (e.g., 5s, 8s, 10s, 13s, 15s, 18s, 20s, 23s, 25s, 28s, or 30s).
[0025] In one instance, Δt ≥ 10s.
[0026] In one example, the temperature W1 of the reaction chamber is directly reduced to a target cooling temperature W2 at a first cooling rate of 5°C / s to 15°C / s (e.g., 5°C / s, 5.5°C / s, 6°C / s, 6.5°C / s, 7°C / s, 7.5°C / s, 7.8°C / s, 8°C / s, 8.3°C / s, 8.5°C / s, 8.8°C / s, 9°C / s, 9.3°C / s, 9.5°C / s, 9.8°C / s, 10°C / s, 10.5°C / s, 11°C / s, 11.5°C / s, 12°C / s, 12.5°C / s, 13°C / s, 13.5°C / s, 14°C / s, 14.5°C / s, or 15°C / s). Controlling the first cooling rate within the aforementioned range can influence the cooling time, optimize equipment capacity, and ensure that the quality of epitaxial silicon wafers remains high while maintaining a high level of capacity.
[0027] In one instance, the first cooling rate is 7.5°C / s to 10°C / s.
[0028] According to one specific embodiment, the temperature W1 of the reaction chamber is directly reduced to a target cooling temperature W2 at a first cooling rate of 5℃ / s-15℃ / s. The temperature difference ΔW between the back side temperature and the front side temperature of the epitaxial silicon wafer is monitored. When -5℃≤ΔW≤5℃, the epitaxial silicon wafer is removed from the reaction chamber. The time point when W2 is reached is taken as the start time t1, and the time point when the epitaxial silicon wafer is removed from the reaction chamber is taken as the end time t2. The end time t2 is related to the start time. t1 The difference △t≥5s.
[0029] According to a specific implementation, the temperature W1 of the reaction chamber is directly reduced to a target cooling temperature W2 at a first cooling rate of 7.5℃ / s-10℃ / s. The difference ΔW between the back side temperature and the front side temperature of the epitaxial silicon wafer is monitored. When -3℃≤ΔW≤3℃, the epitaxial silicon wafer is removed from the reaction chamber. The time point when W2 is reached is taken as the start time t1, and the time point when the epitaxial silicon wafer is removed from the reaction chamber is taken as the end time t2. The difference Δt between the end time t2 and the start time t1 is ≥10s.
[0030] In one example, the cooling process includes: experiencing n intermediate transition temperatures T during the process of reducing W1 to W2. n The temperature remains at each intermediate transition temperature until ΔW ≤ 5℃, where n is a natural number not exceeding 10 (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10), and T n-1 >T n Where W1 can be equivalent to T0, and W2 can be equivalent to T.n+1 W1(T0) > T n-1 >T n >W2(T n+1 ).
[0031] To further improve the temperature uniformity of epitaxial silicon wafers, the process of reducing W1 to W2 is set to different temperature gradients, such as including experiencing n intermediate transition temperatures T. n This reduces the temperature range, improves the temperature uniformity of epitaxial silicon wafers, reduces edge stress on epitaxial silicon wafers, and shortens the time required for epitaxial silicon wafers to meet the temperature requirement of -5℃≤△W≤5℃. As a result, it can improve the quality of epitaxial silicon wafers while increasing production capacity.
[0032] It is understandable that during the cooling process, the temperature of the reaction chamber gradually decreases, therefore T n-1 >T n This means, for example, when n is 2, T1 > T2; when n is 3, T1 > T2 > T3.
[0033] In one instance, T n-1 -T n >10℃ (e.g., 11℃, 30℃, 50℃, 80℃, 100℃, 130℃, 150℃, 180℃, 200℃, 230℃, 250℃, 280℃ or 300℃).
[0034] In one example, when n=1, the intermediate transition temperature is the first transition temperature T1, where W1>T1>W2; The temperature of W1 is reduced to T1 at a first cooling rate of 7.5℃ / s-10℃ / s. The temperature of the reaction chamber is maintained at T1 for 15s≤Δa≤20s. ΔW is monitored. When -5℃≤ΔW≤5℃, the temperature of the reaction chamber is reduced from T1 to W2 at a second cooling rate of 7.5℃ / s-10℃ / s. ΔW is monitored. When -5℃≤ΔW≤5℃, the epitaxial silicon wafer is removed from the reaction chamber. The starting time t1 is the time when W2 is reached, and the ending time t2 is the time when the epitaxial silicon wafer is removed from the reaction chamber. The difference between the ending time t2 and the starting time t1 is 15s≤Δt≤20s.
[0035] During the process of the temperature in the reaction chamber decreasing from W1 to W2, an intermediate transition temperature is set, which can further improve the temperature uniformity of the prepared epitaxial silicon wafer, while also reducing the cooling span and shortening the time for ΔW to satisfy -5℃≤ΔW≤5℃. This can further improve the quality of the epitaxial silicon wafer and further increase production capacity.
[0036] In one instance, when n=1, [(W1+W2) / 2]-25≤T1≤[(W1+W2) / 2]+25.
[0037] In one example, when n=2, the intermediate transition temperature includes a first transition temperature T1 and a second transition temperature T2, where W1>T1>T2>W2; The temperature of W1 is reduced to T1 at a first cooling rate of 7.5℃ / s-10℃ / s. The temperature of the reaction chamber is maintained at T1 for 5s ≤ Δa1 ≤ 10s, and ΔW is monitored. When -5℃ ≤ ΔW ≤ 5℃, the temperature of the reaction chamber is reduced from T1 to T2 at a second cooling rate of 7.5℃ / s-10℃ / s. The temperature of the reaction chamber is maintained at T2 for 5s ≤ Δa2 ≤ 10s, and ΔW is monitored. When -5℃ ≤ ΔW ≤ 5℃, the temperature of the reaction chamber is reduced from T2 to W2 at a third cooling rate of 7.5℃ / s-10℃ / s, and ΔW is monitored. When -5℃ ≤ ΔW ≤ 5℃, the epitaxial silicon wafer is removed from the reaction chamber for 5s ≤ Δt ≤ 10s.
[0038] During the process of the temperature in the reaction chamber decreasing from W1 to W2, two intermediate transition temperatures are set, which can further improve the temperature uniformity of the prepared epitaxial silicon wafer, while also reducing the cooling span and shortening the time for ΔW to satisfy -5℃≤ΔW≤5℃. This can further improve the quality of the epitaxial silicon wafer and further increase production capacity.
[0039] In one instance, when n=2, [(W1-W2)×2 / 3+W2]-25≤T1≤[(W1-W2)×2 / 3+W2]+25, [(W1-W2) / 3+W2]-25≤T2≤[(W1-W2) / 3+W2]+25.
[0040] A second aspect of the present invention provides an epitaxial silicon wafer, which is prepared by the method described in the first aspect of the present invention.
[0041] In one instance, the edge stress of the epitaxial silicon wafer is ≤5% (e.g., 5%, 4.5%, 4%, 3.5%, 3%, 2.5%, 2%, 1.5%, 1%, 0.5%, 0.1%, 0.05%, or 0.01%).
[0042] In this invention, such as Figure 1As shown, the edge stress of the epitaxial silicon wafer is tested in a region where the distance L from the edge line of the epitaxial silicon wafer is 0-30 mm (e.g., 5 mm, 10 mm, 15 mm, 20 mm, 25 mm, or 30 mm). For example, if the distance L from the edge line 11 in the epitaxial silicon wafer 1 is circle line 12, the test area for the edge stress of the epitaxial silicon wafer is the region between the edge line 11 and circle line 12. Specifically, when L is 20 mm, it means that the edge stress is tested in a region of 0-20 mm from the edge of the epitaxial silicon wafer.
[0043] In one example, the thickness of the epitaxial layer on the epitaxial silicon wafer is 2μm-6μm (e.g., 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm or 6μm).
[0044] The epitaxial silicon wafers prepared by the method described in the first aspect of the present invention have lower edge stress and higher edge stress uniformity, resulting in better quality and longer service life.
[0045] The present invention will be described in detail below through embodiments. The embodiments described herein are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0046] The following examples illustrate the method for preparing epitaxial silicon wafers according to the present invention and the epitaxial silicon wafers prepared by the method.
[0047] Example 1 S1: A silicon wafer is heat-treated in a reaction chamber at a temperature of W1 (W1 is 1100℃) to obtain a silicon wafer epitaxial substrate; the heat treatment atmosphere includes hydrogen, and the time is 40s; S2: The silicon wafer epitaxial substrate is brought into contact with a film-forming gas to grow an epitaxial layer on the surface of the silicon wafer epitaxial substrate, thereby obtaining an epitaxial silicon wafer; the film-forming gas includes a silicon source gas and a doping gas, the silicon source gas is trichlorosilane SiHCl3, and the doping gas is diborane B2H6; the volume ratio of the silicon source gas to the volume of the doping gas is 40:1; S3: Monitor temperature difference: Perform a cooling process on the epitaxial silicon wafer. The cooling process includes: during the process of reducing W1 to the target cooling temperature W2 (W2 is 850°C), it goes through two intermediate transition temperatures, namely the first transition temperature T1 (T1 is 1050°C) and the second transition temperature T2 (T2 is 950°C), where W1 > T1 > T2 > W2. The temperature of W1 is reduced to T1 at a first cooling rate of 8.5°C / s, and the temperature of the reaction chamber is maintained at T1 for a time Δa1 of 10s. ΔW is monitored. When ΔW reaches 2.4°C, the temperature of the reaction chamber is reduced from T1 to T2 at a second cooling rate of 8.5°C / s, and the temperature of the reaction chamber is maintained at T2 for a time Δa2 of 10s. ΔW is monitored. When ΔW reaches 2.9°C, the temperature of the reaction chamber is reduced from T2 to W2 at a third cooling rate of 8.5°C / s, and ΔW is monitored. When ΔW reaches 2.6°C, the epitaxial silicon wafer is removed from the reaction chamber for a time Δt of 10s.
[0048] Example 2 S1: A silicon wafer is heat-treated in a reaction chamber at a temperature of W1 (W1 is 1100℃) to obtain a silicon wafer epitaxial substrate; the heat treatment atmosphere includes hydrogen, and the time is 40s; S2: The silicon wafer epitaxial substrate is brought into contact with a film-forming gas to grow an epitaxial layer on the surface of the silicon wafer epitaxial substrate, thereby obtaining an epitaxial silicon wafer; the film-forming gas includes a silicon source gas and a doping gas, the silicon source gas is trichlorosilane SiHCl3, and the doping gas is diborane B2H6; the volume ratio of the silicon source gas to the volume of the doping gas is 40:1; S3: Monitor temperature difference: Perform a cooling process on the epitaxial silicon wafer, the cooling process includes: during the process of reducing W1 to the target cooling temperature W2 (W2 is 850℃), it goes through an intermediate transition temperature T1 (T1 is 1000℃), W1>T1>W2; The temperature of W1 is reduced to T1 at a first cooling rate of 8.5°C / s. ΔW is monitored. When the temperature of the reaction chamber is maintained at T1 for Δa for 15s, ΔW is 3.4°C. The temperature of the reaction chamber is then reduced from T1 to W2 at a second cooling rate of 8.5°C / s. ΔW is monitored. When ΔW is 3.2°C, the epitaxial silicon wafer is removed from the reaction chamber. The starting time t1 is the time when W2 is reached, and the ending time t2 is the time when the epitaxial silicon wafer is removed from the reaction chamber. The difference between the ending time t2 and the starting time t1 is Δt, which is 15s.
[0049] Example 3 S1: A silicon wafer is heat-treated in a reaction chamber at a temperature of W1 (W1 is 1100℃) to obtain a silicon wafer epitaxial substrate; the heat treatment atmosphere includes hydrogen, and the time is 40s; S2: The silicon wafer epitaxial substrate is brought into contact with a film-forming gas to grow an epitaxial layer on the surface of the silicon wafer epitaxial substrate, thereby obtaining an epitaxial silicon wafer; the film-forming gas includes a silicon source gas and a doping gas, the silicon source gas is trichlorosilane SiHCl3, and the doping gas is diborane B2H6; the volume ratio of the silicon source gas to the volume of the doping gas is 40:1; S3: Monitor temperature difference: Directly reduce the temperature W1 of the reaction chamber to the target cooling temperature W2 (W2 is 850℃) at a first cooling rate of 8.5℃ / s. Monitor the temperature difference ΔW between the back side temperature and the front side temperature of the epitaxial silicon wafer. When ΔW is 4.7℃, remove the epitaxial silicon wafer from the reaction chamber. The time point when W2 is reached is taken as the start time t1, and the time point when the epitaxial silicon wafer is removed from the reaction chamber is taken as the end time t2. The difference Δt between the end time t2 and the start time t1 is 20s.
[0050] Example 4 group This set of examples is used to verify the effects of changing Δt and / or Δa1 and / or Δa2.
[0051] Example 4a The procedure was carried out in accordance with Example 1, except that Δt was 5s.
[0052] Example 4b The process was carried out in accordance with Example 1, except that Δt was 15s. Compared with Example 1, the production efficiency of a single epitaxial silicon wafer was reduced by 1%-2%.
[0053] Example 4c The procedure was carried out in accordance with Example 1, except that △a1 was 5s.
[0054] Example 4d The process was carried out in accordance with Example 1, except that Δa1 was 15s. Compared with Example 1, the production efficiency of a single epitaxial silicon wafer was reduced by 1%-2%.
[0055] Example 4e The procedure was carried out in accordance with Example 1, except that △a2 was 5s.
[0056] Example 4f The process was carried out in accordance with Example 1, except that Δa2 was 15s. Compared with Example 1, the production efficiency of a single epitaxial silicon wafer was reduced by 1%-2%.
[0057] Example 5 group This set of examples is used to verify the effects of changes in the cooling rate.
[0058] Example 5a The process was carried out in accordance with Example 1, except that the first cooling rate was 5°C / s and the second cooling rate was 5°C / s. Compared with Example 1, the production efficiency of a single epitaxial silicon wafer was reduced by 1%-2%.
[0059] Example 5b The same procedure was followed as in Example 1, except that the first cooling rate was 15°C / s and the second cooling rate was 15°C / s.
[0060] Example 5c The process was carried out in accordance with Example 1, except that the first cooling rate was 4°C / s and the second cooling rate was 5°C / s. Compared with Example 1, the production efficiency of a single epitaxial silicon wafer was reduced by 1%-2%.
[0061] Example 5d The same procedure was followed as in Example 1, except that the first cooling rate was 16°C / s and the second cooling rate was 15°C / s.
[0062] Comparative Example 1 S1: A silicon wafer is heat-treated in a reaction chamber at a temperature of W1 (W1 is 1100℃) to obtain a silicon wafer epitaxial substrate; the heat treatment atmosphere includes hydrogen, and the time is 40s; S2: The silicon wafer epitaxial substrate is brought into contact with a film-forming gas to grow an epitaxial layer on the surface of the silicon wafer epitaxial substrate, thereby obtaining an epitaxial silicon wafer; the film-forming gas includes a silicon source gas and a doping gas, the silicon source gas is trichlorosilane, and the doping gas is diborane; the volume ratio of the silicon source gas to the volume of the doping gas is 40:1. S3: Monitor temperature difference: Directly reduce the temperature W1 of the reaction chamber to the target cooling temperature W2 (W2 is 850°C) at a first cooling rate of 8.5°C / s. When the temperature of the reaction chamber drops to the target cooling temperature W2 (W2 is 850°C), remove the epitaxial silicon wafer from the reaction chamber.
[0063] Test case The epitaxial silicon wafers prepared in the examples and comparative examples were subjected to the following tests: 1. Edge stress testing The test area L is 20mm, meaning the edge stress is tested in the 0-20mm region along the edge of the epitaxial silicon wafer. The edge stress test results are characterized using Bad Fraction Analysis, where a defect is defined as an area where the deformation exceeds 40% of the specification limit (DU). DU is a unit of deflection; 40DU indicates that an object undergoes 40 units of deformation under stress, and 1DU = 10... -6Each embodiment and comparative example tested three samples, and the test results for the three edge stresses were obtained respectively.
[0064] The results are recorded in Table 1.
[0065] Table 1 As can be seen from Table 1, by comparing the comparative examples and the embodiments, the edge stress of the epitaxial silicon wafers prepared in the embodiments is significantly reduced. This indicates that by controlling the cooling stage and the temperature difference between the front and back sides of the epitaxial silicon wafer during the preparation of the epitaxial silicon wafer, the edge stress of the epitaxial silicon wafer is reduced, the quality of the epitaxial silicon wafer is improved, and the service life of the epitaxial silicon wafer is extended.
[0066] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.
Claims
1. A method of producing an epitaxial silicon wafer, characterized by, The method comprises the following steps: S1: performing heat treatment on a silicon wafer in a reaction chamber at a temperature of W1 to obtain a silicon wafer epitaxial substrate; S2: contacting the silicon wafer epitaxial substrate with a film-forming gas to grow an epitaxial layer on the surface of the silicon wafer epitaxial substrate, thereby obtaining an epitaxial silicon wafer; S3: monitoring the temperature difference: performing a cooling treatment on the epitaxial silicon wafer to reduce the temperature of the reaction chamber to a target cooling temperature W2, monitoring the difference AW between the back surface temperature of the epitaxial silicon wafer and the front surface temperature of the epitaxial silicon wafer, and when -5℃≤AW≤5℃, removing the epitaxial silicon wafer from the reaction chamber; wherein W1 is 1100℃-1200℃, and W2 is 750℃-900℃.
2. The method of claim 1, wherein, Taking the time point at which the W2 is reached as a starting time t1, and taking the time point at which the epitaxial silicon wafer is removed from the reaction chamber as an ending time t2, the difference Δt between the ending time t2 and the starting time t1 is ≥5s.
3. The method of claim 1, wherein, The atmosphere of the heat treatment comprises hydrogen, and the duration of the heat treatment is 10s-60s.
4. The method of claim 1, wherein, The film-forming gas comprises a silicon source gas and a doping gas, the silicon source gas comprises one or more of dichlorohydrogen silicon, trichlorohydrogen silicon, monosilane and silicon chloride, the doping gas comprises diborane and / or phosphine; the ratio of the volume of the silicon source gas to the volume of the doping gas is (15-100):
1.
5. The method of any one of claims 1-4, wherein, The temperature W1 of the reaction chamber is directly reduced to the target cooling temperature W2 at a first cooling rate of 7.5℃ / s-10℃ / s.
6. The method of any one of claims 1-4, wherein, The temperature reduction cooling process includes: experiencing n intermediate transition temperatures T n , n is a natural number not more than 10, T n-1 > T n .
7. The method of claim 6, wherein, When n=1, the intermediate transition temperature is a first transition temperature T1, and W1>T1>W2; The W1 is reduced to the T1 at a first cooling rate of 7.5℃ / s-10℃ / s, the temperature of the reaction chamber is maintained at the T1 for a time of 15s≤Δa≤20s, and AW is monitored; when -5℃≤AW≤5℃, the temperature of the reaction chamber is reduced from the T1 to the W2 at a second cooling rate of 7.5℃ / s-10℃ / s, AW is monitored, and when -5℃≤AW≤5℃, the epitaxial silicon wafer is removed from the reaction chamber, and 15s≤Δt≤20s.
8. The method of claim 6, wherein, When n=2, the intermediate transition temperature comprises a first transition temperature T1 and a second transition temperature T2, and W1>T1>T2>W2; The temperature of W1 is reduced to T1 at a first cooling rate of 7.5℃ / s-10℃ / s. The temperature of the reaction chamber is maintained at T1 for 5s ≤ Δa1 ≤ 10s, and ΔW is monitored. When -5℃ ≤ ΔW ≤ 5℃, the temperature of the reaction chamber is reduced from T1 to T2 at a second cooling rate of 7.5℃ / s-10℃ / s. The temperature of the reaction chamber is maintained at T2 for 5s ≤ Δa2 ≤ 10s, and ΔW is monitored. When -5℃ ≤ ΔW ≤ 5℃, the temperature of the reaction chamber is reduced from T2 to W2 at a third cooling rate of 7.5℃ / s-10℃ / s, and ΔW is monitored. When -5℃ ≤ ΔW ≤ 5℃, the epitaxial silicon wafer is removed from the reaction chamber for 5s ≤ Δt ≤ 10s.
9. An epitaxial silicon wafer, characterized by, The epitaxial silicon wafer is prepared by the method described in any one of claims 1-8.
10. The epitaxial silicon wafer of claim 9, wherein, The edge stress of the epitaxial silicon wafer is ≤5%; And / or, the thickness of the epitaxial layer of the epitaxial silicon wafer is 2μm-6μm.