Test method and test device therefor

Abstract

The present disclosure relates to the field of integrated circuit testing, and provides a testing method and a testing device thereof, which are applied to a testing tool. The method comprises the following steps: determining an initial position of a chip to be tested in a detection area of the testing tool; determining a position offset between the chip to be tested and a testing position of the detection area according to the initial position; and based on the position offset, controlling at least one movable boundary corresponding to the detection area to generate displacement and push the chip to be tested to the testing position. The method can adapt to various packaging models of the chip to be tested, realize automatic alignment and clamping of the chip to be tested, and automatic configuration of a testing interface, thereby solving the problems of adaptability, precision and efficiency.

Description

Test methods and test apparatus Technical Field

[0001] This disclosure relates to the field of integrated circuit testing, and in particular to a testing method and testing apparatus thereof. Background Technology

[0002] Versatility and flexibility. When faced with application scenarios involving multiple chip types, small-batch debugging, or frequent packaging changes, traditional testing solutions often require redesigning hardware interfaces, leading to extended development cycles, increased testing costs, and difficulty in meeting the needs of rapid iteration in R&D.

[0003] In the circuit probing (CP) stage, if an anomaly is found and the process needs to be transferred to the final test (FT) stage for retesting or functional debugging, the lack of a unified test interface compatible with various package types often causes interruptions. This results in existing test tools generally suffering from poor compatibility, unreliable connections, and severe signal interference. Especially in high-density pin and fine-pitch package applications, probe misalignment, short circuits, or poor contact are prone to occur, seriously affecting the accuracy and repeatability of test results. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this disclosure is to provide a testing method and testing apparatus to solve the problems in the related art.

[0005] This disclosure provides a testing method applied to a testing tool, characterized by comprising the following steps: determining an initial position of a chip under test (DUT) within a test area of ​​the testing tool; the test area being located within a test plane; the DUT carrying an indicator marking indicating its correct posture at the test position; determining a positional offset between the DUT and a test position within the test area based on the initial position, the positional offset including an angular offset of the DUT relative to the correct posture, comprising: determining a small angular offset between the indicator marking of the DUT and a target position within the correct posture; based on the positional offset, controlling at least one movable boundary corresponding to the test area to generate displacement, pushing the DUT to the test position, comprising: determining the direction and magnitude of a rotational component that causes the indicator marking to reach the target position based on the small angular offset; a target moving unit positioned within the at least one movable boundary to push the DUT to the rotational component; and controlling the target moving unit to push the DUT to the correct posture.

[0006] In an embodiment of the first aspect, the chip under test carries an indicator marking indicating its correct orientation at the test position; the position offset also includes an angular offset of the chip under test relative to the correct orientation.

[0007] In an embodiment of the first aspect, the position offset includes a translation component; controlling at least one movable boundary constituting the region to be detected to generate displacement includes: controlling a movable boundary corresponding to the direction of the translation component to move toward the test position based on the direction and magnitude of the translation component.

[0008] In an embodiment of the first aspect, the position offset includes a rotation component; controlling at least one movable boundary corresponding to the area to be detected to generate displacement includes: based on the rotation component, controlling a movable boundary corresponding to the direction of decrease of the rotation component to move toward the test position.

[0009] In an embodiment of the first aspect, the method further includes: redetermining the positional offset between the chip under test and the test position of the region to be tested, wherein the positional offset includes a translation component; and controlling a movable boundary corresponding to the direction of the translation component to move toward the test position based on the direction and magnitude of the translation component.

[0010] In an embodiment of the first aspect, the movable boundary comprises a plurality of independent moving units arranged linearly; based on the position offset, controlling at least one movable boundary corresponding to the area to be tested to generate displacement, and pushing the chip under test to the test position, includes: according to the projection of the chip under test on the movable boundary, controlling at least one of the moving units to form a local movable boundary for movement.

[0011] In an embodiment of the first aspect, the method further includes: controlling multiple movable boundaries to move synchronously toward the chip under test; when any of the movable boundaries contacts the chip under test in the correct orientation or pushes the chip under test to the correct orientation, the movable boundary pauses its movement until all the remaining movable boundaries contact the chip under test.

[0012] In an embodiment of the first aspect, the method further includes: selecting a pin layout mapping relationship corresponding to the package type of the chip under test; and generating a control signal based on the pin layout mapping relationship to activate the electrical path of a metal probe that matches the pin position of the chip under test.

[0013] A second aspect of this disclosure provides a computer-readable storage medium storing a computer program or instructions, which, when executed, perform the test method described in the first aspect above.

[0014] As described above, this disclosure relates to the field of integrated circuit testing and provides a testing method that, through modular design, particularly by integrating functions that can adapt to various package types of chips under test, achieves automatic alignment and clamping of the chips under test, as well as automatic configuration of the test interface, thereby solving the problems of compatibility, accuracy, and efficiency. Attached Figure Description

[0015] Figure 1 shows a flowchart of a testing method for a testing tool according to an embodiment of the present disclosure;

[0016] Figure 2 shows a schematic diagram illustrating the effect of the test tool implementing the test method in one embodiment of this disclosure;

[0017] Figure 3 illustrates the effect of the test tool implementing the test method in one embodiment of this disclosure;

[0018] Figure 4 illustrates the effect of the test tool implementing the test method in one embodiment of this disclosure;

[0019] Figure 5 shows a schematic diagram illustrating the effect of the test tool implementing the test method in one embodiment of this disclosure;

[0020] Figure 6 illustrates the effect of the test tool implementing the test method in one embodiment of this disclosure;

[0021] Figure 7 illustrates the effect of the test tool implementing the test method in one embodiment of this disclosure;

[0022] Figure 8 shows a schematic diagram illustrating the effect of the test tool implementing the test method in one embodiment of this disclosure;

[0023] Figure 9 shows a schematic diagram of the test apparatus in one embodiment of the present disclosure;

[0024] Figure 10 shows a schematic diagram of the structure of a computer device according to an embodiment of the present disclosure. Detailed Implementation

[0025] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the information disclosed herein. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this disclosure can be modified or changed according to different viewpoints and application modules without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement it. This disclosure may be embodied in many different forms and is not limited to the embodiments described herein.

[0027] In this disclosure, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic represented in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples represented in this disclosure, as well as the features of those different embodiments or examples.

[0028] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0029] For the purpose of clarity, devices unrelated to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0030] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" where other components are placed between them. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0031] While the terms first, second, etc., are used in some examples herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, module, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, modules, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0032] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this disclosure. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0033] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the message of the present disclosure, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0034] In existing technologies, traditional test equipment (ATE) is typically customized for specific chip package types. When testing chips with different package types, the entire test equipment needs to be replaced or complex manual adjustments need to be made, resulting in low testing efficiency, high costs, and the risk of human error. This makes it difficult for existing test equipment to achieve a good balance between testing accuracy, flexibility, and efficiency.

[0035] The present invention aims to provide a testing method and a testing device, which, through modular design, particularly by integrating functions that can adapt to various package types of chips under test, realizes automatic alignment and clamping of the chips under test, as well as automatic configuration of the testing interface, thereby solving the problems of compatibility, accuracy and efficiency.

[0036] In the embodiment shown in Figure 1, the testing method provided by the present invention includes:

[0037] Step A1: Determine the initial position of the chip under test within the testing area of ​​the testing tool;

[0038] Step A2: Determine the positional offset between the chip under test and the test position of the area to be tested based on the initial position;

[0039] Step A3: Based on the position offset, control at least one movable boundary corresponding to the area to be tested to generate displacement, and push the chip under test to the test position.

[0040] In some embodiments, for steps A1 and A2, determining the initial position of the chip under test (DUT) within the test area of ​​the testing tool, and determining the positional offset between the DUT and the test position of the test area based on the initial position, may include: when the testing tool detects that the DUT has been placed in a test area (control size system module) within the testing tool, the testing tool determines the initial position of the DUT in the test area, and calculates the positional offset between the geometric center of the DUT at the initial position and the test center corresponding to the test position of the test area.

[0041] Specifically, a vision sensor, such as a high-definition camera, is installed in the area to be inspected (control size system module) of the testing tool to capture images of the chip under test. Further, after acquiring the images, the testing tool identifies information about the chip under test from the images, such as chip model and chip size. The vision sensor can be positioned above or to the side of the area to be inspected.

[0042] After the operator places the chip under test (DUT) in the testing area of ​​the testing tool, the vision sensor captures an image of the testing area. The control system corresponding to the testing tool runs an image processing algorithm, including: recognizing the preset optical positioning marks of the DUT, or directly recognizing the outline of the DUT. The test center (which could be the center of the probe array) corresponding to the test position of the testing area of ​​the testing tool is located at the origin of the camera coordinate system (e.g., X_center=0, Y_center=0, x-axis to the right, y-axis upward). Through image recognition technology, the coordinates of the geometric center of the DUT in the camera coordinate system (e.g., X_chip, Y_chip) are calculated. The coordinates of the test center can be preset fixed values. The control system then calculates the position offset, including the offset position (ΔX, ΔY) = (X_center - X_chip, Y_center - Y_chip).

[0043] In some embodiments, if the horizontal plane of the chip under test rotates relative to the horizontal plane of the area to be tested, the positional offset determined by the testing tool may also include an angular offset, such as an offset angle Δθ. It can be seen that the chip under test located in the area to be tested can rotate 360°, and the value of the offset angle Δθ is between 0° and 90°.

[0044] For step A3: Based on the position offset, control at least one movable boundary corresponding to the area to be tested to generate displacement, and push the chip under test to the test position.

[0045] In some embodiments, the testing tool can control the movement of movable boundaries configured in the area to be tested. Based on the determined positional offset of the chip under test (DUT), it pushes and adjusts the position of the DUT so that it is positioned at the test location, thereby performing the test on the DUT. It should be noted that the shapes of the area to be tested and the DUT in this embodiment can be rectangular, but this is merely an illustrative example and not a limitation of the invention. The area to be tested can also be configured as circular, polygonal, or other regular or irregular shapes, as long as it can form a space capable of accommodating and positioning the chip. Similarly, the package of the DUT can also be of any shape.

[0046] Example 1

[0047] Specifically, as shown in Figure 2, the test area of ​​the testing tool is a rectangular space, and the package of the chip under test is also rectangular. The test area is configured with a first movable boundary 201, a second movable boundary 202, a third movable boundary 203, and a fourth movable boundary 204. Based on the positional offset of the chip under test, the testing tool controls the movement of the movable boundaries, pushing the chip under test towards the test position in the test area. The first movable boundary 201 to the fourth movable boundary 204 can move simultaneously and alternately without interfering with each other. If the positional offset of the chip under test relative to the test area only includes translational offset, the process of the testing tool controlling the movable boundaries can include: based on the direction and magnitude of the translational component, driving the movable boundary corresponding to the offset direction to move towards the test position. That is, determining the values ​​of ΔX and ΔY and their positive and negative markings in the positional offset (ΔX, ΔY). Based on the coordinate origin of the test center (e.g., X_center=0, Y_center0, the horizontal direction to the right is the x-axis, and the vertical direction upward is the y-axis), if ΔX is a positive number, it means that the chip under test is to the right relative to the test position of the test area. Then the test tool controls the first movable boundary 201 on the right side of the test area to move to the left, pushing the chip under test to the left by ΔX. If ΔY is a positive number, the test tool controls the fourth movable boundary 204 on the upper side of the test area to move downward, pushing the chip under test to the lower side by ΔY.

[0048] As can be seen, the technical solution of the above embodiment 1 can accurately quantify the chip position offset into specific values ​​(ΔX, ΔY). The solution uses the direction of offset to drive the movable boundary in that direction to move. Compared with the traditional method of pushing all movable boundaries inward synchronously, it has fewer moving parts, shorter action paths, lower energy consumption, and faster adjustment speed.

[0049] In some embodiments, the chip under test (DUT) carries an indicator marking indicating its correct orientation at the test position. Position offset also includes angular offset of the DUT relative to the correct orientation. The DUT has an indicator marking to identify its mounting orientation, used to determine whether the current orientation of the DUT conforms to a preset mounting orientation. If it is determined not to conform, it indicates that the DUT's output direction is reversed. The testing method of this embodiment makes it difficult to adjust the position of the DUT, preventing the testing tool from properly testing the DUT and thus preventing damage to the DUT due to reversed orientation. For example, in an image capturing the DUT, if the indicator marking is located at the top of the DUT, it indicates that the current orientation of the DUT conforms to the preset mounting orientation; otherwise, it is determined to be reversed.

[0050] Example 2

[0051] In some embodiments, within the same test plane corresponding to the region to be tested, a small angular offset between the indicator of the chip under test and its target position in the correct orientation is determined; based on the small angular offset, the direction and magnitude of the rotational component that would cause the indicator to reach the target position are determined, and a target moving unit is positioned in at least one movable boundary to push the chip under test to reach the rotational component.

[0052] Specifically, as shown in Figure 3, an indicator 20 is provided on the chip under test (DUT). The indicator 20 can be located on the upper side of the DUT, such as the upper right corner or the upper center of the DUT as shown in Figure 3. In some embodiments, if the positional offset of the DUT relative to the test area includes a rotational component, i.e., an angular offset occurs, the process of the test tool controlling the movable boundary can include: based on the rotational component, controlling at least one pair of oppositely positioned movable boundaries to generate displacement, thereby pushing the DUT to eliminate the rotational component. The test tool first needs to determine the position of the indicator 20, and then determine the positional offset relative to the target side of the DUT where the indicator 20 is located, including the value of the offset angle Δθ corresponding to the rotational component and the coordinate axis of the test center of the test area corresponding to the offset angle Δθ, as shown in Figure 3. Here, the offset angle Δθ can be the angle between the target side of the DUT and the x-axis or y-axis corresponding to the origin of the test center, such as the upper side of the DUT where the indicator 20 is located. Referring again to Figure 3, taking the indicator 20 located on the upper side of the chip under test as an example, the offset angle Δθ is the angle between the upper side of the chip under test and the x-axis of the test center, and Δθ is less than a threshold, such as 45°. This indicates that the angular offset between the indicator of the chip under test and its target position in the correct posture is small, that is, the angular offset between the horizontal direction corresponding to the correct posture of the chip under test and the x-axis direction of the target position is small. The test tool controls the second movable boundary 202 and the fourth movable boundary 204 on the lower and upper sides of the test area as target moving units in a suitable position among at least one movable boundary to push the chip under test to reach the rotation component. For example, the test tool controls the second movable boundary 202 and the second fourth movable boundary 204 on the upper and lower sides of the test area to move towards the chip under test simultaneously. By pushing the upper and lower parts of the chip under test simultaneously through the upper and lower movable boundaries, the value of the offset angle Δθ of the chip under test becomes 0, that is, the chip under test is straightened.

[0053] After adjusting the chip under test based on the rotation component, the positional offset between the current position of the chip under test and the test position is recalculated. This positional offset is mainly a translation component. Based on the recalculated translation component, at least one of the movable boundaries is controlled to move.

[0054] As can be seen, if the positional offset of the chip under test relative to the area to be tested includes angular offset and translational offset, the process of the test tool controlling the movable boundary can be as described above. The test tool first straightens the chip under test, then calculates the positional offset between the geometric center of the chip under test and the test center of the area to be tested, and pushes and adjusts the position of the chip under test according to the determined positional offset of the chip under test.

[0055] In some embodiments, continuing to refer to Figure 3, if the offset angle Δθ is the angle between the chip under test and the x-axis of the test center and Δθ is greater than a threshold, such as 45°, it means that the upper side of the chip under test is at an angle between the chip under test and the y-axis of the test center and Δθ is less than a threshold, such as 45°. This indicates that the angular offset between the indicator of the chip under test and its target position in the correct posture is small, that is, the angular offset between the vertical direction corresponding to the correct posture of the chip under test and the y-axis direction of the target position is small. At this time, it is determined that the first movable boundary 201 and the third movable boundary 203 on the upper and lower sides of the test area controlled by the test tool are target moving units in suitable positions to push the chip under test to reach the rotation component. Further, the test tool controls the first movable boundary 201 and the third movable boundary 203 on the upper and lower sides of the test area to move towards the chip under test simultaneously. By pushing the left and right parts of the chip under test simultaneously through the movable boundaries on the left and right sides, the value of the offset angle Δθ of the chip under test becomes 0, that is, the chip under test is straightened.

[0056] As can be seen from Figure 3, the technical solution adopts a step-by-step strategy of first correcting rotation and then correcting translation. After eliminating the rotational deviation (aligning the chip under test), the system recalculates and eliminates the remaining translational offset. This breaks down a complex hybrid offset technique into two simpler and easier-to-solve solutions. It avoids the mutual interference and system instability that may occur when correcting multiple offsets simultaneously, making the entire correction process logically clear and orderly, greatly improving accuracy and reliability.

[0057] In some embodiments, the movable boundary of the region to be detected is composed of a plurality of independent micro-motion units arranged linearly, and the step of controlling the movable boundary to generate displacement includes: selectively driving a subset of the micro-motion units to form a local boundary for movement according to the projection of the chip under test on the boundary.

[0058] The test area (control size system module) of the testing tool can be a square structure. For example, the size of the test area can be 50mm × 50mm, and each movable boundary can be composed of 100 resin units with a side length of 0.5mm arranged linearly. The resin units included in each movable boundary can be a whole movable boundary or form a partially movable boundary.

[0059] Example 3

[0060] Specifically, as shown in Figure 4, when adjusting the position of the chip under test, the testing tool identifies the size and geometric center of the chip under test based on the package model of the chip under test and the acquired image of the chip under test. Furthermore, it determines the positional offset between the geometric center of the chip under test and the testing center of the testing tool based on the preset coordinates of the area to be tested.

[0061] In some embodiments, the area to be tested is configured with a first movable boundary 201 to a fourth movable boundary 204. The first movable boundary 201 to the fourth movable boundary 204 may be formed by a linear arrangement of multiple resin units. The testing tool can also control at least one of the partially movable first movable boundaries 201 to the fourth movable boundary 204 to adjust the position of the chip under test. This includes: the testing tool selecting a portion of the resin units that can cover the projected area of ​​the chip under test on the first movable boundary 201 to form a partially movable first movable boundary 201, and controlling the movement of the partially movable first movable boundary 201 to adjust the position of the chip under test. For example, if the positional offset of the chip under test relative to the area to be tested only includes translation offset (ΔX, 0), if ΔX is a positive number, it indicates that the test position of the chip under test is to the right relative to the test position of the area to be tested. In this case, the testing tool controls the partially movable first movable boundary 201 on the right side of the area to be tested to move to the left, pushing the chip under test to shift to the left by ΔX.

[0062] As can be seen, by designing the movable boundary of the test area as a controllable structure composed of a series of linearly arranged resin units, fine-tuning of the chip's position can be achieved. For example, each resin unit with a side length of 0.5 mm constitutes a fine mechanical adjustment system, enabling the testing tool to guide the chip's movement with high precision, thus achieving accurate alignment. Based on the projected area of ​​the chip's side, only a portion of the resin units corresponding to the actual contact area with the chip is driven, rather than the entire movable boundary. This reduces the number of components, lowers the overall energy consumption of the testing tool, and extends the tool's lifespan and reliability by minimizing component movement. This testing method achieves adaptive adjustment of the position of chips of different sizes, enabling high-precision center alignment and significantly improving the reliability of chip testing.

[0063] Example 4

[0064] In some embodiments, the testing tool can also selectively move a portion of the movable boundary of the movable boundary of the area to be tested, adjusting the rotation component, i.e., the angular offset, in the position offset corresponding to the chip under test.

[0065] As shown in Figure 5, the testing tool can also selectively move a portion of the movable boundary of the test area. This can include: the indicator 20 is located on the target side of the chip under test, and the offset angle Δθ of the rotation component in the position offset corresponding to the target side is the angle between the target side of the chip under test and the x-axis or y-axis of the coordinate axis of the test center. If the target side is the upper side of the chip under test, and the Δθ between the upper side and the x-axis is less than a threshold, such as 45°, the testing tool, based on the upper side corresponding to the indicator 20 of the chip under test, moves multiple movable boundaries parallel to the coordinate axis that forms the offset angle Δθ with the upper side. Within the boundary, a movable boundary close to the upper side is identified, and the projected area on the movable boundary is calculated. For example, the projected area of ​​the upper side on the fourth movable boundary 204 is selected. A portion of the fourth movable boundary 204 is selected, wherein the length of the portion of the fourth movable boundary 204 can be less than the projected area of ​​the chip under test on the fourth movable boundary 204, and the position of the portion of the fourth movable boundary 204 can be close to the side where the indicator mark 20 of the chip under test is located, or even closer to the indicator mark 20 on the chip under test. The indicator mark 20 of the chip under test is shown in Figure 5. The test tool controls the portion of the movable fourth movable boundary 204 to move towards the chip under test, pushing the upper part of the chip under test so that the offset angle Δθ of the chip under test becomes 0, that is, the chip under test is straightened. While pushing the chip under test through the partially movable fourth movable boundary 204, the test tool can also control the second movable boundary 202 to move upward (not shown in Figure 5). The second movable boundary 202 abuts against one side of the chip under test, so that the fourth movable boundary 204 can straighten the chip under test more quickly.

[0066] In some embodiments, the testing tool may also selectively move a portion of the movable boundary of the movable boundary of the area to be tested. This may further include: if the angle Δθ between the target side corresponding to the indicator and one axis of the coordinate system of the test center is greater than a threshold, then the angle Δγ between the target side and another axis is less than the threshold. The testing tool can determine the movable boundary closest to the target side among multiple movable boundaries parallel to the other axis of the test center, and calculate the projected area on that movable boundary. Referring to Figure 6, the indicator 20 is located on the target side of the chip under test. The offset angle Δθ of the rotation component in the position offset corresponding to the target side is the angle between the target side of the chip under test and the x-axis of the coordinate system of the test center. If the target side is the upper side of the chip under test, and the Δθ between the upper side and the x-axis is greater than a threshold (e.g., 45°), the testing tool determines that the offset angle Δγ between the upper side and the y-axis is less than the threshold. Based on the upper side corresponding to the indicator mark 20 of the chip under test, among multiple movable boundaries parallel to the y-axis that forms an offset angle Δγ with the upper side, determine the movable boundary that is close to the upper side, and calculate the projected area on the movable boundary. For example, if the projected area of ​​the upper side on the third movable boundary 203, select a portion of the third movable boundary 203 that is movable. The length of the portion of the third movable boundary 203 can be less than the projected area of ​​the chip under test on the third movable boundary 203, and the position of the portion of the third movable boundary 203 can be close to the side where the indicator mark 20 of the chip under test is located, or even closer to the indicator mark 20 on the chip under test.

[0067] In some embodiments, referring to FIG7, the test tool may also selectively move a portion of the movable boundary of the movable boundary of the region to be tested, which may further include: an indicator being located on the chip under test and the indicator being close to at least two sides of the chip under test. The offset angle Δθ of the rotation component in the position offset corresponding to the chip under test may be: determining a target side from the two sides of the chip under test, and determining the angle between the target side and the target axis (x-axis or y-axis) in the coordinate axis of the test center; based on the coordinate axis of the chip under test and the target side that form the angle, determining the direction of change of the target side of the chip under test as the angle gradually decreases to 0; determining the horizontal or vertical vector corresponding to the direction of change; selecting the horizontal or vertical vector with the smaller vector value; and determining the movable boundary of the region to be tested on the opposite side of the direction corresponding to the horizontal or vertical vector with the smaller vector value. Referring again to Figure 7, select the offset angle Δθ between the upper side of the indicator 20 of the chip under test and the x-axis. Based on the process of the offset angle Δθ gradually decreasing to 0, determine the horizontal vector 2051 or the vertical vector 2052 corresponding to the direction of change of the upper side. The vertical vector has a smaller value. Determine the fourth movable boundary 204 on the side opposite to the direction of the vertical vector, and calculate the projected area on the movable boundary. For example, the projected area of ​​the upper side on the fourth movable boundary 204. Select a portion of the fourth movable boundary 204 that is movable. The length of this portion of the fourth movable boundary 204 can be less than the projected area of ​​the chip under test on the fourth movable boundary 204. The position of this portion of the fourth movable boundary 204 can be close to the side where the indicator 20 of the chip under test is located, or even closer to the indicator 20 on the chip under test. The indicator 20 of the chip under test is shown in Figure 7. The fourth movable boundary 204 of the test tool control section moves towards the chip under test, pushing the upper part of the chip under test so that the offset angle Δθ of the chip under test becomes 0, that is, the chip under test is straightened.

[0068] It can be seen that by selecting a portion of the boundary that is smaller than the projected area of ​​the chip under test on the movable boundary for driving, the applied driving force can be applied to the actual contact area of ​​the chip more concentratedly and accurately, which significantly improves the accuracy of the calibration process.

[0069] Example 5

[0070] In some embodiments, as shown in FIG8, the test method performed by the test tool may further include: controlling the first movable boundary 201 to the fourth movable boundary 204 of the area to be tested to simultaneously approach the chip under test (DUT). When any movable boundary on one side detects contact with the DUT in the correct orientation, the movable boundary on that side pauses, while the other sides continue to advance until all movable boundaries contact the DUT. Alternatively, in other examples, when the DUT in an incorrect orientation is pushed to the correct orientation by a movable boundary on one side, the DUT has been initially aligned. Next, the test tool further determines the positional offset of the geometric center of the DUT relative to the test center of the area to be tested. In this case, the positional offset only includes translational offset (ΔX, ΔY), and the test center can control all or all movable boundaries to align the DUT with the area to be tested.

[0071] As can be seen, the above testing method can omit the step of detecting and processing the offset angle Δθ included in the positional offset of the chip under test. By controlling all movable boundaries to move synchronously, the angular offset of the chip under test is first eliminated, and then the translational offset of the chip under test is further adjusted. This allows the testing tool to eliminate the need to rely on a vision system or complex algorithms to detect and calculate the angular offset, reducing the requirements for sensors and computing power, thereby effectively controlling hardware costs and software complexity.

[0072] In some embodiments, after the test tool adjusts the chip under test (DUT) from its initial position to the test position, the DUT is centered within the horizontal plane of the area to be tested. The geometric center of the DUT is aligned with the center of the adapter plate and the test probe array of the test tool. For a rectangular DUT and the test area of ​​the test tool, each side of the rectangle is parallel to the movable boundary of the test area. The test tool controls the fixing base module to activate the locking mechanism, firmly fixing the DUT and the support frame at the test position to prevent positional displacement due to vibration or thermal expansion during subsequent testing. This process may include:

[0073] Step B1: Identify and place the test chip in the test position;

[0074] Step B2: Voice notification to fix the chip under test;

[0075] Step B3: Control the metal probe to contact the chip under test according to the package type of the chip under test.

[0076] In some embodiments, the method for controlling the contact between the metal probe and the chip under test (DUT) according to the package type of the chip under test is as follows: the testing tool obtains the package type of the chip under test, and configures the metal probe for testing according to the effective pin spacing corresponding to the package type, including:

[0077] Step B31: Select the corresponding pin layout mapping relationship from the pre-stored configuration file according to the package model of the chip under test;

[0078] Step B32: Generate control signals based on pin layout mapping to activate the electrical path of metal probes that match the pins of the chip under test, while placing inactive metal probes in an electrically isolated state.

[0079] Specifically, in some embodiments, a probe array, i.e., an array of metal probes, is integrated at the bottom of the area to be tested. For example, the metal probes have a diameter of 0.1 mm and can be made of metal, such as beryllium copper or palladium-cobalt alloy, to ensure good conductivity, elasticity, and wear resistance. The spacing between the metal probes can be different from the pin density spacing of the chip under test (e.g., the metal probes can be spaced 0.2 mm apart, compared to the pin density spacing of 0.4 mm for the chip under test), forming a probe field. The area of ​​the probe field can be larger than the chip under test in various package types supported by the testing tool.

[0080] In some embodiments, the front end of each metal probe can make contact with a pin of the chip under test, and the rear end of the metal probe is connected to a switch matrix composed of a multi-channel analog switch integrated circuit (IC) or a microelectromechanical relay. This switch matrix acts as an electronic switch, responsible for connecting or disconnecting the connection between a specific probe and the rear-end signal channel under the command of the control system.

[0081] In some embodiments, the package type of the chip under test can be entered by the operator on the human-machine interface of the test tool, or it can be identified by the test tool from the image of the chip under test. For example, the operator selects the package type of the chip under test (such as "BGA256") on the human-machine interface of the test tool. After receiving the instruction, the control system of the test tool calls the corresponding pin layout mapping relationship from the internally stored configuration file. The pin layout mapping relationship can be a data table that specifies the layout of each pin of each chip under test (such as: VDD_1V2 power supply, VSS ground, data line DATA[0], clock line CLK) and the spacing between the pins, and can determine the physical position of the metal probes on the probe array according to the pin layout. The control system of the test tool generates a switch control signal for the probe array according to the parsed pin layout mapping relationship. The switch control signal contains the address information of the metal probes to be activated. For example, for the activated metal probe with address information (A, 15), the switch control signal is "closed"; while for the unmapped metal probe (A, 16), its corresponding switch is instructed to "open".

[0082] As can be seen, the above method enables pre-configuration of the pin layout of the chip under test (DUT). When the package type of the DUT changes, the metal probes can be reconstructed simply by the operator re-entering the information on the human-machine interface or by automatic recognition. This significantly reduces testing time compared to traditional methods (such as manually changing the probe array). Positioning the metal probes using the pre-stored pin layout mapping eliminates errors caused by human operation. When dealing with new DUT package types, only the pin layout mapping needs to be updated, reducing the maintenance cost of the testing tool.

[0083] In some embodiments, an adapter plate may be provided between the probe array of the metal probe and the test channel of the testing tool, and the electrical connection between the metal probe and the adapter plate includes:

[0084] Step C1: Connect the activated metal probes on the probe array to the test path on the adapter board using jumpers;

[0085] Step C2: Based on the electrical connection test path, the electrical signals transmitted to the pins of the chip under test are detected by the activated metal probe, and the chip under test is tested.

[0086] Specifically, in some embodiments, each test path on the adapter board can be labeled with its corresponding signal type, such as VDD_1V2 (1.2V power supply), VSS (ground), CLK (clock), DATA[0] (data bit 0), etc. Each test path can also correspond to a test channel leading to the test tool. The test tool connects all the test paths that need to be tested, such as power supply, ground, clock, data, and control, according to the determined package model of the chip under test, and starts the electrical continuity test.

[0087] Specifically, the test tool applies a DC voltage to a connected test path (such as the DATA[0] pin of the chip under test connected to the test tool ATE_CH015 via an adapter board), and the chip under test can detect the expected voltage; if it is open, no voltage is detected; if it is short-circuited with other paths, the current and voltage values ​​will show abnormalities.

[0088] As can be seen, connecting via an adapter board eliminates the need to design dedicated connection devices for each type of chip under test, making the testing tool more versatile. Combined with automated pin identification, this greatly improves wiring efficiency and accuracy.

[0089] In some embodiments, after the testing of the chip under test is completed, the testing tool needs to disconnect the established electrical connections with the chip under test in sequence, including:

[0090] Step A51: Disconnect the channel resource connection between the adapter board and the test tool;

[0091] Step A52: Then disconnect the channel resource connection between the chip under test and the adapter board;

[0092] Step A53: Disconnect the electrical connection of the metal probe;

[0093] Step A54: Release the clamping device on the chip under test, so that the area under test is reset to its initial state.

[0094] Specifically, in some embodiments, the operator executes a "safe disconnect" or "resource unload" command on the software interface of the testing tool. After the testing tool confirms that the test channel is closed, the test is completed. After disconnecting the test channel on the testing tool side, the testing tool also disconnects the paths of all activated metal probes and places them in a high-resistance state. This disconnects the electrical connection between the metal probes and the pins of the chip under test. Thus, when removing the chip under test, even if there is slight friction or static electricity between the pins of the chip under test and the metal probes, it will not be conducted to the testing tool through the metal probes, protecting the testing tool's test circuitry. The testing tool then controls the locking mechanism for the chip under test to release, releasing the chip under test from its clamping position.

[0095] Figure 9 shows a schematic diagram illustrating an application scenario of the test device 300 in one embodiment of this disclosure.

[0096] In Figure 9, the test device 300 is used to test the chip under test. The test device 300 includes the following functional modules: control size system module 301 and base pin placement module 302. The control size system module 301 and base pin placement module 302 can be referred to as test reconfiguration tool modules.

[0097] The control size system module 301 is used to determine the initial position of the chip under test (DUT) within the test area of ​​the testing tool, and to determine the positional offset between the DUT and the test position within the test area based on the initial position. The DUT carries an indicator marking indicating its correct orientation at the test position. The positional offset also includes an angular offset of the DUT relative to the correct orientation. Based on the positional offset, at least one movable boundary corresponding to the test area is controlled to generate displacement, pushing the DUT to the test position. The control size system module 301 is also used to determine a small angular offset between the indicator marking of the DUT and its target position in the correct orientation; based on the small angular offset, to determine the direction and magnitude of the rotational component that would cause the indicator marking to reach the target position, and a target moving unit positioned within at least one movable boundary to push the DUT to the rotational component; and to control the target moving unit to push the DUT to the correct orientation.

[0098] The base pin placement module 302 is used to select the pin layout mapping relationship corresponding to the package model of the chip under test; and to generate a control signal based on the pin layout mapping relationship to activate the electrical path of the metal probe that matches the pin position of the chip under test.

[0099] In some embodiments, the test reconfiguration tool module may further include a fixing base module 303, which is used to fix the chip under test.

[0100] The test device 300 may also include: an adapter board module 304 and a functional test interface module 305. The adapter board module 304 electrically connects the activated metal probes on the probe array to the test path of the adapter board module 304 via jumpers.

[0101] The functional test interface module 305 tests the chip under test by detecting the electrical signals transmitted to the pins of the chip under test through the activated metal probe according to the test path of the electrical connection.

[0102] In another embodiment of this disclosure, a computer-readable storage medium is provided, wherein program instructions are stored, which are executed to perform the test method of any of the above embodiments.

[0103] Figure 10 shows a schematic diagram of the structure of a computer device according to an embodiment of the present disclosure.

[0104] The computer device 400 includes a bus 401, a processor 402, and a memory 403. The processor 402 and the memory 403 can communicate with each other via the bus 401. The memory 403 can store computer programs or instructions. The processor 402 implements the steps corresponding to the test methods in the above embodiments by running the computer programs or instructions stored in the memory 403.

[0105] Bus 401 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, although only one thick line is used in the diagram, this does not indicate that there is only one bus or one type of bus.

[0106] In some embodiments, processor 402 may be implemented as a central processing unit (CPU), microprocessor unit (MCU), system on chip (System on Chip), or field-programmable array (FPGA). Memory 403 may include volatile memory for temporary data storage during program execution, such as random access memory (RAM).

[0107] The memory 403 may also include non-volatile memory for data storage, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state disk (SSD).

[0108] In some embodiments, the computer device 400 may further include a communication interface 404. The communication interface 404 is used for communication with external devices. In some specific examples, the communication interface 404 may include a signal port of the processor 402, such as I2C, SPI, UART, etc. In still other specific examples, the communication interface 404 may include one or more wired and / or wireless communication circuit modules external to the processor 402. For example, the communication interface 404 may include one or more of, for example, a wired network card, a USB module, a serial interface module, etc. The wireless communication protocols followed by the wireless communication module include one or more of the following: Nearfield communication (NFC) technology, Infrared (IR) technology, Global System for Mobile communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Bluetooth (BT), and Global Navigation Satellite System (GNSS).

[0109] This disclosure also provides a computer-readable storage medium storing a computer program or instructions, which, when run, implement the testing methods described in the above embodiments.

[0110] That is, the method steps in the above embodiments are implemented as software or computer code that can be stored in a recording medium (such as CDROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as computer code that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium after being downloaded via a network, so that the method represented herein can be stored in such software processing on a recording medium using a general-purpose computer, a special processor or programmable or special hardware (such as ASIC or FPGA).

[0111] In another embodiment of this disclosure, a computer program product is provided, comprising: program instructions for performing the test method of any of the above embodiments.

[0112] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the protection scope of this disclosure.

Claims

1. A testing method applied to a testing tool, characterized in that, Includes the following steps: The initial position of the chip under test (DUT) within the test area of ​​the testing tool is determined; the test area is located within a test plane; the DUT carries an indicator marking indicating its correct orientation at the test position; based on the initial position, a positional offset between the DUT and the test position within the test area is determined, the positional offset including an angular offset of the DUT relative to the correct orientation, comprising: determining a small angular offset between the indicator marking of the DUT and its target position in the correct orientation; based on the positional offset, controlling at least one movable boundary corresponding to the test area to generate displacement, pushing the DUT to the test position, comprising: determining, based on the small angular offset, that the indicator marking should reach the target position. The direction and magnitude of the rotation component of the target position; a target moving unit positioned in at least one movable boundary to push the chip under test to the rotation component; controlling the target moving unit to push the chip under test to the correct posture; the movable boundary comprising a plurality of independent moving units arranged linearly; the step of controlling at least one movable boundary corresponding to the area to be tested to generate displacement based on the position offset, and pushing the chip under test to the test position, includes: selecting a portion of the moving units that can cover the projected area of ​​the chip under test on the movable boundary to form a partially movable movable boundary, controlling the movement of the partially movable movable boundary, and adjusting the position of the chip under test.

2. The method as described in claim 1, characterized in that, The position offset includes a translation component; The control that constitutes at least one movable boundary corresponding to the area to be detected to generate displacement includes: based on the direction and magnitude of the translation component, controlling the movable boundary corresponding to the direction of the translation component to move towards the test position.

3. The method as described in claim 1, characterized in that, The control that constitutes at least one movable boundary corresponding to the area to be detected to generate displacement includes: based on the rotation component, controlling the movable boundary corresponding to the direction of decrease of the rotation component to move towards the test position.

4. The method as described in claim 3, characterized in that, Also includes: The positional offset between the chip under test and the test position of the area to be tested is re-determined, wherein the positional offset includes a translation component; Based on the direction and magnitude of the translation component, the movable boundary corresponding to the direction of the translation component is controlled to move towards the test position.

5. The method as described in claim 1, characterized in that, Also includes: Multiple movable boundaries are controlled to move synchronously toward the chip under test. When any movable boundary contacts the chip under test in the correct posture or pushes the chip under test to the correct posture, the movable boundary stops moving until all the remaining movable boundaries contact the chip under test.

6. The method as described in claim 1, characterized in that, Also includes: Based on the package type of the chip under test, a pin layout mapping relationship corresponding to the package type is selected; a control signal is generated based on the pin layout mapping relationship to activate the electrical path of the metal probe that matches the pin position of the chip under test.

7. A computer-readable storage medium, characterized in that, It stores a computer program or instructions that, when executed, perform the test method as described in any one of claims 1 to 6.

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