Preparation method of polycrystalline silicon

Abstract

The invention provides a preparation method of polycrystalline silicon. The plurality of wafers placed in the plurality of wafer clamping grooves sequentially comprise a plurality of first blocking control wafers, a plurality of first monitoring wafers, a plurality of first product wafers, a plurality of second monitoring wafers, a plurality of second product wafers, a plurality of third monitoring wafers and a plurality of second blocking control wafers; silicon oxide layers are arranged on the surface of the first product wafer and the surface of the second product wafer; through reducing the number of the blocking control sheets, at least one wafer clamping groove is arranged between the last first monitoring wafer along the first direction and the first first product wafer along the first direction. And at least one wafer clamping groove is arranged between the last second monitoring wafer in the first direction and the first second product wafer in the first direction, so that the problem of resistivity discretization of polycrystalline silicon in the wafer boat and the product wafers adjacent to the monitoring wafers is effectively inhibited on the basis of low cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processes, and more particularly to a method for preparing polycrystalline silicon. Background Technology

[0002] In semiconductor manufacturing, the POLY (Polycrystalline Silicon Process) refers to a process technology that uses polycrystalline silicon (a material composed of a large number of randomly arranged silicon grains) as the core, and fabricates key structures of semiconductor devices (such as gates, resistors, and local interconnects) through steps such as deposition, doping, and patterning. It is one of the core processes in MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and integrated circuit manufacturing, and its development is closely related to the miniaturization and high performance of semiconductor devices.

[0003] However, in the existing wafer arrangement, the product wafers adjacent to the monitoring wafer in the wafer boat have problems such as uneven polysilicon growth and low polysilicon nucleation density, which leads to polysilicon resistivity dispersion in the aforementioned product wafers. Summary of the Invention

[0004] This invention provides a method for preparing polycrystalline silicon to solve the above-mentioned technical problems, so as to effectively suppress the resistivity dispersion of polycrystalline silicon in the crystal boat and in the product wafer adjacent to the monitoring wafer.

[0005] According to a first aspect of the present invention, a method for preparing polycrystalline silicon is provided, the method comprising: The crystal boat is provided with a number of wafer slots arranged equidistantly along a first direction, and multiple wafers are arranged in the wafer slots of the crystal boat, with a single wafer slot holding a single wafer. Along the first direction, multiple wafers placed in several wafer slots sequentially include several first control wafers, several first monitoring wafers, several first product wafers, several second monitoring wafers, several second product wafers, several third monitoring wafers, and several second control wafers. There is at least one empty wafer slot between the first monitoring wafer and the first product wafer, and there is at least one empty wafer slot between adjacent second monitoring wafers and second product wafers. A silicon oxide layer is provided on the surface of both the first product wafer and the surface of the second product wafer. After placing the wafers, polycrystalline silicon is deposited on the surface of each of the product wafers.

[0006] Optionally, the number of empty wafer slots between adjacent first monitoring wafers and first product wafers is 1.

[0007] Optionally, the spacing between adjacent wafer slots is 6.5 mm, and the spacing between adjacent first monitoring wafers and first product wafers is 13 mm.

[0008] Optionally, the number of empty wafer slots between adjacent second monitoring wafers and second product wafers is 1.

[0009] Optionally, the spacing between adjacent wafer slots is 6.5 mm, and the spacing between adjacent second monitoring wafers and second product wafers is 13 mm.

[0010] Optionally, the difference between the number of the first product wafers and the number of the second product wafers is less than or equal to 1.

[0011] Optionally, the method for depositing polycrystalline silicon on the surface of each of the product wafers includes: The wafer boat is placed into the furnace tube equipment and sealed, and the furnace tube is evacuated to the target pressure; After evacuating the furnace tube to the target pressure, heat the furnace tube to the preset deposition temperature; After heating the furnace tube to a preset deposition temperature, silane gas is introduced into the furnace tube until polycrystalline silicon of the target thickness is deposited on the wafer surface.

[0012] Optionally, the target pressure ranges from 100 mTorr to 400 mTorr.

[0013] Optionally, the preset deposition temperature ranges from 600°C to 650°C.

[0014] Optionally, an oxide layer of a first thickness is deposited on the side of the first monitoring wafer placed adjacent to the first product wafer facing the first product wafer, and on the side of the second monitoring wafer placed adjacent to the second product wafer facing the second product wafer. An oxide layer of a second thickness is deposited on the side of the first product wafer placed adjacent to the first monitoring wafer facing the first monitoring wafer, and on the side of the second product wafer placed adjacent to the second monitoring wafer facing the second monitoring wafer, wherein the first thickness is greater than the second thickness.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the polycrystalline silicon preparation method provided by this invention, by reducing the number of control wafers, at least one wafer slot is arranged between the last first monitoring wafer and the first first product wafer along the first direction, and at least one wafer slot is arranged between the last second monitoring wafer and the first second product wafer along the first direction. This increases the nucleation density of polycrystalline silicon on the surface of the first first product wafer and the first second product wafer along the first direction during the polycrystalline silicon generation process, reduces the crystal nucleus size of the polycrystalline silicon, effectively suppresses the resistivity dispersion problem of polycrystalline silicon generated on the surface of the product wafer adjacent to the first and second monitoring wafers, and also reduces the monitoring cost and manufacturing cost of the wafer. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 An equivalent schematic diagram of wafer arrangement using existing technology; Figure 2 The resistivity waveform of polycrystalline silicon grown on the surface of a product wafer using existing technology; Figure 3 This is an equivalent schematic diagram of the wafer arrangement in this embodiment; Figure 4 This is a resistivity waveform diagram of polycrystalline silicon grown on the surface of the product wafer in this embodiment. Detailed Implementation

[0018] As can be seen from the above, in the existing wafer arrangement, the product wafers adjacent to the monitoring wafer in the crystal boat have problems such as uneven polysilicon growth and low polysilicon nucleation density, which leads to the polysilicon resistivity dispersion problem in the aforementioned product wafers.

[0019] Figure 1 An equivalent schematic diagram of wafer arrangement using existing technology. Figure 2 The resistivity waveform is shown for growing polycrystalline silicon on the surface of a product wafer using existing technology.

[0020] Please refer to Figure 1The reason for the above problem is that the existing technology places wafers sequentially into wafer slots 101 arranged at equal intervals, with each wafer slot 101 holding a single wafer. The wafer arrangement order along the first direction is as follows: baffle control wafer 100, monitoring wafer 102, product wafer 103, monitoring wafer 102, product wafer 103, monitoring wafer 102, and baffle control wafer 100. The baffle control wafer 100 is mainly used for preheating and stabilizing the process chamber, cleaning the chamber, shielding the product wafer 103, and debugging new processes. The monitoring wafer 102 is mainly used for process quality monitoring, film thickness measurement, thin-film resistance measurement, periodic quality inspection, and equipment performance verification. The product wafer 103 is the raw material used to manufacture the final chip product.

[0021] Because the monitoring wafer 102 is inserted between the product wafers 103, there is a situation where the monitoring wafer 102 and the product wafer 103 are adjacent, and the spacing between the wafer slots 101 is typically 6.5 mm. In this narrow and adjacent space, since the surface of the monitoring wafer 102 is a rough and uneven polycrystalline silicon film, while the surface of the product wafer 103 is a uniform oxide film, the rate at which the product wafer 103 adsorbs gas is slower than that of the monitoring wafer 102. This results in a lower nucleation density and a larger nucleus volume of polycrystalline silicon deposited on the surface of the product wafer 103, which in turn leads to a problem of resistivity dispersion in the polycrystalline silicon formed on the surface of the product wafer 103.

[0022] Please refer to Figure 2 It should be noted that the aforementioned resistivity dispersion problem of polycrystalline silicon can be understood as the existence of multiple outliers in the resistivity of polycrystalline silicon, each of which is characterized by a resistivity much lower than normal.

[0023] Given the technical problems existing in the prior art, those skilled in the art typically deposit a silicon nitride layer on the surface of the monitoring wafer to reduce the physical and chemical interactions between the monitoring wafer and the product wafer, thereby suppressing the resistivity outlier problem of polysilicon. However, this method additionally increases the cost of the silicon nitride thin-film equipment and the cost of monitoring the wafer.

[0024] In view of this, the technical solution of the present invention provides a new method for preparing polycrystalline silicon, wherein at least one empty wafer slot is provided between a first monitoring wafer and a first product wafer adjacent in a first direction; and at least one empty wafer slot is provided between a second monitoring wafer and a second product wafer adjacent in a first direction, thereby effectively suppressing the problem of polycrystalline silicon resistivity dispersion in the wafer boat and the product wafer adjacent to the monitoring wafer at a low cost.

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0028] Figure 3 This is an equivalent schematic diagram of the wafer arrangement in this embodiment. Figure 4 This is a resistivity waveform diagram of polycrystalline silicon grown on the surface of the product wafer in this embodiment.

[0029] Please refer to Figure 3 This embodiment provides a method for preparing polycrystalline silicon, the method including: Multiple wafers are arranged in the wafer slots 10 of the crystal boat, and a single wafer is placed in one of the wafer slots 10.

[0030] The crystal boat 90 is provided with a number of wafer slots 10 arranged equidistantly along the first direction. The wafers are placed inside the crystal boat 90. The crystal boat 90 is provided with a number of wafer slots 10 arranged equidistantly along the first direction AA', and each wafer slot 10 holds a single wafer.

[0031] In this embodiment, along the first direction AA', multiple wafers placed in a plurality of wafer slots 10 sequentially include a plurality of first control wafers 20, a plurality of first monitoring wafers 30, a plurality of first product wafers 40, a plurality of second monitoring wafers 50, a plurality of second product wafers 60, a plurality of third monitoring wafers 70, and a plurality of second control wafers 80, and the surfaces of the first product wafers 40 and the second product wafers 60 are both provided with silicon oxide layers.

[0032] In this embodiment, after placing the wafers, polycrystalline silicon is deposited on the surface of each product wafer.

[0033] As can be seen from the above description of the problems of the prior art, since the polycrystalline silicon on the surface of the monitoring wafer is rough and polycrystalline, the monitoring wafer surface has a larger specific surface area and more "dangling bonds". Therefore, the monitoring wafer is more likely to adsorb and catalyze the deposition of precursor gases such as silanes for polycrystalline silicon.

[0034] The silicon oxide layer on the surface of the product wafer is amorphous, uniform and smooth, which makes the chemical properties of the product wafer surface stable and the surface energy low. Its reactivity is much lower than that of polycrystalline silicon. Therefore, it becomes relatively difficult for gas molecules to adsorb on the surface of the product wafer, and higher energy is required to decompose and nucleate the adsorbed gas.

[0035] Furthermore, because the adjacent space between the monitoring wafer and the product wafer in the existing technology is only the size of the adjacent wafer slot 10, the gas molecules in the adjacent space between the monitoring wafer and the product wafer are very limited. Combined with the aforementioned intense reaction on the monitoring wafer surface and the milder reaction on the product wafer surface, the monitoring wafer surface adjacent to the product wafer will consume a large amount of the reactive gas in the adjacent space, leading to a significant decrease in the concentration of reactive gas in that space, and consequently, fewer gas molecules adsorbed on the product wafer surface. Since polycrystalline silicon nucleation requires a certain saturation level of gas adsorbed on the wafer surface, when the gas concentration adsorbed on the product wafer surface is insufficient, the nucleation density of the polycrystalline silicon formed on the product wafer surface will decrease, resulting in large grains in the polycrystalline silicon formed on the product wafer surface. Large grains reduce the number of grain boundaries per unit area, reducing the obstacles for charge carriers to cross within the polycrystalline silicon, thereby enhancing the conductivity of certain areas of the polycrystalline silicon on the product wafer surface, and consequently reducing the resistivity of certain areas of the polycrystalline silicon formed on the product wafer surface, resulting in resistivity dispersion in the polycrystalline silicon formed on the product wafer surface.

[0036] Based on the above principle description, in this embodiment, there is at least one empty wafer slot 10 between the first monitoring wafer 30 and the first product wafer 40 adjacent to each other in the first direction AA', and there is at least one empty wafer slot 10 between the second monitoring wafer 50 and the second product wafer 60 adjacent to each other in the first direction AA'.

[0037] Specifically, in this embodiment, by reducing the number of the first control wafer 20 and the second control wafer 80, an empty wafer slot 10 is left. The positions of the first control wafer 20 and the first monitoring wafer 30 are both moved upward, and the positions of the second product wafer 60, the third monitoring wafer 70, and the second control wafer 80 are all moved downward. This results in at least one empty wafer slot 10 between the first monitoring wafer 30 and the adjacent first product wafer 40, and at least one empty wafer slot 10 between the second monitoring wafer 50 and the adjacent second product wafer 60.

[0038] Therefore, the spacing between the first monitoring wafer 30 and the adjacent first product wafer 40, and the spacing between the second monitoring wafer 50 and the adjacent second product wafer 60, are both increased to at least 13 mm. This increased adjacent space increases the airflow rate and gas flow rate, thereby increasing the nucleation density of polysilicon deposited on the product wafer surface, reducing the polysilicon grain size, and consequently increasing the number of grain boundaries within the polysilicon on the product wafer surface. This increases the resistivity of certain regions of the polysilicon on the product wafer surface, effectively suppressing the resistivity dispersion problem of the polysilicon on the corresponding product wafer surface. For specific effects, please see [link to product wafer surface diagram]. Figure 4 .

[0039] Since this implementation provides vacant wafer slots 10 by reducing the number of control wafers, it not only effectively suppresses the resistivity dispersion problem of polysilicon generated on the surface of the corresponding product wafer without changing the number of product wafers, but also reduces the monitoring cost and manufacturing cost of the wafers.

[0040] It should be noted that both the first product wafer 40 and the second product wafer 60 grow polysilicon only on the surface opposite to the first direction AA'. Therefore, only the first product wafer 40 adjacent to the first monitoring wafer 30 and the second product wafer 60 adjacent to the second monitoring wafer 50 have the problem of polysilicon resistivity dispersion. So it is only necessary to increase the gap between the first monitoring wafer 30 and the first product wafer 40 adjacent to each other in the first direction AA', and to increase the gap between the second monitoring wafer 50 and the second product wafer 60 adjacent to each other in the first direction AA'.

[0041] It should be noted that the first control wafer 20 and the second control wafer 80 are the same type of wafer, only their arrangement positions differ. The first monitoring wafer 30, the second monitoring wafer 50, and the third monitoring wafer 70 are all the same type of wafer, only their arrangement positions differ. The first product wafer 40 and the second product wafer 60 are both the same type of wafer, only their arrangement positions differ.

[0042] In this embodiment, the number of empty wafer slots 10 between adjacent first monitoring wafers 30 and first product wafers 40 is set to one, and the number of empty wafer slots 10 between adjacent second monitoring wafers 50 and second product wafers 60 is also set to one. Of course, the number of empty wafer slots 10 between the wafers is not limited to one, and can be adjusted according to needs, which is not limited here.

[0043] In this embodiment, the difference between the number of the first product wafer 40 and the number of the second product wafer 60 is less than or equal to 1. For example, if the total number of the first product wafer 40 and the second product wafer 60 is set to 125, then the number of the first product wafer 40 is set to 63 and the number of the second product wafer 60 is set to 62; or, the number of the second product wafer 60 is set to 63 and the number of the first product wafer 40 is set to 62. If the total number of the first product wafer 40 and the second product wafer 60 is set to 126, then the number of the first product wafer 40 is set to 63 and the number of the second product wafer 60 is set to 63.

[0044] In this embodiment, the method for depositing polycrystalline silicon on the surface of each of the product wafers may include the following steps: S1: According to the polycrystalline silicon preparation method provided in this embodiment, multiple wafers are arranged in the wafer slot of the crystal boat, and each product wafer has a silicon oxide layer on its surface.

[0045] Specifically, an oxide layer of a first thickness is deposited on the side of the first monitoring wafer placed adjacent to the first product wafer facing the first product wafer, and on the side of the second monitoring wafer placed adjacent to the second product wafer facing the second product wafer.

[0046] In this embodiment, an oxide layer of a second thickness is deposited on the side of the first product wafer placed adjacent to the first monitoring wafer facing the first monitoring wafer, and on the side of the second product wafer placed adjacent to the second monitoring wafer facing the second monitoring wafer, wherein the first thickness is greater than the second thickness.

[0047] Furthermore, the first thickness is 1000 Å, and the second thickness is 100 Å.

[0048] S2: Place the wafer boat into the furnace tube equipment and seal it, and evacuate the furnace tube to the target pressure.

[0049] S3: After evacuating the furnace tube to the target pressure, heat the furnace tube to the preset deposition temperature.

[0050] Specifically, the target pressure ranges from 100 mTorr to 400 mTorr.

[0051] S4: After heating the furnace tube to the preset deposition temperature, silane gas is introduced into the furnace tube until polycrystalline silicon of the target thickness is deposited on the wafer surface.

[0052] Specifically, the preset deposition temperature ranges from 600°C to 650°C.

[0053] In summary, the polycrystalline silicon preparation method and polycrystalline silicon preparation method provided in this embodiment reduce the number of control wafers, ensuring that at least one wafer slot is spaced between the last first monitoring wafer and the first first product wafer along the first direction, and at least one wafer slot is spaced between the last second monitoring wafer and the first second product wafer along the first direction. This increases the nucleation density of polycrystalline silicon on the surface of the first first product wafer and the first second product wafer along the first direction during the polycrystalline silicon generation process, reduces the crystal nucleus size of the polycrystalline silicon, effectively suppresses the resistivity dispersion problem of polycrystalline silicon generated on the surface of the product wafer adjacent to the first and second monitoring wafers, and also reduces the monitoring cost and manufacturing cost of the wafer.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing polycrystalline silicon, characterized in that, The method includes: Multiple wafers are arranged in wafer slots of a crystal boat. The crystal boat is provided with a plurality of wafer slots arranged equidistantly along a first direction. Each wafer slot holds a single wafer. Along the first direction, the multiple wafers placed in the plurality of wafer slots sequentially include a plurality of first control wafers, a plurality of first monitoring wafers, a plurality of first product wafers, a plurality of second monitoring wafers, a plurality of second product wafers, a plurality of third monitoring wafers, and a plurality of second control wafers. There is at least one empty wafer slot between the first monitoring wafer and the first product wafer, and there is at least one empty wafer slot between adjacent second monitoring wafers and second product wafers. The surfaces of the first product wafers and the second product wafers are both provided with a silicon oxide layer. Polycrystalline silicon is deposited on the surface of each of the product wafers.

2. The method for preparing polycrystalline silicon according to claim 1, characterized in that, The number of empty wafer slots between adjacent first monitoring wafers and first product wafers is 1.

3. The method for preparing polycrystalline silicon according to claim 2, characterized in that, The spacing between adjacent wafer slots is 6.5 mm, and the spacing between adjacent first monitoring wafers and first product wafers is 13 mm.

4. The method for preparing polycrystalline silicon according to claim 1, characterized in that, The number of empty wafer slots between adjacent second monitoring wafers and second product wafers is 1.

5. The method for preparing polycrystalline silicon according to claim 4, characterized in that, The spacing between adjacent wafer slots is 6.5 mm, and the spacing between adjacent second monitoring wafers and second product wafers is 13 mm.

6. The method for preparing polycrystalline silicon according to claim 1, characterized in that, The difference between the number of the first product wafers and the number of the second product wafers is less than or equal to 1.

7. The method for preparing polycrystalline silicon according to claim 1, characterized in that, A method for depositing polycrystalline silicon on the surface of each of the product wafers includes: The wafer boat is placed into the furnace tube equipment and sealed, and the furnace tube is evacuated to the target pressure; After evacuating the furnace tube to the target pressure, heat the furnace tube to the preset deposition temperature; After heating the furnace tube to a preset deposition temperature, silane gas is introduced into the furnace tube until polycrystalline silicon of the target thickness is deposited on the wafer surface.

8. The method for preparing polycrystalline silicon according to claim 7, characterized in that, The target pressure ranges from 100 mTorr to 400 mTorr.

9. The method for preparing polycrystalline silicon according to claim 7, characterized in that, The preset deposition temperature range is 600°C to 650°C.

10. The method for preparing polycrystalline silicon according to claim 1, characterized in that, An oxide layer of a first thickness is deposited on the side of the first monitoring wafer placed adjacent to the first product wafer and the side of the second monitoring wafer placed adjacent to the second product wafer facing the second product wafer. An oxide layer of a second thickness is deposited on the side of the first product wafer placed adjacent to the first monitoring wafer facing the first monitoring wafer, and on the side of the second product wafer placed adjacent to the second monitoring wafer facing the second monitoring wafer, wherein the first thickness is greater than the second thickness.

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