Power consumption model construction method, power supply integrity evaluation method, electronic equipment and storage medium

Abstract

The invention provides a power consumption model construction method, a power supply integrity evaluation method, electronic equipment and a storage medium, which are applied to the technical field of computers, and the method comprises the following steps: after obtaining input data for performing dynamic power consumption analysis on a microprocessor architecture, inputting the input data into a first analysis tool to obtain a load current curve; according to the method, the load current curve and the parasitic parameter file are generated through different tools, the data size needing to be processed by a single tool is reduced, and the power consumption model of the microprocessor architecture is obtained. The operation efficiency of a single tool is improved, the time for generating a load current curve and a parasitic parameter model is shortened, and the load current curve and a parasitic parameter file can be synchronously generated, so that the overall time required for creating a chip power consumption model is effectively shortened, the test efficiency is improved, and the simulation test requirement is met.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a power consumption model construction method, a power integrity assessment method, an electronic device, and a storage medium. Background Technology

[0002] With continuous advancements in manufacturing processes, the power consumption and clock speed of microprocessor architectures are constantly increasing. The impact of power supply noise on microprocessor architecture operation is becoming increasingly significant. Power integrity (PI) simulation, which effectively detects power supply noise levels, has become a key verification method to ensure the stable operation of microprocessor architectures. One of the core factors involved in the PI simulation process is the chip power mode (CPM). The inventors have found that existing technologies require a significant amount of time to create CPMs, resulting in long PI simulation test cycles, low efficiency, and difficulty in meeting simulation testing requirements. Summary of the Invention

[0003] The purpose of this application is to provide a power consumption model construction method, a power integrity assessment method, an electronic device, and a storage medium, to solve the problem that the creation of CPM in the prior art requires a lot of time, resulting in long PI simulation test cycles, low efficiency, and difficulty in meeting simulation test requirements.

[0004] In a first aspect, this application provides a power consumption model construction method, applied to power consumption analysis during the pre-silicon verification process of microprocessor architecture, the method comprising: The input data used for dynamic power consumption analysis of the microprocessor architecture is obtained, including physical layout data, cell library power consumption model and timing characteristic data; The physical layout data, the cell library power consumption model, and the timing characteristic data are input into the first analysis tool to obtain a load current curve characterizing the power consumption of the microprocessor architecture over time. The parasitic parameter file of the microprocessor architecture is obtained using a second analysis tool. The parasitic parameter file is used to record the parasitic resistance and parasitic capacitance parameters of the microprocessor architecture. By coupling the load current curve with the parasitic parameter file, the power consumption model of the microprocessor architecture is obtained.

[0005] The power consumption model construction method provided in this application, after acquiring input data for dynamic power consumption analysis of the microprocessor architecture, namely physical layout data, cell library power consumption model, and timing characteristic data, inputs the obtained input data into a first analysis tool to obtain a load current curve characterizing the power consumption of the microprocessor architecture over time. A second analysis tool is then used to obtain the parasitic parameter file of the microprocessor architecture. Finally, the load current curve and the parasitic parameter file are coupled to obtain the power consumption model of the microprocessor architecture. Compared with existing technologies that generate load current curves and parasitic parameter files using the same tool, this application generates load current curves and parasitic parameter files using different tools, reducing the amount of data that a single tool needs to process, improving the operating efficiency of a single tool, and shortening the time required to generate load current curves and parasitic parameter models. Simultaneously, the load current curves and parasitic parameter files can be generated synchronously, thereby effectively shortening the overall time required to create a chip power consumption model. This helps to shorten the PI simulation test cycle, improve test efficiency, and thus meet the simulation test requirements in practical applications.

[0006] In one alternative implementation, the timing characteristic data includes transistor toggle data during runtime testing of a simulation circuit model of the microprocessor architecture. The first analysis tool can perform dynamic power consumption analysis on the microprocessor architecture based on the transistor flip-flop data.

[0007] In the power consumption model construction method provided in this application, the first analysis tool performs dynamic power consumption analysis on the microprocessor architecture based on the transistor switching data during the operation test of the simulation circuit model of the microprocessor architecture. By utilizing the characteristic that transistor switching data can accurately reflect the actual switching activity information of the microprocessor architecture, the reliability of the obtained dynamic power consumption analysis results is effectively improved. At the same time, based on the transistor switching data, the first analysis tool can extract more accurate transient power consumption and current waveforms, ensuring the accuracy of the final output results.

[0008] In one alternative implementation, the physical layout data is recorded in the layout and routing netlist file of the microprocessor architecture; The transistor flip-flop data is recorded in a VCD file.

[0009] In the power consumption model construction method provided in this application, the physical layout data and transistor toggle data are carried out in a way that the physical layout data is recorded by the layout and routing netlist file and the transistor toggle data is recorded by the VCD file. Since the layout and routing netlist and VCD file are obtained during the microprocessor architecture design and pre-simulation test, they do not need to be prepared separately. This setting can shorten the preparation time of input data and further improve the generation efficiency of load current curve.

[0010] In one optional implementation, obtaining the parasitic parameter file of the microprocessor architecture using the second analysis tool includes: Obtain the layout file and manufacturing process file of the microprocessor architecture; The second analysis tool is used to extract the parasitic parameter file of the microprocessor architecture based on the layout file and the manufacturing process file.

[0011] The power consumption model construction method provided in this application provides a specific method for obtaining parasitic parameter files, namely, using a second analysis tool to extract parasitic parameter files based on layout files and manufacturing process files. Since the layout files and manufacturing process files already exist before power consumption model construction, they do not need to be prepared separately when obtaining parasitic parameter files. The extraction of parasitic parameter files can be completed using existing data, which can save data preparation time. Furthermore, compared with related technologies that generate load current curves and parasitic parameter files using the same tool, this method only uses the second analysis tool to extract parasitic parameter files, which can effectively reduce the amount of data that the second analysis tool needs to process, thereby improving the extraction efficiency of parasitic parameter files.

[0012] In an optional implementation, the power consumption model construction method provided in the first aspect of this application further includes: Perform a Fourier transform on the load current curve to obtain the corresponding frequency domain waveform curve; Determine whether the load current curve meets the power integrity assessment requirements based on the frequency bands included in the frequency domain waveform curve.

[0013] In the power consumption model construction method provided in this application, the load current curve is further subjected to Fourier transform to determine the frequency band covered by the load current curve, thereby determining whether the obtained load current curve covers all frequency bands corresponding to the microprocessor architecture and its power supply path, providing a reference for determining whether the obtained load current curve meets the power integrity assessment requirements.

[0014] Secondly, this application provides a power integrity assessment method, applied to power integrity assessment during the pre-silicon verification process of microprocessor architecture, the method comprising: Obtain the power consumption model of the microprocessor architecture. The power consumption model includes a load current curve and a parasitic parameter file. The load current curve is generated by a first analysis tool, and the parasitic parameter file is obtained by a second analysis tool. The parasitic parameter file records the parasitic resistance parameters and parasitic capacitance parameters of the microprocessor architecture. The power distribution network model of the microprocessor architecture is obtained using a third analysis tool; The power distribution network model is coupled with the power consumption model to obtain a power integrity simulation model; Power integrity simulation of the microprocessor architecture is performed based on the power integrity simulation model.

[0015] Based on the above, the power integrity assessment method provided in this application, after obtaining the power consumption model of the microprocessor architecture, uses a third analysis tool to obtain the power distribution network model of the microprocessor architecture, couples the power distribution network model with the power consumption model to obtain a power integrity simulation model, and performs power integrity simulation on the microprocessor architecture based on the power integrity simulation model. Compared with the prior art that generates load current curves and parasitic parameter files using the same tool, this application generates load current curves and parasitic parameter files using different tools, reducing the amount of data that a single tool needs to process, improving the operating efficiency of a single tool, and shortening the time to generate load current curves and parasitic parameter models. At the same time, load current curves and parasitic parameter files can be generated simultaneously, thereby effectively shortening the overall time required to create a chip power consumption model, helping to shorten the PI simulation test cycle, improve test efficiency, and thus meet the PI simulation test requirements in practical applications.

[0016] In one optional implementation, the process of obtaining the load current curve includes: The input data used for dynamic power consumption analysis of the microprocessor architecture is obtained, including physical layout data, cell library power consumption model and timing characteristic data; The physical layout data, the cell library power consumption model, and the timing characteristic data are input into the first analysis tool to obtain a load current curve characterizing the power consumption of the microprocessor architecture over time.

[0017] The power integrity assessment method provided in this application offers a specific way to obtain a load current curve. After obtaining input data for dynamic power consumption analysis of the microprocessor architecture, the input data is input into a first analysis tool, which generates the load current curve. Compared with the prior art, which generates both the load current curve and parasitic parameter file using the same tool, this method only uses the first analysis tool to generate the load current curve. Therefore, it can effectively reduce the amount of data that the first analysis tool needs to process and improve the efficiency of obtaining the load current curve.

[0018] In one optional implementation, the process of obtaining the parasitic parameter file includes: Obtain the layout file and manufacturing process file of the microprocessor architecture; The second analysis tool is used to extract the parasitic parameter file of the microprocessor architecture based on the layout file and the manufacturing process file.

[0019] The power integrity assessment method provided in this application offers a specific approach to obtaining parasitic parameter files. After obtaining the microprocessor architecture layout file and manufacturing process file, a second analysis tool is used to extract the parasitic parameter file based on the obtained layout file and manufacturing process file. Since the layout file and manufacturing process file already exist before the power consumption model is constructed, no separate preparation is required when obtaining the parasitic parameter file. The extraction of the parasitic parameter file can be completed using existing data, which can save data preparation time. Furthermore, compared with related technologies that generate load current curves and parasitic parameter files using the same tool, this method only uses the second analysis tool to extract the parasitic parameter file, which can effectively reduce the amount of data that the second analysis tool needs to process, thereby improving the extraction efficiency of the parasitic parameter file.

[0020] Thirdly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executed by the processor. When the processor executes the computer program, it implements the steps of the power consumption model construction method provided in any embodiment of the first aspect of this application, or implements the steps of the power integrity assessment method provided in any embodiment of the second aspect of this application.

[0021] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the power consumption model construction method provided in any embodiment of the first aspect of this application, or implements the steps of the power integrity assessment method provided in any embodiment of the second aspect of this application. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating a power consumption model construction method provided in an embodiment of this application.

[0024] Figure 2 This is a schematic diagram of the power consumption model for a microprocessor architecture.

[0025] Figure 3 This is a flowchart illustrating another power consumption model construction method provided in an embodiment of this application.

[0026] Figure 4 This is a schematic diagram of the frequency domain waveform curve corresponding to the load current curve.

[0027] Figure 5 This is a flowchart illustrating a power integrity assessment method provided in an embodiment of this application.

[0028] Figure 6 This is a simulation link diagram for power integrity assessment of a microprocessor architecture.

[0029] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0031] To address the problem that existing technologies require significant time to create a CPM (Chip Power Model), resulting in low efficiency in PI (Physical Induction) simulation testing and difficulty in meeting simulation testing requirements, this application provides a power consumption model construction method. Compared to existing technologies that use the same tool to generate load current curves and parasitic parameter files, this application uses different tools to generate load current curves and parasitic parameter files, reducing the amount of data that a single tool needs to process and shortening the time required to generate load current curves and parasitic parameter models. Furthermore, the load current curves and parasitic parameter files can be generated simultaneously, effectively shortening the overall time required to create a chip power consumption model, improving testing efficiency, and thus meeting simulation testing requirements.

[0032] The power consumption model construction method provided in this application embodiment is applied to power consumption analysis in the pre-silicon verification process of microprocessor architecture. Specifically, it is executed by an electronic device, which can be a personal computer, a laptop, or, in some cases, a network-side server.

[0033] See Figure 1 As shown in the embodiments of this application, the power consumption model construction method may include the following steps.

[0034] S100: Obtain input data for dynamic power consumption analysis of the microprocessor architecture.

[0035] In the power consumption model construction method provided in this application embodiment, the input data for performing dynamic power consumption analysis on the microprocessor architecture includes physical layout data, cell library power consumption model, and timing characteristic data.

[0036] Physical layout data includes data related to the physical design and implementation of the microprocessor architecture, such as the layout information of each functional unit in the microprocessor architecture, the wiring information of the interconnections between functional power supplies, and of course, other layout data, which will not be listed here. As an optional implementation method, the layout and routing netlist file of the microprocessor architecture can be obtained. Based on the back-end design flow of the microprocessor architecture, it is known that the layout and routing netlist file obtained after logic synthesis records complete information on the physical design and implementation of the microprocessor architecture, that is, it records the placement position of each circuit component in the microprocessor architecture and the metal line routing information between the circuit components. Through the layout and routing netlist file, physical layout data for dynamic power consumption analysis of the microprocessor architecture can be obtained.

[0037] In the process of microprocessor architecture design, many standard units are required, such as AND gates, OR gates, NOT gates, and flip-flops. The collection of these standard units is called the unit library. Each standard unit in the unit library will inevitably generate a certain amount of power consumption in actual applications. The unit library power consumption model is used to record information related to the power consumption of the aforementioned standard units. This includes not only timing information but also detailed data for calculating internal power consumption and switching power consumption. The unit library power consumption model can be used to instruct EDA (Electronic Design Automation) tools on how to accurately calculate the power consumption of functional units and microprocessor architecture.

[0038] Timing characteristic data refers to data related to the timing characteristics of a microprocessor architecture. In the power consumption model construction method provided in this application, the timing characteristic data includes transistor switching data during the runtime testing of the simulation circuit model of the microprocessor architecture. Based on the working principle of the microprocessor architecture, it is known that the transistor switching process during runtime testing is directly related to the signal transitions during microprocessor architecture operation. Transistor switching data can more accurately determine the transient power consumption and current waveform of the microprocessor architecture. In an optional implementation, an EDA tool performs runtime testing on the simulation circuit model of the microprocessor architecture based on the input test vector. The resulting test results include a VCD file, which contains the transistor switching data of the microprocessor architecture during the test. Therefore, the power consumption model construction method provided in this embodiment can use the VCD file as one of the input data. The specific process of obtaining the VCD file can be implemented with reference to relevant technologies, and this application does not specifically limit it.

[0039] S110. Input the input data into the first analysis tool to obtain the load current curve characterizing the power consumption of the microprocessor architecture over time.

[0040] After obtaining the input data for dynamic power consumption analysis of the microprocessor architecture, the input data is fed into a first analysis tool. This tool then generates a load current curve characterizing the power consumption of the microprocessor architecture over time. As mentioned earlier, the input data includes transistor switching data recorded in a VCD file. Since transistor switching data can be used to characterize the actual signal transitions during microprocessor architecture operation testing, the first analysis tool, based on this transistor switching data, can obtain more accurate transient power consumption and current waveforms, thereby outputting a more precise load current curve with a longer time range, and the entire process is faster.

[0041] S120. Use the second analysis tool to obtain the parasitic parameter file of the microprocessor architecture.

[0042] Compared to existing technologies that use the same tool to generate load current curves and parasitic parameter files, this method uses a second analysis tool, different from the aforementioned first analysis tool, to obtain the parasitic parameter file of the microprocessor architecture. The parasitic parameter file is used to record the parasitic resistance and parasitic capacitance parameters of the microprocessor architecture.

[0043] In the runtime testing of simulation circuit models based on microprocessor architecture, parasitic resistance parameters mainly originate from the metal interconnects within the microprocessor architecture, although other sources are also included, which will not be detailed here. These parasitic resistances are not intentionally generated by the design; rather, they are formed by the bulk resistance of the conductor material itself and the contact resistance between the conductor and the transistor. Extracting these parasitic resistances is crucial in PI simulation testing because they cause IR drop (the voltage drop caused when current (I) flows through resistance (R)) and delay during long-distance signal transmission. This directly affects the timing closure and power integrity of the microprocessor architecture's timing path. Especially at high frequencies, excessive parasitic resistance can lead to timing errors or functional failures, making it a key indicator for evaluating the performance and reliability of the microprocessor architecture.

[0044] Parasitic capacitance parameters mainly refer to the equivalent capacitance formed between interconnects and between conductors and the substrate within a microprocessor architecture due to the insulating medium. Other equivalent capacitances may also be included, but will not be detailed here. Equivalent capacitance charges and discharges with signal changes, a process that significantly increases the dynamic power consumption of the circuit and introduces additional signal transmission delay. To a certain extent, parasitic capacitance is a core factor determining the overall power consumption and maximum operating frequency of a microprocessor architecture.

[0045] Based on the above, this embodiment provides an optional implementation for obtaining parasitic parameter files. First, the layout file (e.g., GDSII file) and manufacturing process file (e.g., ITF file) of the microprocessor architecture are obtained. Then, a second analysis tool is used to extract the parasitic parameter file of the microprocessor architecture based on the layout file and manufacturing process file. In practical applications, the second analysis tool can divide the microprocessor architecture into multiple functional units. Each functional unit is used to implement a preset function of the microprocessor architecture, and parasitic resistance and capacitance parameters are extracted on a unit-by-unit basis, thereby simplifying the difficulty of parasitic parameter extraction. Finally, the parasitic parameters of each functional unit are recorded in the parasitic parameter file. The specific process of obtaining the parasitic parameter file using the second analysis tool based on the layout file and manufacturing process file can be referred to relevant technologies and will not be detailed here.

[0046] S130. Couple the load current curve with the parasitic parameter file to obtain the power consumption model of the microprocessor architecture.

[0047] CPM consists of two parts: parasitic parameters and load current curves. Figure 2 As shown, the parasitic parameters include R die The parasitic resistance parameters and C are represented. die The parasitic capacitance parameter is represented by Is, and the load current curve of the microprocessor architecture is represented by Is. Based on this, after obtaining the load current curve and parasitic parameter file of the microprocessor architecture, the load current curve and the parasitic parameter file are coupled to obtain the power consumption model of the microprocessor architecture. It should be noted that the coupling described in this embodiment does not involve any actual processing operations. When applying the power consumption model for relevant verification, both the load current curve and the parasitic parameter file can be called simultaneously.

[0048] In summary, compared to existing technologies that use the same tool to generate load current curves and parasitic parameter files, this application uses different tools to generate load current curves and parasitic parameter files, reducing the amount of data that a single tool needs to process, improving the operating efficiency of a single tool, and shortening the time to generate load current curves and parasitic parameter models. At the same time, load current curves and parasitic parameter files can be generated simultaneously, thereby effectively shortening the overall time required to create chip power consumption models. This helps to shorten the PI simulation test cycle, improve test efficiency, and thus meet the PI simulation test requirements in practical applications.

[0049] Since the first analysis tool is only used to generate load current curves, the amount of data it needs to process is significantly reduced. Furthermore, by performing dynamic power consumption analysis on the microprocessor architecture based on transistor switching data recorded in VCD files, a load current curve with a wider time range can be obtained. This allows the load current curve to reflect load characteristics at more frequency points, especially covering low-frequency load characteristics. These low-frequency load characteristics enable effective evaluation of the motherboard power supply path of the microprocessor architecture, resulting in a more comprehensive evaluation. Simultaneously, using only the first analysis tool to generate load current curves effectively shortens the time required for curve generation, meeting the testing requirements for rapid evaluation across multiple power domains and test scenarios.

[0050] This application also provides another method for constructing a power consumption model, see [link to relevant documentation]. Figure 3 As shown, the power consumption model construction method provided in this embodiment includes the following steps.

[0051] S200: Obtain input data for dynamic power consumption analysis of the microprocessor architecture.

[0052] In an alternative implementation, S200 may refer to Figure 1 The implementation of S100 in the illustrated embodiment will not be repeated here.

[0053] S210. Input the input data into the first analysis tool to obtain the load current curve characterizing the power consumption of the microprocessor architecture over time.

[0054] In an alternative implementation, S210 may refer to Figure 1 The implementation of S110 in the illustrated embodiment will not be repeated here.

[0055] S220. Perform a Fourier transform on the load current curve to obtain the corresponding frequency domain waveform curve.

[0056] After obtaining the load current curve of the microprocessor architecture, a Fourier transform of the load current curve can be performed to obtain the following... Figure 4 The frequency domain waveform curve shown is as follows, where, Figure 4 In the graphs shown, the horizontal axis represents frequency in GHz, and the vertical axis represents current amplitude in A. Different curves represent the current amplitude of the load current at different frequencies. m1-m5 are typical examples of load current curves. The table shows the frequency and current amplitude corresponding to each load current curve from m1 to m5. The specific process of performing a Fourier transform on the load current curves to obtain the frequency domain waveform can be found in relevant technical documents and will not be detailed here.

[0057] S230. Determine whether the load current curve meets the power integrity assessment requirements based on the frequency bands included in the frequency domain waveform curve. If yes, proceed to S240; otherwise, return to S200.

[0058] In practical applications, the power supply path of a microprocessor architecture includes not only its internal power supply path but also several related parts, such as the power supply module, the power supply path on the motherboard, and the power supply path on the packaging substrate. These related parts have different effective response ranges to load current frequency changes. For example, the frequency range corresponding to the motherboard is 0~KHz, while the frequency range corresponding to the packaging substrate is 10MHz~tens of MHz. In order to obtain more accurate and reliable power integrity assessment results, the wider the frequency range that the load current curve can cover, the better.

[0059] Based on the above, power integrity assessment requirements can be preset by considering the actual situation of the microprocessor architecture and its power supply path. If the frequency bands included in the frequency domain waveform curve obtained in the aforementioned steps can cover the frequency bands required for power integrity assessment, then the obtained load current curve can be determined to meet the power integrity assessment requirements, and subsequent step S240 can be executed. Conversely, if the obtained frequency domain waveform curve does not cover the frequency bands required for power integrity assessment, then the obtained load current curve is determined to not meet the power integrity requirements, and step S200 needs to be returned to regenerate the load current curve. As for the frequency bands required for power integrity assessment, they need to be determined based on the actual performance parameters of the microprocessor architecture and its power supply path; this application does not impose specific limitations on this.

[0060] S240. Use the second analysis tool to obtain the parasitic parameter file of the microprocessor architecture.

[0061] In an alternative implementation, S240 may refer to Figure 1 The implementation of S120 in the illustrated embodiment will not be repeated here.

[0062] S250. Couple the load current curve with the parasitic parameter file to obtain the power consumption model of the microprocessor architecture.

[0063] In an alternative implementation, S250 may refer to Figure 1 The implementation of S130 in the illustrated embodiment will not be repeated here.

[0064] In summary, compared to existing technologies that generate load current curves and parasitic parameter files using the same tool, this application generates load current curves and parasitic parameter files using different tools. This reduces the amount of data that a single tool needs to process and improves the operating efficiency of a single tool, thereby effectively shortening the overall time required to create a chip power consumption model. This helps to shorten the power integrity assessment cycle and improve testing efficiency. Furthermore, building a load model based on a load current curve that meets the power integrity assessment requirements can effectively ensure the effectiveness of subsequent power integrity assessments.

[0065] This application also provides a power integrity assessment method, applied to the power integrity assessment during the pre-silicon verification process of microprocessor architecture. Specifically, it is performed by an electronic device, which can be a personal computer, a laptop, or, in some cases, a network-side server. See also... Figure 5 As shown in the embodiments of this application, the power integrity assessment method may include the following steps.

[0066] S300: Obtain the power consumption model of the microprocessor architecture.

[0067] In the power integrity assessment method provided in this embodiment, the power consumption model of the microprocessor architecture includes a load current curve and a parasitic parameter file. The load current curve is generated by a first analysis tool, and the parasitic parameter file is obtained by a second analysis tool. The parasitic parameter file records the parasitic resistance and parasitic capacitance parameters of the microprocessor architecture. More importantly, the first analysis tool and the second analysis tool are different analysis tools.

[0068] In one alternative implementation, input data for dynamic power consumption analysis of the microprocessor architecture can be obtained, specifically including physical layout data, cell library power consumption model, and timing characteristic data. The obtained physical layout data, cell library power consumption model, and timing characteristic data are input into a first analysis tool to obtain a load current curve characterizing the power consumption of the microprocessor architecture over time.

[0069] In one alternative implementation, the layout file and manufacturing process file of the microprocessor architecture can be obtained, and a second analysis tool can be used to extract the parasitic parameter file of the microprocessor architecture based on the layout file and manufacturing process file.

[0070] By coupling the load current curve with the parasitic parameter file, the power consumption model of the microprocessor architecture can be obtained. As for the specific process of obtaining the power consumption model of the microprocessor architecture, please refer to the relevant content of the aforementioned embodiments, which will not be repeated here.

[0071] S310. Use a third analysis tool to obtain the power distribution network model of the microprocessor architecture.

[0072] As discussed above, the power distribution network of a microprocessor architecture comprises multiple components, such as the power supply module, motherboard, and packaging substrate. Each component has its own power supply path structure and characteristics. Therefore, when constructing the power distribution network model of a microprocessor architecture, a third-party analysis tool can be used to construct passive models of each component (i.e., models composed of passive components such as parasitic inductors, parasitic resistors, and parasitic capacitors). Finally, the passive models of each component are coupled together to obtain the power distribution network model. The specific process of obtaining the power distribution network model using a third-party analysis tool can be found in relevant technical implementations and will not be detailed here.

[0073] S320. Couple the power distribution network model with the power consumption model to obtain the power integrity simulation model.

[0074] Since power supply noise is generated by the combined effect of the impedance of the power distribution network and the load current, coupling the power distribution network model obtained in the previous steps with the power consumption model yields... Figure 6 The power integrity simulation model shown should be noted that, in Figure 6 In the power integrity simulation model shown, the simulation model corresponding to the motherboard includes the simulation model of the power supply module and the motherboard power supply path. The two are not shown separately. The simulation models of the components of the power supply module, motherboard and packaging substrate are all represented by RLC (i.e., resistor, inductor and capacitor) passive components.

[0075] Combination Figure 6 As shown, when the microprocessor architecture is working, the current outputs from the leftmost power supply module, passes through the power supply path on the motherboard (including traces, vias, planes, etc.) to the packaging substrate, then enters the metal interconnect layer of the microprocessor architecture, and finally reaches the transistor circuit of the active layer. This process also includes passive components such as decoupling capacitors and inductors. Because the traces, vias, planes, and other structures themselves contain parasitic inductance, resistance, and capacitance, and the soldering of passive components introduces additional parasitic parameters, the voltage level transmitted to the microprocessor architecture through the actual power supply path is not an ideal level. This is why a power integrity assessment of the microprocessor architecture and its power supply path is necessary. It should be noted that... Figure 6 The power integrity simulation model shown is only an example. In actual applications, the specific architecture of the power integrity simulation model will vary depending on the actual power supply path and the microprocessor architecture.

[0076] S330: Power integrity simulation of microprocessor architecture based on power integrity simulation model.

[0077] The power integrity simulation model is subjected to test stimuli using simulation analysis tools, and the voltage ripple waveform of the operating voltage received by the microprocessor architecture is obtained. Based on the obtained voltage ripple waveform, it is determined whether the voltage noise is within the allowable voltage deviation range. If it is within the voltage deviation range, the power integrity test is determined to be passed. Conversely, if the voltage noise is not within the voltage deviation range, the power integrity test is determined to be failed, and the parameters of the power integrity simulation model need to be further adjusted.

[0078] In summary, the power integrity assessment method provided in this application, after obtaining the power consumption model of the microprocessor architecture, uses a third analysis tool to obtain the power distribution network model of the microprocessor architecture, couples the power distribution network model with the power consumption model to obtain a power integrity simulation model, and performs power integrity simulation on the microprocessor architecture based on the power integrity simulation model. Compared with the prior art that generates load current curves and parasitic parameter files using the same tool, this application generates load current curves and parasitic parameter files using different tools, reducing the amount of data that a single tool needs to process, improving the operating efficiency of a single tool, and shortening the time to generate load current curves and parasitic parameter models. At the same time, load current curves and parasitic parameter files can be generated simultaneously, thereby effectively shortening the overall time required to create a chip power consumption model, helping to shorten the PI simulation test cycle, improve test efficiency, and thus meet the PI simulation test requirements in practical applications.

[0079] Furthermore, since the first analysis tool is only used to generate load current curves, the amount of data it needs to process is significantly reduced. Moreover, by performing dynamic power consumption analysis on the microprocessor architecture based on transistor flip-flop data recorded in VCD files, a load current curve with a larger time range can be obtained. This can cover the low-frequency load characteristics of the motherboard power supply path, making up for the shortcomings of related technologies in assessing low-frequency load characteristics, and further improving the effectiveness of power integrity assessment results.

[0080] Below, for reference Figure 7 The electronic device provided in this embodiment of the invention may include: at least one processor 100, at least one communication interface 200, at least one memory 300, and at least one communication bus 400. In this embodiment of the invention, the number of processor 100, communication interface 200, memory 300, and communication bus 400 is at least one, and the processor 100, communication interface 200, and memory 300 communicate with each other through communication bus 400; obviously, Figure 7 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are optional. Optionally, the communication interface 200 can be an interface of a communication module, such as the interface of a GSM module; the processor 100 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0081] The memory 300 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0082] Specifically, the processor 100 is used to execute the application program in the memory to implement the steps of the power consumption model construction method or power integrity assessment method described above.

[0083] Furthermore, in some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more instructions implementing the above steps are stored. When these one or more instructions are executed by one or more processors, the processors execute the power consumption model construction method or power integrity assessment method described above. For specific implementation details, please refer to the foregoing description; further elaboration is not provided here.

[0084] In addition to the methods and devices described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the power consumption model construction method or power integrity assessment method according to the various embodiments of this application described above.

[0085] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0086] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0087] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0088] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0089] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0090] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0091] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A method for constructing a power consumption model, characterized in that, The method for power consumption analysis applied in the pre-silicon verification process of microprocessor architectures includes: The input data used for dynamic power consumption analysis of the microprocessor architecture is obtained, including physical layout data, cell library power consumption model and timing characteristic data; The physical layout data, the cell library power consumption model, and the timing characteristic data are input into the first analysis tool to obtain a load current curve characterizing the power consumption of the microprocessor architecture over time. The parasitic parameter file of the microprocessor architecture is obtained using a second analysis tool. The parasitic parameter file is used to record the parasitic resistance and parasitic capacitance parameters of the microprocessor architecture. By coupling the load current curve with the parasitic parameter file, the power consumption model of the microprocessor architecture is obtained.

2. The method according to claim 1, characterized in that, The timing characteristic data includes transistor switching data during the running test of the simulation circuit model of the microprocessor architecture; The first analysis tool can perform dynamic power consumption analysis on the microprocessor architecture based on the transistor flip-flop data.

3. The method according to claim 2, characterized in that, The physical layout data is recorded in the layout and routing netlist file of the microprocessor architecture; The transistor flip-flop data is recorded in a VCD file.

4. The method according to claim 1, characterized in that, The step of obtaining the parasitic parameter file of the microprocessor architecture using the second analysis tool includes: Obtain the layout file and manufacturing process file of the microprocessor architecture; The second analysis tool is used to extract the parasitic parameter file of the microprocessor architecture based on the layout file and the manufacturing process file.

5. The method according to claim 1, characterized in that, Also includes: Perform a Fourier transform on the load current curve to obtain the corresponding frequency domain waveform curve; Determine whether the load current curve meets the power integrity assessment requirements based on the frequency bands included in the frequency domain waveform curve.

6. A power integrity assessment method, characterized in that, A power integrity assessment method applied in the pre-silicon verification process of microprocessor architectures, the method comprising: Obtain the power consumption model of the microprocessor architecture. The power consumption model includes a load current curve and a parasitic parameter file. The load current curve is generated by a first analysis tool, and the parasitic parameter file is obtained by a second analysis tool. The parasitic parameter file records the parasitic resistance parameters and parasitic capacitance parameters of the microprocessor architecture. The power distribution network model of the microprocessor architecture is obtained using a third analysis tool; The power distribution network model is coupled with the power consumption model to obtain a power integrity simulation model; Power integrity simulation of the microprocessor architecture is performed based on the power integrity simulation model.

7. The method according to claim 6, characterized in that, The process of obtaining the load current curve includes: The input data used for dynamic power consumption analysis of the microprocessor architecture is obtained, including physical layout data, cell library power consumption model and timing characteristic data; The physical layout data, the cell library power consumption model, and the timing characteristic data are input into the first analysis tool to obtain a load current curve characterizing the power consumption of the microprocessor architecture over time.

8. The method according to claim 6, characterized in that, The process of obtaining the parasitic parameter file includes: Obtain the layout file and manufacturing process file of the microprocessor architecture; The second analysis tool is used to extract the parasitic parameter file of the microprocessor architecture based on the layout file and the manufacturing process file.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, characterized in that, When the processor executes the computer program, it implements the steps of the power consumption model construction method as described in any one of claims 1 to 5, or the steps of the power integrity assessment method as described in any one of claims 6 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the power consumption model construction method as described in any one of claims 1 to 5, or the steps of the power integrity assessment method as described in any one of claims 6 to 8.

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