Mask group plate for ion implantation process and use method

Abstract

The invention provides a mask group plate for an ion implantation process and a use method. The mask group plate comprises a zero-layer mask plate and at least one current mask plate, at least one first overlay mark is arranged on the zero-layer mask plate, and the first overlay mark is of a first rotational symmetry structure with a first symmetry center; at least one second overlay mark is arranged at the position, corresponding to the at least one first overlay mark, of the current mask plate, and the second overlay mark is of a second rotational symmetry structure with a second symmetry center; the second symmetric center coincides with the first symmetric center, the rotational symmetry of the first rotational symmetric structure is the same as that of the second rotational symmetric structure, and the angular displacement of the second overlay mark and the first overlay mark is zero.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a mask set plate for ion implantation process and a use method thereof. BACKGROUND

[0002] In the semiconductor manufacturing process, the photolithography process is a key step for realizing the transfer of circuit patterns, and the overlay precision between multiple photolithography layers directly affects the device performance and yield. At present, the common practice is to define a set of alignment marks in the first layer of photolithography (commonly known as the "Zero layer"), which are repeatedly used in all subsequent photolithography layers for alignment recognition by the photolithography machine.

[0003] However, in actual process flow, the second layer and subsequent continuous multiple layers can be ion implantation layers. After completing ion implantation and removing photoresist, the wafer surface will not retain the pattern structure, resulting in the inability to directly and timely judge the overlay deviation between each ion implantation layer and the Zero layer mark through conventional optical detection methods. In the prior art, only the signal strength generated by the photolithography machine reading the Zero layer mark and the process capability model of the photolithography machine itself can be relied on to indirectly infer whether there is an overlay risk. Generally, the higher the signal strength, the better the alignment state, and if the signal is zero, there is a significant overlay risk. However, due to the lack of real-time and direct detection means, once the signal decays or the machine performance fluctuates, it will be difficult to effectively identify and intervene, and only through electrical testing in the process control monitoring (PCM) or circuit probing (CP) stage after the completion of the entire process, analysis and backtracking can be performed, which has caused a large amount of product loss, resulting in increased cost and decreased yield.

[0004] Therefore, the prior art lacks a real-time and effective monitoring and evaluation technology for overlay precision after photolithography of ion implantation layers (before ion implantation process), and there is a significant quality control blind area, and there is an urgent need for a technology that can realize real-time monitoring and early warning of overlay errors in process layers without pattern retention.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application, and therefore can include information that does not constitute prior art known to those skilled in the art. SUMMARY

[0006] To address the problems in the prior art, the present invention aims to provide a mask assembly and its usage method for ion implantation processes. This mask assembly and its usage method effectively solve the problem of the lack of front-layer markings in the ion implantation process, thereby avoiding product scrap due to overlay misalignment. Furthermore, when overlay misalignment is detected by the mask assembly, it enables timely and effective repair of malfunctioning lithography machines.

[0007] Specifically, a first aspect of the present invention provides a mask assembly for an ion implantation process, comprising a zero-layer mask and at least one current mask;

[0008] The zero-layer mask is provided with at least one set of first markings, and the first set of markings is a first rotationally symmetric structure with a first center of symmetry.

[0009] At least one second set of markings is provided on the current mask at the corresponding position of the at least one first set of markings, and the second set of markings is a second rotationally symmetric structure with a second center of symmetry;

[0010] The second center of symmetry coincides with the first center of symmetry, and the rotational symmetry of the first rotational symmetry structure is the same as that of the second rotational symmetry structure. The angular displacement of the second set of markings and the first set of markings is zero.

[0011] According to a first aspect of the invention, the projection of the inner frame of the first set of markings onto the substrate completely covers the projection of the outer frame of the second set of markings onto the substrate.

[0012] According to a first aspect of the invention, the first set of markings is a triple, quadruple, or hexaple rotationally symmetric structure.

[0013] According to a first aspect of the invention, the distance between the vertices of the first rotationally symmetric structure is greater than 50 μm.

[0014] According to a first aspect of the invention, the distance between the vertices of the first rotationally symmetric structure is between 50 and 200 μm.

[0015] According to a first aspect of the invention, the distance between the projection of the inner frame of the first set of markings on the substrate and the projection of the outer frame of the corresponding second set of markings on the substrate is between 5 and 20 μm.

[0016] A second aspect of the present invention provides a method of using a mask assembly for an ion implantation process, employing the mask assembly for an ion implantation process described in the first aspect, the method comprising the following steps:

[0017] A substrate is provided, and etching marks are obtained on the substrate using a zero-layer mask, the etching marks corresponding to at least one first set of etching marks;

[0018] spinning a photoresist layer on a substrate;

[0019] pattern the photoresist layer using the current mask and obtain a current mark on the photoresist layer, the current mark corresponding to at least one second set of marks;

[0020] determine whether the current mark is aligned with the etching mark, and if so, perform an ion implantation process.

[0021] According to a second aspect of the present application, the step of determining whether the current mark is aligned with the etching mark comprises the steps of:

[0022] determining whether a first center of symmetry of the current mark coincides with a second center of symmetry of the etching mark;

[0023] if the first center of symmetry of the current mark coincides with the second center of symmetry of the etching mark, determining whether an angular displacement of the second set of marks from the first set of marks is less than a set angular threshold;

[0024] if the angular displacement of the second set of marks from the first set of marks is less than the set angular threshold, considering that there is no misalignment in patterning the photoresist layer using the current mask.

[0025] According to a second aspect of the present application, the step of determining whether the first center of symmetry of the current mark coincides with the second center of symmetry of the etching mark comprises the steps of:

[0026] obtaining a first image of the current mark and a second image of the etching mark, respectively;

[0027] identifying the first image and the second image to obtain a third center of symmetry of the first image and a fourth center of symmetry of the second image, respectively;

[0028] determining whether a distance between the third center of symmetry and the fourth center of symmetry is less than a set distance threshold;

[0029] if so, the third center of symmetry of the current mark coincides with the fourth center of symmetry of the etching mark.

[0030] According to a second aspect of the present application, the step of determining whether the angular displacement of the second set of marks from the first set of marks is less than a set angular threshold comprises the steps of:

[0031] obtaining a first vertex information of the first image and a second vertex information of the second image, respectively;

[0032] An angle between a line connecting the third symmetry center and the first vertex information and a line connecting the fourth symmetry center and the second vertex information is obtained, and the angle is an angular displacement between the current mark and the etching mark.

[0033] The mask group plate for ion implantation process has the following technical effects:

[0034] Real-time monitoring and judgment of non-graphic level overlay accuracy are realized, an effective monitoring means is provided for a process level without a reserved mark of a previous layer after ion implantation and other de-gluing, and overlay deviation between the process level and a reference zero layer can be timely and accurately judged, so that a blind area of the prior art which cannot be directly detected is overcome.

[0035] Batch product scrapping caused by overlay deviation is avoided, in-line real-time overlay deviation problems are found, an alarm is triggered immediately and subsequent process flow is interrupted, so that defects are prevented from continuing to spread in the process, large-scale product scrapping and economic loss are effectively reduced, and overall production yield is improved.

[0036] Accurate maintenance and performance improvement of a photolithography device are realized, overlay deviation abnormalities can be quickly and accurately associated to a specific photolithography device, a clear direction is provided for device maintenance, timely and effective targeted maintenance of abnormal devices is supported, device troubleshooting time is significantly reduced, and device utilization and production cycle stability are improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate one embodiment consistent with the present application and, together with the description, function to explain the principles of the application. Other features, objects, and advantages of the application will become apparent from the following detailed description of non-limiting embodiments, when read in connection with the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained from these drawings without creative labor for those skilled in the art. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus repeated descriptions thereof will be omitted. Some block diagrams shown in the drawings are functional entities, which do not necessarily correspond to physically or logically independent entities.

[0038] Figure 1 A structural schematic diagram of a zero layer mask plate of a mask group plate for ion implantation process according to an embodiment of the present application;

[0039] Figure 2 A structural schematic diagram of a current mask plate of a mask group plate for ion implantation process according to an embodiment of the present application;

[0040] Figure 3 A flow chart of a method for using a mask set for ion implantation processes according to an embodiment of the present application;

[0041] Figure 4 A schematic diagram of aligning a current mark with an etch mark according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The present application can also be embodied in a different form, and the specific details disclosed herein are not to be interpreted as limiting but merely as a basis for the claims. It is to be understood that the embodiments shown and described herein are only examples of the many embodiments of the present application. Those skilled in the art will envision many other possible variations that are within the scope of the present application. Therefore, to the extent that the claims following depart from this description, such claims should not be regarded as limited in scope to the specific structures described herein, but should be accorded the full scope consistent with the language of the claims, and the doctrine of equivalents.

[0043] The embodiments of the present application will be described below in detail with reference to the accompanying drawings. The present application can be embodied in various ways, and is not limited to the embodiments described herein.

[0044] In the present application, the expressions "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" mean that a specific feature, structure, material or characteristic represented with the embodiment or example is included in at least one embodiment or example of the present application. Also, the specific features, structures, materials or characteristics represented can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the different embodiments or examples represented in the present application and the features of the different embodiments or examples can be combined and integrated by those skilled in the art without contradiction.

[0045] In order to clearly illustrate the present application, devices irrelevant to the description are omitted, and the same or similar constituent elements are given the same reference numerals throughout the specification.

[0046] Throughout the specification, when a device is said to be "connected" to another device, this includes not only a case of "direct connection" but also a case of "indirect connection" in which other elements are interposed therebetween. In addition, when a device is said to include a certain constituent element, other constituent elements are not excluded unless specifically stated to the contrary, and it means that other constituent elements can be further included.

[0047] When a device is said to be "on" another device, it can be directly on the other device, but can also be accompanied by other devices therebetween. When it is said in contrast that a device is "directly" on another device, there are no other devices therebetween.

[0048] Although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first interface and a second interface, etc. are distinguished from each other. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, steps, operations, elements, components, items, and / or groups but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, items, and / or groups thereof. As used herein, the terms "or" and "and / or" are to be interpreted as inclusive, i.e., as meaning one or any combination of items. Thus, "A, B or C" or "A, B and / or C" means any of the following: A; B; C; A and B; A and C; B and C; A, B and C. This definition applies regardless of the manner in which the items are presented or described in the claims.

[0049] The professional terms used herein are used only to refer to specific embodiments and are not intended to limit the present application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. The meaning of "include" used in the specification is to specify a certain feature, region, integer, step, operation, element, and / or component, and is not to exclude the presence or addition of other features, regions, integers, steps, operations, elements, and / or components.

[0050] Unless otherwise defined herein, all terms used herein including technical terms and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terms defined in commonly used dictionaries are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] The mask set for ion implantation process and the using method of the present application will be further described in conjunction with the accompanying drawings and specific embodiments. It should be understood that each specific embodiment is not a limitation of the protection scope of the present application.

[0052] As technology nodes continue to shrink (e.g., into 5 nm, 3 nm), overlay control of ion implantation becomes as critical as etch overlay, because any slight shift can greatly affect the electrical characteristics of nanoscale transistors.

[0053] The present application provides a mask set for ion implantation process, comprising a zero layer mask and at least one current mask; the zero layer mask is provided with at least one first overlay mark, there are multiple photolithography processes in the chip manufacturing process, the mask used in the first photolithography process in the chip manufacturing process can define the alignment marks of all subsequent layers on the chip, here "zero layer" can be the mask of the first layer or the bottom layer in the photolithography process of semiconductor chip manufacturing, because the mask of the first layer or the bottom layer does not have ready-made alignment marks for reference, it usually needs very high precision laser direct writing or electron beam lithography technology, combined with precise wafer positioning system, to ensure that these initial marks are made in the most ideal position, and the mask set for ion implantation process of the present application is used for overlay of ion implantation process, in order to define the boundary of the doped region, to ensure that the impurities are accurately implanted into the specified electrical region, otherwise it will affect the electrical performance of the device, but will not cause physical short circuit immediately, accordingly, the size or precision requirement of the alignment mark can be lower, therefore, "zero layer" here can also be a layer of mask before the photolithography process corresponding to the ion implantation process, that is, the front layer mask of the ion implantation process, so that the subsequent photolithography process corresponding to the ion implantation process can be accurately overlaid on the correct position.

[0054] The zero layer mask is provided with multiple first overlay marks, the number of overlay marks is related to the size of the mask, and the multiple overlay marks are usually arranged in an array mode on the mask. The first overlay mark is a first rotational symmetry structure with a first symmetry center. Figure 1 The structure diagram of the zero layer mask of the mask set for ion implantation process of an embodiment of the present application, wherein the first overlay mark is a four-fold rotational symmetry structure, more specifically, the first overlay mark is a quadrilateral structure formed by four strip patterns, the above strip pattern can be used to more easily obtain position information such as inner frame, outer frame and vertex in subsequent image recognition.

[0055] The current mask is provided with at least one second overlay mark at a position corresponding to the at least one first overlay mark, that is, the number of second overlay marks provided on the current mask is the same as the number of first overlay marks provided on the zero layer mask, the second overlay mark is a second rotational symmetry structure with a second symmetry center. The second symmetry center coincides with the first symmetry center, and the rotational symmetry of the first rotational symmetry structure is the same as that of the second rotational symmetry structure, and the angular displacement of the second overlay mark and the first overlay mark is zero.

[0056] The second overlay mark can be a pattern different from the first overlay mark in size and structure, but the rotational symmetry structure thereof is completely consistent with the symmetry structure of the first overlay mark, for example, can be the same as the first rotational symmetry structure but the size of the overlay mark is different. Preferably, the projection of the inner frame of the first overlay mark on the substrate completely covers the projection of the outer frame of the second overlay mark on the substrate.

[0057] The second overlay mark can also be other patterns having a symmetry structure completely consistent with the symmetry structure of the first overlay mark, such as Figure 2 The second overlay mark shown is a quadrilateral, which also has a four-fold symmetry structure, and the size of the outer frame is smaller than the size of the inner frame of the first overlay mark.

[0058] Of course, the first overlay mark can be other four-fold symmetry structures, or three-fold or six-fold rotational symmetry structures. The present application realizes real-time monitoring and judgment of overlay precision of no pattern level by setting the overlay mark on the front layer, for example, for the process level after the ion implantation and other de-gluing without the front layer mark reserved, without waiting for the chip probe test / wafer test (PCP / CP) after the entire process flow ends for backtracking analysis, the overlay deviation between the process level and the reference zero layer (front layer) can be timely and accurately judged, the blind area of the prior art which cannot be directly detected is overcome, and early discovery and interception of problems in the semiconductor processing process are realized.

[0059] The present application also provides a use method of the mask set plate for the ion implantation process, which adopts the above-mentioned mask set plate for the ion implantation process, Figure 3 The flow chart of the use method of the mask set plate for the ion implantation process of an embodiment of the present application, specifically, the use method comprises the following steps:

[0060] Step S100: providing a substrate, obtaining an etching mark on the substrate by using a zero layer mask plate, the etching mark corresponding to at least one first overlay mark;

[0061] Step S200: spin coating a photoresist layer on the substrate;

[0062] Step S300: patterning the photoresist layer by using a current mask plate and obtaining a current mark on the photoresist layer, the current mark corresponding to at least one second overlay mark, Figure 4 The schematic diagram of the position alignment of the current mark and the etching mark of an embodiment of the present application.

[0063] Step S400: judging whether the positions of the current mark and the etching mark are aligned or not, if aligned, performing step S510 to carry out the ion implantation process.

[0064] The present application adds a set of exposure outer frames for overlay on a zero layer mask by adding an overlay mark in a semiconductor device photolithography process, and then adds a set of exposure inner frames for overlay on a mask of an implant level, and judges whether there is an overlay deviation problem in the implant level overlay by checking whether the overlay frames of the two layers of patterns are concentric frames. Thus, the defects are prevented from continuing to spread in the process, large-scale product scrapping is effectively reduced, and the overall production yield of the semiconductor device is improved.

[0065] Further, the step of judging whether the positions of the current mark and the etching mark are aligned in the S400 step can include the following steps:

[0066] Step S410: judging whether the second symmetry center of the current mark and the first symmetry center of the etching mark coincide. For example, the S410 step can send a wafer with a patterned photoresist corresponding to a completed ion implantation process into an automatic measurement machine, and the automatic measurement machine is provided with an image acquisition unit and an image processing unit. At this time, the S410 step can include:

[0067] Step S411: acquiring a first image of the current mark and a second image of the etching mark respectively by the image acquisition unit, and adjusting the focal length of the image acquisition unit so that it focuses on different layers of the wafer.

[0068] Step S412: identifying the first image and the second image, and obtaining a third symmetry center of the first image and a second symmetry center of the second image respectively by a set algorithm;

[0069] Step S413: judging whether the distance between the third symmetry center and the fourth symmetry center is less than a set distance threshold; ideally, the distance between the third symmetry center and the fourth symmetry center is zero, and in actual operation, the distance threshold can be set according to the overlay accuracy requirement and the performance requirement of the target semiconductor device.

[0070] If the distance between the third symmetry center of the current mark and the fourth symmetry center of the etching mark is less than the set distance threshold, it is considered that the third symmetry center of the current mark and the fourth symmetry center of the etching mark coincide.

[0071] If the distance between the third symmetry center of the current mark and the fourth symmetry center of the etching mark is greater than or equal to the set distance threshold, step S520 is performed: it is considered that the current mark (photoetching of the current layer) and the etching mark (zero layer) deviate, and at this time, the wafer is no longer subjected to subsequent ion implantation processes.

[0072] The S400 step is to accurately measure the relative position deviation of the etching mark of the zero layer and the current mark of the current ion implantation layer, i.e. the overlay error value, by optical means. If the overlay error value is less than the set threshold, subsequent ion implantation processes can be performed.

[0073] After judging that the first symmetry center of the current mark coincides with the second symmetry center of the etching mark, step S420 can be further executed: judging whether the angular displacement of the second overlay mark relative to the first overlay mark is less than a set angular threshold value;

[0074] If the angular displacement of the second overlay mark relative to the first overlay mark is less than the set angular threshold value, it is considered that there is no displacement in patterning the photoresist layer by using the current mask, and the wafer can be subjected to subsequent ion implantation process.

[0075] The step of judging whether the angular displacement of the second overlay mark relative to the first overlay mark is less than a set angular threshold value comprises the following steps:

[0076] The first vertex information of the first image and the second vertex information of the second image are obtained respectively;

[0077] The included angle between the line connecting the third symmetry center and the first vertex information and the line connecting the fourth symmetry center and the second vertex information is obtained, and the included angle is the angular displacement of the second overlay mark relative to the first overlay mark. The included angle is the angular displacement of the current mark relative to the etching mark, i.e. the angular displacement of the current mask relative to the zero layer mask after overlay.

[0078] The step S400 is to accurately measure the relative position deviation of the etching mark of the zero layer and the current mark of the current ion implantation layer, i.e. the overlay error value, by optical means, such as an optical microscope (or an automatic visual detection system), after the photoresist development in the ion implantation process and before the photoresist stripping. If the overlay error value is less than a set threshold value, subsequent ion implantation process can be performed.

[0079] In order to facilitate the execution of the step S400, the image acquisition unit can be an optical microscope instead of a scanning electron microscope with high resolution but high cost. Correspondingly, the size of the first overlay mark and the second overlay mark is greater than 50 μm, preferably, the size of the first overlay mark and the second overlay mark is between 50 μm and 200 μm, or the distance between the vertices of the first rotational symmetry structure and the distance between the vertices of the second rotational symmetry structure is between 50 μm and 200 μm, such as Figure 1 In the embodiment of the application, the distance between the vertices of the first rotational symmetry structure is the side length of the first overlay mark. Further, the distance between the projection of the inner frame of the first overlay mark on the substrate and the projection of the outer frame of the corresponding second overlay mark on the substrate is between 5 μm and 20 μm. The size of the overlay mark also makes it possible to visually check whether the current mark (photoetching of the current layer) is aligned with the etching mark (zero layer). In the embodiment, the letters indicating the layer are additionally provided on the zero layer mask and the current mask, such as Figure 1 “ZR1” on the zero layer mask, Figure 2The "L1" on the current mask can set the corresponding relationship (such as left alignment of letters) when setting the above text mark, thereby facilitating image recognition or visual inspection.

[0080] Although the embodiments of the present application have been shown and described above, it should be understood by those skilled in the art that the above embodiments are exemplary and cannot be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

[0081] The above is a further detailed description of the present application in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present application is limited to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or replacements can also be made, which should be considered as belonging to the protection scope of the present application.

Claims

1. A mask assembly for ion implantation processes, characterized in that, Includes a zero-layer mask and at least one current mask; The zero-layer mask is provided with at least one set of first markings, and the first set of markings is a first rotationally symmetric structure with a first center of symmetry. At least one second set of markings is provided on the current mask at the corresponding position of the at least one first set of markings, and the second set of markings is a second rotationally symmetric structure with a second center of symmetry; The second center of symmetry coincides with the first center of symmetry, and the rotational symmetry of the first rotational symmetry structure is the same as that of the second rotational symmetry structure. The angular displacement of the second set of markings and the first set of markings is zero.

2. The mask assembly for ion implantation process according to claim 1, characterized in that, The projection of the inner frame of the first set of markings onto the substrate completely covers the projection of the outer frame of the second set of markings onto the substrate.

3. The mask assembly for ion implantation process according to claim 1, characterized in that, The first set of markings has a triple, quadruple, or hexaple rotationally symmetrical structure.

4. The mask assembly for ion implantation process according to claim 1, characterized in that, The distance between the vertices of the first rotationally symmetric structure is greater than 50 μm.

5. The mask assembly for ion implantation process according to claim 1, characterized in that, The distance between the vertices of the first rotationally symmetric structure is between 50 and 200 μm.

6. The mask assembly for ion implantation process according to claim 1, characterized in that, The distance between the projection of the inner frame of the first set of markings on the substrate and the projection of the outer frame of the corresponding second set of markings on the substrate is between 5 and 20 μm.

7. A method of using a mask assembly for ion implantation processes, characterized in that, The method of using the mask assembly for ion implantation process according to any one of claims 1 to 6 includes the following steps: A substrate is provided, and etching marks are obtained on the substrate using a zero-layer mask, the etching marks corresponding to at least one first set of etching marks; Spin-coating a photoresist layer onto a substrate; The current mask is used to pattern a photoresist layer and a current mark is obtained on the photoresist layer, the current mark corresponding to at least one second set of markings; Determine whether the current mark and the etched mark are aligned. If they are aligned, then perform the ion implantation process.

8. The method of using the mask assembly for ion implantation process according to claim 7, characterized in that, The step of determining whether the current mark and the etched mark are aligned includes the following steps: Determine whether the first center of symmetry of the current mark coincides with the second center of symmetry of the etched mark; If the first center of symmetry of the current mark coincides with the second center of symmetry of the etched mark, then determine whether the angular displacement between the second set of etched marks and the first set of etched marks is less than a set angle threshold. If the angular displacement between the second set of markings and the first set of markings is less than the set angle threshold, it is considered that there is no offset in the patterning of the photoresist layer using the current mask.

9. The method of using the mask assembly for ion implantation process according to claim 8, characterized in that, The step of determining whether the first center of symmetry of the current mark coincides with the second center of symmetry of the etched mark includes the following steps: Obtain the first image of the current marker and the second image of the etched marker, respectively; Identify the first image and the second image, and obtain the third center of symmetry of the first image and the fourth center of symmetry of the second image, respectively; Determine whether the distance between the third center of symmetry and the fourth center of symmetry is less than a set distance threshold; If so, the third center of symmetry of the current mark coincides with the fourth center of symmetry of the etched mark.

10. The method of using the mask assembly for ion implantation process according to claim 9, characterized in that, The step of determining whether the angular displacement between the second set of markings and the first set of markings is less than a set angle threshold includes the following steps: Obtain information about a first vertex of the first image and information about a second vertex of the second image, respectively. Obtain the angle between the line connecting the third symmetry center and the first vertex information and the line connecting the fourth symmetry center and the second vertex information, where the angle is the angular displacement between the current mark and the etch mark.

Images