Time division multiplexing system slave, method, and program

Abstract

A time division multiplexing system according to an embodiment of the present invention is provided with a master and a plurality of slaves, the master and the plurality of slaves forming a ring-type communication network, the slaves being configured to transmit data including output permission information to a slave or a master at a subsequent stage, and the slave being configured to transmit the data to the slave or the master at the subsequent stage. When the output enabling / disabling information received by the previous slave is set to an output enabling / disabling state, the control unit resets the output enabling / disabling information to a non-output state and sequentially outputs own data, and before the timing of data transmission by the next slave, the control unit sets the output enabling / disabling information to an output enabling / disabling state and outputs the output enabling / disabling information, and outputs the output enabling / disabling information to an output enabling / disabling state before the timing of data transmission by the next slave. Therefore, the number of terminals is not increased, the circuit scale is not increased, and the power consumption is prevented from being increased.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a slave of a time division multiplex system, a method, and a program. BACKGROUND

[0002] In a conventional time division multiplex system (TDM system), a slave is known to have four terminals, a system clock input terminal, an output flag input terminal, an output flag output terminal, and a data output terminal (for example, refer to Patent Literature 1).

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: U.S. Patent No. 8619821 Specification SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, in the conventional time division multiplex system described above, a terminal for outputting an output flag of a slave of a later stage must be added.

[0008] Further, since all of the output terminals are connected, a high impedance (Hi-Z) circuit is required, and in addition to the problem of an increase in circuit size, there is a problem of an increase in load capacity and an increase in power consumption.

[0009] The present application has been achieved in view of the above-described circumstances, and has an object to provide a time division multiplex system, a slave, a method, and a program which do not cause an increase in the number of terminals, an increase in circuit size, and an increase in power consumption.

[0010] MEANS FOR SOLVING THE PROBLEMS

[0011] The time division multiplex system of the embodiments has one master and a plurality of slaves, the master and the plurality of slaves constitute a communication network in a ring type, and the slave, when transmitting data including output enable information to a slave of a later stage or the master, resets the output enable information to an output disabled state in a case where the output enable information received from a slave of an earlier stage is set to an output enabled state, sequentially outputs own data, and sets the output enable information to the output enabled state and outputs before a slave of a later stage transmits data.

[0012] EFFECTS OF THE INVENTION

[0013] The time division multiplex system, the slave, the method, and the program according to the present application do not cause an increase in the number of terminals, an increase in circuit size, and an increase in power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1is a schematic configuration block diagram of an intelligent speaker device of a time division multiplex system having an embodiment.

[0015] Figure 2 is a configuration explanatory diagram of one example of a sound processing section.

[0016] Figure 3 is an explanatory diagram of a communication system between an MPU and a sound processing section.

[0017] Figure 4 is a diagram of one example of a data format of time division multiplex data of an embodiment.

[0018] Figure 5 is a data format of one example of time slot data corresponding to each slave.

[0019] Figure 6 is an explanatory diagram of a detailed data format of time slot data.

[0020] Figure 7 is an explanatory diagram of a data forwarding state.

[0021] Figure 8 is a flowchart of a data forwarding process of a slave. DETAILED DESCRIPTION

[0022] Next, an embodiment will be described with reference to the drawings.

[0023] Figure 1 is a schematic configuration block diagram of an intelligent speaker device of a time division multiplex system having an embodiment.

[0024] The intelligent speaker device 10 is provided with an MPU 11, a memory section 12, a wireless communication interface (I / F) section 13, a wired communication interface (I / F) section 14, a sound processing section 15, an operation input section 16, a display section 17, an audio output section 18, and a power supply unit 19.

[0025] The MPU 11 controls the entire intelligent speaker device 10.

[0026] The memory section 12 is provided with a RAM as a work table, a flash memory or the like that holds various data as a nonvolatile memory that can be updated, and the like.

[0027] The wireless communication interface (I / F) section 13 is provided with wifi, Bluetooth (registered trademark), and the like, and performs communication with a smartphone, a personal computer, and the like via a wireless communication network.

[0028] The wired communication interface (I / F) section 14 is provided with an Ethernet or the like, and performs communication with a smartphone, a personal computer, and the like via a wired communication network via a communication cable.

[0029] The sound processing section 15 processes the input sound to convert it into input sound data, and outputs it to the MPU 11.

[0030] The operation input section 16 has a plurality of operation members such as a touch panel, operation buttons, and the like, and the user performs various operations.

[0031] The display section 17 has an LED indicator lamp, and displays various information.

[0032] The audio output section 18 performs digital / analog conversion of the sound data input from the MPU 11, and performs acoustic output from a speaker.

[0033] Figure 2 is a configuration explanatory view of an example of a sound processing section.

[0034] The sound processing section 15 has a plurality of (four in the example of Figure 2 the sound processing section 15 has a plurality of (four in the example of

[0035] Each of the microphone units 21-1 to 21-4 has a microphone 21A, an analog / digital converter 21B that performs analog / digital conversion of the output of the microphone 21A and outputs it as input sound data, and a controller 21C that performs control of data transmission and the like.

[0036] Figure 3 is an explanatory view of a communication system between the MPU and the sound processing section.

[0037] The MPU 11 functioning as a master has a system clock output terminal O_SCK, a frame clock output terminal O_WS, and a data input terminal SDI.

[0038] The MPU 11 functioning as a master outputs a system clock signal SCK from the system clock output terminal O_SCK, and outputs a frame clock signal WS from the frame clock output terminal O_WS.

[0039] Here, the system clock signal SCK is connected to the clock input terminal I_SCK of all slaves.

[0040] The frame clock signal WS from the MPU 11 functioning as a master is connected only to the data input terminal I_DT of the slave SL1, which is the primary slave, that is, the microphone unit 21-1.

[0041] Each of the slaves SL1 to SL3 (the microphone units 21-1 to 21-3 in the example of Figure 2 the example of transmits the data from the output terminal O_DT to the data input terminal I_DT of the slave of the next stage.

[0042] Furthermore, only the final-level slave (in Figure 2 In the example, the output terminal O_DT of the microphone unit 21-64 is connected to the data input terminal SDI of the MPU, which functions as the host.

[0043] In this case, when the number of slaves is set to M, the frame clock frequency is set to fs, and the bit width of one time slot is set to N, the clock frequency fsck, which is the frequency of the system clock signal SCK, becomes fsck = fs × M × N.

[0044] In addition, the MPU11, which functions as the master unit, needs to be set to a clock frequency fsck corresponding to the number of slave units.

[0045] Furthermore, the microphone units 21-1 to 21-4, which function as slave devices respectively, can identify the number of slave devices. In the case of a primary slave device, there are methods for identification from the master device via I2C and methods for automatic identification from the slave device itself based on the cycles of fsck and fs.

[0046] Furthermore, in the case of a slave device, the number of slave devices can be automatically identified based on the period of the output flag and the period of fsck within the set data.

[0047] On the other hand, the microphone units 21-1 to 21-4, which function as slave devices, each include: a microphone 21A that converts input sound into an input sound signal (analog signal) and outputs it; an analog-to-digital converter (ADC) 21B that performs analog-to-digital conversion of the input sound signal and outputs it as audio data as described later; and a controller 21C.

[0048] In this case, the MPU11, which functions as the host, and the microphone units 21-1 to 21-4, which function as slaves, form a ring network that sequentially forwards time-division multiplexed data from the microphone units 21-1 to 21-4 to the MPU11.

[0049] That is, by outputting the frame clock signal WS through the MPU11, which functions as the host, the data is transmitted in the order of microphone unit 21-1 → microphone unit 21-2 → microphone unit 21-3 → microphone unit 21-4 → MPU11.

[0050] Figure 4 This is a diagram illustrating an example of the data format for time-division multiplexing data in an implementation method.

[0051] exist Figure 4 The image shows two frames of Time Division Multiplexing Data (DTDM). DTDM is composed of so-called frame data, and one frame can time-division multiplex the data of four slave devices.

[0052] Time-division multiplexed data (DTDM) has four time slots (SLT1 to SLT4) corresponding to the slave device in one frame.

[0053] therefore, Figure 4 Time Division Multiplexing (DTDM) data can forward audio data from 4 slave units, or 4 microphone units, per frame.

[0054] More specifically, at time t0, when the frame clock signal WS rises, for example, after time t1 when the frame clock signal WS falls, data is sequentially transmitted from slave devices SL1 to SL4 to MPU11, which functions as the master. Alternatively, data transmission can also occur when the frame clock signal WS rises.

[0055] Figure 5 This is an example of the data format for the time slot data corresponding to each slave device.

[0056] In this embodiment, such as Figure 5 As shown, the data length of the time slot data DT is set to a fixed length of 32 bits. However, the data length of the time slot data DT is not limited to 32 bits and can be set to any number of bits.

[0057] Figure 6 This is a diagram illustrating the detailed data format of the time slot data.

[0058] The time slot data DT consists of 24 bits of audio data DTa and 8 bits of control data DTc.

[0059] In this case, the audio data DTa data format can be appropriately set according to the specifications of the smart speaker device 10. For example, I2S, Sound-Wire, TDM, etc. can be used.

[0060] The control data DTc includes fixed value data Dfx, format bits Dfm, and output flag bits Dof.

[0061] exist Figure 6 In the example, from the upper bit side to the lower bit side, the fixed value data Dfx is 6 bits, the format bit Dfm and the output flag bit Dof are each 1 bit, totaling 8 bits.

[0062] The fixed-value data Dfx is used to identify the positions of the audio data DTa, format bits Dfm, and output marker bits Dof, and can select any bit width and any value.

[0063] Furthermore, the slave unit of the subsequent stage confirms that the fixed value data Dfx has been input. If it can then confirm that the output flag bit Dof (="1") is 1, it will output its own audio data DTa and control data DTc to the slave unit of the subsequent stage.

[0064] If the bit width of the fixed-value data Dfx is small, it may not be able to be separated from the audio data DTa, leading to false detections. Furthermore, increasing the bit width of the fixed-value data Dfx can suppress false detections, but correspondingly, the amount of information usable as audio data DTa decreases, thus eliminating its correlation with the audio data. Therefore, the detection accuracy and the accuracy of the audio data DTa become a trade-off.

[0065] The lowest bit in the control data DTc is the output flag bit Dof.

[0066] The output flag bit DoF serves as output capability information, indicating whether the slave device can output its own data.

[0067] Then, the slave device that receives the output flag bit Dof from the slave device of the preceding stage and has it enabled ("1" in the following description) updates the audio data DTa of its corresponding time slot in the time division multiplexed data DTDM, and outputs it to the slave or master device of the following stage.

[0068] In this case, each slave device processes the audio data DTa corresponding to the slave device in the preceding stage or the audio data DTa corresponding to itself, based on the control data DTc, and outputs it to the slave device or master device in the following stage.

[0069] Figure 7 This is a diagram illustrating the data forwarding status.

[0070] Figure 8 This is a flowchart of the data forwarding process for the slave device.

[0071] exist Figure 7 In the audio data DTa, "D_init" indicates a state where no valid data has been stored yet. For example, it is data where all 24 bits are 0, indicating the initial state.

[0072] Furthermore, in the following explanation, the time required for the data corresponding to a timeslot to be forwarded to the next-level slave device will be referred to as the unit timeslot time.

[0073] Furthermore, the time from the latest timing when the frame clock signal WS transitions to the "H" level to the time until the unit time slot elapses is called the first time slot period; the time from the timing of the first time slot period to the time until the unit time slot elapses is called the second time slot period; the time from the timing of the second time slot period to the time until the unit time slot elapses is called the third time slot period; and the time from the timing of the third time slot period to the time until the unit time slot elapses is called the fourth time slot period.

[0074] Figure 7(A) is an explanatory diagram of the input and output data in the microphone unit 21-1, which functions as a slave device.

[0075] First, the controller 21C of the microphone unit 21-1, which functions as a slave device, determines during the first time slot whether a frame clock signal WS has been input to the input terminal I_DT. Figure 8 Step S11).

[0076] In this case, the latest frame clock signal WS is input as input data from the MPU11, which functions as the host, to the input terminal I_DT. Figure 8 Step S11; Yes), therefore the controller 21C of the microphone unit 21-1, which functions as a slave SL1, outputs its own transmission data ( Figure 8 Step S13).

[0077] More specifically, the controller 21C of the microphone unit 21-1 outputs 24 bits of audio data DTa-1 bit by bit during the data transmission timing corresponding to the first time slot.

[0078] Next, the controller 21C1 of microphone unit 21-1 outputs 8 bits of control data DTc-1 bit by bit.

[0079] Then, in order to indicate that the corresponding audio data DTa-1 was output during the first time slot, the controller 21C of the microphone unit 21-1 notifies the microphone unit 21-2 that it is in an output-ready state by setting the least significant bit of the control data DTc-1, the output flag bit Dof, to "1". Figure 8 Step S14).

[0080] As a result of the above actions, microphone unit 21-1 transmits its corresponding data, namely the first slave data D_SL1, to microphone unit 21-2 on the downstream side.

[0081] Here, the controller 21C of the microphone unit 21-1 determines whether a frame clock signal WS has been input to the input terminal I_DT during the second time slot to the fourth time slot (step S11).

[0082] In this case, no frame clock signal WS is input to the input terminal I_DT (step S11; no), so the controller 21C of the microphone unit 21-1 determines whether the output of the transmission data of the front-end slave that has input the frame clock signal WS to the input terminal I_DT is in the output state (step S15).

[0083] In this stage, the lowest bit (= the seventh bit) of the control data DTc-1, which is equivalent to the output yes / no information of the transmission data of the front-end slave, is the output flag bit Dof=0, and the output yes / no information is in the no-output state (step S15; no). Therefore, the controller 21C of the microphone unit 21-1 outputs the initial data as transmission data during the second time slot to the fourth time slot and ends the processing (step S16).

[0084] Figure 7 (B) is an explanatory diagram of the input and output data in the microphone unit 21-2, which functions as a slave device.

[0085] During the first time slot, the controller 21C of the microphone unit 21-2, which functions as a slave device, first determines whether a frame clock signal WS has been input to the input terminal I_DT. Figure 8 Step S11).

[0086] exist Figure 8 In step S11, the frame clock signal WS was not input to the input terminal I_DT. Figure 8 Step S11; No), therefore the controller 21C of microphone unit 21-2 determines whether the output status of the transmitted data of the pre-amplifier that input the frame clock signal WS to the input terminal I_DT is output ( Figure 8 Step S15).

[0087] That is, when the transmission of data of microphone unit 21-2, which functions as slave SL2, is completed, the controller 21C extracts the least significant bit of the control data DTc-1 during the first time slot, and determines whether the output flag bit Dof = "1".

[0088] In this case, since the output flag bit Dof, which is the least significant bit of the control data DTc-1 during the first time slot, is "1" ( Figure 8 Step S15; Yes), so the controller 21C of the microphone unit 21-2 determines that it is the one that should update the data next, and resets the output flag bit Dof, which is the lowest bit of the control data DTc-1 during the first time slot, to a non-output state, i.e., "0" ( Figure 8 Step S12).

[0089] Next, the controller 21C of the microphone unit 21-2, which functions as the slave unit SL2, outputs its own transmission data. Figure 8 Step S13).

[0090] More specifically, the controller 21C of the microphone unit 21-2 outputs 24 bits of audio data DTa-1 bit by bit during the data transmission timing corresponding to the first time slot.

[0091] Next, the controller 21C of the microphone unit 21-2 outputs 8 bits of control data DTc-1 bit by bit, with the output flag bit Dof changed.

[0092] Next, the controller 21C of the microphone unit 21-2 outputs 24 bits of audio data DTa-2 bit by bit during the data transmission timing for the second time slot.

[0093] Then, in order to indicate that the corresponding audio data DTa-2 was output during the second time slot, the controller 21C of the microphone unit 21-2 notifies the microphone unit 21-3 that it is in an output-ready state by setting the least significant bit of the control data DTc-2, the output flag bit Dof, to "1". Figure 8 Step S14).

[0094] As a result of the above actions, the controller 21C of microphone unit 21-2 transmits its corresponding data, namely the second slave data D_SL2, and the transmission data from the upstream microphone unit 21-1 to the downstream microphone unit 21-3.

[0095] Figure 7 (C) is an explanatory diagram of the input and output data in the microphone unit 21-3, which functions as a slave device.

[0096] During the second time slot, firstly, the controller 21C of the microphone unit 21-3, which functions as a slave device, determines whether a frame clock signal WS has been input to the input terminal I_DT. Figure 8 Step S11).

[0097] exist Figure 8 In step S11, the frame clock signal WS was not input to the input terminal I_DT. Figure 8 Step S11; No), therefore the controller 21C of microphone unit 21-3 determines whether the output of the transmitted data of microphone unit 21-2, which functions as a pre-amplifier slave (i.e., slave SL2), is in an output state. Figure 8 Step S15).

[0098] That is, when the data transmission of the microphone unit 21-3, which functions as a slave SL3, is completed, the controller 21C extracts the least significant bit of the control data DTc-2 during the second time slot, the output flag bit Dof, and determines whether the output flag bit Dof = "1".

[0099] In this case, since the output flag bit Dof, which is the least significant bit of the control data DTc-2 during the second time slot, is "1" ( Figure 8 Step S15; Yes), so the controller 21C of the microphone unit 21-3 determines that it is the one that should update the data next, and resets the output flag bit Dof, which is the lowest bit of the control data DTc-2 during the second time slot, to a non-output state, i.e., "0" ( Figure 8 Step S12).

[0100] Next, the controller 21C of the microphone unit 21-3, which functions as the slave unit SL3, outputs its own transmission data. Figure 8 Step S13).

[0101] More specifically, during the data transmission timing corresponding to the first time slot, the controller 21C of microphone unit 21-3 first outputs 24 bits of audio data DTa-1 bit by bit. Next, the controller 21C of microphone unit 21-3 outputs 8 bits of control data DTc-1 bit by bit.

[0102] Next, the controller 21C of the microphone unit 21-3 outputs 24 bits of audio data DTa-2 bit by bit during the data transmission timing corresponding to the second time slot, and then outputs 8 bits of control data DTc-2 bit by bit with the output flag bit Dof changed.

[0103] Next, the controller 21C of the microphone unit 21-3 outputs 24 bits of audio data DLT-3 bit by bit during the data transmission timing corresponding to the third time slot, and then outputs 8 bits of control data DTc-3 bit by bit.

[0104] Then, in order to indicate that the corresponding audio data DTa-3 was output during the third time slot, the controller 21C of the microphone unit 21-3 notifies the microphone unit 21-4, which functions as the next-level slave, that it is in an output-ready state by setting the output flag bit Dof, which is the least significant bit of the control data DTc-3, to "1". Figure 8 Step S14).

[0105] As a result of the above actions, the controller 21C of microphone unit 21-3 transmits the third slave data D_SL3, which is the data corresponding to itself, as well as the transmission data from microphone unit 21-1 and microphone unit 21-2 on the upstream side, to microphone unit 21-4 on the downstream side.

[0106] Figure 7 (D) is an explanatory diagram of the input and output data in the microphone unit 21-4, which functions as a slave device.

[0107] During the third time slot, firstly, the controller 21C of the microphone unit 21-4, which functions as a slave device, determines whether a frame clock signal WS has been input to the input terminal I_DT. Figure 8 Step S11).

[0108] exist Figure 8 In step S11, the frame clock signal WS was not input to the input terminal I_DT. Figure 8 Step S11; No), therefore the controller 21C of microphone unit 21-4 determines whether the output of the transmitted data of microphone unit 21-3, which functions as a slave unit SL3 in the preamplifier, is in an output state. Figure 8 Step S15).

[0109] That is, when the data transmission of the microphone unit 21-4, which functions as a slave SL4, is completed, the controller 21C extracts the least significant bit of the control data DTc-3 during the third time slot, the output flag bit Dof, and determines whether the output flag bit Dof = "1".

[0110] In this case, since the output flag bit Dof, which is the least significant bit of the control data DTc-3 during the third time slot, is "1" ( Figure 8 Step S15; Yes), so the controller 21C of the microphone unit 21-4 determines that it is the one that should update the data next, and resets the output flag bit Dof, which is the lowest bit of the control data DTc-3 during the third time slot, to a non-output state, i.e., "0" ( Figure 8 Step S12).

[0111] Next, the controller 21C of the microphone unit 21-4, which functions as the slave unit SL4, outputs its own transmission data. Figure 8 Step S13).

[0112] More specifically, during the data transmission timing corresponding to the first time slot, the controller 21C of microphone unit 21-4 first outputs 24 bits of audio data DTa-1 bit by bit. Next, the controller 21C of microphone unit 21-4 outputs 8 bits of control data DTc-1 bit by bit.

[0113] Next, the controller 21C of the microphone unit 21-4 outputs 24 bits of audio data DTa-2 bit by bit during the data transmission timing corresponding to the second time slot, and then outputs 8 bits of control data DTc-2 bit by bit.

[0114] Furthermore, during the data transmission timing corresponding to the third time slot, the controller 21C of the microphone unit 21-4 outputs 24 bits of audio data DLT-3 bit by bit, and then outputs 8 bits of control data DTc-3 bit by bit with the output flag bit Dof changed.

[0115] Furthermore, the controller 21C of the microphone unit 21-4 outputs 24 bits of audio data DTa-4 bit by bit during the data transmission timing corresponding to the fourth time slot, and then outputs 8 bits of control data DTc-4 bit by bit.

[0116] Furthermore, in order to indicate that the corresponding audio data DTa-4 was output during the fourth time slot, the controller 21C of the microphone unit 21-4 notifies the MPU11, which functions as the host, by setting the output flag bit Dof, which is the least significant bit of the control data DTc-4, to "1".

[0117] Therefore, the MPU11, which functions as the host, can detect the end of data transmission.

[0118] As a result of the above actions, microphone unit 21-4 transmits its own data and the transmission data from microphone units 21-1 to microphone units 21-3 on the upstream side to MPU11 on the downstream side.

[0119] That is, at the end of the fourth time slot, all audio data DTa from microphone units 21-1 to 21-4 is transmitted to MPU11, which functions as the host.

[0120] Here, the parallel operation of the controller 21C for microphone units 21-1 to 21-4 will be explained.

[0121] During the first time slot, in parallel with the operation of the controller 21C of microphone unit 21-1, the controllers 21C of microphone units 21-2 to 21-4 determine whether a frame clock signal WS has been input to the input terminal I_DT. Figure 8 Step S11).

[0122] In this case, no frame clock signal WS is input to the input terminal I_DT. Figure 8 Step S11; No), therefore, the controller 21C of microphone units 21-2 to 21-4 determines whether the output status of the transmission data of the pre-amplifier that input the frame clock signal WS to the input terminal I_DT is output ( Figure 8 Step S15).

[0123] In this stage, the lowest bit of the control data DTc-1, which is equivalent to the output permission information of the preceding slave device, i.e., the output flag bit Dof = 0, indicating that the output permission information is not output. Figure 8 Step S15; No), therefore, the controller 21C of microphone units 21-2 to 21-4 outputs the initial data as transmission data during the first time slot and ends the processing ( Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Step S16).

[0124] Furthermore, during the second to fourth time slots, the same actions are performed in parallel as during the first time slot.

[0125] As described above, the MPU11 processes the audio data DTa transmitted from the microphone units 21-1 to 21-4 and transmits the sound data to a smartphone or personal computer via a wireless communication interface or a wired communication interface for use as sound for calls, web conferencing, etc.

[0126] Effects of the implementation method

[0127] As explained above, the above embodiments do not result in an increase in the number of terminals or an increase in circuit size, and can suppress an increase in power consumption.

[0128] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0129] For example, in the above description, a 1-bit output flag bit is used as output permission information to indicate whether or not one can output its own data, but it can also be configured as multi-bit information.

[0130] -Explanation of Figure Markers-

[0131] 10 Smart Speaker Devices

[0132] 11 MPU

[0133] 12. Memory Section

[0134] 13 Wireless Communication Interface Section

[0135] 14 Wired Communication Interface Section

[0136] 15. Sound Processing Department

[0137] 16 Operation Input Section

[0138] 17 Display Section

[0139] 18 Audio Output Section

[0140] 19 Power Supply Units

[0141] Microphone units 21-1 to 21-4

[0142] 21A microphone

[0143] 21B Analog / Digital Converter

[0144] 21C Controller

[0145] D_SL1 First Slave Data

[0146] D_SL2 Second Slave Data

[0147] D_SL3 Third Slave Data

[0148] D_SL4 Fourth Slave Data

[0149] DT time slot data

[0150] DTDM (Time Division Multiplexing) data

[0151] DTa audio data

[0152] DTc control data

[0153] Dfm format bits

[0154] Dfx fixed value data

[0155] DoF output flag bits

[0156] I_DT Data Input Terminal

[0157] O_DT data output terminal

[0158] O_SCK System Clock Output Terminal

[0159] O_WS frame clock output terminal

[0160] SCK system clock signal

[0161] SDI data input terminals

[0162] SL1~SL4 slave

[0163] SLT1~SLT4 time slots

[0164] I_SCK clock input terminal

[0165] WS frame clock signal.

Claims

1. A time-division multiplexing system, comprising one master and multiple slave devices, characterized in that, The host and the multiple slave devices form a ring-shaped communication network. When the slave device transmits data including output yes / no information to a subsequent slave device or master device, if the output yes / no information received from the preceding slave device is set to an output-enabled state, it resets the output yes / no information to an output-disabled state and outputs its own data sequentially. Before the timing of data transmission by the lower-level slave device, the output availability information is set to an output-ready state and then output.

2. The time-division multiplexing system according to claim 1, wherein, Output flags are used as output yes / no information.

3. The time-division multiplexing system according to claim 1, wherein, If the host is input with output capability information indicating whether it is set to the output capability state, the data transmission ends.

4. The time-division multiplexing system according to claim 1, wherein, The slave device obtains the total number of slave devices constituting the time-division multiplexing system by receiving a notification from the master device, or by automatically obtaining the total number of slave devices constituting the time-division multiplexing system by counting the number of system clocks within one clock frame.

5. The time-division multiplexing system according to claim 1, wherein, The data mentioned includes audio data and control data. The slave device processes the audio data based on the control data and outputs it to the slave device in the next stage or to the master device.

6. A slave device capable of cooperating with a master device and other slave devices to form a ring-shaped communication network, said ring-shaped communication network constituting a time-division multiplexing system, characterized in that, When transmitting data including output yes / no information to the slave or master device at the next level, if the output yes / no information received from the slave device at the previous level is set to an output-enabled state, the output yes / no information is reset to an output-disabled state, and the data is output sequentially. Before the timing of data transmission by the lower-level slave device, the output availability information is set to an output-ready state and then output.

7. A method executed by a slave device, wherein the slave device, together with a master device and other slave devices, forms a ring-shaped communication network, the ring-shaped communication network constituting a time-division multiplexing system, characterized in that, The method comprises the following steps: When transmitting data including output yes / no information to the slave or master device at the next level, if the output yes / no information received from the slave device at the previous level is set to an output-enabled state, the output yes / no information is reset to an output-unenabled state, and the data is output sequentially. as well as Before the timing of data transmission by the lower-level slave device, the output availability information is set to an output-ready state and then output.

8. A program for controlling a slave device via a computer, the slave device being capable of cooperating with a master device and other slave devices to form a ring-shaped communication network, the ring-shaped communication network constituting a time-division multiplexing system, characterized in that, The computer functions as a unit in the following ways: When transmitting data including output yes / no information to the slave or master device at the next level, if the output yes / no information received from the slave device at the previous level is set to an output-enabled state, the output yes / no information is reset to an output-unenabled state, and the data is output sequentially. as well as Before the timing of data transmission by the lower-level slave device, the output availability information is set to an output-ready state and then output.

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