Differential type serial underwater acoustic chip array structure and chip

Abstract

The application discloses a differential series underwater acoustic chip array structure and a chip, and belongs to the technical field of micro-electro-mechanical systems. The chip array structure is sequentially provided with upper electrode positive and negative ends, a piezoelectric layer, interconnection lines embedded in and penetrating the upper and lower electrode positive and negative ends, and an insulating layer and lower electrode positive and negative ends penetrating the insulating layer from top to bottom. The above structure is deposited on an SOI layer, and the SOI layer is sequentially provided with a device silicon layer, a buried oxygen layer and a back substrate from top to bottom. The cavities are arranged on the back substrate, and the cavities penetrate the back substrate from bottom to top, and each cavity defines a chip unit. The upper and lower electrodes are electrically connected to adjacent chip units through the upper and lower electrode positive and negative interconnection lines, and a chip-level differential series structure is formed. The application improves the array output voltage through reasonable differential positive and negative electrode series array arrangement, and further improves the chip sensitivity.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of micro-electro-mechanical systems, and particularly relates to a differential series hydroacoustic chip array structure and a chip. BACKGROUND

[0002] The piezoelectric acoustic chip is mainly used for hydrophones, but is not limited to hydrophones. The hydrophone is a key component of a hydroacoustic monitoring system. In the hydrophone, the main device for electric-acoustic conversion is an acoustic sensor chip, and the electric-acoustic conversion efficiency of the chip determines the performance of the hydrophone. The main quantitative standard for the electric-acoustic conversion efficiency is the sensitivity of the chip. The higher the sensitivity, the more excellent the electric-acoustic conversion efficiency. The piezoelectric acoustic chip mainly improves the sensitivity of the chip by improving the chip structure.

[0003] At present, the improvement of the chip structure mainly focuses on the improvement of the unit structure, and the chip array is generally arranged in parallel. For example, a MEMS piezoelectric film acoustic chip array is composed of a bottom SOI substrate, upper and lower electrodes and a piezoelectric film located between the upper and lower electrodes. The upper electrode is composed of an electrode wafer located in the central region of the piezoelectric film and an outer lead, both of which are electrically conductive and are in direct contact with the piezoelectric film. When the piezoelectric film acoustic chip array is deformed by a force, positive charges are generated in the central 70% region of the piezoelectric film, and heterogeneous charges are generated in the edge 20% region. The lead wire passes through the 20% heterogeneous charge region and is interconnected with the electrode wafer. The chip array structure improves the reliability, but does not improve the output voltage, and the improvement of the sensitivity is limited.

[0004] For example, a Chinese invention patent with the authorization announcement number CN114034377B discloses a double-layer AIN piezoelectric film hydrophone chip unit, a chip and a hydrophone. The chip unit includes an SOI substrate, a first AIN piezoelectric layer, a first electrode layer, a separation layer, a second AIN piezoelectric layer and a second electrode layer arranged in order from bottom to top. The chip is arranged in parallel, but the unit adopts a piezoelectric stack structure, which improves the output voltage and the sensitivity, but due to the limitation of the process, the more the layers, the more difficult the polarization, and the more serious the stress accumulation between the layers, so the effect is limited. SUMMARY

[0005] Based on the above technical problems, the application provides a differential series hydroacoustic chip array structure and a chip.

[0006] The technical solution adopted by the application is as follows:

[0007] A differential series hydroacoustic chip array structure includes an SOI layer, an insulating layer and a sensitive structure layer arranged in order from bottom to top, and the sensitive structure layer includes an upper electrode positive terminal, an upper electrode negative terminal, a piezoelectric layer, a lower electrode positive terminal, a lower electrode negative terminal, an upper and lower electrode positive terminal interconnection line and an upper and lower electrode negative terminal interconnection line.

[0008] The upper electrode positive end and the upper electrode negative end are arranged on the upper side of the piezoelectric layer, the lower electrode positive end and the lower electrode negative end are arranged on the lower side of the piezoelectric layer, the upper electrode negative end is arranged outside the edge of the upper electrode positive end, the lower electrode negative end is arranged outside the edge of the lower electrode positive end, and the upper electrode positive end is directly above the lower electrode positive end, and the upper electrode negative end is directly above the lower electrode negative end.

[0009] The SOI layer is provided with cavities, and the upper electrode positive end, the upper electrode negative end, the lower electrode positive end and the lower electrode negative end are all directly above the cavities, and each cavity defines a chip unit.

[0010] The lower electrode positive end is connected with the upper electrode positive end of the adjacent chip unit through the upper and lower electrode positive end interconnection line, and the lower electrode negative end is connected with the upper electrode negative end of the adjacent chip unit through the upper and lower electrode negative end interconnection line, so that the adjacent chip units are arranged in series.

[0011] The chip units are arranged in an array, and a plurality of chip units form a chip array structure.

[0012] Preferably, the upper electrode positive end and the lower electrode positive end are both in the shape of a circular disc, and the upper electrode negative end and the lower electrode negative end each include two arc-shaped segments symmetrically arranged on both sides of the edge of the upper electrode positive end or the lower electrode positive end.

[0013] Preferably, the upper electrode positive end is directly above the center region of the cavity, and occupies an area of 70% of the area of the chip unit; and the upper electrode negative end occupies an area of 20% of the outer edge of the chip unit.

[0014] Preferably, the upper electrode positive end is connected with a first connecting line, the lower electrode positive end is connected with a second connecting line, the first connecting line and the second connecting line are arranged in opposite directions, and the first connecting line and the second connecting line are connected through the upper and lower electrode positive end interconnection line; the two arc-shaped segments of the upper electrode negative end are respectively connected with a third connecting line and a fourth connecting line, and the two arc-shaped segments of the lower electrode negative end are respectively connected with a fifth connecting line and a sixth connecting line, the third connecting line and the fifth connecting line are connected through the upper and lower electrode negative end interconnection line, and the fourth connecting line and the sixth connecting line are connected through the upper and lower electrode negative end interconnection line; and through holes corresponding to the upper and lower electrode positive end interconnection line and the upper and lower electrode negative end interconnection line are arranged at corresponding positions on the piezoelectric layer.

[0015] Preferably, the upper electrode positive end of one of the chip units in the chip array structure is connected with an upper electrode positive end output line, and the upper electrode negative end is connected with an upper electrode negative end output line; the lower electrode positive end of one of the chip units is connected with a lower electrode positive end output line, and the lower electrode negative end is connected with a lower electrode negative end output line; and through holes corresponding to the upper electrode negative end output line and the lower electrode negative end output line are arranged at corresponding positions on the piezoelectric layer.

[0016] Preferably, the insulating layer is provided with embedding entrances matched with the positive end of the upper electrode, the negative end of the upper electrode, the positive end of the lower electrode, the negative end of the lower electrode, the second connecting wire, the fifth connecting wire and the sixth connecting wire, and the insulating layer is equal in thickness to the positive end of the upper electrode, the negative end of the upper electrode, the positive end of the lower electrode, the negative end of the lower electrode, the second connecting wire, the fifth connecting wire and the sixth connecting wire.

[0017] Preferably, the SOI layer comprises a back substrate, a buried oxygen layer and a device silicon layer arranged in sequence from bottom to top, and the cavity is arranged on the back substrate and penetrates the back substrate from bottom to top.

[0018] Preferably, the positive end of the upper electrode, the negative end of the upper electrode, the positive end of the lower electrode and the negative end of the lower electrode are Mo electrodes; and the upper and lower electrode positive end interconnection wire, the upper and lower electrode negative end interconnection wire, the first connecting wire, the second connecting wire, the third connecting wire, the fourth connecting wire, the fifth connecting wire and the sixth connecting wire are all made of Mo material.

[0019] Preferably, the insulating layer is made of silicon dioxide or silicon nitride material; and the piezoelectric layer is made of AlN, ZnO2 or PZT material.

[0020] The application further provides a differential series-connected underwater acoustic chip array structure.

[0021] The application has the following beneficial technical effects:

[0022] The piezoelectric underwater acoustic chip array structure constructed by the application adopts chip units arranged in an array, and the positive end of the upper electrode and the positive end of the lower electrode, and the negative end of the upper electrode and the negative end of the lower electrode between adjacent chip units are arranged in series; the application improves the array output voltage by reasonably arranging the differential series-connected positive and negative electrodes in an array, thereby improving the sensitivity of the chip. Moreover, the chip array structure adopted by the application can unlimitedly increase the chip units while improving the output voltage, can overcome the processing drawbacks of the stacked structure, and the chip-level series connection also significantly reduces the circuit loss. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 FIG. 1 is a structural schematic diagram of an embodiment of the differential series-connected underwater acoustic chip array structure of the application;

[0024] Figure 2 FIG. 2 is an exploded view of an embodiment of the differential series-connected underwater acoustic chip array structure of the application;

[0025] Figure 3 FIG. 3 is a structural schematic diagram of the insulating layer and the sensitive structure layer of the differential series-connected underwater acoustic chip array structure of the application;

[0026] Figure 4The differential array structure is an electrical schematic diagram; wherein (a) is a four-array series array schematic diagram of the application, and (b) is a traditional four-layer series array schematic diagram.

[0027] In the figure: 101 - insulation layer, 102 - upper electrode positive terminal, 103 - upper electrode negative terminal, 104 - piezoelectric layer, 105 - lower electrode positive terminal, 106 - lower electrode negative terminal, 107 - upper and lower electrode positive terminal interconnection line, 108 - upper and lower electrode negative terminal interconnection line, 109 - device silicon layer, 110 - cavity, 111 - back substrate, 112 - buried oxygen layer, 113 - first connecting line, 114 - second connecting line, 115 - third connecting line, 116 - fourth connecting line, 117 - fifth connecting line, 118 - sixth connecting line, 119 - via hole, 120 - upper electrode positive terminal output line, 121 - upper electrode negative terminal output line, 122 - lower electrode positive terminal output line, 123 - lower electrode negative terminal output line, 124 - through hole, and 125 - embedding entrance. DETAILED DESCRIPTION

[0028] The existing series array structure of the underwater acoustic chip, such as the multi-layer stacked structure, has the following disadvantages:

[0029] (1) Stress accumulation: The core of the multi-layer stacked structure is to enhance the piezoelectric effect (such as displacement output or charge collection) through series connection. However, each layer of piezoelectric material will generate internal stress under the action of an electric field (such as the expansion and contraction deformation caused by the inverse piezoelectric effect of piezoelectric ceramics). The more the number of layers, the more serious the stress accumulation between the layers. When the stress exceeds the bending strength or the interfacial bonding strength of the material, it will cause interlayer cracking, delamination, and damage to the integrity of the structure, thereby losing the piezoelectric performance.

[0030] (2) Difficult polarization: Piezoelectric materials need to be polarized to ensure piezoelectric performance. After the traditional stacked electrode multi-layer stacking, the internal electric field distribution is more complex, and the polarization electric field (such as electric field strength and direction) needs to be optimized to ensure the polarization consistency of each layer of material. The more the number of layers, the more difficult the polarization. Therefore, it cannot be stacked indefinitely.

[0031] Based on this, the application proposes a differential series array structure of an underwater acoustic chip and a chip, and the core mechanism is to construct an internal and external differential series array, which can obtain double the number of series connection of the traditional wafer electrode array, significantly improve the output voltage, and thus improve the sensitivity.

[0032] The application will be further described in conjunction with the drawings and specific embodiments.

[0033] With reference to the drawings, a differential type serial hydrophone chip array structure comprises, from bottom to top, an SOI layer, an insulating layer 101 and a sensitive structure layer, wherein the sensitive structure layer comprises an upper electrode positive terminal 102, an upper electrode negative terminal 103, a piezoelectric layer 104, a lower electrode positive terminal 105, a lower electrode negative terminal 106, an upper-lower electrode positive terminal interconnection line 107 and an upper-lower electrode negative terminal interconnection line 108. The upper electrode positive terminal 102 and the upper electrode negative terminal 103 are arranged on the upper side of the piezoelectric layer 104, and the lower electrode positive terminal 105 and the lower electrode negative terminal 106 are arranged on the lower side of the piezoelectric layer 104. The upper electrode negative terminal 103 is arranged outside the edge of the upper electrode positive terminal 102, the lower electrode negative terminal 106 is arranged outside the edge of the lower electrode positive terminal 105, and the upper electrode positive terminal 102 is directly above the lower electrode positive terminal 105, and the upper electrode negative terminal 103 is directly above the lower electrode negative terminal 106.

[0034] As shown in Figure 1 , Figure 2 , the upper electrode positive terminal 102 and the lower electrode positive terminal 105 are both in the shape of a circular wafer, i.e., a circular wafer-shaped electrode. The upper electrode negative terminal 103 and the lower electrode negative terminal 106 each comprise two arc-shaped segments symmetrically arranged on both sides of the edge of the upper electrode positive terminal 102 or the lower electrode positive terminal 105.

[0035] The SOI layer comprises, from bottom to top, a back substrate 111, a buried oxygen layer 112 and a device silicon layer 109, and a cavity 110 is arranged on the back substrate 111. The cavity 110 penetrates through the back substrate 111 from bottom to top. The upper electrode positive terminal 102, the upper electrode negative terminal 103, the lower electrode positive terminal 105 and the lower electrode negative terminal 106 are all directly above the cavity 110, and each cavity 110 defines a chip unit. That is, each cavity 110 and the upper electrode positive terminal 102, the upper electrode negative terminal 103, the lower electrode positive terminal 105 and the lower electrode negative terminal 106 arranged above it can be regarded as a chip unit.

[0036] The upper electrode positive terminal 102 is directly opposite the central region of the cavity 110 and occupies an area of 70% of the chip unit. The upper electrode negative terminal 103 occupies an area of 20% of the outer edge of the chip unit. The lower electrode positive terminal 105 and the upper electrode positive terminal 102 are arranged directly opposite each other, and the lower electrode negative terminal 106 and the upper electrode negative terminal 103 are arranged directly opposite each other. Therefore, the lower electrode positive terminal 105 and the lower electrode negative terminal 106 each occupy an area of 70% of the chip unit and an area of 20% of the outer edge of the chip unit.

[0037] As shown in Figure 2 , the lower electrode positive terminal 105 is connected to the upper electrode positive terminal of the adjacent chip unit through the upper-lower electrode positive terminal interconnection line 107, and the lower electrode negative terminal 106 is connected to the upper electrode negative terminal of the adjacent chip unit through the upper-lower electrode negative terminal interconnection line 108, so that the adjacent chip units are arranged in series.

[0038] The chip units are multiple and arranged in an array, forming a chip array structure. For example... Figure 1 , Figure 2 The diagram shows a layout of four chip units arranged in a row. Of course, this connection method can be used to expand horizontally and vertically to form a matrix array structure.

[0039] As a further design of the present invention, such as Figure 2 As shown, the upper electrode's positive end is connected to the first connecting line 113, and the lower electrode's positive end is connected to the second connecting line 114. The first connecting line 113 and the second connecting line 114 are staggered vertically and arranged facing each other, within the same vertical plane. The first connecting line 113 and the second connecting line 114 are connected by an interconnecting line 107 between the upper and lower electrode positive ends, which is arranged vertically. That is, the top surface of the interconnecting line 107 directly contacts the bottom surface of the end of the first connecting line 113, and the bottom surface of the interconnecting line 107 directly contacts the top surface of the end of the second connecting line 114, thus forming an electrical connection. The two arc-shaped segments at the negative end of the upper electrode are respectively connected to the third connecting line 115 and the fourth connecting line 116, and the two arc-shaped segments at the negative end of the lower electrode are respectively connected to the fifth connecting line 117 and the sixth connecting line 118. Similar to the arrangement of the first and second connecting lines, the third connecting line 115 and the fifth connecting line 117 are staggered vertically and facing each other in the same vertical plane, and the fourth connecting line 116 and the sixth connecting line 118 are staggered vertically and facing each other in the same vertical plane. The third and fifth connecting lines, and the fourth and sixth connecting lines, are connected by the upper and lower electrode negative end interconnecting lines 108, that is, two upper and lower electrode negative end interconnecting lines 108 are provided and arranged vertically. If the top surface of one of the upper and lower electrode negative end interconnecting lines is in direct contact with the bottom surface of the end of the third connecting line, and the bottom surface of the upper and lower electrode negative end interconnecting line is in direct contact with the top surface of the end of the fourth connecting line, electrical conductivity is formed. Through holes 119 are provided at corresponding positions in the piezoelectric layer 104 to match the interconnection lines of the positive and negative ends of the upper and lower electrodes, respectively.

[0040] As can be seen, the positive terminal of the upper electrode is connected to the positive terminal of the lower electrode of the adjacent chip unit through the interconnection line between the positive terminals of the upper and lower electrodes, thus forming an electrical connection. The negative terminal of the upper electrode is connected to the negative terminal of the lower electrode of the adjacent chip unit through the interconnection line between the negative terminals of the upper and lower electrodes, thus forming an electrical connection.

[0041] One of the chip units in the chip array structure (such as...) Figure 1 , Figure 2 The positive terminal of the upper electrode of the leftmost chip unit is connected to the positive terminal output line 120, and the negative terminal of the upper electrode is connected to the negative terminal output line 121. One of the chip units (e.g....) Figure 1 , Figure 2The lower electrode positive end of the rightmost chip unit in the array, or the chip unit at the end of the array, is connected to the lower electrode positive end output line 122, and the lower electrode negative end is connected to the lower electrode negative end output line 123. The through hole 124 corresponding to the upper electrode negative end output line and the lower electrode negative end output line is arranged at the corresponding position on the piezoelectric layer. That is, the piezoelectric layer is thick and perfectly matched with the upper and lower electrode positive end interconnection lines, the upper and lower electrode negative end interconnection lines, the lower electrode positive end output line 122, the lower electrode negative end output line 123, and the like.

[0042] The upper electrode positive end output line 120, the upper electrode negative end output line 121, the lower electrode positive end output line 122, and the lower electrode negative end output line 123 can be connected to another row of edge chip units, or can be used as the total output line of the chip array structure.

[0043] Further, the insulating layer 101 is provided with an embedded entrance 125 matched with the lower electrode positive end, the lower electrode negative end, the second connecting line, the fifth connecting line, and the sixth connecting line. As shown in the figure, the embedded entrance 125 is matched with the shape and size of the lower electrode positive end, the lower electrode negative end, and the connecting lines. Figure 2 The insulating layer 101 is thick with the lower electrode positive end, the lower electrode negative end, the second connecting line, the fifth connecting line, and the sixth connecting line. That is, the insulating layer is thick and perfectly matched with the lower electrode positive end, the lower electrode negative end, the second connecting line, the fifth connecting line, and the sixth connecting line.

[0044] The upper electrode positive end 102, the upper electrode negative end 103, the lower electrode positive end 105, and the lower electrode negative end 106 are all Mo electrodes. The upper and lower electrode positive end interconnection lines 107, the upper and lower electrode negative end interconnection lines 108, the first connecting line 113, the second connecting line 114, the third connecting line 115, the fourth connecting line 116, the fifth connecting line 117, and the sixth connecting line 118 are all made of Mo material.

[0045] The insulating layer 101 is made of silicon dioxide or silicon nitride material, and of course other insulating materials can also be used. The piezoelectric layer 104 is made of AlN, ZnO2, or PZT material, and of course other piezoelectric materials can also be used.

[0046] The application also provides a differential series underwater acoustic chip, which uses a plurality of differential series underwater acoustic chip array structures as described above, and all the underwater acoustic chip array structures are connected in series.

[0047] In summary, the application discloses a differential series underwater acoustic chip array structure taking four chip units as an example, which is arranged from top to bottom as a positive electrode end and a negative electrode end of an upper electrode, a piezoelectric layer, an interconnection line embedded in and penetrating through the positive electrode end and the negative electrode end of the upper and lower electrodes, and an insulating layer and a positive electrode end and a negative electrode end penetrating through the insulating layer. The structure is deposited on an SOI layer, and the SOI layer is sequentially composed of a top silicon layer (a device silicon layer), a buried oxygen layer and a substrate layer (a back substrate). The substrate layer has a cavity and defines a chip unit. The upper and lower electrodes are electrically connected to adjacent chip units through the interconnection line of the positive electrode end and the negative electrode end of the upper and lower electrodes, and a chip-level differential series structure is formed. The application improves the array output voltage through reasonable differential positive and negative electrode series array arrangement, and further improves the chip sensitivity.

[0048] The principle based on the differential series underwater acoustic chip array structure of the application is as follows:

[0049] The piezoelectric equivalent capacitance is the capacitance value of the capacitor equivalent to the electrical behavior of the piezoelectric material under the action of the electric field. It reflects the ability of the piezoelectric material to store electric energy, and is the core parameter in the electrical model of the piezoelectric device. The upper electrode, the central piezoelectric layer and the lower electrode on each chip unit form a piezoelectric equivalent capacitance.

[0050] The calculation formula of the piezoelectric equivalent capacitance is as follows:

[0051]

[0052] Among them:

[0053] : piezoelectric equivalent capacitance (unit: farad, F);

[0054] : dielectric constant of piezoelectric material (unit: farad / meter, F / m);

[0055] : electrode area (unit: square meter, m²);

[0056] : thickness of piezoelectric material (unit: meter, m).

[0057] In the array, the total piezoelectric equivalent capacitance , after the array is connected in series , the total piezoelectric equivalent capacitance is smaller than any single piezoelectric equivalent capacitance when connected in series. The charge remains unchanged after the series connection, and the output voltage is significantly increased .

[0058] In the traditional parallel electrode, the piezoelectric equivalent capacitance is arranged in parallel. The total capacitance is the sum of the capacitances of each unit, the total output voltage is equal to the voltage of each unit, and the total charge is the sum of the capacitances of each unit.

[0059] Figure 4 The differential array structure is an electrical schematic diagram; wherein (a) is a four-array series array schematic diagram of the application, and (b) is a traditional four-layer series array schematic diagram. It can be known from comparison that the chip array structure of the application is a two-dimensional planarization of the traditional multi-layer stacked structure, which avoids the polarization difficulty and stress accumulation problem caused by too many stacked layers of the traditional multi-layer stacked electrode. In the case of circuit series, the charges of all capacitors are equal, the reciprocal of the total capacitance is equal to the sum of the reciprocals of each capacitance, and the total voltage is the sum of the voltages of each capacitor.

[0060] The high-sensitivity differential series underwater acoustic chip array structure of the application has a core action mechanism of constructing a chip-level series array, which reduces the total piezoelectric equivalent capacitance of the array while maintaining the output charge unchanged. In addition, the chip-level series method also significantly reduces the circuit loss.

[0061] As can be seen, the differential series underwater acoustic chip array structure of the application can significantly improve the output voltage, thereby improving the array sensitivity.

[0062] The parts not mentioned in the above method can be realized by adopting or referring to the existing technology.

[0063] Of course, the above description is only for the preferred embodiments of the application, and the application is not limited to the above-mentioned embodiments. It should be noted that any person skilled in the art can make all equivalent substitutions and obvious modifications under the teaching of the present application, which are within the scope of the present application, and should be protected by the present application.

Claims

1. A differential series underwater acoustic chip array structure, characterized in that: It includes an SOI layer, an insulating layer and a sensitive structure layer arranged sequentially from bottom to top. The sensitive structure layer includes an upper electrode positive terminal, an upper electrode negative terminal, a piezoelectric layer, a lower electrode positive terminal, a lower electrode negative terminal, an interconnection line between the upper and lower electrode positive terminals and an interconnection line between the upper and lower electrode negative terminals. The upper electrode positive end and the upper electrode negative end are disposed on the upper side of the piezoelectric layer, the lower electrode positive end and the lower electrode negative end are disposed on the lower side of the piezoelectric layer, the upper electrode negative end is disposed on the outer edge of the upper electrode positive end, the lower electrode negative end is disposed on the outer edge of the lower electrode positive end, and the upper electrode positive end is directly above the lower electrode positive end, and the upper electrode negative end is directly above the lower electrode negative end. The SOI layer has cavities, and the positive end of the upper electrode, the negative end of the upper electrode, the positive end of the lower electrode, and the negative end of the lower electrode are all located directly above the cavities. Each cavity defines a chip unit. The positive end of the lower electrode is connected to the positive end of the upper electrode of the adjacent chip unit through the interconnection line between the positive ends of the upper and lower electrodes, and the negative end of the lower electrode is connected to the negative end of the upper electrode of the adjacent chip unit through the interconnection line between the negative ends of the upper and lower electrodes, so that the adjacent chip units are arranged in series. The chip units are arranged in multiple arrays, and the multiple chip units constitute a chip array structure. Both the positive end of the upper electrode and the positive end of the lower electrode are circular, and both the negative end of the upper electrode and the negative end of the lower electrode include two arc-shaped segments, which are symmetrically arranged on both sides of the edge of the positive end of the upper electrode or the positive end of the lower electrode. The upper electrode positive end is connected to the first connecting line, and the lower electrode positive end is connected to the second connecting line. The first and second connecting lines are arranged facing each other and are connected by an interconnecting line between the upper and lower electrode positive ends. The two arc-shaped segments of the upper electrode negative end are respectively connected to the third and fourth connecting lines, and the two arc-shaped segments of the lower electrode negative end are respectively connected to the fifth and sixth connecting lines. The third and fifth connecting lines, and the fourth and sixth connecting lines, are all connected by an interconnecting line between the upper and lower electrode negative ends. Through holes adapted to the interconnecting lines between the upper and lower electrode positive ends and the upper and lower electrode negative ends are respectively provided at corresponding positions in the piezoelectric layer. In the chip array structure, the positive terminal of the upper electrode of one chip unit is connected to the positive terminal output line of the upper electrode, and the negative terminal of the upper electrode is connected to the negative terminal output line of the upper electrode; the positive terminal of the lower electrode of one chip unit is connected to the positive terminal output line of the lower electrode, and the negative terminal of the lower electrode is connected to the negative terminal output line of the lower electrode. A through hole adapted to the negative terminal output line of the upper electrode and the negative terminal output line of the lower electrode is provided at the corresponding position on the piezoelectric layer. The insulating layer is provided with an insertion port that is adapted to the positive end of the lower electrode, the negative end of the lower electrode, the second connection line, the fifth connection line, and the sixth connection line. The insulating layer has the same thickness as the positive end of the lower electrode, the negative end of the lower electrode, the second connection line, the fifth connection line, and the sixth connection line.

2. The differential series underwater acoustic chip array structure according to claim 1, characterized in that: The positive end of the upper electrode is located in the central region directly opposite the cavity, occupying 70% of the chip unit area; the negative end of the upper electrode occupies 20% of the outer edge area of ​​the chip unit.

3. The differential series underwater acoustic chip array structure according to claim 1, characterized in that: The SOI layer includes a back substrate, a buried oxide layer and a device silicon layer arranged sequentially from bottom to top. The cavity is disposed on the back substrate and passes through the back substrate from bottom to top.

4. The differential series underwater acoustic chip array structure according to claim 1, characterized in that: The upper electrode positive end, upper electrode negative end, lower electrode positive end, and lower electrode negative end are all Mo electrodes; the upper and lower electrode positive end interconnection line, upper and lower electrode negative end interconnection line, first line, second line, third line, fourth line, fifth line, and sixth line are all made of Mo material.

5. The differential series underwater acoustic chip array structure according to claim 1, characterized in that: The insulating layer is made of silicon dioxide or silicon nitride; the piezoelectric layer is made of AlN, ZnO2 or PZT.

6. A differential series underwater acoustic chip, characterized in that: Several differential series underwater acoustic chip array structures as described in any one of claims 1-5 are employed, and all underwater acoustic chip array structures are connected in series.

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