AlOxP-type dipole MOS device and preparation method thereof

Abstract

The invention provides an AlOx P-type dipole MOS device and a preparation method thereof, the AlOx P-type dipole MOS device comprises a P-type silicon substrate, a SiO2 thin film, a HfO2 thin film, an AlOx thin film, a TiN thin film and a W thin film which are arranged from bottom to top, a Ni thin film is deposited on the back surface of a silicon wafer of the P-type silicon substrate, after an ultrathin AlOx dipole layer is deposited on the HfO2 thin film, the SiO2 thin film, the HfO2 thin film and the AlOx thin film are grown in situ in a whole process by adopting an ALD process through ultra-short-time high-temperature annealing, and the W thin film is deposited on the back surface of a silicon wafer of the W thin film. Flat-band voltage regulation and control of the MOS device are achieved through fire driving, Al is diffused into HfO2 after driving annealing, a dipole is formed on a High k / SiO2 interface layer, the local chemical environment and charge distribution at the interface are changed, and therefore a fixed electric dipole layer is formed.

Description

TECHNICAL FIELD

[0001] The application relates to the field of electronic information, and in particular to an AlO x P-type dipole MOS device and preparation method thereof. BACKGROUND

[0002] Under the background of continuous evolution of semiconductor devices towards ultra-large scale integration and high performance and low power consumption, as the core device of advanced process nodes, the gate-all-around field effect transistor (GAA-FET) puts forward strict requirements for the precise regulation of threshold voltage V TH . As a key parameter determining the switching characteristics and power consumption level of the device, the regulation technology of threshold voltage has become the core bottleneck for performance breakthrough of high-k / metal gate MOSFET devices.

[0003] Compared with the traditional effective work function (EWF) adjustment method relying on the adjustment of metal thickness, the dipole engineering has the significant advantage of occupying no volume and has become a research hotspot in the field of V TH regulation. This technology realizes work function modulation through charge redistribution at the gate stack interface, does not need to directly contact the device channel region, fundamentally avoids the introduction of lattice damage and Coulomb scattering centers, and can maximize the high mobility of carriers (electrons and holes), thereby guaranteeing the drive current and switching speed of the device, and perfectly meeting the dual demands of performance and power consumption of advanced devices. At present, among the gate dielectric material systems, HfO2 has become a widely used high-k gate dielectric material in the industry due to its excellent dielectric properties, thermal stability and process compatibility, and its preparation technology has reached a mature industrial level.

[0004] The dipole layer, as the core component of the dipole regulation technology, needs to meet two core requirements of "ultra-thin uniformity" and "low equivalent gate oxide thickness (EOT) increment": on the one hand, it needs to achieve the expected V TH shift effect through precise thickness control, and on the other hand, it needs to avoid the significant increase of device EOT caused by its own thickness, so as to ensure that the leakage characteristics of the device are not negatively affected. Atomic layer deposition (ALD) technology is recognized as the optimal technical path for preparing high-performance dipole layers due to its atomic-level controllability of thickness and excellent film uniformity. Current dipole formation processes mainly include two types: dipole first and dipole last. The former deposits the dipole layer on the SiO2 interface layer (IL), and then deposits the high-k (HK) layer; the latter first deposits the HK layer, and then deposits the dipole formation layer on its surface, and drives the dipole material to diffuse to the HK / IL interface through high-heat budget annealing to realize regulation. In NMOS devices, according to V THThe offset direction can classify dipole layers into n-type and p-type: n-type dipole layers can make V TH Negative shift has been studied extensively and the technology is relatively mature; however, p-type dipole layers require the realization of V... TH Forward shift is more difficult in terms of material selection and process implementation. There are currently few experimental reports on it, and the candidate material system is extremely limited. Only a few materials such as Al2O3 have been initially applied. Moreover, existing processes generally have problems such as uneven dipole distribution, high interface state density, and difficulty in EOT control. It is difficult to meet the high performance requirements of advanced process nodes of 3nm and below, which has become a key bottleneck restricting the full implementation of multi-threshold technology. Summary of the Invention

[0005] The purpose of this invention is to provide an AlO x P-type dipole MOS devices and their fabrication methods, employing an ALD process for in-situ growth of SiO2 thin films, HfO2 thin films, and AlO2 thin films throughout the entire process. x Thin film, and in HfO x Ultrathin AlO deposited on thin films x After the dipole layer, flat-band voltage regulation of the MOS device was achieved through ultra-short-time high-temperature annealing.

[0006] To achieve the above objectives, this technical solution provides an AlO x The fabrication method of a P-type dipole MOS device includes the following steps: S1: SiO2 thin film, HfO2 thin film and AlO2 thin film are sequentially grown in situ on a P-type silicon substrate using the ALD process. x The thin film is used to obtain the first device; S2: The first device is thermally annealed and then subjected to ultraviolet light exposure and patterning to obtain the second device; S3: TiN thin film and W thin film are sequentially deposited on the second device using a physical vapor deposition system, and the residual photoresist is removed to obtain the third device; S4: A Ni thin film is deposited on the back side of the P-type silicon substrate of the third device and then subjected to metallization annealing to obtain AlO. x P-type dipole MOS device.

[0007] like Figure 1 As shown, the AlO prepared by this method x A P-type dipole MOS device comprises, from bottom to top, a P-type silicon substrate, a SiO2 thin film, an HfO2 thin film, and an AlO2 thin film. x Thin films, TiN films, and W films are used, with a Ni film deposited on the back side of a P-type silicon substrate. This scheme employs the PE-ALD process to grow ultrathin AlO2 films in situ on HfO2 films. xThe thin film, through ultra-short time high temperature annealing, achieves shallow diffusion of Al ions to form P-type dipoles, precisely controlling the flat band voltage of MOS devices, and has the advantages of low leakage current and low interface state density.

[0008] Specifically, a 1.4–2 nm SiO2 thin film is obtained by ALD growth on a p-type silicon substrate. This scheme employs the ALD process to sequentially grow SiO2, HfO2, and AlO2 thin films in situ. x Thin films, this end-to-end ALD in-situ growth is carried out continuously within a single vacuum chamber, with no vacuum disruption between layers. This allows for the direct growth of the next layer of material at the atomic scale, forming clear, pure, and steep interfaces to ensure stronger chemical bonding and fewer interface defects.

[0009] In some embodiments, the P-type silicon substrate is first cleaned with an SCl solution.

[0010] In some embodiments, SiO2 thin films, HfO2 thin films, and AlO2 thin films are sequentially grown in situ on a P-type silicon substrate using an ALD process. x The thin film yielded the first device. Further, on a p-type silicon substrate, 1.4–2 nm SiO2 thin films, 1–2 nm HfO2 thin films, and 3–6 Å AlO2 thin films were sequentially grown in situ using an ALD process. x The thin film yields the first device.

[0011] Regarding the growth of SiO2 thin films: The silicon substrate was pretreated with O plasma for 5-10 seconds. Tris(dimethylamino)silane precursor was introduced into the reaction chamber and pulsed for 2-5 seconds. N2 was used as the purging gas and purged for 5-8 seconds. Then, O2 plasma precursor was introduced into the reaction chamber and pulsed for 3-5 seconds. N2 was then purged for 5-8 seconds to obtain SiO2 thin film.

[0012] In some embodiments, the reaction temperature in the reaction chamber for SiO2 film growth is controlled at 250~280 °C.

[0013] This approach uses tris(dimethylamino)silane as the silicon source and O2 plasma as the oxygen source to grow SiO2 thin films in situ on silicon substrates. The core advantages of O plasma pretreatment and a growth temperature of 250~280℃ are: O plasma pretreatment cleans the interface of the silicon substrate and enhances the nucleation ability; combined with the highly active O2 plasma in the PE-ALD process and suitable precursor pulse and purge parameters, a dense, low-defect, and uniformly thick SiO2 thin film is grown in situ under mild conditions of 250~280℃. This ensures excellent interface bonding with HfO2 and subsequent AlOx layers, avoiding gate dielectric leakage and increased interface state density. It also meets the requirements of low thermal budget and ALD in-situ integration process. Stronger chemical bonding and fewer interface defects lay a key foundation for achieving precise voltage control of devices, and the process is mature and easy to mass-produce.

[0014] Regarding the growth of HfO2 thin films: The SiO2 thin film was pretreated with O plasma for 5-10 s. The tetrakis(dimethylamino)hafnium precursor was introduced into the reaction chamber and pulsed for 400-800 ms. N2 was used as the purge gas. After purging for 5-8 s, the O2 plasma precursor was introduced into the reaction chamber and pulsed for 3-5 s. N2 was then used to purge for 5-8 s to obtain the HfO2 thin film.

[0015] In some embodiments, the reaction temperature in the reaction chamber for the growth of the HfO2 thin film is controlled at 250~280 °C.

[0016] This scheme uses tetra(dimethylamino)hafnium as the hafnium source and O2 plasma as the oxygen source to grow HfO2 films in situ on SiO2 films. The core advantages of O plasma pretreatment and a growth temperature of 250~280℃ are: O plasma pretreatment cleans the interface of the SiO2 film, ensuring no byproduct residue from the previous reaction. Combined with the highly active O2 plasma in the PE-ALD process and suitable precursor pulse and purging parameters, a dense, low-defect, and uniformly thick HfO2 film is grown in situ under mild conditions of 250~280℃. This ensures a high-quality interface bonding with SiO2 and subsequent AlOx layers, forming a clear, pure, and steep interface, avoiding gate dielectric leakage and increased interface state density. This lays a key foundation for the formation of stable P-type dipoles through ultra-short-time shallow diffusion of Al ions and the realization of precise voltage control of the device. Moreover, the process is mature and easy to mass-produce.

[0017] About AlO x Thin film growth: First, pretreatment with O plasma for 5-10 s is performed. Then, trimethylaluminum precursor is introduced into the reaction chamber with a pulse of 150-200 ms, and N2 is used as the purge gas for 5-8 s. Next, O2 plasma precursor is introduced into the reaction chamber with a pulse of 2-4 s, followed by N2 purge for 5-8 s to obtain AlO. x film.

[0018] In some embodiments, AlO x The reaction temperature in the reaction chamber for thin film growth is controlled at 200~280°C.

[0019] This method uses trimethylaluminum as the aluminum source and O2 plasma as the oxygen source to grow AlO2 in situ on SiO2 thin films. x Thin films. Leveraging the high stability and moderate reactivity of trimethylaluminum, combined with highly reactive oxygen species from O2 plasma, ultrathin (3-6 Å) and uniformly dense AlO2 films were grown in situ at mild temperatures via O2 plasma pretreatment and precise ALD process parameter control. x The thin film ensures both the adhesion to the underlying AlO₂ x The excellent interface of the thin film enables precise shallow diffusion of Al ions to the HfO2 / SiO2 interface to form a stable P-type dipole during subsequent ultra-short-time high-temperature annealing, achieving a flat band voltage offset of ~250 mV. At the same time, it suppresses gate dielectric damage and leakage current. Furthermore, the process is compatible with HfO2 growth in situ, mature and easy to mass-produce, providing key support for low power consumption and advanced process adaptation of devices.

[0020] In some embodiments, this scheme employs a PE-ALD growth mode to sequentially grow SiO2 thin films, HfO2 thin films, and AlO2 thin films on a silicon substrate using an ALD process. x The first device is obtained by thin film deposition, and the radio frequency power during the deposition process is set to 100~120 W, the pressure in the reaction chamber is maintained at 0.8~1.2 torr, and the pressure difference between the reaction chamber and the outer chamber is stabilized at 6.0~7.5 torr.

[0021] Regarding step S2, this scheme performs thermal annealing on the first device. The thermal annealing atmosphere is high-purity nitrogen, the time is 1~2 seconds, the temperature is 700~800 °C, and the cavity pressure is ~1×10⁻⁶. 3 Pa, the annealing temperature rise rate and annealing time were set to 45~50 °C / s and 1~2 s, respectively.

[0022] It is important to note that this scheme employs ultra-short-time high-temperature annealing to drive the first device and achieve flat-band voltage regulation of the MOS device. After the driving annealing, Al diffuses into HfO2 and forms dipoles at the High k / SiO2 interface layer, altering the local chemical environment and charge distribution at this interface, thereby forming a fixed electric dipole layer. This dipole layer directly modulates the total voltage drop across the gate dielectric layer, effectively changing the effective work function of the metal gate. The short-time high-temperature annealing allows Al ions to diffuse shallowly into the High k / SiO2 interface layer while avoiding damage to the gate dielectric. The HfO2 maintains a continuous structure without island crystallization, keeping the device leakage current at a very low level.

[0023] Furthermore, a photolithography machine is used for ultraviolet light exposure and patterning. Positive photoresist is selected, the exposure time is 6-9 seconds, and the development and fixing time is 35-40 seconds.

[0024] Regarding step S3: In this scheme, a physical vapor deposition (PVD) system is used to deposit TiN thin films and W thin films sequentially on the second device, and a stripping process is used to remove the residual photoresist to obtain the third device.

[0025] In some embodiments, the thickness of the TiN film is 5-10 nm, and the thickness of the W film is 40-50 nm.

[0026] The TiN thin film and the underlying HfO2 / AlO in this scheme x Both the gate dielectric and the upper W thin film exhibit strong adhesion, which solves the problem of poor bonding between the W thin film and the oxide interface, preventing electrode peeling. Simultaneously, it can form a stable interface with HfO2 without damaging AlO. x The structural integrity of the dipole layer is ensured. The W thin film in this design provides a low-resistance conductive path, reduces the series resistance of the gate electrode, guarantees the device drive current and switching speed, and meets the high-performance requirements of MOSFETs.

[0027] Regarding step S4: This scheme uses an electron beam evaporation (EBE) system to deposit a Ni thin film on the back side of a P-type silicon substrate.

[0028] In some embodiments, the thickness of the Ni film is 40-50 nm.

[0029] Furthermore, metallization followed by annealing was performed using RTP (Regenerative Thermal Phosphating). The annealing atmosphere was a nitrogen-hydrogen mixture, the time was 20-30 minutes, the temperature was 400-500 °C, and the chamber pressure was ~1×10⁻⁶. 3 Pa.

[0030] As mentioned earlier, the AlO solution provided by this method xThis paper explores a novel p-dipole MOS device fabrication method that combines rapid thermal annealing with controlled annealing temperature and time. The integration process for this device, specifically AlO2, is designed. x Dipole last structure, in-situ growth of 1.4~2 nm SiO2, 1~2 nm HfO2 and 3~6 Å AlO2 using ALD technology in a single step. x Thin film, under a nitrogen gas atmosphere at 700-800 ℃ 1 - After a 2s high-temperature drive-in, the fabricated MOS capacitor was subjected to electrical testing and analysis using a semiconductor analyzer, including CV (capacitance-voltage), Cf (capacitance-frequency), and IV (current-voltage) tests. The analysis examined the VFB shift caused by AlOx and the device leakage current, revealing that the MOS structure capacitor, after metallization and annealing following the growth of the top electrode, exhibited a flat-band voltage shift of ~250 mV. VFB), and has advantages such as low interface state density and low thin film leakage.

[0031] Secondly, such as Figure 1 As shown, this solution provides an AlO x A P-type dipole MOS device comprises, from bottom to top, a P-type silicon substrate, a SiO2 thin film, an HfO2 thin film, and an AlO2 thin film. x Thin films, TiN thin films and W thin films, and Ni thin films are deposited on the back side of the silicon wafer of the P-type silicon substrate.

[0032] It should be noted that SiO2 thin films, HfO2 thin films, and AlO2 thin films... x The thin films were all deposited on a P-type silicon substrate using the ALD process.

[0033] In some embodiments, the thickness of the SiO2 film is 1.4~2 nm.

[0034] In some embodiments, the HfO2 thin film is 1~2 nm, and the AlO2 thin film is... x The thickness of the film is 3-6 Å.

[0035] In some embodiments, the thickness of the TiN film is 5-10 nm, the thickness of the W film is 40-50 nm, and the thickness of the Ni film is 40-50 nm.

[0036] It should be noted that the AlOx thin film is deposited on top of the HfO2 thin film, which belongs to the "dipole last" process structure. This design allows AlOx to act as a "dipole ion source layer". During the subsequent ultra-short high-temperature annealing at 700~800℃ for 1~2s, Al ions can diffuse directionally to the HfO2 / SiO2 interface to form a P-type dipole. This avoids the defect interference introduced by the additional interface in the "dipole first" process and reflects the technical characteristics of "precise positioning and uniform distribution" of dipoles.

[0037] Furthermore, the AlOx film thickness of this scheme is only 3-6 Å, which is atomically ultrathin, perfectly meeting the core requirement of "thin and uniform P-type dipole layer"—ensuring sufficient total Al ion content and forming a sufficiently dense P-type dipole at the HfO2 / SiO2 interface after ultrashort annealing, achieving a flat-band voltage shift of ~250mV. It avoids the increase in equivalent gate oxide thickness (EOT) due to excessive thickness, ensuring that the device drive current is not affected, which reflects the technical feature of "volume-free control" of the dipole.

[0038] Compared with existing technologies, this technical solution has the following characteristics and beneficial effects: In terms of structure, this solution adopts a dipole-last architecture with AlOx deposited on HfO2, which is different from the dipole-first process where gallium oxide is located between SiO2 and HfO2. It does not require the introduction of an additional interface, thus avoiding the generation of new defects and scattering centers. At the same time, the AlOx layer also serves as a protective layer, which can suppress the diffusion of metal gate atoms into HfO2. Furthermore, the core film thickness is reduced to an extreme degree, with the AlOx thickness controlled at 3-6 Å and the HfO2 thickness at 1-2 nm, which is much thinner than the combination of gallium oxide and hafnium oxide in the existing technology, perfectly meeting the miniaturization requirements of advanced processes at 3nm and below.

[0039] In terms of process technology, the innovative PE-ALD technology is adopted to grow SiO2 thin films, HfO2 thin films and AlO2 thin films in situ throughout the entire process. xThin films are grown directly at the atomic scale, forming clear, pure, and steep interfaces to ensure stronger chemical bonding and fewer interface defects. Using O2 plasma as the oxygen source, no subsequent annealing at 200-300℃ is required, and hydrocarbon impurities in the precursor can be effectively removed, resulting in denser oxide films. The pretreatment process only requires O plasma treatment of the silicon substrate to achieve interface cleaning and nucleation optimization, significantly improving process stability and efficiency. At the same time, a pioneering 700~800℃, 1~2s ultra-short-time high-temperature annealing process drives Al ions to diffuse shallowly to the HfO2 / SiO2 interface to form dipoles, avoiding gate dielectric damage caused by traditional long-time annealing, and achieving more precise dipole positioning.

[0040] These innovative designs have yielded significant benefits: the flat-band voltage offset of the device reaches ~250mV, far exceeding the control effect of existing technologies, and the control consistency is strong, accurately meeting the multi-threshold technology requirements of MOSFETs; the interface state density is as low as 2.47×10¹², the CV curve hysteresis is minimal, the HfO2 maintains a continuous structure without crystallization damage, the device leakage current remains at a low level, and the reliability is greatly improved; the ultra-thin layer design and low thermal budget process are compatible with advanced processes of 3nm and below, balancing miniaturization and high drive current, breaking through the performance bottleneck caused by the traditional dipole layer thickening; at the same time, the process is highly compatible with existing MOSFET production lines, requiring no large-scale equipment modification, simplifying the process, and providing high stability, effectively reducing mass production costs and technical risks, filling the technological gap of limited p-dipole materials and limited control effects, and has important application value in the manufacturing of advanced semiconductor devices in the field of electronic information. Attached Figure Description

[0041] Figure 1 The AlO provided by this solution x A schematic diagram of the structure of a P-type dipole MOS device.

[0042] Figure 2 This is a schematic diagram of the MOS device provided in the example.

[0043] Figure 3 This solution provides AlO under annealing conditions of 800℃-1.5s. x Capacitance-voltage (CV) curves of a P-type dipole MOS device at different frequencies.

[0044] Figure 4 This solution provides AlO under annealing conditions of 800℃-10s. x Capacitance-voltage (CV) curves of a P-type dipole MOS device at different frequencies.

[0045] Figure 5 This solution provides AlO under annealing conditions of 800℃-1.5s. x Capacitance-voltage (CV) curves of a P-type dipole MOS device and a comparative MOS device tested at 1 MHz.

[0046] Figure 6 This solution provides AlO under annealing conditions of 800℃-10s. x Capacitance-voltage (CV) curves of a P-type dipole MOS device and a comparative MOS device tested at 1 MHz.

[0047] Figure 7 The AlO provided by this solution x The graph shows the change in conductance as a function of test frequency for a P-type dipole MOS device extracted using the parallel conductance method for a 6 Å dipole device.

[0048] Figure 8 The AlO provided by this solution x Leakage current of P-type dipole MOS devices and comparative MOS devices under annealing conditions of 800℃-1.5 s and 800℃-10 s. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0050] Example: Fabrication of the AlOx P-type dipole MOS device according to this scheme: The silicon substrate was cleaned using SC1 solution; Using the above-described ALD process, 2 nm SiO2 films and 2 nm HfO2 films were grown, and 6 Å AlO2 films were grown in situ. xThin film; growth temperature is 280 °C, RF power during deposition is set to 100 W, reaction chamber pressure is maintained at 0.9 torr, and pressure difference between reaction chamber and outer chamber is stabilized at 7.5 torr. In the SiO2 thin film ALD growth process, the sample substrate is first pretreated with O plasma for 10 s, then tris(dimethylamino)silane precursor is introduced into the reaction chamber for 3 s pulse, N2 is used as purge gas, and purging is performed for 6 s to remove reaction residues and gaseous byproducts. O2 plasma precursor is introduced for 3 s, and N2 is purged for 6 s to remove byproducts generated in the previous pulse reaction. In the HfO2 thin film ALD growth process, the sample is first pretreated with O plasma for 5 s. Then, a tetrakis(dimethylamino)hafnium precursor is pulsed into the reaction chamber for 500 ms, and N2 is used as the purge gas for 5 s to remove reaction residues and gaseous byproducts. Next, an O2 plasma precursor is introduced for 3 s, followed by N2 purging for 5 s to remove byproducts generated in the previous pulse reaction. x In the thin film ALD growth process, the sample substrate is first pretreated with O plasma for 5 s. Then, the trimethylaluminum precursor is introduced into the reaction chamber and pulsed for 150 ms. N2 is used as the purge gas and purges for 5 s to remove reaction residues and gaseous byproducts. O2 plasma precursor is introduced for 2 s, and N2 is purged for 5 s to remove byproducts generated in the previous pulse reaction. This process is repeated periodically.

[0051] Annealing was performed using a rapid heat treatment (RTP) system, with a high-purity nitrogen atmosphere, a time of 1.5 s, a temperature of 800 °C, and a chamber pressure of 1 × 10⁻⁶. 3 Pa, the annealing temperature rise rate and annealing time were set to 50°C / s and 1.5s, respectively.

[0052] A photolithography machine was used for ultraviolet light exposure and patterning. Positive photoresist was selected, the exposure time was 8 s, and the development and fixing time was 35 s. A 5 nm titanium nitride (TiN) film and a 50 nm tungsten (W) film were sequentially deposited using a physical vapor deposition (PVD) system; residual photoresist was removed using a lift-off process. A 50 nm metallic nickel (Ni) thin film was deposited on the back side of a silicon wafer using an electron beam evaporation (EBE) system; Metallization followed by annealing was performed using RTP (Regenerative Thermal Phosphating). The annealing atmosphere was a nitrogen-hydrogen mixture, the treatment time was 30 min, the temperature was 400 °C, and the chamber pressure was 1 × 10⁻⁶. 3 Pa.

[0053] Comparative example: Fabrication of MOS in comparison: The silicon substrate was cleaned using SC1 solution; 2 nm SiO2 and 2 nm HfO2 films were grown using the ALD process described above. The growth temperature was 280 °C, the RF power during deposition was set to 100 W, the reaction chamber pressure was maintained at 0.9 torr, and the pressure difference between the reaction chamber and the outer chamber was stabilized at 7.5 torr. During the SiO2 film ALD growth process, the sample substrate was first pretreated with O plasma for 10 s. Then, tris(dimethylamino)silane precursor was introduced into the reaction chamber and pulsed for 3 s. N2 was used as the purge gas and purged for 6 s to remove reaction residues and gaseous byproducts. O2 plasma precursor was then introduced for 3 s, and N2 was purged for 6 s to remove byproducts generated in the previous pulse reaction. In the HfO2 thin film ALD growth process, the sample substrate is first pretreated with O plasma for 5 s. Then, a tetrakis(dimethylamino)hafnium precursor is introduced into the reaction chamber and pulsed for 500 ms. N2 is used as the purge gas to purge for 5 s to remove reaction residues and gaseous byproducts. O2 plasma precursor is introduced for 3 s, and N2 is purged for 5 s to remove byproducts generated in the previous pulse reaction. This process is repeated periodically.

[0054] Annealing was performed using a rapid heat treatment (RTP) system, with a high-purity nitrogen atmosphere, a time of 1.5 s, a temperature of 800 °C, and a chamber pressure of 1 × 10⁻⁶. 3 Pa, the annealing temperature rise rate and annealing time were set to 50°C / s and 1.5s, respectively.

[0055] A photolithography machine was used for ultraviolet light exposure and patterning. Positive photoresist was selected, the exposure time was 8 s, and the development and fixing time was 35 s. A 5 nm titanium nitride (TiN) film and a 50 nm tungsten (W) film were sequentially deposited using a physical vapor deposition (PVD) system; residual photoresist was removed using a lift-off process. A 50 nm metallic nickel (Ni) thin film was deposited on the back side of a silicon wafer using an electron beam evaporation (EBE) system; Metallization followed by annealing was performed using RTP (Regenerative Thermal Phosphating). The annealing atmosphere was a nitrogen-hydrogen mixture, the treatment time was 30 min, the temperature was 400 °C, and the chamber pressure was 1 × 10⁻⁶. 3 Pa.

[0056] Comparative MOS such as Figure 2 As shown, the MOS device consists of a P-type silicon substrate, a SiO2 thin film, a HfO2 thin film, a TiN thin film, and a W thin film arranged from bottom to top, and a Ni thin film is deposited on the back side of the P-type silicon substrate.

[0057] test: The MOS capacitors prepared in the examples and comparative examples were subjected to electrical tests and analyses using a semiconductor analyzer, including CV (capacitance-voltage), Cf (capacitance-frequency), and IV (current-voltage) tests, to analyze the VFB offset caused by AlOx and the leakage current of the devices.

[0058] like Figure 3 and Figure 4 As shown, Figure 3 and Figure 4 The figures show the capacitance-voltage (CV) curves of the AlOx P-type dipole MOS device provided by this scheme at different frequencies, obtained under annealing conditions of 800℃-1.5 s and 800℃-10 s, respectively. It can be seen that the CV sweep curve hysteresis is significantly smaller at 1.5 s compared to 10 s, indicating fewer mobile and trapped charges at the interface and oxide layer, a lower interface state density, and a capacitor structure with higher quality, more stable performance, and better controllability.

[0059] like Figure 5 and Figure 6 As shown, Figure 5 The AlO2 provided by this scheme is annealed at 800℃ for 1.5 s. x The capacitance-voltage (CV) curves of the P-type dipole MOS device and the MOS device provided in the comparison example were obtained by testing at 1 MHz. Figure 6 The AlO2 solution provided by this method is annealed at 800℃ for 10 seconds. x The capacitance-voltage (CV) curves of the P-type dipole MOS device and the MOS device provided in the comparative example were obtained at 1 MHz. It can be seen that under both annealing conditions, the increase in device EOT is kept below 2 Å. However, the VFB offset reaches 250 mV after adding the dipole layer to the 1.5 s annealed device, while the VFB offset reaches 150 mV after adding the dipole layer to the 10 s annealed device. Furthermore, the hysteresis offset voltage of the 10 s annealed device reaches 70 mV, significantly affecting the judgment of VFB offset and indicating poor device interface.

[0060] like Figure 7 As shown, Figure 7 It is provided by AlO x The conductivity of a P-type dipole MOS device inserted into a 6 Å dipole device, extracted using the parallel conductivity method, versus test frequency, yields an interface state density of 2.47 × 10⁻⁶. 12 It is on the order of 12. Figure 8 It is provided by AlO xThe leakage current of the P-type dipole MOS device and the MOS device provided in the comparative example under the conditions of annealing at 800℃ for 1.5 s and annealing at 800℃ for 10 s is as follows: It can be seen that the leakage current is on the same order of magnitude under both annealing conditions, indicating that the two annealing conditions have little impact on the leakage current and ensure the normal operation of the device.

[0061] Those skilled in the art should understand that the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An AlO x The method for fabricating a P-type dipole MOS device is characterized by, Includes the following steps: S1: Using the ALD process, 1.4~2 nm SiO2 thin films, 1~2 nm HfO2 thin films, and 3~6 Å AlO2 films are sequentially grown in situ on a P-type silicon substrate. x The thin film is used to obtain the first device; S2: The first device is thermally annealed and then exposed to ultraviolet light and patterned to obtain the second device. The thermal annealing is performed in a high-purity nitrogen atmosphere for 1-2 seconds at a temperature of 700-800°C. S3: TiN thin film and W thin film are sequentially deposited on the second device using a physical vapor deposition system, and the residual photoresist is removed to obtain the third device; S4: A Ni thin film is deposited on the back side of the P-type silicon substrate of the third device and then subjected to metallization annealing to obtain AlO. x P-type dipole MOS device.

2. The AlO according to claim 1 x The method for fabricating a P-type dipole MOS device is characterized by, The P-type silicon substrate was pretreated with O plasma for 5-10 seconds. Tris(dimethylamino)silane precursor was introduced into the reaction chamber and pulsed for 2-5 seconds. N2 was used as the purging gas. After purging for 5-8 seconds, O2 plasma precursor was introduced into the reaction chamber and pulsed for 3-5 seconds. N2 was then purged for 5-8 seconds to obtain SiO2 thin film.

3. The AlO according to claim 1 x The method for fabricating a P-type dipole MOS device is characterized by, The SiO2 thin film was pretreated with O plasma for 5-10 s. The tetrakis(dimethylamino)hafnium precursor was introduced into the reaction chamber and pulsed for 400-800 ms. N2 was used as the purge gas. After purging for 5-8 s, the O2 plasma precursor was introduced into the reaction chamber and pulsed for 3-5 s. N2 was then used to purge for 5-8 s to obtain the HfO2 thin film.

4. The AlO according to claim 1 x The method for fabricating a P-type dipole MOS device is characterized by, Pretreatment with O2 plasma for 5–10 s was performed, followed by a 150–200 ms pulse of trimethylaluminum precursor into the reaction chamber, with N2 as the purge gas for 5–8 s. Then, O2 plasma precursor was introduced into the reaction chamber for a 2–4 ​​s pulse, followed by N2 purge for 5–8 s to obtain AlO2. x film.

5. The AlO according to claim 1 x The method for fabricating a P-type dipole MOS device is characterized by, The cavity pressure is ~1×10 3 Pa, the annealing temperature rise rate and annealing time were set to 45~50 °C / s and 1~2 s, respectively.

6. The AlO according to claim 1 x The method for fabricating a P-type dipole MOS device is characterized by, TiN and W films were sequentially deposited on the second device using a physical vapor deposition system, and the residual photoresist was removed using a lift-off process to obtain the third device; a Ni film was deposited on the back side of a P-type silicon substrate using an electron beam evaporation system.

7. The AlO according to claim 1 x The method for fabricating a P-type dipole MOS device is characterized by, Metallization followed by annealing was performed using RTP (Regenerative Thermal Phosphating). The annealing atmosphere was a nitrogen-hydrogen mixture, the time was 20-30 minutes, the temperature was 400-500 °C, and the chamber pressure was ~1×10⁻⁶. 3 Pa.

8. An AlO x A P-type dipole MOS device, characterized in that... include: Including, from bottom to top, a P-type silicon substrate, SiO2 thin film, HfO2 thin film, and AlO2. x Thin films, TiN thin films and W thin films, and Ni thin films are deposited on the back side of the silicon wafer of the P-type silicon substrate.

9. The AlO according to claim 8 x A P-type dipole MOS device, characterized in that... The thickness of SiO2 films is 1.4~2 nm, HfO2 films are 1~2 nm, and AlO2 films are... x The thickness of the thin film is 3-6 Å, the thickness of the TiN thin film is 5-10 nm, the thickness of the W thin film is 40-50 nm, and the thickness of the Ni thin film is 40-50 nm.

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