ESD protection device with high holding voltage and protection method

Abstract

The application provides an ESD protection device with high holding voltage and a protection method. The device comprises a substrate, a first N-type well layer, a first P-type well layer, a second N-type well layer and a second P-type well layer which are arranged in parallel on the surface of the substrate, a deep N-type well layer which is arranged between the first N-type well layer, the first P-type well layer, the second N-type well layer and the substrate, a first P-type doping layer and a second P-type doping layer which are arranged on the first N-type well layer, the second P-type doping layer extends to the first P-type well layer, and a first groove is arranged between the first P-type doping layer and the second P-type doping layer. The deep N-type well layer is arranged below the first N-type well layer, the first P-type well layer and the second N-type well layer, so that the SCR discharge path is changed from a traditional lateral path to a three-dimensional path containing a longitudinal path, the total discharge path length is effectively lengthened without increasing the lateral length of the device, and the holding voltage of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge protection for integrated circuits, and more specifically to ESD protection devices and methods with high holding voltage. Background Technology

[0002] Electrostatic discharge (ESD) is the charge transfer phenomenon that occurs when objects with different electrostatic potentials approach or come into direct contact. Many electronic components are highly sensitive to static electricity; even a small amount can cause their internal structure to break down, leading to performance degradation or even complete failure. For example, during manufacturing, a single electrostatic pulse can cause some functions of a chip to be lost. With the continuous development of integrated circuits and semiconductor processes, and the shrinking of process dimensions, the requirements for ESD protection are becoming increasingly stringent.

[0003] Thyristors, also known as silicon controlled rectifiers (SCRs), are commonly used ESD protection devices and belong to the category of hysteresis devices. Due to their inherent positive feedback mechanism, they possess advantages such as high discharge current per unit area, low on-resistance, and strong robustness, making them a hot research topic in the industry. However, the original SCR device has a high trigger voltage and a low holding voltage, making it unsuitable for direct application. A more commonly used SCR device is the modified SCR (MSCR), which reduces the trigger voltage by adding a highly doped region. However, its holding voltage remains low, making it prone to false triggering at higher operating voltages (e.g., 5V), affecting normal circuit operation and even causing failure.

[0004] To address these issues, increasing the length of the SCR path (i.e., the anode-cathode spacing) is generally necessary. However, this increases the layout area, leading to decreased robustness per unit area and increased cost. Therefore, novel device structures are needed to improve robustness per unit area. Summary of the Invention

[0005] The purpose of this invention is to solve the problem in the prior art that SCR devices need to have their paths stretched laterally to increase the holding voltage, which leads to an increase in layout area and a decrease in robustness per unit area.

[0006] A first aspect of the present invention provides a high holding voltage ESD protection device, comprising:

[0007] Substrate;

[0008] The surface of the substrate is covered with a first N-type well layer, a first P-type well layer, a second N-type well layer, and a second P-type well layer in parallel.

[0009] A deep N-type well layer is provided between the first N-type well layer, the first P-type well layer, the second N-type well layer and the substrate;

[0010] A first P-type doped layer and a second P-type doped layer are covered on the first N-type well layer, the second P-type doped layer extends to the first P-type well layer, and a first trench is provided between the first P-type doped layer and the second P-type doped layer;

[0011] The second P-type well layer is provided with a first N-type doped layer and a third P-type doped layer, a second trench is provided between the first N-type doped layer and the third P-type doped layer, and a third trench is provided between the second P-type doped layer and the first N-type doped layer.

[0012] The first P-type doped layer is connected to the anode;

[0013] The second P-type doped layer, the first N-type doped layer, and the third P-type doped layer are all connected to the cathode.

[0014] Furthermore, the first trench extends to the first N-type well layer;

[0015] The second trench extends into the second P-type well layer;

[0016] The third trench extends to the first P-type well layer, the second N-type well layer, and the second P-type well layer.

[0017] Furthermore, the first P-type doped layer, the first N-type well layer, the deep N-type well layer, the second N-type well layer, and the second P-type well layer together constitute a parasitic PNP transistor.

[0018] Furthermore, the first N-type well layer, the deep N-type well layer, the second N-type well layer, the second P-type well layer, and the first N-type doped region together constitute a parasitic NPN transistor.

[0019] Furthermore, the parasitic PNP transistor and the parasitic NPN transistor constitute an SCR structure.

[0020] Furthermore, the first P-type doped layer, the first N-type well layer, and the second P-type doped layer form a PNP transistor.

[0021] Furthermore, the PNP transistor forms a trigger path;

[0022] The SCR structure forms the main discharge path.

[0023] Furthermore, the substrate is a P-type substrate.

[0024] A second aspect of the present invention provides a high holding voltage ESD protection method, employing a high holding voltage ESD protection device as described in any of the preceding claims.

[0025] When the ESD voltage reaches the sum of the forward bias voltage of the first P-type doped layer or the first N-type well layer and the reverse bias voltage of the first N-type well layer or the second P-type doped layer, the trigger path formed by the first P-type doped layer, the first N-type well layer and the second P-type doped layer is turned on.

[0026] When the ESD voltage increases further, the parasitic PNP transistor formed by the first P-type doped layer, the first N-type well layer, the deep N-type well layer, the second N-type well layer, and the second P-type well layer, together with the first N-type well layer, the deep N-type well layer, the second N-type well layer, the second P-type well layer, and the first N-type doped region, forms a parasitic NPN transistor, creating a positive feedback path. The parasitic PNP transistor and the parasitic NPN transistor together form an SCR structure, and the main discharge path formed by the SCR structure is turned on.

[0027] Furthermore, in the triggering path, the current flows from the first P-type doped layer, through the first N-type well layer, to the second P-type doped layer;

[0028] In the main discharge path, the current flows from the first P-type doped layer, through the first N-type well layer, the deep N-type well layer, the substrate, and the second P-type well layer, back to the first N-type doped layer.

[0029] Alternatively, it can flow through the first N-type well layer, the deep N-type well layer, the second N-type well layer, and the second P-type well layer to the first N-type doped layer.

[0030] Compared with the prior art, the present invention has at least the following beneficial effects: by setting a deep N-type well layer below the first N-type well layer, the first P-type well layer, and the second N-type well layer, the SCR discharge path is transformed from a traditional lateral path into a three-dimensional path including a longitudinal path, effectively extending the total discharge path length without increasing the lateral length of the device, thereby improving the device's holding voltage; at the same time, since the device layout area remains compact, the discharge capability per unit area (robustness) can be maintained or even improved, solving the contradiction in the prior art that improving the holding voltage must sacrifice the layout area or performance per unit area, and achieving a balance between high holding voltage and high robustness. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained as provided without creative effort.

[0032] Figure 1 This is a cross-sectional view of a traditional GGNMOS device;

[0033] Figure 2 This is a cross-sectional view of a traditional MSCR device;

[0034] Figure 3 This is a cross-sectional view of an ESD protection device according to an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the discharge path of the ESD protection device during operation in one embodiment of the present invention;

[0036] Figure 5 This is a comparison chart of the current-voltage (IV) characteristics of an ESD protection device and a GGNMOS device under ESD simulation in one embodiment of the present invention;

[0037] Figure 6 This is a comparison chart of the IV characteristics of an ESD protection device and a traditional MSCR device under ESD simulation in one embodiment of the present invention;

[0038] Figure 7 This is a comparison diagram of the lattice temperature of an ESD protection device and a GGNMOS device under ESD simulation in one embodiment of the present invention.

[0039] Figure 8 This is a comparison diagram of the lattice temperature of an ESD protection device and a traditional MSCR device under ESD simulation in one embodiment of the present invention.

[0040] Wherein, 1-substrate; 2-first N-type well layer; 3-first P-type well layer; 4-second N-type well layer; 5-second P-type well layer; 6-deep N-type well layer; 7-first trench; 8-third trench; 9-second trench; 10-first P-type doped layer; 11-second P-type doped layer; 12-first N-type doped layer; 13-third P-type doped layer. Detailed Implementation

[0041] The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being broadly known to those skilled in the art and is not intended to limit the invention.

[0042] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0043] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer as explained below. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0044] Please refer to Figure 1 This is a cross-sectional view of a traditional GGNMOS, i.e., a gate-grounded NMOS transistor. Connecting the drain of the NMOS to the anode and the gate to the source, while simultaneously connecting the gate and source to the cathode, forms a GGNMOS. The parasitic NPN transistor in a GGNMOS consists of an N-type doped layer (equivalent to the emitter) connected to the cathode, a P-type well layer (equivalent to the base), and an N-type doped layer (equivalent to the collector) connected to the anode. When an ESD event occurs, the anode potential rises rapidly. When it reaches the avalanche breakdown voltage of the N-type doped layer / P-type well layer, current flows through the P-type well layer, causing a voltage drop. At this point, the collector junction of the NPN transistor is reverse-biased, and the emitter junction is forward-biased, causing the parasitic NPN transistor to turn on and discharge the ESD current. GGNMOS typically has a high holding voltage, therefore it is often used in ESD protection at higher operating voltages (e.g., 5V), but its discharge capability per unit area is relatively weak.

[0045] Please refer to Figure 2This is a cross-sectional view of a traditional MSCR device. The parasitic PNP transistor consists of a P-type doped layer (equivalent to the emitter) connected to the anode, an N-type well layer (equivalent to the base) below the P-type doped layer connected to the anode, and a P-type well layer (equivalent to the collector). The parasitic NPN transistor consists of an N-type well layer (equivalent to the collector), a P-type well layer (equivalent to the base), and an N-type doped layer (equivalent to the emitter) connected to the cathode. The N-type doped layer bridging the N-type and P-type well layers reduces the trigger voltage of the SCR path. When an ESD event occurs, the anode potential rises rapidly. The device turns on when the sum of the forward bias voltage of the P-type doped layer / N-type well layer and the reverse bias voltage of the N-type doped layer / P-type well layer is reached, allowing a small current to dissipate via the surface path of the device. As the current increases further, a voltage drop occurs as the current flows through the N-type well layer. At this point, the parasitic PNP transistor in the SCR path turns on, and simultaneously, the collector junction of the parasitic NPN transistor is reverse-biased while the emitter junction is forward-biased, causing the parasitic NPN transistor to turn on as well. Ultimately, the parasitic PNP and NPN transistors form a positive feedback path, thereby discharging a large amount of ESD current. To obtain a sufficient holding voltage, a sufficient SCR path length must be ensured, thus increasing the device area.

[0046] Example 1

[0047] This embodiment provides an ESD protection device with high holding voltage. Please refer to [reference needed]. Figures 3-4 ,include:

[0048] Substrate 1.

[0049] The surface of the substrate 1 is covered with a first N-type well layer 2, a first P-type well layer 3, a second N-type well layer 4, and a second P-type well layer 5 arranged side by side.

[0050] A deep N-type well layer 6 is provided between the first N-type well layer 2, the first P-type well layer 3 and the second N-type well layer 4 and the substrate 1.

[0051] The first N-type well layer 2 is covered with a first P-type doped layer 10 and a second P-type doped layer 11, the second P-type doped layer 11 extends to the first P-type well layer 3, and a first trench 7 is provided between the first P-type doped layer 10 and the second P-type doped layer 11.

[0052] The second P-type well layer 5 is provided with a first N-type doped layer 12 and a third P-type doped layer 13. A second trench 9 is provided between the first N-type doped layer 12 and the third P-type doped layer 13, and a third trench 8 is provided between the second P-type doped layer 11 and the first N-type doped layer 12.

[0053] The first P-type doped layer 10 is connected to the anode.

[0054] The second P-type doped layer 11, the first N-type doped layer 12, and the third P-type doped layer 13 are all connected to the cathode.

[0055] Specifically, substrate 1 is a P-type substrate 1. In this embodiment, the first N-type well layer 2, the first P-type well layer 3, the second N-type well layer 4, the second P-type well layer 5, the deep N-type well layer 6, the first P-type doped layer 10, the second P-type doped layer 11, the first N-type doped layer 12, and the third P-type doped layer 13 are all made of Si material.

[0056] Furthermore, the first trench 7 extends to the first N-type well layer 2.

[0057] The second trench 9 extends to the second P-type well layer 5.

[0058] The third trench 8 extends to the first P-type well layer 3, the second N-type well layer 4, and the second P-type well layer 5.

[0059] Furthermore, the first P-type doped layer 10, the first N-type well layer 2, the deep N-type well layer 6, the second N-type well layer 4, and the second P-type well layer 5 together constitute a parasitic PNP transistor.

[0060] Furthermore, the first N-type well layer 2, the deep N-type well layer 6, the second N-type well layer 4, the second P-type well layer 5, and the first N-type doped region together constitute a parasitic NPN transistor.

[0061] Furthermore, the parasitic PNP transistor and the parasitic NPN transistor constitute an SCR structure.

[0062] Furthermore, the first P-type doped layer 10, the first N-type well layer 2, and the second P-type doped layer 11 form a PNP transistor.

[0063] Furthermore, the PNP transistor forms a trigger path.

[0064] The SCR structure forms the main discharge path.

[0065] In the SCR device of this embodiment, the PNP trigger path of the device is formed by the first P-type doped layer 10 connected to the electrical anode, the first N-type well layer 2 below it, and the second P-type doped layer 11 connected to the electrical cathode. The first P-type doped layer 10 (equivalent to the emitter), the first N-type well layer 2, the second N-type well layer 4, the deep N-type well layer 6 (equivalent to the base), and the second P-type well layer 5 (equivalent to the collector) together constitute a parasitic PNP transistor; the first N-type well layer 2, the second N-type well layer 4, the deep N-type well layer 6 (equivalent to the collector), the second P-type well layer 5 (equivalent to the base), and the first N-type doped layer 12 (equivalent to the emitter) together constitute a parasitic NPN transistor; the parasitic PNP transistor and the parasitic NPN transistor together constitute the SCR structure.

[0066] In this invention, to further improve the holding voltage, a first P-type well layer 3 is inserted beneath the second P-type doped layer 11 connected to the electrical cathode, dividing the N-type well layer into two parts (a first N-type well layer 2 and a second N-type well layer 4), and the two parts of the N-type well layer (the first N-type well layer 2 and the second N-type well layer 4) are connected by a deep N-type well layer 6. This structure, while maintaining the overall length of the device, longitudinally lengthens the discharge path of the SCR to improve the holding voltage.

[0067] Example 2

[0068] This embodiment provides a high holding voltage ESD protection method, employing the high holding voltage ESD protection device as described in Embodiment 1.

[0069] When the ESD voltage reaches the sum of the forward bias voltage of the first P-type doped layer 10 or the first N-type well layer 2 and the reverse bias voltage of the first N-type well layer 2 or the second P-type doped layer 11, the trigger path formed by the first P-type doped layer 10, the first N-type well layer 2 and the second P-type doped layer 11 is turned on.

[0070] When the ESD voltage increases further, the parasitic PNP transistor formed by the first P-type doped layer 10, the first N-type well layer 2, the deep N-type well layer 6, the second N-type well layer 4, and the second P-type well layer 5, together with the first N-type well layer 2, the deep N-type well layer 6, the second N-type well layer 4, the second P-type well layer 5, and the first N-type doped region, forms a parasitic NPN transistor, which forms a positive feedback path. The parasitic PNP transistor and the parasitic NPN transistor form an SCR structure, and the main discharge path formed by the SCR structure is turned on.

[0071] Furthermore, in the triggering path, the current flows from the first P-type doped layer 10, through the first N-type well layer 2, to the second P-type doped layer 11.

[0072] In the main discharge path, the current flows from the first P-type doped layer 10, through the first N-type well layer 2, the deep N-type well layer 6, the substrate 1, and the second P-type well layer 5, to the first N-type doped layer 12.

[0073] Alternatively, it can flow through the first N-type well layer 2, the deep N-type well layer 6, the second N-type well layer 4, and the second P-type well layer 5 to the first N-type doped layer 12.

[0074] Specifically, in this embodiment, the triggering path in the initial stage of ESD discharge is that the PNP transistor conducts through avalanche breakdown of the N-type well layer / P-type doped layer. When an ESD event occurs, the anode voltage rises rapidly. When the sum of the forward bias voltage of the P-type doped layer / N-type well layer and the reverse bias voltage of the N-type well layer / P-type doped layer is reached, the PNP triggering path conducts. In the PNP triggering path, the P-type doped layer / N-type well layer junction is the base-emitter junction of the parasitic PNP transistor. Its forward bias conduction allows some carriers to enter the P substrate, thereby increasing the base potential of the parasitic NPN transistor and turning on the NPN transistor. At this time, a positive feedback path is formed, and the SCR path (i.e., the main discharge path) conducts to discharge a large amount of ESD current. The P-type well layer (i.e., the P-type well layer surrounded by the N-type well layer and the deep N-type well layer) is... Figure 3 The first P-type well layer 3) is grounded through the second P-type doped layer 11, and therefore cannot serve as part of the SCR path. This causes the actual SCR path to be pushed deeper into the substrate 1, thereby longitudinally extending the discharge path of the SCR and helping to improve the holding voltage of the device.

[0075] The following discussion uses specific simulation experiments as examples:

[0076] Please refer to Figures 5-8 Multiple current pulses were used to simulate the electrical characteristics of the device under ESD events. The rise time of the current pulses was 10 ns, the pulse width was 100 ns, and the current amplitude gradually increased. The average voltage and current values ​​between 70 ns and 90 ns were taken as a set of current-voltage (IV) data for each simulation result. The simulation data were recorded and IV curves were plotted. The total lengths of the GGNMOS device, the conventional MSCR device, and the SCR device in this embodiment were 5.5 μm, 9 μm, and 16 μm, respectively; the width of each device was 50 μm.

[0077] 1) First, compare the basic electrical characteristics of GGNMOS, traditional MSCR, and the SCR device in this embodiment. The simulated IV curves of the SCR device and GGNMOS device in this embodiment are as follows: Figure 5As shown, the holding voltage of the GGNMOS is 5.8V; the holding voltage of the SCR device in this embodiment is 7.3V. Compared to GGNMOS, the SCR device in this embodiment shows a significant improvement in holding voltage. The IV curves of the SCR device and the traditional MSCR device in this embodiment are shown in the figure. Figure 6 As shown, the trigger voltage of a traditional MSCR is 14V, and the holding voltage is 5.5V. In this embodiment, the trigger voltage of the SCR device is 10.3V, and the holding voltage is 7.3V. Compared to a traditional MSCR, the holding voltage of the SCR device in this embodiment is significantly improved.

[0078] 2) By comparing the discharge capabilities of GGNMOS, traditional MSCR, and the SCR device in this embodiment, a maximum lattice temperature exceeding 1000K is defined as the failure criterion. Simulation results are as follows: Figure 7 As shown, under ESD simulation with a current of 0.7A, the maximum lattice temperature of the GGNMOS is 1058K, indicating that the device is close to failure. Since the total length of the GGNMOS device is 5.5μm, and the total length of the SCR device in this embodiment is 9μm, with a width of 50μm for both, the area of ​​the SCR device in this embodiment is approximately 1.64 times that of the GGNMOS device. To compare the discharge capability per unit area, the current applied to the SCR device in this embodiment is approximately 1.64 times that applied to the GGNMOS in the simulation. Therefore, a 0.7A ESD-like pulse is applied to the GGNMOS, and a 1.15A ESD-like pulse is applied to the SCR in this embodiment. Under ESD simulation with a current of 1.15A, the maximum lattice temperature of the SCR in this embodiment initially rises to a peak of 880K, but as the SCR turns on, its maximum lattice temperature rapidly decreases and finally stabilizes at 450K, significantly lower than that of the GGNMOS. Therefore, compared to GGNMOS, the SCR in this embodiment has a higher failure current and a stronger discharge capability per unit area current.

[0079] Under ESD simulation with a current of 1.9A, the maximum lattice temperature of a traditional MSCR is 1055K, indicating that the device is close to failure. The simulation results are as follows: Figure 8As shown. The total length of a traditional MSCR device is 16 μm, while the total length of the SCR device in this embodiment is 9 μm. Both devices have a width of 50 μm, meaning the area of ​​the SCR device in this embodiment is approximately 0.58 times that of the traditional MSCR device. To compare the discharge capability per unit area, the current applied to the SCR device in this embodiment during simulation is approximately 0.58 times that applied to the traditional MSCR. Therefore, a 1.1A ESD-like pulse is applied to the SCR in this embodiment. Under the 1.1A ESD simulation, the maximum lattice temperature of the SCR in this embodiment initially rises to a peak of 780K, but as the SCR turns on, its maximum lattice temperature rapidly decreases and finally stabilizes at 410K, significantly lower than that of the traditional MSCR. Therefore, compared to the traditional MSCR, the SCR in this embodiment has a higher failure current and a stronger discharge capability per unit area.

[0080] In summary, the PNP-triggered SCR device of this application utilizes a PNP structure to trigger the SCR path and inserts a P-type well layer connected to the electrical cathode within the N-type well layer, thereby improving the overall holding voltage of the device. While achieving a sufficient holding voltage, compared to GGNMOS and MSCR devices, the SCR device of this application exhibits stronger discharge capability per unit area and can be used for ESD protection at medium to high operating voltages (e.g., 5V).

[0081] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A high holding voltage ESD protection device, characterized in that, include: Substrate; The surface of the substrate is covered with a first N-type well layer, a first P-type well layer, a second N-type well layer, and a second P-type well layer in parallel. A deep N-type well layer is provided between the first N-type well layer, the first P-type well layer, the second N-type well layer and the substrate; A first P-type doped layer and a second P-type doped layer are covered on the first N-type well layer, the second P-type doped layer extends to the first P-type well layer, and a first trench is provided between the first P-type doped layer and the second P-type doped layer; The second P-type well layer is provided with a first N-type doped layer and a third P-type doped layer, a second trench is provided between the first N-type doped layer and the third P-type doped layer, and a third trench is provided between the second P-type doped layer and the first N-type doped layer. The first P-type doped layer is connected to the anode; The second P-type doped layer, the first N-type doped layer, and the third P-type doped layer are all connected to the cathode.

2. The high holding voltage ESD protection device as described in claim 1, characterized in that, The first trench extends to the first N-type well layer; The second trench extends into the second P-type well layer; The third trench extends to the first P-type well layer, the second N-type well layer, and the second P-type well layer.

3. The high holding voltage ESD protection device as described in claim 1, characterized in that, The first P-type doped layer, the first N-type well layer, the deep N-type well layer, the second N-type well layer, and the second P-type well layer together constitute a parasitic PNP transistor.

4. The high holding voltage ESD protection device as described in claim 3, characterized in that, The first N-type well layer, the deep N-type well layer, the second N-type well layer, the second P-type well layer, and the first N-type doped region together constitute a parasitic NPN transistor.

5. The high holding voltage ESD protection device as described in claim 4, characterized in that, The parasitic PNP transistor and the parasitic NPN transistor constitute an SCR structure.

6. The high holding voltage ESD protection device as described in claim 5, characterized in that, The first P-type doped layer, the first N-type well layer, and the second P-type doped layer form a PNP transistor.

7. The high holding voltage ESD protection device as described in claim 6, characterized in that, The PNP transistor forms the trigger path; The SCR structure forms the main discharge path.

8. The high holding voltage ESD protection device as described in claim 1, characterized in that, The substrate is a P-type substrate.

9. A high-holding-voltage ESD protection method, employing the high-holding-voltage ESD protection device as described in any one of claims 1-8, characterized in that, When the ESD voltage reaches the sum of the forward bias voltage of the first P-type doped layer or the first N-type well layer and the reverse bias voltage of the first N-type well layer or the second P-type doped layer, the trigger path formed by the first P-type doped layer, the first N-type well layer and the second P-type doped layer is turned on. When the ESD voltage increases further, the parasitic PNP transistor formed by the first P-type doped layer, the first N-type well layer, the deep N-type well layer, the second N-type well layer, and the second P-type well layer, together with the first N-type well layer, the deep N-type well layer, the second N-type well layer, the second P-type well layer, and the first N-type doped region, forms a parasitic NPN transistor, creating a positive feedback path. The parasitic PNP transistor and the parasitic NPN transistor together form an SCR structure, and the main discharge path formed by the SCR structure is turned on.

10. The high holding voltage ESD protection method as described in claim 9, characterized in that, In the triggering path, the current flows from the first P-type doped layer, through the first N-type well layer, to the second P-type doped layer; In the main discharge path, the current flows from the first P-type doped layer, through the first N-type well layer, the deep N-type well layer, the substrate, and the second P-type well layer, back to the first N-type doped layer. Alternatively, it can flow through the first N-type well layer, the deep N-type well layer, the second N-type well layer, and the second P-type well layer to the first N-type doped layer.

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