High-precision clock frequency and phase detection system and method
By using adaptive gate time and three-level resolution phase detection, combined with intelligent data fusion algorithms, the contradiction between accuracy and speed in frequency measurement equipment is resolved, achieving high-precision frequency and high-resolution phase measurement, while reducing system complexity and cost.
Patent Information
- Application Number
- CN202511761202.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-02-24
AI Technical Summary
In existing technologies, frequency measurement equipment struggles to balance accuracy and speed, while phase measurement equipment is costly and has limited resolution, making it difficult to achieve both high-precision frequency measurement and high-resolution phase measurement within the same system.
By employing adaptive gate timing technology and three-level resolution phase detection, combined with intelligent data fusion algorithms, high-precision frequency measurement and high-resolution phase measurement are achieved through dynamic adjustment and data processing of the frequency measurement module and the phase measurement module.
While ensuring measurement speed, it significantly improves frequency measurement accuracy and phase measurement resolution, reduces system complexity and cost, and achieves a balance between high performance and low cost.
Smart Images
Figure CN121567121A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic measurement technology, specifically relating to a high-precision clock frequency and phase discrimination system and method. Background Technology
[0002] In the field of electronic measurement, especially in high-speed communication, test and measurement, and clock synchronization systems, it is necessary to accurately measure the frequency difference and phase difference between two clock signals. Existing technologies mainly employ frequency measurement based on digital counters and phase measurement based on time-to-digital converters (TDCs), but these solutions have significant drawbacks.
[0003] For frequency measurement, traditional methods such as direct counting require counting clock cycles within a fixed gate time. To achieve a measurement accuracy of 1Hz, a 1-second gate time is theoretically required for a 100MHz clock, resulting in slow measurement speed and an inability to respond quickly to frequency changes. If the gate time is shortened to pursue measurement speed, the frequency resolution will be significantly reduced, creating an irreconcilable contradiction between accuracy and speed.
[0004] Phase measurements are typically achieved by determining the time difference between the rising edges of two clock signals. This relies on high-frequency system clock counting, and the phase resolution is limited by the system clock period. For example, with a 100MHz system clock (10ns period), the phase measurement resolution can only reach a maximum of 10ns. To improve the resolution, a higher frequency system clock is required, which inevitably increases system cost and power consumption and is also limited by device performance.
[0005] In addition, existing technologies include systems that integrate frequency counters and phase detectors, but the two modules usually operate independently, failing to resolve the aforementioned contradictions between accuracy and speed, resolution and cost, and making it difficult to achieve high-precision frequency measurement and high-resolution phase measurement simultaneously in the same system.
[0006] Therefore, there is an urgent need for a technical solution that can balance frequency measurement accuracy and speed, improve phase measurement resolution, and control system complexity and cost. Summary of the Invention
[0007] The purpose of this invention is to overcome the shortcomings of the prior art and to propose a system and method that can simultaneously achieve high-precision frequency measurement and high-resolution phase measurement.
[0008] First, this invention discloses a high-precision clock frequency and phase detection system, comprising the following modules: Clock input and preprocessing module: used to receive the reference clock signal and the clock signal under test, and to shape, de-jitter and synchronize the clock signal to ensure the stability of subsequent measurements; Frequency measurement module: used to count the reference clock and the clock under test. The reference clock generates an adjustable gate signal and dynamically adjusts the gate time according to the frequency difference of the last measurement. When the frequency difference is large, a short gate time is used, and when the frequency difference is small, a long gate time is used. Phase measurement module: Employs time-to-digital converter technology to measure the time difference between the rising edges of the reference clock and the clock under test through a combination of coarse and fine measurements. The coarse measurement utilizes system clock counting, while the fine measurement uses digital interpolation technology to measure time intervals less than one system clock cycle. Data processing and control module: controls the entire measurement process, adjusts parameters based on the measurement results of the frequency measurement module and the phase measurement module, implements an adaptive algorithm, and fuses multiple measurement results through a filtering algorithm to calculate the final frequency difference and phase difference, and outputs a valid data signal; Output interface module: Provides a standard interface to output measurement results, including frequency difference, phase difference, and valid data signal.
[0009] Furthermore, the gate time adjustment strategy of the frequency measurement module satisfies: T = min (1, 1 / |Δf_curr|) Where: Δf_curr is the frequency difference of the previous measurement, and the minimum upper limit of the gate time is 1μs, and the maximum upper limit is 10s.
[0010] Furthermore, the digital interpolation technology of the phase measurement module is implemented through a high-speed tapped delay chain, which subdivides the system clock cycle into multiple small intervals and determines the fine measurement value by detecting the propagation position of the signal on the delay chain.
[0011] Furthermore, the high-speed tap delay chain is a carry chain in the FPGA.
[0012] Furthermore, the initial gate time of the frequency measurement module is 1ms. When the measured frequency difference is greater than 100Hz, the next measurement uses a gate time of 10ms; when the measured frequency difference is less than 100Hz, the next measurement uses a gate time of 1s.
[0013] Furthermore, the data processing and control module adjusts the parameters as follows: weighted average fusion is applied to the frequency measurement data, with the weight proportional to the gate time; outliers are removed from the phase measurement data before averaging.
[0014] Furthermore, the data processing and control module uses the rate of change of phase difference to assist frequency measurement. The frequency difference is obtained by dividing the change in phase difference by the time interval, and is cross-checked with the direct frequency measurement result.
[0015] Furthermore, the present invention also provides a high-precision clock frequency and phase detection method, comprising the following steps: S1: After the system is powered on and reset, the frequency is measured using the default gate time to obtain a rough frequency difference; S2: Adjust the gate time according to the coarse frequency difference. When the coarse frequency difference is greater than the preset threshold, use a shorter gate time. When the coarse frequency difference is less than the preset threshold, use a longer gate time. S3: While performing frequency measurement, start phase measurement and continuously measure the time difference between the rising edges of two clocks; S4: Collect frequency and phase measurement data, filter the frequency measurement values, and perform statistical processing on the phase measurement values; S5: Once the frequency and phase data are stable, output the final measurement result.
[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. Adaptive Gate Time Technology: This invention breaks through the traditional trade-off between accuracy and speed in frequency measurement. Through adaptive gate time technology, the system can automatically adjust the gate time according to the characteristics of the input signal, thereby significantly improving measurement accuracy while maintaining measurement speed. The application of this technology enables frequency measurement equipment to provide consistent high-precision measurement results over a wider frequency range, maintaining excellent measurement performance in both high and low frequency bands.
[0017] 2. Three-Level Resolution Phase Detection: This invention effectively overcomes the limitations of traditional system clocks by employing a three-level resolution phase detection method. In traditional frequency measurements, the resolution of the system clock often limits measurement accuracy, especially when processing high-frequency signals. The three-level resolution phase detection technology, through innovative signal processing methods, achieves high-precision measurement of the signal phase, enabling the system to maintain high-speed measurement while simultaneously achieving accurate signal frequency measurement.
[0018] 3. Intelligent Data Fusion Algorithm: To improve the system's reliability and measurement accuracy, this invention employs an intelligent data fusion algorithm. This algorithm effectively integrates information from multiple measurement data sources, eliminating random and systematic errors during the measurement process through intelligent data processing and analysis, thereby improving the overall system's measurement accuracy and reliability. The application of this algorithm makes frequency measurement results more stable and reliable, significantly reducing measurement errors.
[0019] 4. Unified Optimized Architecture: This invention employs a unified optimized system architecture design. This design enables the system to simultaneously achieve high-precision frequency and phase measurements. By optimizing the system architecture, not only is the overall system performance improved, but the system complexity is also simplified, making the system more stable and reliable. This unified optimized architecture design provides a more flexible and efficient solution for frequency measurement equipment.
[0020] 5. Cost-Effective Design: Cost-effectiveness was fully considered during the research and development of this technology. By adopting a design philosophy that combines high performance with low cost, this technology successfully achieves a perfect balance between the two. This design not only ensures the excellent performance of the system but also significantly reduces the system's manufacturing cost, making the frequency measurement equipment more economical and practical. This cost-effective design gives this technology a wider range of market application prospects. Attached Figure Description
[0021] The accompanying drawings are incorporated in and form part of this specification, and together with the description serve to explain the principles of the invention.
[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a diagram of the architecture of the high-precision clock frequency and phase detection system of the present invention. Detailed Implementation
[0024] Exemplary embodiments will now be described in detail. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples consistent with some aspects of the invention as detailed in the appended claims.
[0025] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Example
[0026] First, this invention discloses a high-precision clock frequency and phase detection system, comprising the following modules: Clock input and preprocessing module: used to receive the reference clock signal and the clock signal under test, and to shape, de-jitter and synchronize the clock signal to ensure the stability of subsequent measurements; may include differential to single-ended conversion (if the input is a differential signal).
[0027] Frequency measurement module: It counts the reference clock and the clock under test respectively. The reference clock generates an adjustable gate signal and dynamically adjusts the gate time according to the frequency difference of the previous measurement. When the frequency difference is large, a short gate time is used, and when the frequency difference is small, a long gate time is used. For example, if the initial gate time is 1ms, and the measured frequency difference is 100Hz, the next measurement will use a gate time of 1s to improve accuracy.
[0028] Phase Measurement Module: Employing time-to-digital converter (TDC) technology, this module measures the time difference between two rising clock edges using a combination of coarse and fine measurements. The coarse measurement utilizes the system clock for counting, while the fine measurement uses digital interpolation to measure time intervals less than one system clock cycle. Specifically, it uses TDC technology to measure the time difference between two rising clock edges. TDC Implementation: It utilizes a high-speed tapped delay chain (such as a carry chain in an FPGA) to interpolate the system clock cycle, achieving picosecond-level resolution. Phase measurement includes coarse counting and fine measurement: coarse counting uses the system clock, while fine measurement uses the tap position of the delay chain.
[0029] Data processing and control module: Controls the entire measurement process, adjusts parameters based on the measurement results from the frequency and phase measurement modules, implements an adaptive algorithm, and fuses multiple measurement results through a filtering algorithm to calculate the final frequency difference and phase difference, and outputs a valid data signal; controls the entire measurement process and adjusts parameters based on the frequency and phase measurement results.
[0030] Specifically, the system implements an adaptive algorithm: dynamically adjusting the gate time and measurement mode based on the frequency difference trend. Data fusion: combining multiple measurement results using a filtering algorithm (such as Kalman filtering) improves accuracy and stability. The final frequency difference and phase difference are calculated, and the valid data signal is output.
[0031] Output interface module: Provides a standard interface to output measurement results, including frequency difference, phase difference, and valid data signal.
[0032] Specifically, it provides standard SPI interface output of measurement results. The output includes: frequency difference (32-bit signed integer, in Hz), phase difference (32-bit unsigned integer, in ps), and data valid signal.
[0033] like Figure 1 As shown, from left to right, the topmost module is the clock input preprocessing module, which receives external clock signals and connects to the frequency measurement module and the phase measurement module respectively.
[0034] The frequency measurement module and the phase measurement module are bidirectionally connected, and both are connected to the data fusion processing module below. The data fusion processing module receives feedback signals from the adaptive control module on its left side.
[0035] The data fusion processing module is connected to the result output module on the right, forming a complete signal processing and output link.
[0036] The core ideas of this invention include the following aspects: 1. Frequency Measurement: Employs multi-cycle synchronous measurement technology with adaptive gate time. While traditional fixed gate time (e.g., 1 second) can achieve a resolution of 1Hz, the measurement time is long and the response speed is slow. We dynamically adjust the gate time based on the current frequency difference being measured. When the frequency difference is large, a short gate time is used for rapid acquisition; when the frequency difference is small, a long gate time is used to improve accuracy.
[0037] 2. Phase Measurement: Combining coarse and fine measurements. Coarse measurement utilizes system clock counting, while fine measurement uses digital interpolation techniques (such as TDC) to measure time intervals less than one system clock cycle, achieving high-resolution phase detection.
[0038] 3. Data Fusion: Employing intelligent filtering algorithms (such as Kalman filtering or moving average filtering) and adaptive data processing, it simultaneously outputs high-precision frequency and phase information.
[0039] Furthermore, the gate time adjustment strategy of the frequency measurement module satisfies: T = min (1, 1 / |Δf_curr|) Where: Δf_curr is the frequency difference of the previous measurement, and the minimum upper limit of the gate time is 1μs, and the maximum upper limit is 10s.
[0040] Specifically, adaptive gate time frequency measurement: Traditional frequency measurement: Frequency = Count value / Gate time. With a fixed gate time, the trade-off between accuracy and speed needs to be addressed. A specific solution is: Assuming the target frequency accuracy is Δf (e.g., 1Hz), the gate time T must be at least 1 / Δf seconds. However, if the current frequency difference is known to be approximately Δf_curr, T can be adjusted based on Δf_curr. The adjustment strategy is: T = min(1, 1 / |Δf_curr|) seconds, but with upper and lower limits set, for example, a minimum gate time of 1µs and a maximum of 10s. In actual implementation, a reference clock is used to generate the gate signal, and the gate time is determined by the number of cycles of the reference clock. For example, if the reference clock is 100MHz, a 1-second gate requires 100e6 cycles to count. A 1ms gate requires 100e3 cycles to count.
[0041] Furthermore, the digital interpolation technology of the phase measurement module is implemented through a high-speed tapped delay chain, which subdivides the system clock cycle into multiple small intervals and determines the fine measurement value by detecting the propagation position of the signal on the delay chain.
[0042] Specifically, the TDC phase measurement principle is as follows: A delay chain is used to subdivide the system clock period into multiple small intervals. The time interval is measured by detecting the propagation position of the signal on the delay chain. The specific implementation is as follows: a) Assuming the system clock is 100MHz with a period of 10ns, we use a delay chain to divide 10ns into 256 parts, resulting in a resolution of approximately 39ps. b) Measuring the time difference between the rising edges of two clocks: When the rising edge of the reference clock arrives, TDC counting is started (coarse counting begins, and the delay chain starts working simultaneously); when the rising edge of the clock being measured arrives, TDC is stopped, and the coarse and fine counts (the tap positions of the delay chain) are recorded. c) Time difference = Coarse count × System clock period + Fine count × Delay chain resolution.
[0043] Furthermore, the high-speed tap delay chain is a carry chain in the FPGA.
[0044] Furthermore, the initial gate time of the frequency measurement module is 1ms. When the measured frequency difference is greater than 100Hz, the next measurement uses a gate time of 10ms; when the measured frequency difference is less than 100Hz, the next measurement uses a gate time of 1s.
[0045] Furthermore, the data processing and control module employs a weighted average fusion method for the frequency measurement data, with the weights proportional to the gate time; for the phase measurement data, outliers are first removed before averaging.
[0046] Furthermore, the data processing and control module uses the rate of change of phase difference to assist frequency measurement. The frequency difference is obtained by dividing the change in phase difference by the time interval, and is cross-checked with the direct frequency measurement result.
[0047] Specifically, for frequency measurement data: due to the adaptive gate time, the accuracy of each measurement varies, so a weighted average is used, with the weight proportional to the gate time (the longer the gate time, the greater the weight); for phase measurement data: multiple consecutive measurements are taken, obvious outliers (such as sudden changes due to jitter) are removed, and then the average is taken; the correlation between frequency and phase data: the frequency difference is the rate of change of the phase difference, so we can use the change in phase difference to assist in frequency measurement; for example, the frequency difference can be obtained by dividing the change in phase difference by the time interval, and then cross-checked with the direct frequency measurement results.
[0048] Furthermore, the present invention also provides a high-precision clock frequency and phase detection method, comprising the following steps: S1: After the system is powered on and reset, the frequency is measured using the default gate time to obtain a rough frequency difference; S2: Adjust the gate time according to the coarse frequency difference. When the coarse frequency difference is greater than the preset threshold, use a shorter gate time. When the coarse frequency difference is less than the preset threshold, use a longer gate time. S3: While performing frequency measurement, start phase measurement and continuously measure the time difference between the rising edges of two clocks; S4: Collect frequency and phase measurement data, filter the frequency measurement values, and perform statistical processing on the phase measurement values; S5: Once the frequency and phase data are stable, output the final measurement result.
[0049] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention.
[0050] It should be understood that the present invention is not limited to the content already described above, and various modifications and changes can be made without departing from its scope. The scope of the present invention is limited only by the appended claims.
Claims
1. A high-precision clock frequency and phase detection system, characterized in that, Includes the following modules: Clock input and preprocessing module: used to receive the reference clock signal and the clock signal under test, and to shape, de-jitter and synchronize the clock signal to ensure the stability of subsequent measurements; Frequency measurement module: used to count the reference clock and the clock under test. The reference clock generates an adjustable gate signal and dynamically adjusts the gate time according to the frequency difference of the last measurement. When the frequency difference is large, a short gate time is used, and when the frequency difference is small, a long gate time is used. Phase measurement module: Employs time-to-digital converter technology to measure the time difference between the rising edges of the reference clock and the clock under test through a combination of coarse and fine measurements. The coarse measurement utilizes system clock counting, while the fine measurement uses digital interpolation technology to measure time intervals less than one system clock cycle. Data processing and control module: controls the entire measurement process, adjusts parameters based on the measurement results of the frequency measurement module and the phase measurement module, implements an adaptive algorithm, and fuses multiple measurement results through a filtering algorithm to calculate the final frequency difference and phase difference, and outputs a valid data signal; Output interface module: Provides a standard interface to output measurement results, including frequency difference, phase difference, and valid data signal.
2. The high-precision clock frequency and phase detection system according to claim 1, characterized in that, The gate time adjustment strategy of the frequency measurement module satisfies: T = min (1, 1 / |Δf_curr|) Where: Δf_curr is the frequency difference of the previous measurement, and the minimum upper limit of the gate time is 1μs, and the maximum upper limit is 10s.
3. The high-precision clock frequency and phase detection system according to claim 1, characterized in that, The digital interpolation technology of the phase measurement module is implemented through a high-speed tapped delay chain, which subdivides the system clock cycle into multiple small intervals and determines the fine measurement value by detecting the propagation position of the signal on the delay chain.
4. The high-precision clock frequency and phase detection system according to claim 3, characterized in that, The high-speed tap delay chain is a carry chain in the FPGA.
5. A high-precision clock frequency and phase detection system according to claim 1, characterized in that, The initial gate time of the frequency measurement module is 1ms. When the measured frequency difference is greater than 100Hz, the next measurement uses a gate time of 10ms; when the measured frequency difference is less than 100Hz, the next measurement uses a gate time of 1s.
6. The high-precision clock frequency and phase detection system according to claim 1, characterized in that, The parameter adjustment in the data processing and control module is as follows: weighted average fusion is applied to the frequency measurement data, with the weight proportional to the gate time; outliers are removed from the phase measurement data before averaging.
7. A high-precision clock frequency and phase detection system according to claim 1, characterized in that, The data processing and control module uses the rate of change of phase difference to assist frequency measurement. The frequency difference is obtained by dividing the change of phase difference by the time interval, and is cross-checked with the direct frequency measurement result.
8. A high-precision clock frequency and phase detection method based on any one of claims 1 to 7, characterized in that, Includes the following steps: S1: After the system is powered on and reset, the frequency is measured using the default gate time to obtain a rough frequency difference; S2: Adjust the gate time according to the coarse frequency difference. When the coarse frequency difference is greater than the preset threshold, use a shorter gate time. When the coarse frequency difference is less than the preset threshold, use a longer gate time. S3: While performing frequency measurement, start phase measurement and continuously measure the time difference between the rising edges of two clocks; S4: Collect frequency and phase measurement data, filter the frequency measurement values, and perform statistical processing on the phase measurement values; S5: Once the frequency and phase data are stable, output the final measurement result.