Precision reconfigurable high-speed time domain analog-to-digital converter

Abstract

The invention relates to a precision reconfigurable high-speed time domain analog-to-digital converter, which comprises a voltage-time converter used for converting a received input voltage signal into a time pulse signal so as to transmit the time pulse signal to a reconfigurable pipeline time-to-digital converter, and outputting a one-bit digital code to a digital logic circuit at the same time; the reconfigurable pipeline time-to-digital converter comprises n stages of pipelines, and the total effective stage number of the n stages of pipelines is controlled by a first configuration signal. The quantization precision of each level of assembly line is independently configured between 1.5 bits and 2 bits, and the n levels of assembly lines work in parallel in an odd-even assembly line level alternating mode; each stage of assembly line is quantized and generates a current stage of digital code, and the quantized residual time quantity is amplified as output and provided for the next stage of assembly line; and the digital logic circuit sums all the received digital codes into M-bit effective digital codes according to weights. The device can adapt to various high-speed application scenes with different precision requirements.

Description

Technical Field

[0001] This invention belongs to the field of data converter design technology, specifically relating to a high-speed time-domain analog-to-digital converter with reconfigurable precision. Background Technology

[0002] With the continuous advancement of semiconductor process technology, CMOS process technology nodes have evolved from the micrometer scale to the nanometer scale. This places higher demands on the performance of analog-to-digital converters (ADCs), especially in applications requiring a balance between high speed and high precision, such as high-speed communication, precision instruments, and medical imaging. Among various ADC architectures, voltage-domain pipelined ADCs have long been considered one of the ideal solutions for achieving high-speed, high-precision ADC conversion due to their good balance between speed and precision. However, in this type of architecture, each stage except the final pipeline stage includes a high-gain, high-bandwidth operational amplifier as a voltage margin amplifier. This not only significantly increases the overall circuit design complexity but also leads to high system power consumption, further exacerbating the difficulty of implementation at advanced process nodes.

[0003] To overcome the bottleneck of margin amplifiers in voltage-domain designs, highly digitized time-domain analog-to-digital converters (ADCs) have attracted widespread attention in recent years. This type of architecture utilizes time amplifiers to achieve margin amplification in the time domain, effectively reducing design complexity and power consumption, and is more conducive to implementation in advanced CMOS processes. However, existing time-domain pipelined converters, such as time-to-digital converters based on gated delay lines, typically have their accuracy fixed during the design phase, making it impossible to dynamically adjust the conversion accuracy according to the needs of different application scenarios during operation. This greatly limits their application flexibility and system energy efficiency. Therefore, how to achieve a time-domain ADC that maintains high-speed characteristics while possessing reconfigurable accuracy during operation has become a pressing technical problem to be solved in this field. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a high-speed time-domain analog-to-digital converter with reconfigurable precision. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a high-speed time-domain analog-to-digital converter with reconfigurable precision, comprising: Voltage-to-time converters, reconfigurable pipelined time-to-digital converters, and digital logic circuits; The voltage-to-time converter is used to convert the received input voltage signal into a time pulse signal for transmission to the first stage pipeline of the reconfigurable pipelined time-to-digital converter, and simultaneously outputs a 1-bit digital code to the digital logic circuit. The reconfigurable pipelined time-to-digital converter includes cascaded n-stage pipelines. The total effective number of the n-stage pipelines is controlled by a first configuration signal. The quantization accuracy of each pipeline stage can be independently configured between 1.5 bits and 2 bits. Under a unified clock control signal, the n-stage pipelines operate in parallel by alternating between odd and even pipeline stages for sampling and quantization-margin amplification. Each pipeline quantizes the input time pulse signal to generate the digital code of that stage, and amplifies the residual time of quantization as the output, which is then provided to the next pipeline as its input time pulse signal. The digital logic circuit is used to receive a 1-bit digital code sent by the voltage-time converter and a multi-bit digital code generated by the reconfigurable pipeline time-digit converter; and to perform digital weighting and summation of all digital codes according to their respective weights to output an M-bit valid digital code.

[0005] Compared with the prior art, the beneficial effects of the present invention are as follows: To address the problem that existing analog-to-digital converters (ADCs) are fixed at the design stage and cannot dynamically adjust conversion accuracy according to different application scenarios during operation, this invention provides a high-speed time-domain ADC with reconfigurable accuracy. By introducing a dual reconfigurable architecture—configurable total pipeline stages and independently configurable accuracy per stage (between 1.5 bits and 2 bits)—the converter can flexibly adjust the overall conversion accuracy according to actual application requirements, thereby significantly improving system applicability and energy efficiency while maintaining high-speed conversion. This architecture fully utilizes the characteristics of highly digitized circuits, replacing traditional voltage margin amplifiers with time amplifiers, effectively reducing design complexity and power consumption. This invention enables a single converter to adapt to various application scenarios with different accuracy requirements, achieving optimized configuration of performance and power consumption at the system level, and broadening the application scenarios of high-speed time-domain ADCs. Attached Figure Description

[0006] Figure 1 This is a structural block diagram of the high-speed time-domain analog-to-digital converter with reconfigurable precision provided in the embodiments of the present invention; Figure 2 This is a schematic diagram of the circuit connection of each stage of the production line provided in the embodiment of the present invention. Detailed Implementation

[0007] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0008] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0009] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0010] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0011] The following is a detailed description of a high-speed time-domain analog-to-digital converter with reconfigurable precision proposed in this invention, with reference to the accompanying drawings.

[0012] Figure 1 This is a structural block diagram of a high-speed time-domain analog-to-digital converter with reconfigurable precision provided in an embodiment of the present invention. For example... Figure 1As shown, it includes: a voltage-to-time converter, a reconfigurable pipelined time-to-digital converter, and digital logic circuitry; wherein, the voltage-to-time converter is used to convert the received input voltage signal into a time pulse signal for transmission to the first stage pipeline of the reconfigurable pipelined time-to-digital converter, and simultaneously outputs a 1-bit digital code to the digital logic circuitry; the reconfigurable pipelined time-to-digital converter includes n cascaded pipelines, the total effective number of n pipelines being controlled by a first configuration signal, wherein the quantization precision of each pipeline stage can be independently configured between 1.5 bits and 2 bits, and the n pipelines in... Under a unified clock control signal, sampling and quantization-margin amplification are performed in parallel using an alternating odd and even pipeline stage. Each pipeline stage quantizes the input time pulse signal, generates its own digital code, and amplifies the residual time value as the output, providing it to the next pipeline stage as its input time pulse signal. The digital logic circuit receives the 1-bit digital code sent by the voltage-time converter and the multi-bit digital code generated by the reconfigurable pipelined time-to-digital converter. It then performs digital weighting and summation of all digital codes according to their respective weights, outputting an M-bit valid digital code.

[0013] Here, the total effective number of n pipeline stages is controlled by the first configuration signal, meaning the ADC's resolution is variable. For example, assuming the chip physically integrates 10 pipeline stages, in a scenario requiring 12-bit resolution, the first configuration signal is set to: enable all 10 pipeline stages; the input signal sequentially passes through all 10 pipeline stages, with the first 9 stages configured in 1.5-bit mode and the 10th stage configured in 2-bit mode. Combined with the 1-bit digital code output from the voltage-to-time converter, a 12-bit digital code is ultimately generated as a valid output. In a scenario requiring 8-bit resolution, the first configuration signal is set to: enable only the first 6 stages; the first 5 pipeline stages are configured in 1.5-bit mode, the 6th stage is configured in 2-bit mode, and combined with the 1-bit digital code output from the voltage-to-time converter, a 8-bit digital code is ultimately generated as a valid output.

[0014] The specific circuit structure of this analog-to-digital converter is described here. It should be noted that the voltage-to-time converter and digital logic circuit are existing circuit structures, and will not be elaborated upon here for the sake of simplicity.

[0015] Figure 2 This is a schematic diagram of the circuit connection of each stage of the production line provided in an embodiment of the present invention. Figure 2 As shown, each stage of the pipeline includes: an OR gate, a gated delay line, a digital code generator, an output switch array, a margin signal amplifier, and a quantization precision configuration group; the first input of the OR gate is connected to the circuit trigger signal Trigger, and the second input is connected to the time pulse signal T from the voltage-to-time converter or the previous stage pipeline. INThe output terminal is connected to the first to eighth input terminals of the gated delay line; the reset terminal of the gated delay line is connected to the reset signal SET; the first to third output terminals of the gated delay line are respectively connected to the first to third input terminals of the digital code generator, and the first to third clock terminals of the digital code generator are connected to the trigger signal Clk. FF The first to third outputs of the digital code generator are all connected to the inputs of the digital logic circuit; the fourth to sixth outputs of the gated delay line are respectively connected to the first to third inputs of the output switch array, and the output of the output switch array is connected to the input of the margin signal amplifier; the output of the margin signal amplifier is connected to the second input of the OR gate of the next stage pipeline; the digital code generator is used to trigger the Clk signal. FF Under the control of [unclear], the quantization state of the gated delay line is latched and the current level digital code is output; the quantization precision configuration group is coupled to the reset terminal and the first input terminal of the gated delay line, as well as the third clock terminal and the ground terminal of the digital code generator, respectively, to configure the quantization precision of the current pipeline to 1.5 bits or 2 bits in response to the precision configuration signal; an OR gate is used to [unclear] the circuit trigger signal Trigger and the time pulse signal T [unclear]. IN Perform a logical OR operation to generate the enable control signal EN for the gated delay line; the gated delay line is used to control the time pulse signal T during the effective period of the enable control signal EN. IN The pulse width is quantized, and its quantized state is output to the digital code generator.

[0016] Specifically, the gated delay lines consist of eight identical, serially connected lines with the same delay time. The output of the delay or gate is connected to the enable terminal of each delay.

[0017] Based on this, the output switch array includes switch S0, switch S1 and switch S2; one end of switch S0 is located between the fourth and fifth delay units, one end of switch S1 is located between the sixth and seventh delay units, and one end of switch S2 is located at the output terminal of the eighth delay unit; the other ends of switch S0, switch S1 and switch S2 are all connected to the input terminal of the margin signal amplifier.

[0018] Preferably, the digital code generator includes three D flip-flops with identical structures; the D terminal of the first D flip-flop is positioned between the third and fourth delay units, the D terminal of the second D flip-flop is positioned between the fifth and sixth delay units, and the D terminal of the third D flip-flop is positioned between the seventh and eighth delay units; the clock terminal of each D flip-flop is connected to a trigger signal Clk. FF The output terminals are each connected to one input terminal of a digital logic circuit.

[0019] Here, the circuit trigger signal Trigger, the reset signal SET, and the trigger signal Clk are... FF The timing sequence is generated and synchronized with a unified clock control signal; the effective level of the reset signal SET is used to initialize the state of the gated delay line; the effective level of the circuit trigger signal Trigger is used for margin amplification operation; the trigger signal Clk... FF The effective edge is used to control the digital code generator to latch the quantization state of the gated delay line.

[0020] Preferably, the quantization accuracy configuration group includes a programmable switch S M1 Programmable switch S M2 Programmable switch S M3 and programmable switch S M4 Programmable switch S M1 and programmable switch S M2 The programmable switch S operates in the opposite manner. M3 and programmable switch S M4 The operating states are reversed; programmable switch S M1 Programmable switch S is set at the first input of the gated delay line. M2 The programmable switch S is located at the reset terminal of the gate delay line. M3 and programmable switch S M4 All are set at the clock input of the third D flip-flop; programmable switch S M3 When the circuit is turned on, the clock input of the third D flip-flop is connected to the trigger signal Clk. FF Programmable switch S M3 When turned off, there is no signal input at the clock input of the third D flip-flop; programmable switch S M4 When the circuit is turned on, the clock input of the third D flip-flop is grounded, and the programmable switch S... M4 When switched off, it is not grounded; in programmable switch S M1 and programmable switch S M4 On, and programmable switch S M2 and programmable switch S M3 In the off state, all eight delays in the gated delay line operate normally, and the third D flip-flop is disabled, thus configuring the current pipeline's quantization precision to 1.5-bit mode; with programmable switch S... M1 and programmable switch S M4 Off, and programmable switch S M2 and programmable switch S M3 When the circuit is on, the first delayer in the gated delay line loses its delay function, the remaining seven delayers work normally, and the third D flip-flop is enabled, thus configuring the quantization precision of the current pipeline to 2-bit mode.

[0021] For example, in the programmable switch SM1 and programmable switch S M4 On, and programmable switch S M2 and programmable switch S M3 In the case of shutdown, due to S M1 On, S M2 With the first delay in the gated delay line enabled by EN, all eight delays are functioning normally. The effective portion of the entire gated delay line used for quantization consists of eight delays. The third D flip-flop is connected via S... M4 When connected to ground, its output is locked to a low level and does not participate in quantization.

[0022] At this point, only the first two D flip-flops are active. This is based on the input time signal T. IN The width of the gated delay line will produce different states, but the final latched output code is only one of three numeric codes: 00, 01, and 11. This is precisely the characteristic output of a 1.5-bit pipeline.

[0023] For example, in the programmable switch S M1 and programmable switch S M4 Disconnect, and programmable switch S M2 and programmable switch S M3 When the circuit is on, due to the programmable switch S M1 Disconnect and programmable switch S M2 The gated delay line is activated when the reset terminal of the first delay is connected to SET. When SET goes high, the first delay is immediately enabled, and after a delay time... Then, the SET signal is passed to the input of the second delay unit, and then when T... IN Upon arrival, quantization is performed again. At this point, the first delay unit fails, leaving only seven effective delay units in the entire gated delay line; simultaneously, due to S... M3 On and S M4 Disconnect, trigger signal Clk FF The clock signal is connected to the third D flip-flop, enabling it to perform quantization operations normally. At this time, all three D flip-flops in the digital code generator are working normally, fully latching the state of the gated delay line, and generating four digital codes: 000, 001, 011, and 111, achieving a complete 2-bit resolution.

[0024] Through the coordinated configuration of these four switches, the system cleverly reconfigures the number of comparator thresholds and the effective length of the gated delay line at the hardware level, thereby achieving seamless configuration between 1.5-bit (3 output codes, with redundancy) and 2-bit (4 output codes, without redundancy) quantization accuracies. This not only changes the resolution of this stage but also affects the accuracy and fault tolerance of the entire ADC chain by altering the margin propagation characteristics.

[0025] The above describes the circuit connection relationship of a single-stage pipeline. Now, a specific example will be used to illustrate the working process of a single-stage pipeline.

[0026] Assume the pulse width of the time pulse signal input to a certain stage of the pipeline is 4.6. Furthermore, the quantization precision of this pipeline stage is 1.5 bits. The time pulse signal undergoes reset-sampling-quantization-margin amplification sequentially within the single-stage pipeline. Specifically: (1) Reset Phase: In the initial reset phase, the circuit trigger signal Trigger, the reset signal SET, and the D flip-flop trigger signal Clk are activated. FF All are at low level. At this time, the outputs of all eight delay circuits inside the gated delay line are reset to low level, and the entire circuit is in a reset state.

[0027] (2) Sampling Phase: When the reset signal SET goes high, the system enters the sampling phase. After the SET signal goes high for a short period, the input time pulse signal T is activated. IN When the signal is high, after an OR gate operation, the enable control signal EN becomes high, and the gated delay line starts working. Because T... IN The pulse width is 4.6. When T IN During the period of holding the high level, the high level of the SET signal is propagated step by step through the gated delay line. At T IN After the transition to low level, the outputs of delay units 1 to 4 have become high level, while the outputs of delay units 5 to 8 remain low level.

[0028] (3) Quantization stage: After the sampling stage is completed, the trigger signal Clk is triggered. FF A valid rising edge is generated, and the three D flip-flops simultaneously sample the signal state at their respective inputs. At this time: The first D flip-flop (connected between delays 3 and 4) samples a high level; The second D flip-flop (connected between delays 5 and 6) samples a low level; The third D flip-flop is disabled, so its output is always low. Therefore, the digital code output by this stage of the pipeline is D2D1D0=001.

[0029] (4) Margin amplification stage: According to the quantization result D2D1D0=001, switch S1 in the output switch array is turned on. When the circuit trigger signal Trigger goes high, the EN signal becomes valid again, and the SET signal is transmitted to the input of the time amplifier TA through the path of the turned-on switch S1 (i.e., between the sixth and seventh delayers).

[0030] The time difference between the rising edge of the Trigger signal and the rising edge of the S1 path output is the quantization residual time. .

[0031] The quantization residual time is amplified by the time amplifier TA at a predetermined gain and then passed to the next stage time-to-digital converter for further quantization processing, thus completing the entire workflow of this stage of the pipeline.

[0032] In one possible implementation, the n-stage pipeline operates in parallel with alternating odd and even pipeline stages, performing sampling and quantization-margin amplification under a unified clock control signal. This includes: in response to the unified clock control signal being at a first level, odd-numbered pipeline stages perform sampling operations, while even-numbered pipeline stages perform quantization and margin amplification operations; in response to the unified clock control signal being at a second level, odd-numbered pipeline stages perform quantization and margin amplification operations, while even-numbered pipeline stages perform sampling operations. The last pipeline stage does not perform margin amplification.

[0033] For example, assuming n is 4, the unified clock control signal is CLK, the first level is high, and the second level is low. Table 1 shows the operating status of each pipeline when CLK is high; Table 2 shows the operating status of each pipeline when CLK is low.

[0034] Table 1

[0035] Table 2

[0036] The operation of a single-stage pipeline is a circuit-level description. It explains in detail the four specific, time-sequential stages that any independent pipeline stage must go through to complete a single signal processing operation.

[0037] Taking the first-stage production line (odd-numbered stages) as an example: When the system clock is high (first level): odd-numbered stages (such as stage 1) perform sampling operations; this corresponds to the (1) reset phase and (2) sampling phase in the operation of a single-stage pipeline. During this half-cycle, the first-stage pipeline is dedicated to receiving and sampling the input signal T from the voltage-time converter (VTC). IN .

[0038] When the system clock goes low (second level): odd-numbered stages (such as stage 1) perform quantization and margin amplification operations. This corresponds to the (3) quantization stage and (4) margin amplification stage in the operation of a single-stage pipeline. In this half-cycle, the first-stage pipeline uses the results of sampling in the first half-cycle to perform internal quantization (generate digital code D1) and amplify the time margin, preparing it for output to the next stage.

[0039] Here, the digital logic circuit performs digital weighted summation in the following manner: Using the 1-bit digital code output by the voltage-time converter as the most significant bit, the digital codes output by each stage of the reconfigurable pipelined time-to-digital converter are concatenated according to their order and weight in the pipeline structure to generate an M-bit significant digital code.

[0040] It should be noted that the weights of the digital codes in each pipeline stage are different. The weight of each pipeline stage depends on its position and precision within the pipeline. Therefore, digital logic circuits need to dynamically adjust the weights based on the configuration and number of stages.

[0041] For example, to configure a time-domain analog-to-digital converter (ADC) with 12-bit precision, 10 pipeline stages are enabled. The first 9 pipeline stages are configured with 1.5-bit precision, providing quantization and margin generation capabilities. The last pipeline stage is configured with 2-bit precision, which, combined with the 1 most significant bit output generated by the voltage-time converter, produces a total 12-bit precision output.

[0042] To address the problem that existing analog-to-digital converters (ADCs) are fixed at the design stage and cannot dynamically adjust conversion accuracy according to different application scenarios during operation, this invention provides a high-speed time-domain ADC with reconfigurable accuracy. By introducing a dual reconfigurable architecture—configurable total pipeline stages and independently configurable accuracy per stage (between 1.5 bits and 2 bits)—the converter can flexibly adjust the overall conversion accuracy according to actual application requirements, thereby significantly improving system applicability and energy efficiency while maintaining high-speed conversion. This architecture fully utilizes the characteristics of highly digitized circuits, replacing traditional voltage margin amplifiers with time amplifiers, effectively reducing design complexity and power consumption. Simultaneously, it employs an alternating odd-even stage parallel operating mechanism to ensure stable operation at high throughput. This invention enables a single converter to adapt to various application scenarios with different accuracy requirements, achieving optimized configuration of performance and power consumption at the system level, and broadening the application scenarios of high-speed time-domain ADCs.

[0043] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-speed time-domain analog-to-digital converter with reconfigurable precision, characterized in that, include: Voltage-to-time converters, reconfigurable pipelined time-to-digital converters, and digital logic circuits; The voltage-to-time converter is used to convert the received input voltage signal into a time pulse signal for transmission to the first stage pipeline of the reconfigurable pipelined time-to-digital converter, and simultaneously outputs a 1-bit digital code to the digital logic circuit. The reconfigurable pipelined time-to-digital converter includes cascaded n-stage pipelines. The total effective number of the n-stage pipelines is controlled by a first configuration signal. The quantization accuracy of each pipeline stage can be independently configured between 1.5 bits and 2 bits. Under a unified clock control signal, the n-stage pipelines operate in parallel by alternating between odd and even pipeline stages for sampling and quantization-margin amplification. Each pipeline quantizes the input time pulse signal to generate the digital code of that stage, and amplifies the residual time of quantization as the output, which is then provided to the next pipeline as its input time pulse signal. The digital logic circuit is used to receive a 1-bit digital code sent by the voltage-time converter and a multi-bit digital code generated by the reconfigurable pipeline time-digit converter; and to perform digital weighting and summation on all digital codes according to their respective weights to output an M-bit valid digital code.

2. The high-speed time-domain analog-to-digital converter with reconfigurable precision according to claim 1, characterized in that, Each stage of the pipeline includes: an OR gate, a gated delay line, a digital code generator, an output switch array, a margin signal amplifier, and a quantization precision configuration group. The first input of the OR gate is connected to a circuit trigger signal Trigger, and the second input is connected to a time pulse signal T from the voltage-time converter or the previous stage pipeline. IN The output terminal is connected to the first to eighth input terminals of the gated delay line. The reset terminal of the gated delay line is connected to the reset signal SET. The first to third outputs of the gated delay line are respectively connected to the first to third inputs of the digital code generator, and the first to third clock inputs of the digital code generator are connected to a trigger signal Clk. FF The first to third output terminals of the digital code generator are all connected to the input terminals of the digital logic circuit; The fourth to sixth outputs of the gated delay line are respectively connected to the first to third inputs of the output switch array, and the output of the output switch array is connected to the input of the margin signal amplifier; the output of the margin signal amplifier is connected to the second input of the OR gate of the next stage pipeline. The digital code generator is used in the trigger signal Clk FF Under the control of [the system], the quantization state of the gated delay line is latched, and the digital code of this level is output; The quantization precision configuration group is coupled to the reset terminal and the first input terminal of the gated delay line, as well as the third clock terminal and the ground terminal of the digital code generator, respectively, and is used to configure the quantization precision of the current pipeline to 1.5 bits or 2 bits in response to the precision configuration signal. The OR gate is used to control the circuit trigger signal Trigger and the time pulse signal T. IN Perform a logical OR operation to generate the enable control signal EN for the gated delay line; The gated delay line is used to adjust the time pulse signal T during the effective period of the enable control signal EN. IN The pulse width is quantized, and its quantized state is output to the digital code generator.

3. The high-speed time-domain analog-to-digital converter with reconfigurable precision according to claim 2, characterized in that, The gated delay lines consist of eight identical, serially connected lines with the same delay time. The delay is a timer; the output of the OR gate is connected to the enable terminal of each delay.

4. The high-speed time-domain analog-to-digital converter with reconfigurable precision according to claim 3, characterized in that, The output switch array includes switch S0, switch S1 and switch S2; One end of switch S0 is located between the fourth and fifth delay units, one end of switch S1 is located between the sixth and seventh delay units, and one end of switch S2 is located at the output terminal of the eighth delay unit. The other ends of switch S0, switch S1, and switch S2 are all connected to the input terminal of the margin signal amplifier.

5. The high-speed time-domain analog-to-digital converter with reconfigurable precision according to claim 3, characterized in that, The digital code generator comprises three D flip-flops with identical structures; The D terminal of the first D flip-flop is set between the third and fourth delays, the D terminal of the second D flip-flop is set between the fifth and sixth delays, and the D terminal of the third D flip-flop is set between the seventh and eighth delays. The clock input of each D flip-flop is connected to the trigger signal Clk. FF The output terminals are each connected to one input terminal of the digital logic circuit.

6. The high-speed time-domain analog-to-digital converter with reconfigurable precision according to claim 2, characterized in that, The quantization accuracy configuration group includes a programmable switch S M1 Programmable switch S M2 Programmable switch S M3 and programmable switch S M4 The programmable switch S M1 and the programmable switch S M2 The programmable switch S operates in the opposite manner. M3 and the programmable switch S M4 Their work status is the opposite; The programmable switch S M1 The programmable switch S is located at the first input terminal of the gated delay line. M2 The programmable switch S is located at the reset terminal of the gate delay line. M3 and the programmable switch S M4 All of these are set at the clock input of the third D flip-flop; The programmable switch S M3 When the circuit is turned on, the clock input of the third D flip-flop is connected to the trigger signal Clk. FF The programmable switch S M3 When turned off, there is no signal input at the clock input of the third D flip-flop; the programmable switch S M4 When the circuit is turned on, the clock terminal of the third D flip-flop is grounded, and the programmable switch S... M4 When switched off, it is not grounded; In the programmable switch S M1 and the programmable switch S M4 The programmable switch S is turned on. M2 and the programmable switch S M3 In the off state, all eight delayers in the gated delay line operate normally, and the third D flip-flop is disabled, thereby configuring the quantization precision of the current pipeline to 1.5-bit mode; In the programmable switch S M1 and the programmable switch S M4 Off, and the programmable switch S M2 and the programmable switch S M3 When the circuit is on, the first delayer in the gated delay line loses its delay function, the remaining seven delayers work normally, all D flip-flops in the digital code generator work normally, and thus the quantization precision of the current pipeline is configured to 2-bit mode.

7. The high-speed time-domain analog-to-digital converter with reconfigurable precision according to claim 2, characterized in that, The n-stage pipeline operates in parallel with sampling and quantization-margin amplification, alternating between odd and even pipeline stages, under a unified clock control signal. This includes: In response to the unified clock control signal being at the first level, the odd-numbered pipeline stages perform sampling operations, while the even-numbered pipeline stages perform quantization and margin amplification operations. In response to the unified clock control signal being at the second level, the odd-numbered pipeline stages perform quantization and margin amplification operations, while the even-numbered pipeline stages perform sampling operations.

8. The high-speed time-domain analog-to-digital converter with reconfigurable precision according to claim 7, characterized in that, The circuit trigger signal Trigger, the reset signal SET, and the trigger signal Clk FF The timing sequence is generated and synchronized with the unified clock control signal; The effective level of the reset signal SET is used to initialize the state of the gated delay line; The effective level of the circuit trigger signal Trigger is used to initiate the margin amplification operation. The trigger signal Clk FF The effective edge is used to control the digital code generator to latch the quantization state of the gated delay line.

9. The high-speed time-domain analog-to-digital converter with reconfigurable precision according to claim 1, characterized in that, The digital logic circuit performs digital weighted summation in the following manner: The 1-bit digital code output by the voltage-time converter is taken as the most significant bit. The digital codes output by each stage of the reconfigurable pipeline time-to-digital converter are concatenated according to their order and weight in the pipeline structure to generate the M-bit significant digital code.

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