Groove type device and manufacturing method thereof

Abstract

The invention provides a trench type device and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a trench in a semiconductor layer; depositing a silicon film on the bottom and the side wall of the groove in a shape-preserving manner, wherein the thickness of the silicon film on the bottom of the groove is greater than that on the side wall; the silicon film is oxidized, the silicon film is converted into a silicon dioxide film, a gate dielectric layer covering the bottom and the side wall of the groove is formed, the thickness of the gate dielectric layer at the bottom of the groove is larger than that of the gate dielectric layer at the side wall, and the semiconductor layer is made of silicon carbide. The gate dielectric layer with the bottom thicker than the side wall is formed through conformal deposition of the silicon film and oxidation, so that the problem that the gate dielectric layer at the bottom of the groove is too thin is effectively solved, and the breakdown characteristic and reliability of the device are improved. In addition, in combination with a low-temperature process condition, surface decomposition of silicon carbide can be further inhibited, generation of carbon clusters is reduced, and thus channel resistance is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device manufacturing technology, and in particular to a trench device based on silicon carbide material and a method for manufacturing the same. Background Technology

[0002] In the development of silicon carbide (SiC) power devices, trench-type metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted widespread attention due to their ability to effectively reduce on-resistance and increase current density. However, fabricating a high-quality gate dielectric layer in trench structures still faces many challenges. In traditional thermal oxidation processes, which directly oxidize the silicon carbide surface at high temperatures to form a silicon dioxide layer, there is a difference in oxidation rate between the crystal plane at the bottom of the SiC trench and the non-major planes on the sidewalls. The oxide layer thickness at the bottom of the trench is typically less than that on the sidewalls. This thickness inhomogeneity makes the device prone to bottom breakdown under high electric fields, limiting the potential for increasing the gate bias voltage. Furthermore, the difference in binding energy between silicon and carbon atoms in SiC makes carbon residue during oxidation particularly prominent. The resulting carbon clusters significantly reduce carrier mobility in the channel region, affecting the reliability and long-term stability of the device. Summary of the Invention

[0003] To address the aforementioned issues, this disclosure proposes an optimized trench device and its manufacturing method. By conformally depositing a silicon film and oxidizing it to form a gate dielectric layer with a bottom thickness greater than that on the sidewalls, the problem of an excessively thin gate dielectric layer at the bottom of the trench is effectively improved, thereby enhancing the device's breakdown characteristics and reliability.

[0004] According to one aspect of the embodiments of this disclosure, a method for manufacturing a trench-type device is provided, comprising:

[0005] Trenches are formed in a semiconductor layer, the semiconductor layer being made of silicon carbide;

[0006] A conformal deposition of a silicon film is performed on the bottom and sidewalls of the trench, the thickness of the silicon film at the bottom of the trench being greater than its thickness on the sidewalls; and the silicon film is then oxidized to form a gate dielectric layer covering the bottom and sidewalls of the trench.

[0007] The thickness of the gate dielectric layer at the bottom of the trench is greater than its thickness on the sidewall.

[0008] Optionally, the silicon film deposition step is performed at a temperature below the silicon carbide surface reconstruction temperature.

[0009] Optionally, the material of the silicon film includes at least one of polycrystalline silicon and amorphous silicon.

[0010] Optionally, when the silicon film is made of polycrystalline silicon, the silicon film deposition step is performed at a temperature of 600-650°C.

[0011] Optionally, if the silicon film is made of amorphous silicon, the silicon film deposition step is performed at a temperature of 500-550°C.

[0012] Optionally, the step coverage of the silicon film deposited at the bottom and sidewalls of the trench is less than 1.

[0013] Optionally, the oxidation treatment is carried out under conditions insufficient to induce oxidation of the silicon carbide material.

[0014] Optionally, before oxidizing the silicon film, the method further includes anisotropic etching of the deposited silicon film to adjust the silicon film thickness ratio between the bottom and sidewalls of the trench.

[0015] According to another aspect of the present disclosure, a trench-type device is provided, which is manufactured by the manufacturing method described above.

[0016] Optionally, the trench-type device is a MOSFET or an IGBT.

[0017] One of the above technical solutions has the following beneficial effects:

[0018] After forming trenches in a silicon carbide semiconductor layer, a silicon film with uneven thickness distribution is conformally deposited at its bottom and sidewalls, making the silicon film thicker at the bottom of the trench than at the sidewalls. The entire silicon film is then completely oxidized to silicon dioxide, forming a gate dielectric layer with a thick bottom and thin sidewalls. The core of this technique lies in utilizing the thickness difference during silicon film deposition, which is naturally inherited and transformed into a non-uniform thickness distribution of the gate dielectric layer during subsequent oxidation. This avoids the problem of controlling the oxidation rate uniformity when directly oxidizing silicon carbide at high temperatures in traditional processes. Since the bottom of the trench is where the main current channel of the device is located, a thicker gate dielectric layer helps improve the breakdown voltage and long-term reliability in this region, while a thinner dielectric layer on the sidewalls helps maintain sufficient gate control capability, achieving optimized electric field distribution and a balance between device performance. Furthermore, this method uses indirect oxidation, avoiding the increased interface state density that may be caused by direct oxidation of the silicon carbide surface at high temperatures, thus improving the gate interface quality.

[0019] Silicon carbide (SiC) materials are prone to surface atomic reconstruction or decomposition at high temperatures, releasing free carbon atoms that aggregate to form carbon clusters. These carbon clusters remain at the gate dielectric-semiconductor interface, becoming carrier scattering centers or trapped states, leading to negative effects such as decreased channel mobility, unstable threshold voltage, and increased leakage current. By controlling the deposition temperature below the reconstruction temperature, the thermal decomposition behavior of the SiC surface can be effectively suppressed, maintaining its crystal integrity and significantly reducing the enrichment of carbon elements at the interface, thus improving the interface electrical performance. This condition is particularly suitable for power device applications requiring high-quality interface characteristics, providing a fundamental guarantee for achieving high-stability and high-efficiency trench MOSFETs.

[0020] The silicon film material can be selected from at least one of polycrystalline silicon and amorphous silicon, which provides flexibility and technical compatibility advantages for process implementation. Polycrystalline silicon has good thermal stability and high carrier mobility, making it suitable for applications with high structural stability requirements; while amorphous silicon, due to its lower deposition temperature and excellent step coverage, is particularly suitable for conformal filling in high aspect ratio trench structures, effectively avoiding the formation of voids or gaps. Choosing one or a combination of these two materials allows for optimized configuration based on the specific device structure and process window, ensuring uniform deposition of the silicon film in complex geometries while also maintaining the integrity and controllability of subsequent oxidation conversion.

[0021] Furthermore, in the deposition process of amorphous silicon (a-Si), the deposition temperature is 500~550°C, a temperature range that fully demonstrates the technical advantages of low-temperature deposition of amorphous silicon. Within this temperature range, amorphous silicon can achieve high-quality, high-conformity thin film growth through low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), which is particularly suitable for integrated circuit processes sensitive to thermal budgets. Low-temperature deposition not only reduces the thermal shock to the silicon carbide substrate but also further suppresses the possibility of surface carbon precipitation, contributing to a cleaner interface state. In addition, the lower the growth temperature of the silicon film, the smaller the grain size and the lower the stress. Growing low-stress a-Si at low temperatures (500~550°C) and oxidizing it to prepare the gate dielectric layer helps to effectively reduce channel resistance. At the same time, low-stress films can reduce the generation of interfacial mismatch dislocations and improve the bonding stability between the dielectric layer and the silicon carbide substrate.

[0022] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0024] Figures 1 to 5 The diagram shows a partial structural schematic of the method for fabricating trench-type devices according to an embodiment of this disclosure. Detailed Implementation

[0025] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0026] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0027] To describe a situation where it is located directly on another layer or another area, this article will use expressions such as "directly on top of" or "on and adjacent to".

[0028] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0029] In related technologies, in order to improve the problem of increased channel resistance caused by the remaining carbon clusters after the Si atoms in the semiconductor material are supplied during the preparation of the thermal oxide layer of SiC material, post-oxidation annealing (POA) is used after the oxide layer preparation is completed. However, it still cannot improve the problem of the thin gate dielectric layer at the bottom of the trench.

[0030] To simultaneously address the issues of increased channel resistance and uneven gate dielectric layer thickness, this disclosure proposes a method for preparing the gate dielectric layer by depositing a silicon film at low temperatures and then performing controlled oxidation. The specific implementation process of this method is as follows:

[0031] like Figure 1 As shown, a body region 110 is formed in the semiconductor layer 101.

[0032] The semiconductor layer 101 has opposing first surfaces 101a and second surfaces 101b, and the body region 110 extends inward from the first surface 101a. In this embodiment, the body region 110 includes a deep region and a shallow region, wherein the bottom depth of the deep region is greater than the bottom depth of the shallow region.

[0033] Furthermore, a trench 102 is formed in the semiconductor layer 101. The trench 102 penetrates the shallow region of the body region 110 and extends into the semiconductor layer 101, with its sidewalls and bottom exposing different regions of the semiconductor layer 101, respectively.

[0034] Furthermore, a silicon film 103 is conformally deposited on the bottom and sidewalls of trench 102, such as... Figure 2 As shown.

[0035] This deposition process can be achieved using chemical vapor deposition (CVD) techniques, such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0036] During the deposition process, by precisely controlling process parameters such as the flow rate of the reaction gas, the chamber pressure, and the deposition temperature, the step coverage of the silicon film 103 deposited at the bottom and sidewalls of the trench 102 is less than 1.

[0037] More specifically, the deposited silicon film 103 has a thickness d1 at the bottom of the trench 102 and a thickness d2 on the sidewalls, satisfying a thickness distribution relationship of d1 > d2. This thickness difference is due to the fact that, under the trench geometry, the incident flux of the deposited material on the bottom surface is generally higher than that on the sidewalls, especially in trenches with high aspect ratios, where this deposition rate difference is more significant, thus naturally forming a thicker silicon film structure at the bottom. In this embodiment, the material of the silicon film 103 can be polycrystalline silicon or amorphous silicon, the selection of which depends on the device performance requirements and process integration conditions. The step of depositing the silicon film 103 is performed under conditions below the silicon carbide surface reconstruction temperature.

[0038] Furthermore, the silicon film 103 is subjected to an oxidation treatment to transform it into a silicon dioxide film, thereby forming a gate dielectric layer 121 covering the bottom and sidewalls of the trench 102, such as... Figure 3 As shown.

[0039] The oxidation process is preferably carried out under conditions that are insufficient to cause significant oxidation of the underlying silicon carbide semiconductor layer 101. For example, by controlling parameters such as oxidation temperature, oxidation time, and oxidant partial pressure, the oxidation reaction is ensured to be mainly confined to the deposited silicon film 103 itself. Since the oxidation rate of silicon is much higher than that of silicon carbide, and the oxidation process has a self-limiting characteristic, this method can effectively avoid interface defects and carbon cluster residues caused by direct oxidation of the silicon carbide trench surface. After oxidation transformation, the original silicon film 103 is transformed into a gate dielectric layer 121 made of silicon dioxide, and fully inherits the thickness distribution characteristics of the deposition stage, that is, a region with a larger thickness d3 is formed at the bottom of the trench, while a region with a smaller thickness d4 is formed on the sidewall, and the relationship d3>d4 is satisfied.

[0040] In some embodiments, when the material of the silicon film 103 is polycrystalline silicon (Poly-Si), the step of depositing the silicon film 103 is performed at a temperature of 600~650°C.

[0041] This temperature range represents an optimized process window for low-pressure chemical vapor deposition (LPCVD) of polycrystalline silicon. It effectively avoids thermal damage to the silicon carbide semiconductor layer 101 caused by excessively high temperatures while ensuring sufficient deposition rate and film quality. Polycrystalline silicon films deposited at this temperature exhibit good crystallinity and step coverage, adapting to the complex morphology of trench structures. More importantly, this temperature range is significantly lower than the surface reconstruction temperature of silicon carbide, effectively suppressing carbon clusters generated on the silicon carbide surface due to thermal decomposition during deposition, laying the foundation for the subsequent formation of a high-quality gate interface.

[0042] In some embodiments, when the material of the silicon film 103 is amorphous silicon (a-Si), the step of depositing the silicon film 103 is performed at a temperature of 500~550°C.

[0043] This lower temperature range is particularly suitable for the deposition of amorphous silicon, whether achieved via LPCVD or PECVD techniques. The low-temperature deposition process further reduces the thermal budget for the silicon carbide semiconductor layer 101, minimizing the risk of thermal stress accumulation and interface reactions. Amorphous silicon films grown under these conditions exhibit lower internal stress and a more uniform amorphous structure, characteristics that result in better interface quality and lower interface state density for the subsequent oxidation-formed silicon dioxide gate dielectric layer. Experiments show that the gate dielectric layer prepared using this low-temperature process significantly reduces channel resistance and improves device conduction performance.

[0044] Furthermore, the lower the growth temperature of the silicon film 103, the smaller its microstructure characteristics, such as grain size, and the lower the internal stress of the film. Depositing amorphous silicon (a-Si) at a low temperature of 500–550 °C yields amorphous films with low internal stress. The gate dielectric layer 121 of silicon dioxide formed after oxidation of this film exhibits excellent interface properties. This low-stress characteristic helps alleviate the built-in stress caused by the difference in lattice constant and thermal expansion coefficient between silicon dioxide and silicon carbide, thereby significantly reducing the generation of mismatch dislocations at the interface. Lower interface defect density means fewer carrier scattering centers, which is crucial for improving carrier mobility in the channel, thus directly contributing to the effective reduction of channel resistance.

[0045] Meanwhile, the lower process temperature also helps control the thermal budget of the entire manufacturing process, avoiding surface degradation of silicon carbide materials that may be caused by high-temperature processes. This process route, combining low-temperature deposition and oxidation, not only achieves precise control of the gate dielectric layer thickness but also simultaneously optimizes the interface electrical properties and mechanical stability, providing comprehensive technical support for the fabrication of high-performance, high-reliability silicon carbide trench power devices. Compared to traditional high-temperature thermal oxidation processes, this method demonstrates significant advantages in interface quality control and device performance improvement.

[0046] Furthermore, the manufacturing method described in this disclosure has the advantage of simplified processes compared to traditional methods, eliminating the post-oxidation annealing step traditionally used to improve interface properties. In traditional direct thermal oxidation of silicon carbide processes, post-oxidation annealing is a necessary step to repair interface defects and passivate interface states, but it is ineffective in improving the uneven distribution of the gate dielectric layer thickness. This method, however, reduces the generation of interface carbon clusters and interface stress at the source by depositing a silicon film and oxidizing it to form the gate dielectric layer at a low temperature, thereby obtaining a gate interface with inherently superior quality. This not only avoids the additional high-temperature annealing process, simplifying the process steps and reducing manufacturing costs, but also reduces other negative effects that may be caused by high-temperature annealing, such as impurity redistribution or device structural stability issues.

[0047] In some embodiments, an anisotropic etching process may be performed before oxidizing the silicon film 103.

[0048] This etching step is used to fine-tune the thickness ratio of the deposited silicon film 103, specifically selectively removing a portion of the silicon film 103 on the sidewalls of the trench 102 while relatively preserving the thickness of the silicon film 103 in the bottom region of the trench 102. By controlling the process time and etching conditions of the anisotropic etching, the ratio between the silicon film thickness d1 at the bottom of the trench 102 and the silicon film thickness d2 on the sidewalls can be further increased, thus laying the foundation for subsequent oxidation to form a gate dielectric layer 121 with a better thickness distribution. This step provides additional process freedom, allowing the thickness difference of the final gate dielectric layer 121 at the bottom and sidewalls of the trench 102 to more precisely meet the electric field management requirements of the device design.

[0049] Furthermore, after the gate dielectric layer 121 is formed, gate electrode material 122 can be deposited on top of it to complete the fabrication of the trench gate structure, such as... Figure 4 As shown.

[0050] Because the gate dielectric layer 121 has a relatively large thickness at the bottom of the trench, it significantly enhances the electric field withstand capability of this region, effectively suppressing the risk of breakdown under high gate voltage, thereby improving the device's blocking voltage and long-term reliability. Simultaneously, the relatively thin sidewalls of the gate dielectric layer help maintain sufficient gate control capability, ensuring good conduction characteristics in the channel region. This gate dielectric layer structure design, with a thick bottom and thin sidewalls, achieves an optimized balance between breakdown characteristics and conduction performance in trench-type silicon carbide power devices. Subsequent conventional process steps, such as source and drain, interlayer dielectric layers, and metal interconnects, can be performed to finally complete the trench-type device.

[0051] like Figure 5 As shown, this embodiment also discloses a trench-type device, which is manufactured using the aforementioned method.

[0052] The trench device includes: a semiconductor layer 101, a body region 110, a trench gate, a source region 130, a body contact region 140, an interlayer dielectric layer 150, a first conductive layer 160, and a second conductive layer 170. The semiconductor layer 101 has opposing first surfaces 101a and second surfaces 101b, and a trench extends from the first surface 101a toward the second surface 101b into the semiconductor layer 101. The trench gate is located within the trench and includes a gate dielectric layer 121 covering the inner surface of the trench and a gate electrode material 122 filling the trench. In this embodiment, the thickness of the gate dielectric layer 121 at the bottom of the trench is greater than the thickness at the sidewalls of the trench.

[0053] Body region 110 is located in the semiconductor layers 101 on both sides of the trench gate. Along the width direction of the trench gate, body region 110 is divided into connected deep-doped and shallow-doped regions. The shallow-doped region is adjacent to the trench gate, connected to the sidewalls of the trench gate, and not in contact with the bottom. The junction depth of the deep-doped region can exceed the bottom of the trench gate, thereby effectively enhancing the uniformity of the electric field distribution of the device. Source region 130 and body contact region 140 are located within body region 110, wherein source region 130 is adjacent to the trench sidewalls.

[0054] In this embodiment, the semiconductor layer 101 is, for example, a SiC substrate or a stacked structure consisting of a substrate and an epitaxial layer. The body region 110 and the body contact region 140 are of a first conductivity type. The portion of the semiconductor layer 101 where the body region 110 is not formed can serve as a drift region. The drift region and the source region 130 are of a second conductivity type. The doping concentration of the body contact region 140 is greater than that of the body region 110. The first conductivity type and the second conductivity type are opposite. The first conductivity type is either P-type or N-type, and the second conductivity type is either P-type or N-type.

[0055] An interlayer dielectric layer 150 is located on the first surface 101a and covers the trench gate. A first conductive layer 160 is located on the interlayer dielectric layer 150 and is electrically connected to the source region 130 and the body contact region 140. A second conductive layer 170 is located on the second surface 101b and is electrically connected to the bottom of the semiconductor layer 101. The first conductive layer 160 serves as the source, and the second conductive layer 170 serves as the drain.

[0056] The trench-type device of this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). For example, a drain contact region can be formed on the second surface 101b of the semiconductor layer, and the conductivity type of the drain contact region can be set to either a first conductivity type or a second conductivity type. However, the embodiments disclosed herein are not limited to this. Those skilled in the art can make other settings for the conductivity type of each region in the semiconductor layer as needed to use the trench-type device as a MOSFET or an IGBT.

[0057] The present disclosure has been described in detail above with reference to specific embodiments, but the present disclosure is not limited to the details of the above embodiments. Without departing from the spirit and scope of the present disclosure, those skilled in the art can make various equivalent modifications, substitutions or variations to the technical solutions of the present disclosure, and such modifications, substitutions or variations should all be covered within the protection scope defined by the claims of the present disclosure.

Claims

1. A method for manufacturing a trench-type device, comprising: Trenches are formed in a semiconductor layer, the semiconductor layer being made of silicon carbide; A conformal deposition of a silicon film is performed on the bottom and sidewalls of the trench, wherein the thickness of the silicon film at the bottom of the trench is greater than that at the sidewalls; and the silicon film is oxidized to form a gate dielectric layer covering the bottom and sidewalls of the trench. The thickness of the gate dielectric layer at the bottom of the trench is greater than its thickness on the sidewall.

2. The manufacturing method according to claim 1, wherein, The silicon film deposition step is performed at a temperature below the silicon carbide surface reconstruction temperature.

3. The manufacturing method according to claim 1, wherein, The silicon film is made of at least one of polycrystalline silicon and amorphous silicon.

4. The manufacturing method according to claim 3, wherein, When the silicon film is made of polycrystalline silicon, the silicon film deposition step is performed at a temperature of 600~650°C.

5. The manufacturing method according to claim 3, wherein, When the silicon film is made of amorphous silicon, the silicon film deposition step is performed at a temperature of 500~550°C.

6. The manufacturing method according to claim 1, wherein, The step coverage of the silicon film deposited at the bottom and sidewalls of the trench is less than 1.

7. The manufacturing method according to claim 1, wherein, The oxidation treatment is carried out under conditions insufficient to induce oxidation of the silicon carbide material.

8. The manufacturing method according to any one of claims 1 to 7, further comprising, before oxidizing the silicon film: The deposited silicon film is subjected to anisotropic etching to adjust the ratio of silicon film thickness at the bottom to the sidewalls of the trench.

9. A trench-type device, wherein, The trench-type device is manufactured by the manufacturing method according to any one of claims 1 to 8.

10. The trench-type device according to claim 9, wherein, The trench-type device is a MOSFET or an IGBT.

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