Silicon carbide power device and preparation method thereof, silicon carbide MOSFET and silicon carbide IGBT

Abstract

The invention provides a silicon carbide power device and a preparation method thereof, a silicon carbide MOSFET and a silicon carbide IGBT, relates to the technical field of semiconductors, and aims to comprehensively improve dynamic and static characteristics and reliability of the silicon carbide power device. The silicon carbide power device comprises a silicon carbide substrate, an epitaxial drift layer, a plurality of polygonal cells and a plurality of expansion cells. Each polygonal cell comprises a polygonal well region and a straight-edge JFET region, and each straight-edge JFET region is located between adjacent parallel edges of every two adjacent polygonal well regions. The extension cell comprises a well region extension region and a JFET channel, the well region extension region and the polygonal well region are synchronously formed under the same process, each vertex angle of the polygonal well region extends outwards to form the well region extension region, and the shape of the well region extension region is a polygon or a polygon-like shape. The JFET channel is located between the at least two adjacent well region extension regions and is communicated with the at least two adjacent straight JFET regions. The width of the JFET channel is smaller than or equal to the width of the straight edge JFET region and is larger than or equal to two times of the width of an on-state depletion region in the JFET channel.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a silicon carbide power device and its fabrication method, a silicon carbide MOSFET and a silicon carbide IGBT. Background Technology

[0002] Currently, silicon carbide power devices have broad prospects in high-voltage, high-frequency, and high-temperature applications due to their advantages such as high breakdown voltage and low on-resistance. Key parameters of silicon carbide MOSFETs include withstand voltage, specific on-resistance, and reverse transfer capacitance. Trade-offs must be made during design, and performance is commonly evaluated using Baliga quality factor (B-FOM) and high-frequency quality factor (HF-FOM). In addition, reliability is also important, and its evaluation indicators include the maximum electric field of the gate dielectric and the ratio of input capacitance to reverse transfer capacitance.

[0003] However, how to improve the dynamic and static characteristics of the device while maintaining the high reliability of silicon carbide power devices remains a problem to be solved. Summary of the Invention

[0004] This application proposes a silicon carbide power device and its fabrication method, as well as a silicon carbide MOSFET and a silicon carbide IGBT, aiming to comprehensively improve the dynamic and static characteristics and reliability of silicon carbide power devices.

[0005] To achieve the above objectives, embodiments of this application provide the following technical solutions: On one hand, a silicon carbide power device is provided, comprising a silicon carbide substrate, an epitaxial drift layer, a plurality of polygonal cells, and a plurality of extended cells. The epitaxial drift layer is disposed on the silicon carbide substrate. The plurality of polygonal cells are disposed on the surface of the epitaxial drift layer away from the silicon carbide substrate. Each polygonal cell includes a polygonal well region and a straight-edge JFET region, with adjacent edges of two adjacent polygonal well regions being parallel, and the straight-edge JFET region located between the parallel edges of two adjacent polygonal well regions. The plurality of extended cells are disposed on the surface of the epitaxial drift layer away from the silicon carbide substrate. Each extended cell includes a well region extension region and a JFET channel. The well region extension region is formed synchronously with the polygonal well region using the same process, and each vertex of the polygonal well region extends outward to form a well region extension region, the shape of which is polygonal or quasi-polygonal. The JFET channel is located between at least two adjacent well region extension regions and is interconnected with at least two adjacent straight-edge JFET regions. The width of the JFET channel is less than or equal to the width of the straight-edge JFET region, and greater than or equal to twice the width of the on-state depletion region within the JFET channel.

[0006] In the embodiments described above, the silicon carbide power device includes a silicon carbide substrate, an epitaxial drift layer, a plurality of polygonal cells, and a plurality of extended cells. The epitaxial drift layer is disposed on the silicon carbide substrate. The plurality of polygonal cells are disposed on the surface of the epitaxial drift layer away from the silicon carbide substrate. The polygonal cells include polygonal well regions and straight-edge JFET regions, with adjacent edges of two adjacent polygonal well regions being parallel, and the straight-edge JFET regions being located between the parallel edges of two adjacent polygonal well regions.

[0007] Furthermore, multiple extended cells are disposed on the surface of the epitaxial drift layer away from the silicon carbide substrate. The extended cells include well extension regions and JFET channels. The well extension regions are formed synchronously with the polygonal well regions using the same process. Each vertex of the polygonal well region extends outward to form a well extension region, and the shape of the well extension regions is polygonal or quasi-polygonal. It is understood that the edges of the well extension regions are straight edges. This arrangement can improve the dynamic and static characteristics of silicon carbide power devices.

[0008] The JFET channel is located between at least two adjacent well extension regions and is interconnected with at least two adjacent straight-edge JFET regions. The width of the JFET channel is less than or equal to the width of the straight-edge JFET region and greater than or equal to twice the width of the on-state depletion region within the JFET channel. It is understood that the above configuration increases the channel density of the silicon carbide power device in the on-state and reduces the specific on-resistance of the silicon carbide power device, thereby improving the conduction and blocking characteristics of the silicon carbide power device.

[0009] Understandably, each vertex of the polygonal well region in the polygonal cell expands outward. While ensuring the conduction performance of the silicon carbide power device, this reduces the area of ​​the straight-edge JFET region located between the parallel edges of two adjacent polygonal well regions, thus decreasing the reverse transfer capacitance of the silicon carbide power device. Because both the specific on-resistance and reverse transfer capacitance are reduced, the power consumption of the silicon carbide power device under high-frequency operating conditions is also lowered.

[0010] Furthermore, the arrangement of the well extension region reduces the distance between the vertices of multiple polygonal well regions, thereby decreasing the electric field and improving reliability at that location. In summary, the overall performance of the silicon carbide power device of this application is improved, achieving synergistic optimization among the static characteristics, dynamic characteristics, and reliability of the silicon carbide power device, thus comprehensively enhancing its dynamic and static characteristics and reliability.

[0011] In some embodiments, the orthographic projection of the well extension region onto the silicon carbide substrate is polygonal or polygonal in shape, and the well extension region includes multiple sides with an included angle or a rounded transition between adjacent sides. In the two sides where the apex of the polygonal well region is located, the well extension region partially overlaps with at least one side.

[0012] In some embodiments, the plurality of polygonal cells include multiple rows and multiple columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first and second directions are parallel to the silicon carbide substrate and intersect each other. Along the first direction, well extension regions connected to adjacent polygonal well regions are interconnected. Along the second direction, JFET channels are formed between well extension regions connected to adjacent polygonal well regions. The polygonal well regions are rectangular in shape, and the JFET channels are located between adjacent well extension regions, with the JFET channels having a straight-line shape.

[0013] In some embodiments, the plurality of polygonal cells include multiple rows and multiple columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first and second directions are parallel to the silicon carbide substrate and intersect each other. Along the first direction, a portion of the JFET channel is formed by the well extension regions connected to adjacent polygonal well regions. Along the second direction, another portion of the JFET channel is formed by the well extension regions connected to adjacent polygonal well regions. The polygonal well regions are rectangular in shape, and the JFET channel is located between four adjacent well extension regions, forming a cross shape.

[0014] In some embodiments, the plurality of polygonal cells include multiple rows and multiple columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first and second directions are parallel to the silicon carbide substrate and intersect each other. There are at least two adjacent rows of polygonal well regions. In one row of polygonal well regions, well extension regions connected to adjacent polygonal well regions are interconnected along the first direction. In another row of polygonal well regions, well extension regions connected to adjacent polygonal well regions are spaced apart along the first direction to form a portion of a JFET channel. Well extension regions connected to adjacent polygonal well regions are spaced apart along the second direction to form another portion of a JFET channel. The polygonal well regions are rectangular in shape, and the JFET channel is located between four adjacent well extension regions, and the JFET channel is T-shaped.

[0015] In some embodiments, the plurality of polygonal cells include multiple rows and multiple columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first and second directions are parallel to the silicon carbide substrate and intersect each other. The plurality of polygonal cells include at least one cell group, which includes two rows and two columns of polygonal cells. The cell group includes diagonally opposite first and second polygonal well regions, as well as diagonally opposite third and fourth polygonal well regions. Well region extension regions connected to the first polygonal well regions and connected to the second polygonal well regions are connected to form isolation regions, which isolate at least two straight-edge JFET regions.

[0016] In some embodiments, multiple polygonal cells are periodically arranged along a third, fourth, and fifth direction parallel to the silicon carbide substrate. The third, fourth, and fifth directions are not parallel and intersect each other. The polygonal well regions are hexagonal in shape, with the vertices of three adjacent polygonal well regions close to each other. A portion of the JFET channel is formed between any two adjacent well region extension regions, and the JFET channel is Y-shaped.

[0017] On the other hand, a method for fabricating a silicon carbide power device is also provided. This method is used to fabricate the silicon carbide power device as described in the above embodiments, and the fabrication method includes: A masking layer is deposited on the surface of the epitaxial drift layer, and the masking layer has a through ion implantation window; Ion implantation is performed on the epitaxial drift layer through the ion implantation window at a temperature range of 450℃ to 550℃ to form polygonal well regions and well region extension regions.

[0018] On the other hand, a silicon carbide MOSFET is also provided, which includes a silicon carbide power device as described in the above embodiments, a Schottky electrode, a gate, a source, and a drain. A Schottky contact region is provided within the polygonal well region of at least a portion of the polygonal cells, or a Schottky contact region is provided within the straight-edge JFET region. The Schottky electrode covers the Schottky contact region and is electrically connected to the source.

[0019] In some embodiments, the straight-edge JFET region is provided with a Schottky contact region. Multiple polygonal cells comprise multiple rows and columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first and second directions are parallel to the silicon carbide substrate and intersect each other. Along the first direction, adjacent straight-edge JFET regions are connected through a JFET channel, and Schottky electrodes and gates are alternately arranged above the straight-edge JFET regions.

[0020] On the other hand, a silicon carbide IGBT is also provided, which includes a silicon carbide power device, a gate, an emitter, and a collector as described in the above embodiments.

[0021] The silicon carbide MOSFETs and their fabrication methods described above, as well as the silicon carbide IGBTs, have the same structure and beneficial technical effects as the silicon carbide power devices provided in some of the above embodiments, and will not be repeated here. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0023] Figure 1 A top view of a silicon carbide power device provided in an embodiment of this application; Figure 2 for Figure 1 A partial cross-sectional view along section line AA' of a portion of the film layer in a silicon carbide power device; Figure 3 A top view of another silicon carbide power device provided in an embodiment of this application; Figure 4 A top view of another silicon carbide power device provided in an embodiment of this application; Figure 5 A top view of another silicon carbide power device provided in an embodiment of this application; Figure 6 A top view of another silicon carbide power device provided in an embodiment of this application; Figure 7 A flowchart illustrating the fabrication method of silicon carbide power devices provided in this application embodiment; Figure 8 A top view of a silicon carbide MOSFET provided in an embodiment of this application; Figure 9 A top view of another silicon carbide MOSFET provided in an embodiment of this application; Figure 10 A top view of another silicon carbide MOSFET provided in an embodiment of this application; Figure 11 for Figure 10 A top view of a portion of the film layer of a silicon carbide MOSFET. Figure 12 for Figure 10 and Figure 11 A partial cross-sectional view of the silicon carbide MOSFET along section line BB'; Figure 13 for Figure 10 and Figure 11 A partial cross-sectional view of the silicon carbide MOSFET along section line CC'; Figure 14 This is a schematic diagram of the structure of a silicon carbide IGBT provided in an embodiment of this application.

[0024] Figure label: 1. Silicon carbide power device; 2. Silicon carbide substrate; 21. JFET channel; 22. Well region extension region; 23. Straight-edge JFET region; 3. Epitaxial drift layer; 31. Width of straight-edge JFET region; 33. Width of JFET channel; 34. Overlap length of well region extension region and polygonal well region; 35. Channel length; 4. JFET region; 41. Polygonal cell; 42. Extended cell; 43. Schottky contact region; 5. First region; 6. Polygonal well region; 61. First polygonal well region; 62. Second polygonal well region; 7. Second region; 8. Gate; 9. Gate oxide layer; 11. Source; 12. Schottky electrode; 13. Drain; 14. Emitter; 15. Collector. Detailed Implementation

[0025] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0026] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0027] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0028] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0029] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0030] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0031] Compared with traditional silicon-based power devices, silicon carbide (SiC) power devices have advantages such as high breakdown voltage, low on-resistance, fast switching speed, and good high temperature resistance, and have broad application prospects in high-voltage, high-frequency, and high-temperature fields such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible DC transmission.

[0032] Key parameters for the dynamic and static electrical performance of silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) include breakdown voltage (BV), specific on-resistance (Ron, sp), and reverse transfer capacitance (Crss). For applications with specific bus voltages, devices with higher BV offer greater safety margins, making the system more reliable. Reducing specific on-resistance significantly reduces power loss in the on-state, improving overall energy efficiency and reducing heat generation; it also allows for smaller chip area while maintaining the same operating current, thus reducing cost. Crss dominates the switching characteristics of the device; reducing Crss can accelerate switching speed, reduce switching losses, thereby reducing the dynamic power consumption of the system and enabling the device to operate at higher frequencies.

[0033] However, the design of the above parameters often involves contradictions, requiring trade-offs. Typically, the Baliga quality factor (B-FOM) and the high-frequency quality factor (HF-FOM) are chosen as indicators for comprehensively evaluating the static and dynamic performance of a device. Here, B-FOM = BV 2 / Ron,sp,HF-FOM=Ron×Crss,A higher B-FOM means better overall conduction and blocking characteristics of the device, while a lower HF-FOM means lower power consumption during high-frequency operation.

[0034] Furthermore, reliability is also a crucial performance characteristic of devices, and its evaluation metrics include the maximum electric field of the gate dielectric (e.g., silicon oxide) and the ratio of input capacitance (Ciss) to reverse transfer capacitance. For example, silicon carbide exhibits a high electric field in its resistive state, and since the dielectric constant of silicon carbide is approximately three times that of silicon oxide, this means that at the silicon carbide-silicon oxide interface, the electric field in silicon oxide is about three times that in silicon carbide. This can lead to an excessively large electric field in silicon oxide, causing premature device breakdown. SiC MOSFETs typically operate at high frequencies, and voltage changes at the drain are conducted to the gate via Crss, potentially causing false turn-on. A higher Ciss / Crss ratio helps prevent false turn-on.

[0035] Furthermore, the core of power device design is usually to optimize the quality factor as much as possible without significantly increasing the difficulty of the process and the manufacturing cost, while maintaining high reliability.

[0036] Currently, planar SiC MOSFETs are typically configured with a strip cell structure. While this structure offers good manufacturability and high reliability, it suffers from low channel density and high Ron and sp. Polygonal cells offer even higher channel density, effectively reducing Ron and sp and possessing the potential to improve B-FOM; however, they present challenges in high-frequency performance and reliability.

[0037] In related technologies, SiC MOSFETs can also be configured as rectangular cells. Under the same process conditions, rectangular cells have a higher channel density and lower Ron and sp than strip cells. However, their JFET region area is larger, resulting in a significant increase in Crss. HF-FOM and Ciss / Crss are often inferior to those of strip cells.

[0038] On the other hand, the diagonal width of the JFET region at the intersection of the vertices of the well regions of two adjacent rectangular cells is 1.41 times that of the conventional JFET region, resulting in a significant increase in the gate oxide electric field and a substantial decrease in reliability. Although CRSs and reliability can be improved by reducing the JFET width or density, this increases Ron, sp, reduces B-FOM, and the width of the JFET region is limited by factors such as device process technology.

[0039] Furthermore, SiC MOSFETs are commonly used in inductive load circuits, typically requiring an anti-parallel freewheeling diode in conjunction. However, due to the high on-state voltage drop and reverse recovery loss of the parasitic body diode in SiC MOSFETs, as well as the risk of bipolar degradation, they are unsuitable for use as freewheeling diodes, often necessitating an additional anti-parallel freewheeling diode in practical circuits. If a Schottky barrier diode (SBD) is monolithically integrated with the MOSFET, the device not only exhibits a lower on-state voltage drop and reverse recovery loss during reverse conduction but also effectively suppresses body diode conduction and avoids the risk of bipolar degradation, thus eliminating the need for an additional anti-parallel freewheeling diode in the circuit.

[0040] Meanwhile, compared to parallel discrete devices, MOSFETs and integrated SBDs can share drift regions and terminations, reducing overall chip area, saving module packaging costs, lowering parasitic parameters, and improving system efficiency. Existing MOSFETs with integrated SBDs typically integrate the SBD within the well region. To make room for the Schottky contacts, MOSFETs with integrated SBDs require wider cell periods than pure MOSFETs, further reducing channel density, resulting in higher Ron and sp, and a decrease in B-FOM. Moreover, the JFET region below the gate is separated from the SBD contact region; when the MOSFET or SBD is turned on, a portion of each region cannot provide a current path, leading to wasted area.

[0041] Related technologies often only consider how to improve reliability, on-resistance, or dynamic characteristics when designing polygon cells, without giving comprehensive consideration to them in order to significantly improve their overall performance.

[0042] Therefore, embodiments of this application provide a silicon carbide power device. Figure 1 A top view of a silicon carbide power device provided in an embodiment of this application; Figure 2 for Figure 1 A partial cross-sectional view along section line AA' of a portion of the film layer in a silicon carbide power device.

[0043] See Figure 1 and Figure 2 The silicon carbide power device 1 includes a silicon carbide substrate 2, an epitaxial drift layer 3, multiple polygonal cells 41, and multiple extended cells 42.

[0044] An epitaxial drift layer 3 is disposed on a silicon carbide substrate 2. Exemplarily, the conductivity type of the epitaxial drift layer 3 and the silicon carbide substrate 2 can be the same or different. Exemplarily, the conductivity type of both the silicon carbide substrate 2 and the epitaxial drift layer 3 can be N-type, or both can be P-type, or one can be N-type and the other P-type. The embodiments of this application illustrate this by assuming that the epitaxial drift layer 3 and the silicon carbide substrate 2 have the same conductivity type, and both are N-type.

[0045] For example, the doping concentration of conductive ions in the silicon carbide substrate 2 is greater than the doping concentration of conductive ions in the epitaxial drift layer 3. For instance, the doping concentration of conductive ions in the silicon carbide substrate 2 can be in the range of 10-1. 18 cm -3 ~10 20 cm -3 The doping concentration of the epitaxial drift layer 3 can be in the range of 10. 14 cm -3 ~10 16 cm -3 .

[0046] See Figure 1 Multiple polygonal cells 41 are disposed on the surface of the epitaxial drift layer 3 on the side away from the silicon carbide substrate 2. Exemplarily, this application does not limit the number of polygonal cells 41. An embodiment of this application illustrates the example of a silicon carbide power device 1 including four polygonal cells 41.

[0047] The polygonal cell 41 includes a polygonal well region 6 and a straight-edge JFET region 23. The adjacent edges of two adjacent polygonal well regions 6 are parallel, and the straight-edge JFET region 23 is located between the parallel edges of two adjacent polygonal well regions 6. It can be understood that the area between the adjacent edges of two adjacent polygonal well regions 6 is the JFET region. Since the two edges are parallel, the JFET region can be called the "straight-edge JFET region".

[0048] See also Figure 1 Multiple extended cells 42 are disposed on the surface of the epitaxial drift layer 3 on the side away from the silicon carbide substrate 2. Each extended cell 42 includes a well extension region 22 and a JFET channel 21. The well extension region 22 is formed synchronously with the polygonal well region 6 using the same process. Each vertex of the polygonal well region 6 extends outward to form the well extension region 22. The shape of the well extension region 22 is polygonal or polygon-like. For example, the shape of the well extension region 22 can be quadrilateral, hexagonal, or octagonal, etc.

[0049] For example, in the fabrication of silicon carbide power device 1, a high-temperature ion implantation process is typically used to implant ion-doped regions, including a well extension region 22. When ion implantation is performed on the epitaxial drift layer 3, the shape of the apex of the well extension region 22 may become irregular. This is mainly due to the combined effects of multiple factors, including channel effect, material surface condition, implantation angle and dose control, material thermodynamic response, and post-implantation processing.

[0050] Therefore, it is understandable that, due to the aforementioned factors, the shape of the well extension region 22 may be a polygon or a polygon-like shape. A polygon-like shape refers to a type of graphic that is close to a polygon in shape but does not completely conform to the geometric characteristics of a traditional polygon. For example, in the embodiments provided in this application, the outward expansion of the apex of the well extension region 22 may be a straight line or a curve, and its shape may be a polygon or close to a polygon.

[0051] Understandably, see Figure 1 Each vertex of the polygonal well region 6 expands outward, thus reducing the distance between adjacent vertexes of adjacent polygonal well regions 6 and between relative vertexes of opposite polygonal well regions 6. This further reduces the distance at the intersection of the vertexes of multiple polygonal well regions 6, thereby further reducing the electric field at this location and improving the reliability of the silicon carbide power device 1.

[0052] See also Figure 1 The JFET channel 21 is located between at least two adjacent well region extension regions 22 and is interconnected with at least two adjacent straight-edge JFET regions 23. The width 33 of the JFET channel 21 is less than or equal to the width 31 of the straight-edge JFET region 23, and greater than or equal to twice the width of the on-state depletion region within the JFET channel 21.

[0053] Understandably, the width of the depletion region of the silicon carbide power device 1 will vary with voltage under different applied voltage conditions. When the silicon carbide power device 1 is turned on, i.e., when the silicon carbide power device 1 is in the on-state, the JFET channel 21 can also serve as a current flow path, thereby reducing the specific on-resistance, improving the on and off characteristics of the silicon carbide power device 1, and reducing power consumption, thus improving the overall dynamic and static characteristics and reliability of the silicon carbide power device 1.

[0054] For example, see Figure 1In this embodiment, the width 33 of the JFET channel 21 is illustrated as being smaller than the width 31 of the straight-edge JFET region 23. It is understood that no part of the JFET channel 21 in the well region extension region 22 is wider than the straight-edge JFET region 23. By making the width 31 of the straight-edge JFET region 23 wider, the electric field at the apex intersection of the polygonal well region 6 is reduced, improving the breakdown voltage performance of the silicon carbide power device 1 and enhancing its reliability.

[0055] For example, see Figure 1 The four polygonal cells 41 extend outward from their adjacent vertices to form four well extension regions 22. There is at least one JFET channel 21 between the four well extension regions 22. The four well extension regions 22 and the JFET channel 21 together form an extension cell 42.

[0056] For example, the JFET channel 21 and the straight-edge JFET region 23 have the same doping type and distribution, and the polygonal well region 6 and the well region extension region 22 have the same doping type and distribution. For instance, the JFET channel 21 and the straight-edge JFET region 23 can be doped with the same concentration of N-type conductive ions, and the polygonal well region 6 and the well region extension region 22 can be doped with the same concentration of P-type conductive ions.

[0057] For example, see [link to previous article] Figure 1 and Figure 2 The silicon carbide power device 1 also includes a first region 5 and a second region 7. The polygonal well region 6, the well region extension region 22, and the second region 7 have the same conductivity type, and are all of the second conductivity type. The silicon carbide substrate 2, the epitaxial drift layer 3, the straight-edge JFET region 23, the JFET channel 21, and the first region 5 have the same conductivity type, and are all of the first conductivity type.

[0058] For example, P-type ions are implanted in the polygonal well region 6, the well extension region 22, and the second region 6. Both of these regions have P-type conductivity. The polygonal well region 6 can also be called a "P-well," and the second region 7 can also be called a "P+ contact region." The silicon carbide substrate 2, the epitaxial drift layer 3, the straight-edge JFET region 23, the JFET channel 21, and the first region 5 all have N-type conductivity. N-type ions are implanted in the first region 5, and the first region 5 can also be called an "N+ contact region."

[0059] In the above embodiments of this application, the silicon carbide power device 1 includes a silicon carbide substrate 2, an epitaxial drift layer 3, a plurality of polygonal cells 41, and a plurality of extended cells 42. The epitaxial drift layer 3 is disposed on the silicon carbide substrate 2. The plurality of polygonal cells 41 are disposed on the surface of the epitaxial drift layer 3 away from the silicon carbide substrate 2. The polygonal cell 41 includes a polygonal well region 6 and a straight-edge JFET region 23, wherein the adjacent edges of two adjacent polygonal well regions 6 are parallel, and the straight-edge JFET region 23 is located between the parallel edges of two adjacent polygonal well regions 6.

[0060] Furthermore, multiple extended cells 42 are disposed on the surface of the epitaxial drift layer 3 on the side away from the silicon carbide substrate 2. The extended cells 42 include well extension regions 22 and JFET channels 21. The well extension regions 6 and the polygonal well regions 22 are formed synchronously under the same process. Each vertex of the polygonal well region 6 extends outward to form the well extension region 22, and the shape of the well extension regions 22 is polygonal or quasi-polygonal. It is understood that the edges of the well extension regions 22 are straight edges. This arrangement can improve the dynamic and static characteristics and reliability of the overall silicon carbide power device 1.

[0061] The JFET channel 21 is located between at least two adjacent well extension regions 22 and is interconnected with at least two adjacent straight-edge JFET regions 23. The width 33 of the JFET channel 21 is less than or equal to the width 31 of the straight-edge JFET region 23, and greater than or equal to twice the width of the on-state depletion region within the JFET channel 21. It can be understood that the above configuration increases the conductive path or conductive area of ​​the silicon carbide power device 1 in the on-state, thereby improving the conduction characteristics of the silicon carbide power device 1.

[0062] Understandably, each vertex of the polygonal well region 6 of the polygonal cell 41 expands outward, which reduces the area of ​​the straight-edge JFET region 23 between the parallel sides of two adjacent polygonal well regions 6 while ensuring the conduction performance of the silicon carbide power device 1, thereby reducing the reverse transfer capacitance of the silicon carbide power device 1.

[0063] For example, compared to traditional strip cells, the structure in the embodiments of this application increases channel density and reduces channel resistance. Compared to traditional rectangular cells that fully cover the apex intersection, the structure in the embodiments of this application reduces JFET resistance. Compared to traditional rectangular cells, the structure in the embodiments of this application has only a slightly increased specific on-resistance, reduced reverse transfer capacitance, and significantly improved reliability.

[0064] Furthermore, the arrangement of the well region extension region 22 reduces the distance between the vertices of the multiple polygonal well regions 6, thereby reducing the electric field and improving the reliability at that location. In summary, the overall performance of the silicon carbide power device 1 of this application is improved, achieving synergistic optimization among the static characteristics, dynamic characteristics, and reliability of the silicon carbide power device 1, thus comprehensively improving the dynamic and static characteristics and reliability of the silicon carbide power device 1.

[0065] In some embodiments, see Figure 1 The orthographic projection of the well extension region 22 onto the silicon carbide substrate 2 is polygonal or polygon-like, and the well extension region 22 includes multiple sides, with an included angle or arc transition between adjacent sides. For example, the orthographic projection of the well extension region 22 onto the silicon carbide substrate 2 can be any polygon such as a rectangle, parallelogram, trapezoid, hexagon, or octagon. The sides of the aforementioned polygon can be at least one of straight lines or arcs.

[0066] Under ideal conditions, the orthographic projection of the well extension region 22 formed by high-temperature ion implantation onto the silicon carbide substrate 2 is polygonal, with adjacent sides being straight lines and having an included angle. In real-world processes, the shape of the apex of the well extension region 22 may be irregular. In this case, the well extension region 22 is a polygonal-like region with a rounded transition between adjacent sides.

[0067] Regardless of whether the shape of the orthographic projection of the well extension region 22 on the silicon carbide substrate 2 is polygonal or polygonal-like, each vertex of the well extension region 22 extends outward, thereby reducing the distance between adjacent vertexes of adjacent polygonal well regions 6 and between relative vertexes of relative polygonal well regions 6, further reducing the distance at the intersection of the vertexes of multiple polygonal well regions 6, thereby further reducing the electric field at this location and improving the reliability of this location, thus improving the reliability of the silicon carbide power device 1.

[0068] In the two sides where the apex of the polygonal well region 6 is located, the well region extension region 22 partially overlaps with at least one side. It is understood that the well region extension region 22 can extend from at least one of the two sides where the apex of the polygonal well region 6 is located. By setting the well region extension region 22 to extend from the two sides where the apex of the polygonal well region 6 is located, it effectively extends the apex of the well region, thereby reducing the distance at the intersection of the apexes of the multiple polygonal well regions 6, reducing the electric field at this location, and improving the reliability of the silicon carbide power device 1.

[0069] For example, when the orthographic projection of the polygonal well region 6 onto the silicon carbide substrate 2 is rectangular, the two sides where the apex of the polygonal well region 6 is located are both right-angled sides. The well region extension region 22 extends outward from the aforementioned right-angled sides and overlaps with the polygonal well region 6 to form a single unit. The orthographic projection of the well region extension region 22 onto the silicon carbide substrate 2 can also be rectangular, and the outlines of the overlap between the well region extension region 22 and the polygonal well region 6 are perpendicular to each other.

[0070] For example, the overlap length 34 between the well extension region 22 and the polygonal well region 6 can be set to be less than or equal to the channel length 35. When the silicon carbide power device 1 is turned on, the well extension region 22 can hardly affect the current distribution. Since the channel current during conduction is mainly concentrated on the straight edge portion of the polygonal well region 6, the channel current density at its apex is low, so the well extension region 22 configured in this way has almost no impact on the channel resistance. Furthermore, since the width of the JFET channel 21 is greater than twice the width of the on-state depletion region, a current path still exists within the JFET channel 21, only slightly increasing the JFET resistance compared to a conventional polygonal cell.

[0071] In some embodiments, see Figure 1 Along the first direction X, the well extension regions 22 connected by two adjacent polygonal well regions 6 are interconnected. Along the second direction Y, JFET channels 21 are formed between the well extension regions 22 connected by two adjacent polygonal well regions 6. The polygonal well regions 6 are rectangular in shape, and the JFET channels 21 are located between two adjacent well extension regions 22, and the JFET channels 21 are in a straight line shape.

[0072] For example, see Figure 1 At each vertex of the polygonal well region 6, a well region extension region 22 is provided. Adjacent well region extension regions 22 are connected in the horizontal direction to form a whole, while they are separated in the vertical direction. The JFET channel 21 is sandwiched between the separated well region extension regions 22 and is in a straight line shape. The left and right sides of the well region extension region 22 are connected to the straight edge JFET region 23.

[0073] It is understood that the rectangular polygonal well region 6 includes four vertices, all of which extend outward. The vertices along the first direction X are interconnected, while the vertices along the second direction Y are separated. Thus, adjacent vertices of adjacent polygonal well regions 6 in the first direction X are connected, and the distance between adjacent vertices of adjacent polygonal well regions 6 in the second direction Y is reduced. The distance between relative vertices of relative polygonal well regions 6 is also reduced, thereby further reducing the distance at the intersection of the vertices of multiple polygonal well regions 6, thereby further reducing the electric field at this location and improving the reliability of this location, thus improving the reliability of the silicon carbide power device 1.

[0074] For example, see [link to previous article] Figure 1Subsequently, a gate can be added to the silicon carbide power device 1. The gate can be positioned above the connected well extension region 22 and the polygonal well region 6, thereby increasing the input capacitance (Ciss). Simultaneously, the presence of the well extension region 22 reduces the total facing area between the gate and the JFET region. Furthermore, the depletion region introduced by the well extension region 22 further reduces the depletion capacitance of the reverse transmission, thus reducing the reverse transmission capacitance (Crss). This significantly improves the high-frequency quality factor (HF-FOM) and Ciss / Crss ratio of the silicon carbide power device 1, thereby reducing the power consumption of the silicon carbide power device 1 in high-frequency operation and reducing the possibility of false turn-on.

[0075] Figure 3 This is a top view of another silicon carbide power device provided in an embodiment of this application.

[0076] In some embodiments, see Figure 3 The plurality of polygonal cells 41 include multiple rows and multiple columns. Each row of polygonal cells 41 is arranged along a first direction X, and each column of polygonal cells 41 is arranged along a second direction Y. Both the first direction X and the second direction Y are parallel to the silicon carbide substrate 2, and the first direction X and the second direction Y intersect. The embodiments of this application are illustrated with the example of the first direction X and the second direction Y being perpendicular.

[0077] The plurality of polygonal cells 41 includes at least one cell group, the cell group comprising two rows and two columns of polygonal cells 41. The cell group includes a first polygonal well region 61 and a second polygonal well region 62 diagonally opposite, and a third polygonal well region 63 and a fourth polygonal well region 64 diagonally opposite.

[0078] The first polygonal well region 61 is connected to the well region extension region 22, and the well region extension region 22 is connected to the second polygonal well region 62 to form an isolation region 60. The isolation region 60 isolates at least two straight-edge JFET regions 23.

[0079] It is understandable that the well extension regions 22 opposite to the first polygonal well region 61 and the second polygonal well region 62 are connected to form a single unit, and the isolation region 60 isolates the area located in... Figure 4 The straight-edge JFET regions 23 of the polygonal cells 41 in the lower left and upper right corners. By setting the isolation region 60, the area of ​​the JFET channel 21 is reduced, thereby further reducing the overall area of ​​the JFET, making the reverse transfer capacitance of the silicon carbide power device 1 smaller, and thus reducing the power consumption of the silicon carbide power device 1 under high-frequency operating conditions.

[0080] For example, see [link to previous article] Figure 3At the apex of the rectangular well region 6, adjacent well region extension regions 22 in the second and fourth quadrants connect to form a single unit, while well region extension regions 22 in the first and third quadrants are separated from other well region extension regions 22. Two JFET channels 21 are sandwiched between adjacent separated well region extension regions 22, both in a straight line shape. The upper right JFET channel 21 connects to the right and upper straight-edge JFET regions 23, and the lower left JFET channel 21 connects to the left and lower straight-edge JFET regions 23. The well region extension regions 22 overlap and merge with the well region 6, for example, the angle between their overlapping contours is 135°.

[0081] Furthermore, no part of the JFET channel 21 in the well region extension region 22 is wider than the straight-edge JFET region 23. By making the width 31 of the straight-edge JFET region 23 wider, the electric field at the intersection of the apex corners of the polygonal well region 6 is reduced, thereby improving the breakdown voltage of the silicon carbide power device 1 and its reliability.

[0082] Furthermore, the width 33 of the JFET channel 21 is less than or equal to the width 31 of the straight-edge JFET region 23, and greater than or equal to twice the width of the on-state depletion region within the JFET channel 21. It is understood that, compared to a traditional strip cell, the structure in this embodiment increases the channel density, while maintaining blocking characteristics similar to a traditional strip cell. Moreover, compared to a traditional rectangular cell, the structural arrangement in this embodiment hardly affects the channel density, with only a slight increase in total resistance and a significant improvement in reliability.

[0083] For example, see [link to previous article] Figure 3 Subsequently, a gate can be added to the silicon carbide power device 1. The gate can be positioned above the connected well extension region 22 and the polygonal well region 6, thereby increasing the input capacitance (Ciss). Simultaneously, the presence of the well extension region 22 reduces the total facing area between the gate and the JFET region. Furthermore, the depletion region introduced by the well extension region 22 further reduces the depletion capacitance of the reverse transmission, thus reducing the reverse transmission capacitance (Crss). This significantly improves the high-frequency quality factor (HF-FOM) and Ciss / Crss ratio of the silicon carbide power device 1, thereby reducing the power consumption of the silicon carbide power device 1 in high-frequency operation and reducing the possibility of false turn-on.

[0084] like Figure 3 The specific on-resistance of the silicon carbide power device 1 shown is similar to that of the traditional rectangular cell device, and is significantly lower than that of the strip cell device under the same process conditions. Furthermore, compared with the traditional rectangular cell device, the silicon carbide power device 1 has a higher Ciss, a lower Crss, better dynamic performance, a significantly smaller maximum electric field in the resistive state, and higher reliability.

[0085] Figure 4 This is a top view of another silicon carbide power device provided in an embodiment of this application.

[0086] In some embodiments, see Figure 4 The plurality of polygonal cells 41 include multiple rows and multiple columns. Each row of polygonal cells 41 is arranged along a first direction X, and each column of polygonal cells 41 is arranged along a second direction Y. Both the first direction X and the second direction Y are parallel to the silicon carbide substrate 2, and the first direction X and the second direction Y intersect. The embodiments of this application are illustrated with the example of the first direction X and the second direction Y being perpendicular.

[0087] Along the first direction X, a portion of the JFET channel 21 is formed between the well extension regions 22 connected by two adjacent polygonal well regions 6. Along the second direction Y, another portion of the JFET channel 21 is formed between the well extension regions 22 connected by two adjacent polygonal well regions 6. The polygonal well regions 6 are rectangular in shape, and the JFET channel 21 is located between four adjacent well extension regions 22, and the JFET channel 21 is cross-shaped.

[0088] For example, a well extension area 22 is provided at each vertex of the polygonal well area 6. All well extension areas 22 are separated from each other. The JFET channel 21 is sandwiched between adjacent well extension areas 22 in a cross shape. The well extension area 22 is connected to the straight-edge JFET areas 23 in four directions.

[0089] It is understood that the polygonal well region 6, which is rectangular in shape, includes four vertices. These four vertices extend outward and are separated from each other. Therefore, the distance between adjacent vertices of adjacent polygonal well regions 6 and the distance between relative vertices of opposite polygonal well regions 6 are reduced. This further reduces the distance at the intersection of the vertices of multiple polygonal well regions 6, thereby further reducing the electric field at this location and improving the reliability of this location, thus improving the reliability of the silicon carbide power device 1.

[0090] For example, see [link to previous article] Figure 4 In the well region extension region 22, no part of the JFET channel 21 is wider than the straight-edge JFET region 23. By making the width 31 of the straight-edge JFET region 23 wider, the electric field at the apex intersection of the polygonal well region 6 is reduced, the breakdown voltage of the silicon carbide power device 1 is improved, and the reliability of the silicon carbide power device 1 is also improved.

[0091] Furthermore, the width 33 of the JFET channel 21 is less than or equal to the width 31 of the straight-edge JFET region 23, and is greater than or equal to twice the width of the on-state depletion region within the JFET channel 21. It can be understood that the above configuration increases the conductive path or conductive area of ​​the silicon carbide power device 1 in the on-state, thereby improving the conduction characteristics of the silicon carbide power device 1.

[0092] For example, see [link to previous article] Figure 4 Subsequently, a gate can be added to the silicon carbide power device 1. The gate can be positioned above the connected well extension region 22 and the polygonal well region 6, thereby increasing the input capacitance (Ciss). Simultaneously, the presence of the well extension region 22 reduces the total facing area between the gate and the JFET region. Furthermore, the depletion region introduced by the well extension region 22 further reduces the depletion capacitance of the reverse transmission, thus reducing the reverse transmission capacitance (Crss). This significantly improves the high-frequency quality factor (HF-FOM) and Ciss / Crss ratio of the silicon carbide power device 1, thereby reducing the power consumption of the silicon carbide power device 1 in high-frequency operation and reducing the possibility of false turn-on.

[0093] Figure 5 This is a top view of another silicon carbide power device provided in an embodiment of this application.

[0094] In some embodiments, see Figure 5 The plurality of polygonal cells 41 include multiple rows and multiple columns. Each row of polygonal cells 41 is arranged along a first direction X, and each column of polygonal cells 41 is arranged along a second direction Y. Both the first direction X and the second direction Y are parallel to the silicon carbide substrate 2, and the first direction X and the second direction Y intersect. The embodiments of this application are illustrated with the example of the first direction X and the second direction Y being perpendicular.

[0095] There are at least two adjacent rows of polygonal well regions 6. In one row of polygonal well regions 6, along a first direction, the well region extension areas 22 connected to adjacent polygonal well regions 6 are interconnected. In another row of polygonal well regions 6, along the first direction, the well region extension areas 22 connected to adjacent polygonal well regions 6 are spaced apart to form a portion of a JFET channel 21. Along a second direction, the well region extension areas 22 connected to adjacent polygonal well regions 6 are spaced apart to form another portion of a JFET channel 21. The polygonal well regions 6 are rectangular in shape, and the JFET channel 21 is located between four adjacent well region extension areas 22, and the JFET channel 21 is T-shaped.

[0096] It is understood that the rectangular polygonal well region 6 includes four vertices, all of which extend outward to form well region extension regions 22. At the intersection of the vertices of the polygonal well region 6, the two upper well region extension regions 22 are interconnected and become one, while the lower well region extension region 22 is separate. The JFET channel 21 is sandwiched between the adjacent separate well region extension regions 22 and is T-shaped, connecting with the straight-edge JFET regions 23 in the left, lower, and right directions. This further reduces the distance at the intersection of the vertices of the multiple polygonal well regions 6, thereby further reducing the electric field at this location and improving the reliability of the silicon carbide power device 1.

[0097] For example, see [link to previous article] Figure 5 In the well region extension region 22, no part of the JFET channel 21 is wider than the straight-edge JFET region 23. By making the width 31 of the straight-edge JFET region 23 wider, the electric field at the apex intersection of the polygonal well region 6 is reduced, the breakdown voltage of the silicon carbide power device 1 is improved, and the reliability of the silicon carbide power device 1 is also improved.

[0098] Furthermore, the width 33 of the JFET channel 21 is less than or equal to the width 31 of the straight-edge JFET region 23, and greater than or equal to twice the width of the on-state depletion region within the JFET channel 21. When the silicon carbide power device 1 is in the conducting state, the JFET channel 21 can also carry current. It is understood that the above configuration increases the conductive path or conductive area of ​​the silicon carbide power device 1 in the conducting state, thereby improving the conduction characteristics of the silicon carbide power device 1.

[0099] For example, the well extension region 22 overlaps and merges with the well region 6, with the contours of the overlap being perpendicular to each other. No part of the JFET channel 21 in the well extension region 22 is wider than the straight-edge JFET region 23. By making the width 31 of the straight-edge JFET region 23 wider, the electric field at the apex intersection of the polygonal well region 6 is reduced, improving the breakdown voltage of the silicon carbide power device 1 and its reliability.

[0100] And, as Figure 5 The silicon carbide power device 1 shown has a higher channel density, and its specific on-resistance is significantly lower than that of a strip cell device under the same process conditions. Furthermore, compared with traditional rectangular cells, it has a larger Ciss, a smaller Crss, a larger Ciss / Crss ratio, better dynamic performance, a significantly smaller maximum electric field in the resistive state, and higher reliability.

[0101] Figure 6 This is a top view of another silicon carbide power device provided in an embodiment of this application.

[0102] In some embodiments, see Figure 6 Along the third direction α, the fourth direction β, and the fifth direction γ parallel to the silicon carbide substrate 2, multiple polygonal cells 41 are periodically arranged. The third direction α, the fourth direction β, and the fifth direction γ are not parallel and intersect each other. The polygonal well region 6 is hexagonal in shape. The vertices of three adjacent polygonal well regions 6 are close to each other. The interval between any two adjacent well region extension regions 6 forms a part of the JFET channel 21. The JFET channel 21 is Y-shaped.

[0103] For example, the embodiments of this application are illustrated by taking the third direction α, the fourth direction β and the fifth direction γ as being 120° apart, and the polygonal well region 6 is hexagonal in shape.

[0104] Understandably, a well extension region 22 is provided at each vertex of the hexagonal polygonal well region 6. All well extension regions 22 are separated from each other, and the JFET channel 21 is sandwiched between adjacent well extension regions 22 in a Y-shape. The JFET channel 21 is connected to the straight-edge JFET regions 23 in the third direction α, the fourth direction β, and the fifth direction γ.

[0105] For example, see [link to previous article] Figure 6 The well extension region 22 overlaps and merges with the well region 6, with the outlines at the overlap being perpendicular to each other. No part of the JFET channel 21 in the well extension region 22 is wider than the straight-edge JFET region 23. By making the width 31 of the straight-edge JFET region 23 wider, the electric field at the apex intersection of the polygonal well region 6 is reduced, improving the breakdown voltage of the silicon carbide power device 1 and its reliability.

[0106] The polygonal well region 6 with a hexagonal structure has a similar channel density to the polygonal well region 6 with a quadrilateral structure. Furthermore, by setting the well region extension region 22, the electric field at the intersection of the vertices of the polygonal well region 6 is reduced, which improves the withstand voltage of the silicon carbide power device 1 and enhances its dynamic characteristics and reliability. This enables synergistic optimization of the dynamic characteristics, static characteristics, and reliability of the silicon carbide power device 1 to obtain the comprehensive performance that best matches the specific application requirements.

[0107] For example, see [link to previous article] Figure 6 In the well region extension region 22, no part of the JFET channel 21 is wider than the straight-edge JFET region 23. By making the width 31 of the straight-edge JFET region 23 wider, the electric field at the apex intersection of the polygonal well region 6 is reduced, the breakdown voltage of the silicon carbide power device 1 is improved, and the reliability of the silicon carbide power device 1 is also improved.

[0108] Furthermore, the width 33 of the JFET channel 21 is less than or equal to the width 31 of the straight-edge JFET region 23, and is greater than or equal to twice the width of the on-state depletion region within the JFET channel 21. It can be understood that the above configuration increases the conductive path or conductive area of ​​the silicon carbide power device 1 in the on-state, thereby improving the conduction characteristics of the silicon carbide power device 1.

[0109] On the other hand, a method for fabricating silicon carbide power devices is also provided. Figure 7This is a flowchart illustrating a method for fabricating a silicon carbide power device according to an embodiment of this application. This method is used to fabricate the silicon carbide power device 1 as described in the above embodiment.

[0110] See Figure 7 The above preparation method includes the following steps S1 and S2: Step S1: Deposit a masking layer on the surface of the epitaxial drift layer 3. The masking layer has a through ion implantation window.

[0111] For example, the material of the masking layer can be polysilicon or silicon oxide. A masking layer of a predetermined thickness can be deposited on the surface of the epitaxial drift layer 3, and an ion implantation window can be formed after removing all or part of the masking layer in the predetermined area using photolithography and etching processes.

[0112] For example, prior to step S1 above, a silicon carbide substrate 2 with a high doping concentration is selected, and an epitaxial drift layer 3 of silicon carbide material is grown on the silicon carbide substrate 2. For example, the doping concentration of conductive ions in the silicon carbide substrate 2 can be in the range of 10. 18 cm -3 ~10 20 cm -3 The doping concentration of the epitaxial drift layer 3 can be in the range of 10. 14 cm -3 ~10 16 cm -3 .

[0113] Step S2: Ion implantation is performed on the epitaxial drift layer 3 through the ion implantation window at a temperature range of 450℃~550℃ to form a polygonal well region 6 and a well region extension region 22, thereby forming a silicon carbide power device 1.

[0114] For example, after forming the polygonal well region 6 and the well region extension region 22, the epitaxial drift layer 3 is subjected to multiple photolithography, etching and ion implantation processes to form the first region 5, the second region 7, the straight-edge JFET region 23 and the JFET channel 21.

[0115] On the other hand, a silicon carbide MOSFET is also provided. Figure 8 A top view of a silicon carbide MOSFET provided in an embodiment of this application; Figure 9 A top view of another silicon carbide MOSFET provided in an embodiment of this application; Figure 10 A top view of another silicon carbide MOSFET provided in an embodiment of this application; Figure 11 for Figure 10 A top view of a portion of the film layer of a silicon carbide MOSFET. Figure 12 for Figure 10 and Figure 11 A partial cross-sectional view of the silicon carbide MOSFET along section line BB'; Figure 13 for Figure 10 and Figure 11 A partial cross-sectional view of the silicon carbide MOSFET along section line CC'.

[0116] See Figures 8-13 The silicon carbide MOSFET 100 includes a silicon carbide power device 1, a Schottky electrode 12, a gate 8, a source 11, and a drain 13 as described in the above embodiment. Figure 10 Gate 8 is not shown in the structure. Figure 11 The structure shown only includes the gate 8, source 11, and Schottky electrode 12.

[0117] In this configuration, the epitaxial drift layer 3 and the silicon carbide substrate 2 have the same conductivity type. For example, both the epitaxial drift layer 3 and the silicon carbide substrate 2 can be N-type, in which case the silicon carbide MOSFET 100 is an N-channel device. Alternatively, both the epitaxial drift layer 3 and the silicon carbide substrate 2 can be P-type, in which case the silicon carbide MOSFET 100 is a P-channel device.

[0118] In the silicon carbide MOSFET 100, at least a portion of the polygonal cell 41 has a Schottky contact region 43 within its polygonal well region 6, or a straight-edge JFET region 23 has a Schottky contact region 43. It is understood that in this embodiment provided by the present application, the silicon carbide MOSFET 100 integrates a Schottky diode (SBD).

[0119] Schottky electrode 12 covers Schottky contact region 43 and is electrically connected to source 11. It is understood that a Schottky contact is formed on the surface of epitaxial drift layer 3 within Schottky contact region 43 with the Schottky electrode 12 directly covering it, and Schottky electrode 12 is short-circuited to source 11 of silicon carbide MOSFET 100.

[0120] The above configuration allows the silicon carbide MOSFET100 to exhibit lower on-state voltage drop and reverse recovery loss when reverse-biased, effectively suppressing body diode conduction and avoiding bipolar degradation risks, without requiring an additional anti-parallel freewheeling diode in the circuit. Furthermore, compared to parallel discrete devices, the MOSFET and integrated SBD can share the drift region and termination, reducing the overall chip area, saving module packaging costs, lowering parasitic parameters, and improving system efficiency.

[0121] For example, see Figure 8The polygonal well region 6 is rectangular and periodically arranged in the first direction X and the second direction Y. A well region extension region 22 is provided at each vertex of the polygonal well region 6. Adjacent well region extension regions 22 are connected in the lateral direction to form a single unit, but are separated in the longitudinal direction. A JFET channel 21 is sandwiched between adjacent separated well region extension regions 22 in a straight line shape, and the JFET channel 21 is connected to the straight-edge JFET regions 23 on both the left and right sides.

[0122] Furthermore, an SBD is integrated within each MOSFET polygonal cell 41, meaning that a Schottky contact region 43 is provided within each polygonal well region 6. The surface of the epitaxial drift layer 3 at this location forms a Schottky contact with the Schottky electrode 12 that subsequently covers this surface, thereby embedding an SBD within the power MOSFET.

[0123] In the forward conduction state (Vds>0), due to the arrangement of the well region extension region 22, the power consumption of the silicon carbide power device 1 is reduced and the reliability is increased. For details of this effect, please refer to the description in this application. Figure 1 The corresponding embodiment. In the case of reverse freewheeling (Vds<0), since the turn-on voltage of the Schottky junction is significantly lower than that of the body diode, the silicon carbide MOSFET100 is unipolarly turned on by the SBD, and the body diode is suppressed. Therefore, the diode forward voltage drop, reverse recovery time, reverse recovery current and reverse recovery loss can be significantly reduced, while also avoiding the risk of bipolar degradation.

[0124] Alternatively, for example, see Figure 9 The SBD is integrated in only half of the MOSFET polygonal cells 41, and the Schottky contact region 43 is located in the polygonal well region 6. The other half is a pure MOSFET polygonal cell 41. The MOSFET polygonal cells 41 with integrated SBD and the pure MOSFET polygonal cells 41 are arranged continuously in the horizontal direction and alternately in the vertical direction.

[0125] In the forward conduction state (Vds>0), both the specific on-resistance and reverse transfer capacitance of the silicon carbide power device 1 decrease, resulting in reduced power consumption and increased reliability. In the reverse freewheeling state (Vds<0), it is unipolarly conducted by the SBD.

[0126] Because the SBD requires a certain area, under the same process conditions, the width of the MOSFET polygonal cell 41 integrating the SBD needs to be greater than the width of the pure MOSFET polygonal cell 41. Therefore, as Figure 10 The structure shown can further increase the channel density, thereby giving the MOSFET a lower specific on-resistance.

[0127] For example, embodiments of this application can also adjust the ratio of MOSFET to SBD according to the application to balance their energy consumption, thereby reducing overall system heat generation and increasing power density.

[0128] For example, in this application Figure 7 In the corresponding embodiment, after ion implantation, a gate oxide layer 9 can be formed on the gate region, and a material film layer of the gate 8 can be deposited. For example, the material of the gate 8 can be polysilicon. The material of the gate oxide layer 9 can be silicon oxide, and the gate oxide layer 9 can be formed by thermal oxidation or chemical vapor deposition.

[0129] Next, a first layer of contact metal (such as nickel) is sputtered and deposited on the source region, and then rapidly annealed to form an ohmic contact. After sputtering and depositing a second layer of metal on the surface of the epitaxial drift layer 3, the source 11 and gate 8 are formed by photolithography and etching.

[0130] For example, after sputtering and depositing a first layer of contact metal (such as nickel) on the source region, another layer of contact metal (such as titanium) is sputtered and deposited on top of the contact metal, i.e., on the surface of the Schottky contact region 43, and then rapidly annealed to form the Schottky contact. Furthermore, the aforementioned second metal layer connects the source 11 of the MOSFET to the contact metal within the Schottky contact region 43, thereby becoming the source 11 of the silicon carbide MOSFET 100 integrating a Schottky diode.

[0131] Finally, metal is deposited on the side of the silicon carbide substrate 2 away from the epitaxial drift layer 3 to form the drain 13, thereby forming the silicon carbide MOSFET 100.

[0132] In some embodiments, see Figures 10-13 The straight-edge JFET region 23 is provided with a Schottky contact region 43. Multiple polygonal cells 41 comprise multiple rows and columns, with each row of polygonal cells 41 arranged along a first direction X and each column of polygonal cells 42 arranged along a second direction Y. Both the first direction X and the second direction Y are parallel to the silicon carbide substrate 2 and intersect each other. Along the first direction X, two adjacent straight-edge JFET regions 23 are connected through a JFET channel 21, and Schottky electrodes 12 and gates 8 are alternately arranged above the straight-edge JFET regions 23.

[0133] For example, see Figure 10 and Figure 11The polygonal well region 6 is rectangular. Adjacent well region extension regions 22 are connected in the first direction X to form a single unit, but separated in the second direction Y. The JFET channel 21 is sandwiched between adjacent separated well region extension regions 22 in a straight line shape, and is connected to the straight-edge JFET regions 23 on both the left and right sides. The vertical straight-edge JFET regions 23 are all isolated from each other, and a gate 8 is disposed above each of them. Schottky contact regions 43 are staggered in multiple horizontal straight-edge JFET regions 23, and no gate 8 is disposed above these horizontal straight-edge JFET regions 23.

[0134] For example, see Figure 13 Above the straight-edge JFET region 23, gates 8 and Schottky electrodes 12 are alternately arranged along direction X, and the straight-edge JFET region 23 and JFET channel 21 are completely connected along direction X. Finally, each polygonal well region 6 of the silicon carbide MOSFET 100 has three sides with gates 8 to form a channel, and the remaining side has no gate 8 but has a Schottky contact region 43. Furthermore, only one of the adjacent straight-edge JFET regions 23 has a Schottky contact region 43.

[0135] See Figure 10 and Figure 11 The straight-edge JFET region 23 below the gate 8 is connected to the straight-edge JFET region 23 below the Schottky electrode 12 by the JFET channel 21. Thus, when the MOSFET is turned on or the SBD is turned on, the entire horizontal JFET region can serve as a current path, effectively improving the chip area utilization and effectively reducing the JFET resistance.

[0136] Furthermore, the arrangement of polygonal cells 41 increases channel density and reduces channel resistance. Therefore, the silicon carbide MOSFET 100 provided in this application has lower MOSFET specific on-resistance and SBD on-state voltage drop, while maintaining better dynamic characteristics and high reliability.

[0137] On the other hand, a silicon carbide IGBT200 (Insulated-Gate Bipolar Transistor) is also provided. Figure 14 This is a schematic diagram of the structure of a silicon carbide IGBT provided in an embodiment of this application.

[0138] See Figure 14 The silicon carbide IGBT 200 includes a silicon carbide power device 1, a gate 8, an emitter 14, and a collector 15 as described in the above embodiments.

[0139] In this design, the epitaxial drift layer 3 and the silicon carbide substrate 2 have different conductivity types. For example, the silicon carbide substrate 2 can be P-type, and the epitaxial drift layer 3 can be N-type; in this case, the silicon carbide MOSFET 100 is an N-channel device. Alternatively, the silicon carbide substrate 2 can be N-type, and the epitaxial drift layer 3 can be P-type; in this case, the silicon carbide MOSFET 100 is a P-channel device.

[0140] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A silicon carbide power device, characterized in that, include: silicon carbide substrate; An epitaxial drift layer is disposed on the silicon carbide substrate; Multiple polygonal cells are disposed on the surface of the epitaxial drift layer away from the silicon carbide substrate; each polygonal cell includes a polygonal well region and a straight-edge JFET region, with adjacent edges of two adjacent polygonal well regions being parallel, and the straight-edge JFET region being located between the parallel edges of two adjacent polygonal well regions. Multiple extended cells are disposed on the surface of the epitaxial drift layer away from the silicon carbide substrate; each extended cell includes a well region extension region and a JFET channel, the well region extension region and the polygonal well region are formed synchronously under the same process, each vertex of the polygonal well region extends outward to form the well region extension region, the shape of the well region extension region is polygonal or quasi-polygonal; the JFET channel is located between at least two adjacent well region extension regions and is interconnected with at least two adjacent straight-edge JFET regions; the width of the JFET channel is less than or equal to the width of the straight-edge JFET region, and greater than or equal to twice the width of the on-state depletion region within the JFET channel.

2. The silicon carbide power device according to claim 1, characterized in that, The shape of the orthographic projection of the well region extension region on the silicon carbide substrate is polygonal or polygon-like, and the well region extension region includes multiple sides with an included angle or arc transition between adjacent sides; In the two sides where the apex of the polygonal well region is located, the extended area of ​​the well region partially overlaps with at least one side.

3. The silicon carbide power device according to claim 1, characterized in that, The plurality of polygonal cells include multiple rows and multiple columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first direction and the second direction are parallel to the silicon carbide substrate and intersect each other. Along the first direction, the well extension regions connected by two adjacent polygonal well regions are interconnected; along the second direction, the well extension regions connected by two adjacent polygonal well regions are spaced apart to form the JFET channel; the polygonal well regions are rectangular in shape, and the JFET channel is located between two adjacent well extension regions, and the JFET channel is in the shape of a straight line.

4. The silicon carbide power device according to claim 1, characterized in that, The plurality of polygonal cells include multiple rows and multiple columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first direction and the second direction are parallel to the silicon carbide substrate and intersect each other. Along the first direction, a portion of the JFET channel is formed between the well extension regions connected by two adjacent polygonal well regions; Along the second direction, the expansion regions of the well regions connected by two adjacent polygonal well regions form another part of the JFET channel; the polygonal well regions are rectangular in shape, and the JFET channel is located between four adjacent expansion regions, and the JFET channel is cross-shaped.

5. The silicon carbide power device according to claim 1, characterized in that, The plurality of polygonal cells include multiple rows and multiple columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first direction and the second direction are parallel to the silicon carbide substrate and intersect each other. There are at least two adjacent rows of polygonal well regions. In one row of polygonal well regions, along the first direction, the well region extension areas connected by two adjacent polygonal well regions are interconnected. In the other row of polygonal well regions, along the first direction, the well region extension areas connected by two adjacent polygonal well regions are spaced apart to form part of the JFET channel. Along the second direction, the well extension regions connected by two adjacent polygonal well regions form another part of the JFET channel; the polygonal well regions are rectangular in shape, and the JFET channel is located between four adjacent well extension regions, and the JFET channel is T-shaped.

6. The silicon carbide power device according to claim 1, characterized in that, The plurality of polygonal cells include multiple rows and multiple columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first direction and the second direction are parallel to the silicon carbide substrate and intersect each other. The plurality of polygonal cells include at least one cell group, the cell group including two rows and two columns of polygonal cells; the cell group includes a first polygonal well region and a second polygonal well region diagonally opposite, as well as a third polygonal well region and a fourth polygonal well region diagonally opposite. The first polygonal well region is connected to the well region extension region, and the second polygonal well region is connected to form an isolation region, which isolates at least two straight-edge JFET regions.

7. The silicon carbide power device according to claim 1, characterized in that, Along a third, fourth, and fifth direction parallel to the silicon carbide substrate, the plurality of polygonal cells are arranged periodically, and the third, fourth, and fifth directions are not parallel and intersect each other; The polygonal well region is hexagonal in shape, with the vertices of three adjacent polygonal well regions close to each other, and the extension regions of any two adjacent well regions are spaced apart to form a portion of the JFET channel, which is Y-shaped.

8. A method for fabricating a silicon carbide power device, characterized in that, Used to prepare silicon carbide power devices as described in any one of claims 1 to 7; The preparation method includes: A masking layer is deposited on the surface of the epitaxial drift layer, the masking layer having a through ion implantation window; Ions are implanted into the epitaxial drift layer through the ion implantation window at a temperature range of 450°C to 550°C to form a polygonal well region and a well region extension region.

9. A silicon carbide MOSFET, characterized in that, Includes a silicon carbide power device as described in any one of claims 1 to 7, a Schottky electrode, a gate, a source, and a drain; At least some of the polygonal cells have a Schottky contact region in their polygonal well regions, or the straight-edge JFET region has a Schottky contact region. The Schottky electrode covers the Schottky contact area and is electrically connected to the source electrode.

10. The silicon carbide MOSFET according to claim 9, characterized in that, The straight-edge JFET region is provided with a Schottky contact region; The plurality of polygonal cells include multiple rows and multiple columns, with each row of polygonal cells arranged along a first direction and each column of polygonal cells arranged along a second direction. Both the first direction and the second direction are parallel to the silicon carbide substrate and intersect each other. Along the first direction, two adjacent straight-edge JFET regions are connected through the JFET channel, and the Schottky electrode and the gate are alternately arranged above the straight-edge JFET regions.

11. A silicon carbide IGBT, characterized in that, It includes the silicon carbide power device, gate, emitter, and collector as described in any one of claims 1 to 7.

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