Test screening method and system for enhancing electrical interference resistance of chip

Abstract

The invention provides a test screening method and system for enhancing electrical interference resistance of a chip, and belongs to the technical field of integrated circuit testing, and the method comprises the steps: building a topological network interference model which comprises a topological connection relation among a chip power pin, a grounding pin and a signal pin, the interference source parameters are set according to the rated voltage range and the interference distance of the chip; constructing an interference path to form three groups of test structures; obtaining current distribution parameters, including determining an initial current value, calculating a voltage drop value and determining a test current value; executing an interference simulation test; when the simulation result meets a preset condition, dynamically adjusting the distance between the test structures in the topological network interference model to form an optimized test model; and performing chip batch screening according to the optimized test model, constructing an accurate interference model according to a topology network theory, optimizing current distribution parameters, dynamically adjusting a test structure, and realizing high-precision test and efficient screening of the anti-electrical interference capability of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit testing, in particular to a test screening method and system for enhancing chip anti-electromagnetic interference. BACKGROUND

[0002] With the continuous improvement of integrated circuit integration and the increasing complexity of application environment, the chip anti-electromagnetic interference capability becomes a key factor affecting product reliability. The traditional chip anti-electromagnetic interference test method mainly relies on empirical parameter setting and simple circuit model, which is difficult to accurately simulate complex electromagnetic interference environment, resulting in large differences between test results and actual application scenarios.

[0003] Currently, the chip anti-electromagnetic interference test mainly has the following problems: first, the test accuracy is insufficient, the existing method is based on a simplified model, which is difficult to fully consider the complex circuit topology structure and interference propagation path inside the chip; second, the test efficiency is low, the conventional method needs a large amount of redundant test, which takes a long time; third, the adaptability is poor, the test scheme needs to be redesigned for different types of chips, and there is a lack of unified test framework.

[0004] Therefore, there is an urgent need for a test method and system that can accurately model the chip circuit topology structure and efficiently screen the chip anti-electromagnetic interference capability. SUMMARY

[0005] The purpose of the present application is to provide a chip anti-electromagnetic interference test screening method and system based on topology network theory, which realizes high-precision test and efficient screening of chip anti-electromagnetic interference capability by constructing an accurate topology network interference model, optimizing current distribution parameters and dynamically adjusting test structure.

[0006] The present application provides a test screening method for enhancing chip anti-electromagnetic interference, which comprises:

[0007] Establishing a topology network interference model, the topology network interference model comprising the topology connection relationship of the power pin, ground pin and signal pin of the chip, and the interference source parameters, the interference source parameters being set according to the rated voltage range and interference distance of the chip;

[0008] Constructing an interference path, comprising:

[0009] Connecting the power pin of the chip with the first analog ground pin, and connecting the ground pin of the chip with the second analog ground pin to form a first group of test structures;

[0010] Selecting a group of continuous positions from all the first analog ground pins, connecting the continuous positions together to form a first interference path, and connecting the signal pins together based on the first interference path to form a second group of test structures;

[0011] selecting a set of continuous positions from all second analog ground pins, connecting the continuous positions together to form a second interference path, and connecting a first signal pin with the second interference path based on the second interference path to form a third set of test structures;

[0012] obtaining current distribution parameters, including:

[0013] determining initial current values of nodes in the topology network interference model according to theoretical current values of the chip;

[0014] obtaining voltage values of signal pins in the topology network interference model, and calculating a voltage drop value of the chip according to the voltage values of the signal pins and voltage values of power supply pins;

[0015] determining test current values of each test structure based on the voltage drop value, and adding corresponding current values at corresponding positions of each test structure in the topology network interference model;

[0016] performing an interference simulation test to obtain a simulation result of the topology network interference model;

[0017] when the simulation result meets a preset condition, dynamically adjusting distances between each test structure in the topology network interference model to form an optimized test model;

[0018] performing chip batch screening according to a simulation result of the optimized test model.

[0019] Preferably, the step of establishing the topology network interference model specifically includes:

[0020] converting a physical structure of the chip into a set of digital nodes, each pin being mapped as a node in a topology network;

[0021] dividing the nodes into a power supply domain, a connection domain and a signal domain based on functional blocks of the chip;

[0022] establishing connection relationships between the nodes to form an initial topology graph according to design specifications of the chip;

[0023] adding an interference source in the initial topology graph, parameters of the interference source being set according to a rated voltage range and an interference distance of the chip.

[0024] Preferably, the step of constructing the interference path specifically includes:

[0025] selecting continuous position points with the highest connectivity from the first analog ground pins to form the first interference path;

[0026] performing cluster analysis on the signal pins to identify a set of nodes sensitive to interference;

[0027] based on the set of nodes sensitive to interference, constructing the second set of test structures such that the signal pins are connected together;

[0028] selecting a continuous position point with the highest interference propagation efficiency from the second analog ground pin to form the second interference path;

[0029] connecting the first signal pin and the second interference path to form the third set of test structures.

[0030] Preferably, the step of obtaining current distribution parameters specifically includes:

[0031] extracting a theoretical current value from the specification parameters of the chip;

[0032] using the theoretical current value as the edge weight of the topology network to construct an initial current distribution model;

[0033] obtaining the voltage value of each signal pin in the topology network interference model;

[0034] calculating the voltage drop value of the chip according to the voltage value of the signal pin and the voltage value of the power pin;

[0035] based on the voltage drop value and the connection relationship of the topology network, calculating the distribution of current in the network;

[0036] evaluating the balance degree of current distribution to identify abnormal points and singular regions in the current distribution;

[0037] determining the test current value of each test structure according to the abnormal points and singular regions.

[0038] Preferably, the step of performing interference simulation testing specifically includes:

[0039] setting interference simulation parameters, including interference source type, interference strength, interference frequency, and duration;

[0040] performing electromagnetic interference simulation in the topology network interference model;

[0041] obtaining the response result of the topology network interference model;

[0042] extracting key indicators such as interference response sensitivity, result consistency, coverage integrity, and screening accuracy;

[0043] comparing the key indicators with preset conditions.

[0044] Preferably, the step of dynamically adjusting the topological network interference model comprises:

[0045] Analyzing the simulation results to identify areas that need optimization;

[0046] Determining key adjustment parameters, including distances between test structures, connection relationships, and functional domain boundaries;

[0047] Generating a topological structure adjustment scheme;

[0048] According to the adjustment scheme, gradually adjusting the distances between test structures in the topological network interference model;

[0049] Verifying the performance of the adjusted model;

[0050] When the performance improvement is below a preset threshold, confirming the final optimized test model.

[0051] Preferably, the step of performing batch screening of chips according to the simulation results of the optimized test model comprises:

[0052] Setting batch test parameters according to the optimized test model;

[0053] Connecting multiple chips to be tested in parallel to the test equipment;

[0054] Performing interference testing on the multiple chips to be tested according to the test structures and parameters in the optimized test model;

[0055] Collecting test data for each chip, including voltage response, current distribution, and signal integrity;

[0056] Evaluating the anti-electromagnetic interference performance of each chip based on a preset screening threshold;

[0057] Marking chips that meet the requirements as qualified and marking chips that do not meet the requirements as unqualified.

[0058] Preferably, the preset conditions include:

[0059] Interference response sensitivity is higher than 95%;

[0060] Result consistency is higher than 98%;

[0061] Coverage completeness is higher than 90%;

[0062] Screening accuracy is higher than 97%.

[0063] Preferably, the key adjustment parameters further include:

[0064] Node centrality for evaluating the importance of a node in the network;

[0065] a clustering coefficient for evaluating the degree of clustering of nodes;

[0066] a path complexity for evaluating the characteristics of interference propagation paths;

[0067] a network entropy for evaluating the determinism and stability of a topological network.

[0068] The test screening system for enhancing the anti-electromagnetic interference of a chip comprises:

[0069] a topological network construction module for establishing a topological network interference model, wherein the topological network interference model comprises a topological connection relationship of power supply pins, ground pins and signal pins of a chip, and interference source parameters, and the interference source parameters are set according to a rated voltage range of the chip and an interference distance;

[0070] an interference path construction module for constructing an interference path, comprising: connecting the power supply pins of the chip with first analog ground pins, connecting the ground pins of the chip with second analog ground pins, to form a first group of test structures; selecting a group of continuous positions from all the first analog ground pins, connecting the continuous positions together to form a first interference path, and connecting the signal pins together based on the first interference path to form a second group of test structures; selecting a group of continuous positions from all the second analog ground pins, connecting the continuous positions together to form a second interference path, and connecting the first signal pins with the second interference path based on the second interference path to form a third group of test structures;

[0071] a current distribution module for obtaining current distribution parameters, comprising: determining initial current values of nodes in the topological network interference model according to theoretical current values of the chip; obtaining voltage values of the signal pins in the topological network interference model, and calculating voltage drop values of the chip according to the voltage values of the signal pins and the voltage values of the power supply pins; determining test current values of the test structures based on the voltage drop values, and adding corresponding current values at corresponding positions of the test structures in the topological network interference model;

[0072] a simulation execution module for executing interference simulation tests to obtain simulation results of the topological network interference model;

[0073] a topological optimization module for dynamically adjusting distances between the test structures in the topological network interference model to form an optimized test model when the simulation results meet preset conditions;

[0074] a chip screening module for executing batch screening of chips according to simulation results of the optimized test model.

[0075] The present application has the following beneficial effects:

[0076] 1. Test accuracy is significantly improved: By constructing an accurate interference model based on topological network theory, considering the complex circuit topological structure and interference propagation path inside the chip, the test results are closer to the actual application scenario, and the test accuracy is improved by about 40%.

[0077] 2. Test efficiency is greatly improved: By adopting a dynamic topological adaptive adjustment mechanism, about 50% of invalid tests are reduced, significantly improving the batch screening efficiency, and a test speed of more than 100 chips per hour can be realized.

[0078] 3. Strong adaptability: Through adaptive adjustment of the topological network, the system can quickly adapt to different types of chip structures, reducing the development cycle of new chip test schemes, and providing a unified test framework for different application scenarios.

[0079] 4. High interpretability: By visualizing the interference propagation mechanism through topology, the fault positioning accuracy is improved, which helps to guide the optimization and improvement of chip anti-interference design. BRIEF DESCRIPTION OF DRAWINGS

[0080] Figure 1 is a flow chart of a chip anti-electric interference test screening method provided by an embodiment of the present application;

[0081] Figure 2 is a structural block diagram of a chip anti-electric interference test screening system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0082] Please refer to Figure 1 - Figure 2 , the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for illustration and explanation of the present application, and are not intended to limit the present application.

[0083] As shown in Figure 1 , the present application provides a chip anti-electric interference test screening method, which comprises the following steps:

[0084] In a preferred embodiment of the present application, the process of establishing a topological network interference model includes converting the physical structure of the chip into a set of digital nodes, and mapping the pins as nodes in the topological network; based on the chip function block, the nodes are divided into power domain, interface domain and signal domain; according to the chip design specification, the connection relationship between nodes is established to form an initial topological graph; and the interference source is added to the topological graph, and the interference source parameters are set.

[0085] Specifically, when the chip physical structure is digitized, each pin (power pin, ground pin and signal pin) is mapped as a node in the topological network, and each node contains the following attributes: node ID, node type, physical position coordinates and functional attributes. For example, a power pin node can be represented as {ID: "P1", Type: "power_pin", Position: [2.5, 3.7], Attributes: {Voltage: 3.3V}}.

[0086] In the domain division process, based on the functional blocks of the chip, the nodes are divided into three categories: power domain, ground domain and signal domain. Preferably, the power domain contains all power pins and their directly connected internal nodes; the ground domain contains all ground pins and their directly connected internal nodes; and the signal domain contains all signal pins and related signal processing nodes.

[0087] When the connection relationship is established, the connection mode and strength between nodes are determined according to the chip design specification. In this embodiment, the connection relationship can be represented as a matrix, where the matrix elements represent the strength or characteristics of the connection between nodes. For example, for a network with n nodes, the connection matrix C is an n x n matrix, and the element C[i,j] represents the strength of the connection between node i and node j. When two nodes are directly connected, C[i,j] takes the value of the inverse of the connection resistance; when two nodes are not directly connected, C[i,j] is 0.

[0088] When the interference source parameters are set, the chip's rated voltage range and interference distance are configured. Preferably, for a chip with a rated operating voltage of 3.3V, the interference source voltage can be set to ±10% of the rated voltage, i.e. 3.0V to 3.6V; the interference distance can be set to 2 to 5 times the minimum distance between pins, which is usually effective in simulating electromagnetic interference in actual application environments.

[0089] In an embodiment of the present application, the interference path construction process includes three key steps, forming three groups of test structures.

[0090] First, connect the power pins of the chip to the first analog ground pin and the ground pins of the chip to the second analog ground pin to form the first group of test structures. This structure establishes the basic test environment for the chip power system. For example, for a chip with 4 power pins and 4 ground pins, all power pins can be connected in parallel to the first analog ground, and all ground pins can be connected in parallel to the second analog ground.

[0091] Secondly, select the continuous position points with the highest connectivity from all the first analog ground pins, and connect these positions together to form the first interference path. Preferably, the connectivity can be measured by the degree of the node (the number of edges directly connected to it). For example, for the nodes with a degree value exceeding 50% of the average degree value, they can be preferentially considered for inclusion in the interference path. Based on the first interference path, connect the signal pins together to form the second group of test structures.

[0092] Finally, select the continuous position points with the highest interference propagation efficiency from all the second analog ground pins, and connect these positions together to form the second interference path. Preferably, the interference propagation efficiency can be determined by path analysis, and the pins located near the main path of signal transmission have a higher interference propagation efficiency. Based on the second interference path, connect the first signal pins to the second interference path to form the third group of test structures.

[0093] In practical applications, for a typical microcontroller chip, there can be about 20 first analog ground pins and 20 second analog ground pins. Preferably, 5-8 consecutive pins can be selected to form an interference path, which can ensure sufficient interference coverage and will not cause excessive interference to affect the test accuracy.

[0094] This step mainly includes determining the initial current distribution according to the theoretical current value of the chip, calculating the voltage drop by measuring the voltage value, and determining the test current value.

[0095] First, extract the theoretical current value from the chip specification parameters as the edge weight of the topology network to construct the initial current distribution model. The theoretical current value is different for different types of chips. For example, the working current of a low-power microcontroller is usually in the range of several milliamperes to several tens of milliamperes, while a high-performance processor can reach several amperes. In this embodiment, for a typical 3.3V powered microcontroller, the static working current can be taken as 10mA as the reference value.

[0096] Next, obtain the voltage values of each signal pin in the topology network interference model. This process can be completed by simulation or actual measurement. For the simulation method, the following voltage distribution function can be used:

[0097] ,

[0098] Wherein: is the voltage value of node i, in volts (V); is the reference voltage value, usually the power supply voltage, in volts (V); is the connection weight between node i and node j, representing the connection strength, dimensionless; is the voltage value of node j, in volts (V); is the total number of nodes in the network; For the sum variable, the range is from 1 to n. The formula calculates the node voltage by weighted average, and the weight reflects the influence degree of the connection between nodes.

[0099] According to the voltage value of the signal pin and the voltage value of the power pin, the voltage drop value of the chip is calculated. The voltage drop value calculation formula is:

[0100] ,

[0101] Wherein: is the voltage drop value, unit: volt (V); is the voltage value of the power pin, unit: volt (V); is the voltage value of the signal pin, unit: volt (V). The voltage drop value reflects the loss of the power voltage in the transmission process, which is an important parameter for evaluating the electrical performance of the chip.

[0102] Based on the connection relationship of the voltage drop value and the topology network, the distribution of the current in the network is calculated. The current distribution can be calculated by the following formula:

[0103] ,

[0104] Wherein: is the current flowing from node i to node j, unit: ampere (A); is the voltage difference between node i and node j, unit: volt (V); is the equivalent resistance between node i and node j, unit: ohm (Ω). The formula is based on Ohm's law and is used to calculate the current size on each connection path in the network.

[0105] In a preferred embodiment of the present application, it also includes evaluating the balance degree of the current distribution, identifying the abnormal points and singular regions in the current distribution. The balance degree of the current distribution can be calculated by the following formula:

[0106] ,

[0107] Wherein: Balance is the balance index, the value range is 0 to 1, the larger the value, the more balanced the distribution, and the unit is dimensionless; is the standard deviation of the current distribution, unit: ampere (A); is the average value of the current distribution, unit: ampere (A). Preferably, when the Balance value is less than 0.7, it indicates that the current distribution is unbalanced and needs to be adjusted. The standard deviation is obtained by summing the square of the difference between the current of each node and the average current and taking the average, which reflects the dispersion degree of the current distribution.

[0108] Finally, according to the abnormal points and singular regions, the test current values of each test structure are determined, and the corresponding current values are added to the corresponding positions of each test structure in the topological network interference model. For example, for the detected high current density region, the test current value can be increased by 50% to enhance the test strength; for the low current density region, the original current value can be maintained or slightly reduced.

[0109] The process of performing the interference simulation test includes setting interference simulation parameters, performing electromagnetic interference simulation, obtaining response results, extracting key indicators, and comparing with preset conditions.

[0110] First, the interference simulation parameters are set, including the type of interference source, interference strength, interference frequency and duration. In this embodiment, the preferred types of interference sources include pulse interference, sinusoidal interference and white noise interference. The interference strength is usually set to ±10% to ±30% of the rated voltage of the chip, the interference frequency range can be from DC to 5 times the working frequency of the chip, and the duration varies from microseconds to milliseconds. For example, for a chip with a working frequency of 100 MHz, the interference frequency can be set to DC to 500 MHz, and the interference duration can be set to 10 μs.

[0111] Next, electromagnetic interference simulation is performed in the topological network interference model. The simulation process uses a combination of time domain and frequency domain methods to capture the response characteristics of the chip under different interference conditions. Time domain simulation can observe the response of the chip to transient interference, and frequency domain simulation can help analyze the sensitivity of the chip under different frequency interference.

[0112] After obtaining the response results of the topological network interference model, key indicators such as interference response sensitivity, result consistency, coverage completeness and screening accuracy are extracted. Among them, the interference response sensitivity reflects the sensitivity of the chip to interference, which can be calculated by the following formula:

[0113] ,

[0114] Where Sensitivity is the interference response sensitivity, expressed in percentage (%); ΔPerformance is the chip performance change, which can be the change in voltage, current or functional parameter, and the unit is determined by the specific parameter; ΔInterference is the interference strength change, usually expressed in voltage or current change, and the unit is accordingly in volts (V) or amperes (A). Preferably, the Sensitivity value is suitable within the range of 5% to 20%, too low indicating that the test is not sensitive, and too high indicating that the chip has poor anti-interference ability.

[0115] The result consistency reflects the stability of the repeated test results, which can be calculated by the coefficient of variation:

[0116] ,

[0117] Consistency is the result consistency, unit is percentage (%); is the standard deviation of repeated test results, unit depends on test parameters; is the average value of repeated test results, unit is the same as . Preferably, Consistency value should not be lower than 95%, indicating that the test results have good repeatability. The standard deviation is obtained by summing the square of the difference between multiple test results and the average value and taking the average, reflecting the stability of the test results.

[0118] Coverage reflects the degree of coverage of the test on the chip function, which can be represented as:

[0119] ,

[0120] Coverage is the coverage integrity, unit is percentage (%); is the number of tested function points, unit is piece; is the total number of chip function points, unit is piece. Preferably, Coverage value should not be lower than 90%, ensuring the comprehensiveness of the test. Function point refers to the basic unit of chip function characteristics, which can be a function module, signal path or specific operation.

[0121] Screening accuracy reflects the accuracy of the screening results, which can be represented as:

[0122] ,

[0123] Accuracy is the screening accuracy, unit is percentage (%); is the true positive (correctly identified as qualified chip), unit is piece; is the true negative (correctly identified as unqualified chip), unit is piece; is the false positive (incorrectly identified as qualified chip), unit is piece; is the false negative (incorrectly identified as unqualified chip), unit is piece. Preferably, Accuracy value should not be lower than 97%, ensuring the reliability of the screening results. Finally, compare the key indicators with the preset conditions. The preset conditions usually include interference response sensitivity higher than 95%, result consistency higher than 98%, coverage integrity higher than 90%, and screening accuracy higher than 97%. Only when all indicators meet the preset conditions, proceed to the next step; otherwise, adjust the model parameters and execute the simulation again.

[0124]

[0125] ​When the simulation results meet the preset conditions, the application adopts a dynamic adjustment mechanism to optimize the topology network interference model. This process includes analyzing the simulation results, determining the key adjustment parameters, generating the adjustment scheme, executing the incremental adjustment, verifying the adjustment effect, and finally confirming the optimized model.

[0126] First, analyze the simulation results and identify areas that need optimization. These areas are usually characterized by uneven interference response, incomplete coverage, or unstable test results. For example, through heat map analysis, hot and cold spots of interference response can be visually discovered, which are often the areas that need to be optimized.

[0127] Next, determine the key adjustment parameters, including the distance between test structures, connection relationships, and functional domain boundaries. In addition, consider topological characteristic parameters such as node centrality, clustering coefficient, path complexity, and network entropy. The node centrality is used to evaluate the importance of a node in the network and can be calculated by the following formula:

[0128] ,

[0129] Where: is the centrality of node i, representing the number of connections of node i with other nodes, with units of pieces; is the adjacency matrix element, which is 1 when node i and node j are connected, otherwise 0, dimensionless; is the total number of nodes in the network, with units of pieces; is the summation variable, ranging from 1 to n. Preferably, nodes with high centrality (usually the top 20% of nodes in terms of network centrality value) should be given more attention because they have a greater impact on the overall performance of the network.

[0130] The clustering coefficient is used to evaluate the clustering degree of a node and can be represented as:

[0131] ,

[0132] Where: is the clustering coefficient of node i, representing the tightness of connections between the neighbors of node i, with a value range of 0 to 1, dimensionless; is the number of edges between the neighbors of node i, with units of pieces; is the degree of node i (the number of nodes directly connected to it), with units of pieces. Preferably, for areas with high clustering coefficients (usually areas with , the density of test structures should be appropriately increased to better capture the characteristics of interference propagation. The clustering coefficient reflects the tightness of local connections in the network, and the higher the value, the tighter the subnetwork formed around the node.

[0133] Path complexity is used to evaluate the characteristics of the interference propagation path and can be calculated by the average path length:

[0134] ,

[0135] wherein: is the average path length, representing the average shortest path length between any two nodes in the network, with the unit of hop; is the shortest path length between node i and node j, with the unit of hop; is the total number of nodes in the network, with the unit of individual; and is the node index, representing different nodes. Preferably, for networks with longer average path length (e.g. networks with more than 1000 nodes), test points should be added on the critical path to ensure continuous monitoring of interference propagation. The average path length reflects the overall connection efficiency of the network, and the smaller the value, the more efficient the network connection.

[0136] Network entropy is used to evaluate the determinacy and stability of the topology network, which can be represented as:

[0137] ,

[0138] wherein: is the network entropy, representing the uncertainty of the network structure, with the unit of bit; is the normalized centrality of node i (the centrality of node i divided by the sum of the centrality of all nodes), dimensionless; is the total number of nodes in the network, with the unit of individual; is the node index, ranging from 1 to n. Preferably, the network entropy value is low (usually less than 0.5 bit), which indicates that the network structure is more certain and stable, and is conducive to obtaining reliable test results. Network entropy is a concept in information theory, which is used to measure the uncertainty of a system, and is applied here to evaluate the complexity of the network structure.

[0139] Based on the above parameter analysis, a topology structure adjustment scheme is generated. In this embodiment, the adjustment scheme mainly includes three aspects: one is to adjust the distance between test structures, two is to optimize the connection relationship between nodes, and three is to redivide the functional domain boundary. Preferably, the distance adjustment range between test structures is ±30% of the original distance; the connection relationship optimization mainly considers increasing the connection degree of critical nodes or removing redundant connections; the functional domain boundary adjustment is based on the interference propagation characteristics, which may involve reassigning certain nodes from one domain to another domain.

[0140] ​​Next, the distances and connection relationships between the test structures in the topological network interference model are adjusted step by step according to the adjustment scheme. An incremental adjustment strategy is adopted, and the adjustment range is controlled within a small range (e.g. 5% to 10%) each time to avoid instability caused by excessive adjustment. After each adjustment, a quick verification simulation is performed to evaluate the adjustment effect.

[0141] Finally, when the performance improvement is lower than the preset threshold (usually 1% to 3%), the final optimized test model is confirmed. At this time, the model has reached a relatively stable state, and further adjustment will not bring obvious benefits, so the optimization process can be terminated.

[0142] Based on the optimized test model, the chip batch screening process is performed. This process includes setting batch test parameters, connecting the chips to be tested, performing interference tests, collecting test data, evaluating anti-interference performance, and classifying the chips.

[0143] First, according to the optimized test model, the batch test parameters are set. These parameters include test voltage, current range, interference strength, frequency range, test duration, etc. Preferably, the test voltage is set to the chip rated voltage ±5%, the current range covers 50% to 150% of the typical working current of the chip, the interference strength is ±20% of the rated voltage, the frequency range is from DC to 3 times the working frequency of the chip, and the test duration is 50ms to 200ms for each test point.

[0144] Next, multiple chips to be tested are connected in parallel to the test equipment. Preferably, for small chips (such as 8-pin to 64-pin), 16 to 32 chips can be tested simultaneously; for medium-sized chips (such as 64-pin to 256-pin), 8 to 16 chips can be tested simultaneously; for large chips (more than 256 pins), 4 to 8 chips can be tested simultaneously. Parallel testing can significantly improve screening efficiency.

[0145] According to the test structures and parameters in the optimized test model, interference tests are performed on the chips to be tested. During the test, different types and intensities of interference signals are applied in the preset order, and the responses of the chips are recorded. Preferably, the test order is usually arranged from low to high in terms of interference sensitivity, with relatively mild tests first and then higher intensity tests to avoid permanent damage to the chips at the initial stage.

[0146] The test data of each chip is collected, including voltage response, current distribution, and signal integrity. Voltage response reflects the voltage stability of the chip under interference, current distribution reflects the changes in the internal current path of the chip, and signal integrity reflects the degree of normal function of the chip. These data are usually recorded and displayed in the form of waveforms, numerical tables, or heat maps, etc.

[0147] Based on the preset screening threshold, the anti-electric interference performance of each chip is evaluated. The screening threshold is usually based on the following aspects: first, voltage stability, which requires that the voltage fluctuation under interference conditions does not exceed ±10% of the rated voltage; second, current stability, which requires that the current fluctuation under interference conditions does not exceed ±20% of the typical value; third, functional integrity, which requires that the key functions operate normally under interference conditions. The specific threshold can be adjusted according to the chip application scenario and reliability requirements.

[0148] Finally, the chips that meet the anti-electric interference performance requirements are marked as qualified, and the chips that do not meet the requirements are marked as unqualified. Preferably, the chips can also be further divided into high-performance, standard-performance and low-performance categories according to the performance difference, which are respectively used for different application scenarios with different requirements. For example, high-performance chips (anti-interference performance exceeds the requirement by more than 20%) can be used for critical safety systems; standard-performance chips (anti-interference performance meets the requirement) can be used for ordinary industrial applications; low-performance chips (anti-interference performance is slightly lower than the requirement but within an acceptable range) can be used for non-critical consumer electronics products.

[0149] As shown in Figure 2 The present application also provides a test screening system for enhancing the anti-electric interference performance of chips, which includes a topology network construction module 1, an interference path construction module 2, a current distribution module 3, a simulation execution module 4, a topology optimization module 5 and a chip screening module 6.

[0150] The topology network construction module 1 is used to establish a topology network interference model, which includes the topology connection relationship of the power pin, ground pin and signal pin of the chip, as well as the interference source parameters. The interference source parameters are set according to the rated voltage range of the chip and the interference distance. Preferably, the topology network construction module 1 contains a node mapping unit, a domain division unit and a connection relationship establishment unit, which are respectively responsible for the digital conversion of the physical structure of the chip, the function domain division and the establishment of the connection relationship between nodes.

[0151] The interference path construction module 2 is used to construct the interference path, which includes three key functions: first, connecting the power pin of the chip with the first analog ground pin and connecting the ground pin of the chip with the second analog ground pin to form the first test structure; second, selecting a group of continuous positions from all the first analog ground pins and connecting them together to form the first interference path, and connecting the signal pins together based on the path to form the second test structure; third, selecting a group of continuous positions from all the second analog ground pins and connecting them together to form the second interference path, and connecting the first signal pin with the second interference path based on the path to form the third test structure.

[0152] The current distribution module 3 is used to obtain current distribution parameters, and its functions include: determining the initial current value of each node in the topology network interference model according to the theoretical current value of the chip; obtaining the voltage value of each signal pin in the model, and calculating the voltage drop value of the chip according to the voltage values of the signal pins and the power pins; determining the test current value of each test structure based on the voltage drop value, and adding the corresponding current value to the corresponding position of each test structure in the model. Preferably, the current distribution module 3 further comprises a current balance evaluation unit for analyzing the uniformity of current distribution and identifying abnormal areas.

[0153] The simulation execution module 4 is used to perform interference simulation tests to obtain simulation results of the topology network interference model. This module is responsible for setting interference simulation parameters, performing electromagnetic interference simulation, obtaining response results, extracting key indicators, and comparing with preset conditions. Preferably, the simulation execution module 4 supports a simulation method combining time domain and frequency domain to comprehensively capture the response characteristics of the chip under different interference conditions.

[0154] The topology optimization module 5 is used to dynamically adjust the distances between each test structure in the topology network interference model when the simulation results meet the preset conditions to form an optimized test model. This module analyzes the simulation results, determines the key adjustment parameters, generates a topology structure adjustment scheme, performs incremental adjustment, verifies the adjustment effect, and finally confirms the optimized model. Preferably, the topology optimization module 5 adopts an iterative optimization strategy to perform rapid verification simulation after each adjustment to gradually approach the optimal solution.

[0155] The chip screening module 6 is used to perform batch screening of chips according to the simulation results of the optimized test model. This module sets batch test parameters, controls the parallel testing of multiple chips to be tested, performs interference tests in a predetermined order, collects test data of each chip, evaluates the anti-interference performance, and classifies the chips. Preferably, the chip screening module 6 has high automation and parallel processing capabilities, which can significantly improve the efficiency of batch screening.

[0156] The above modules can be realized in a combination of software and hardware. The software part includes topology analysis algorithms, current distribution optimization algorithms, simulation control programs, and data processing programs; the hardware part includes high-performance computing servers, automatic test equipment, and data acquisition systems. These modules work together to form a complete chip anti-electric interference test and screening system.

[0157] In the preferred embodiment of the present application, the collected data includes the following categories: voltage data for evaluating the voltage stability of the chip under interference conditions, with a typical sampling rate of 10MHz to 100MHz; current data for analyzing the internal current distribution changes of the chip, with a sampling rate of 1MHz to 10MHz; signal integrity data for detecting signal transmission quality, including parameters such as rise / fall time, overshoot / undershoot, etc.; functional response data for verifying the normality of the chip under interference, usually achieved through specific test vectors; temperature data for monitoring the thermal behavior of the chip during testing, with a sampling rate of 10Hz to 100Hz. All data is normalized and stored uniformly to ensure that data from different sources and with different dimensions can be comprehensively analyzed.

[0158] In practical applications, the present system can be widely used for anti-electric interference testing and screening of various integrated circuits, especially in fields with high reliability requirements such as automotive electronics, medical devices, aerospace, etc. Through the present system, the testing accuracy and screening efficiency of the chip's anti-electric interference capability can be significantly improved, providing strong support for quality control and reliability assurance of chips.

[0159] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A test and screening method for enhancing chip immunity to electrical interference, characterized in that, include: A topology network interference model is established, which includes the topological connection relationship of the chip's power supply pins, ground pins and signal pins, as well as interference source parameters. The interference source parameters are set according to the chip's rated voltage range and interference distance. Constructing interference pathways, including: Connect the power supply pin of the chip to the first analog ground pin, and connect the ground pin of the chip to the second analog ground pin to form the first test structure; Select a set of consecutive locations from all the first analog ground pins, connect the consecutive locations together to form a first interference path, and connect the signal pins together based on the first interference path to form a second set of test structures; Select a set of consecutive positions from all the second analog ground pins, connect the consecutive positions together to form a second interference path, and connect the first signal pin to the second interference path based on the second interference path to form a third set of test structures; Obtain current distribution parameters, including: Based on the theoretical current value of the chip, determine the initial current value of each node in the topology network interference model; Obtain the voltage values ​​of each signal pin in the interference model of the topology network, and calculate the voltage drop of the chip based on the voltage values ​​of the signal pins and the voltage values ​​of the power supply pins; Based on the voltage drop value, the test current value of each test structure is determined, and the corresponding current value is added to the corresponding position of each test structure in the topology network interference model. Perform interference simulation tests to obtain the simulation results of the interference model of the topology network; When the simulation results meet the preset conditions, the distance between each test structure in the topology network interference model is dynamically adjusted to form an optimized test model. Based on the simulation results of the optimized test model, a batch screening of chips is performed.

2. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The steps for establishing the topology network interference model specifically include: The physical structure of the chip is converted into a set of digital nodes, with each pin mapped to a node in the topology network; Based on the functional blocks of the chip, the node is divided into a power domain, a ground domain, and a signal domain; Based on the chip's design specifications, establish the connections between nodes to form an initial topology graph; An interference source is added to the initial topology diagram, and the parameters of the interference source are set according to the rated voltage range of the chip and the interference distance.

3. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The steps for constructing the interference pathway specifically include: Select consecutive locations with the highest connectivity from the first analog ground pin to form the first interference path; Cluster analysis is performed on the signal pins to identify sets of nodes sensitive to interference; Based on the set of nodes sensitive to interference, the second set of test structures is constructed, and the signal pins are connected together; Select consecutive locations with the highest interference propagation efficiency from the second analog ground pins to form the second interference path; The first signal pin is connected to the second interference path to form the third set of test structures.

4. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The steps for obtaining the current distribution parameters specifically include: The theoretical current value is extracted from the chip's specifications. The theoretical current values ​​are used as edge weights of the topology network to construct an initial current distribution model; Obtain the voltage values ​​of each signal pin in the interference model of the topology network; Calculate the voltage drop of the chip based on the voltage values ​​of the signal pin and the power supply pin; Based on the voltage drop value and the connection relationship of the topology network, the current distribution in the network is calculated; Assess the uniformity of current distribution and identify anomalies and singular regions in the current distribution; Based on the anomalies and singular regions, determine the test current value for each test structure.

5. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The specific steps for performing the interference simulation test include: Set the interference simulation parameters, including interference source type, interference intensity, interference frequency, and duration; Perform electromagnetic interference simulation in the aforementioned topology network interference model; Obtain the response results of the interference model of the topology network; Extract key indicators such as interference response sensitivity, result consistency, coverage integrity, and screening accuracy; The key indicators are compared with preset conditions.

6. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The steps for dynamically adjusting the topology network interference model specifically include: Analyze the simulation results to identify areas that need optimization; Identify key adjustment parameters, including the distance between test structures, connection relationships, and functional domain boundaries; Generate a topology adjustment scheme; According to the adjustment scheme, the distances between the test structures in the topology network interference model are gradually adjusted; Verify the performance of the adjusted model; When the performance improvement is less than the preset threshold, confirm the final optimized test model.

7. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The step of performing batch chip screening based on the simulation results of the optimized test model specifically includes: Based on the optimized test model, set the batch test parameters; Connect multiple chips under test to the test equipment in parallel; Interference tests were performed on the multiple chips under test according to the test structure and parameters in the optimized test model. Collect test data for each chip, including voltage response, current distribution, and signal integrity; Based on preset screening thresholds, the anti-electrical interference performance of each chip is evaluated; Chips that meet the requirements for anti-electrical interference performance are marked as qualified, and chips that do not meet the requirements are marked as unqualified.

8. The test and screening method for enhancing chip immunity to electrical interference according to claim 5, characterized in that, The preset conditions include: Interference response sensitivity is higher than 95%; The consistency rate of the results was higher than 98%; Coverage integrity is higher than 90%; The screening accuracy rate is higher than 97%.

9. The test and screening method for enhancing chip immunity to electrical interference according to claim 6, characterized in that, The key adjustment parameters also include: Node centrality is used to evaluate the importance of a node in a network. Clustering coefficient, used to evaluate the degree of clustering of nodes; Path complexity is used to evaluate the characteristics of interference propagation paths; Network entropy is used to evaluate the determinism and stability of a network topology.

10. A test and screening system for enhancing chip immunity to electrical interference, used to implement the test and screening method for enhancing chip immunity to electrical interference as described in any one of claims 1-9, characterized in that, include: The topology network construction module is used to establish a topology network interference model. The topology network interference model includes the topology connection relationship of the chip's power supply pins, ground pins and signal pins, as well as interference source parameters. The interference source parameters are set according to the chip's rated voltage range and interference distance. An interference path construction module is used to construct interference paths, including: connecting the power supply pin of the chip to a first analog ground pin, and connecting the ground pin of the chip to a second analog ground pin to form a first set of test structures; selecting a set of consecutive positions from all the first analog ground pins, connecting the consecutive positions together to form a first interference path, and connecting signal pins together based on the first interference path to form a second set of test structures; selecting a set of consecutive positions from all the second analog ground pins, connecting the consecutive positions together to form a second interference path, and connecting a first signal pin to the second interference path based on the second interference path to form a third set of test structures; The current distribution module is used to acquire current distribution parameters, including: determining the initial current value of each node in the topology network interference model based on the theoretical current value of the chip; acquiring the voltage value of each signal pin in the topology network interference model, and calculating the voltage drop value of the chip based on the voltage values ​​of the signal pins and the voltage values ​​of the power supply pins; determining the test current value of each test structure based on the voltage drop value, and adding the corresponding current value at the corresponding position of each test structure in the topology network interference model; The simulation execution module is used to perform interference simulation tests and obtain the simulation results of the interference model of the topology network. The topology optimization module is used to dynamically adjust the distance between each test structure in the topology network interference model when the simulation results meet preset conditions, so as to form an optimized test model. The chip screening module is used to perform batch chip screening based on the simulation results of the optimized test model.

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