Positioning mark and forming method thereof
By forming staggered openings on the hard mask layer of the positioning marking area, the problem of abnormal material contours under the hard mask layer caused by multiple etchings is solved, thereby improving the product yield of integrated circuit manufacturing.
Patent Information
- Application Number
- CN202511785764.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-02-27
AI Technical Summary
In the integrated circuit manufacturing process, repeated etching of the hard mask layer for positioning marks can cause abnormal contours of the underlying polysilicon layer, affecting product yield.
Multiple staggered openings are formed on the hard mask layer of the positioning mark area to avoid repeated etching at the same location. Positioning marks at different locations are used to meet the requirements of the patterning process and avoid the exposure of the underlying material caused by multiple etchings.
This improved product yield and avoided the problem of abnormal material contours under the hard mask layer caused by multiple etching processes.
Smart Images
Figure CN121586479A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit manufacturing technology, and in particular to a positioning mark and a method for forming the same. Background Technology
[0002] In the integrated circuit manufacturing process, the wafer is divided into multiple exposure areas (shots), and the areas between these exposure areas are dicing tracks. For example... Figure 1 As shown, a locking corner (LC) region is provided on the scribe line area 102. The LC region is used to form positioning marks 103, which are located at the four corners of the exposure area 101. The positioning marks 103 are used to locate the origin of the exposure coordinates. Currently, for the process requirements of the exposure area (i.e., the device area), the LC region where the positioning marks are located is exposed during each photolithography process, and multiple etching processes are performed on the hard mask layer. After multiple etching processes, the hard mask layer in the area where the positioning marks 103 are located will expose the polysilicon layer underneath. Specifically, as shown... Figure 2A As shown, a polysilicon layer 120 is formed on the exposure region 101 and the scribe line region 102 of the semiconductor substrate 100. A hard mask layer 110 is formed on the polysilicon layer 120. The hard mask layer 110 on the scribe line region 102 is used to form positioning marks 103. Figure 2B As shown, during the first photolithography and etching process, a first partial pattern is formed on the hard mask layer 110 of the exposure area 101, and a positioning mark pattern is formed on the hard mask layer 110 of the dicing area 102. Figure 2C As shown, during the second photolithography and etching process, a second pattern is formed on the hard mask layer 110 of the exposure region 101, while the hard mask layer 110 of the dicing region 102 is further degraded. Figure 2D As shown, during the third photolithography and etching process, a third part of the pattern is formed on the hard mask layer 110 in the exposure area 101. The hard mask layer 110 in the dicing area 102 is etched again, even exposing the polysilicon layer 120 underneath. After multiple etching processes, the sidewalls of the polysilicon layer 120 become less smooth, for example, depressions or undercuts occur, forming abnormal polysilicon contours. In particular, the adhesion of the undercut area is poor. In subsequent photolithography processes, the photoresist will flow into the undercut area, causing the concentrated stress during development to cause the photoresist to peel off, affecting the product yield. Summary of the Invention
[0003] This application provides a method for forming positioning marks to avoid abnormal material contours under the hard mask layer, which is beneficial to improving product yield.
[0004] According to some embodiments of this application, one aspect of this application provides a method for forming a positioning mark, including:
[0005] The semiconductor substrate includes an exposure region and a scribe lane region, and a hard mask layer is formed on the exposure region and the scribe lane region, and the scribe lane region has a positioning mark area; a first lithography process and a first etching process are performed on the hard mask layer of the exposure region and the positioning mark area, and a first opening is formed on the hard mask layer of the positioning mark area; a second lithography process and a second etching process are performed on the hard mask layer of the exposure region and the positioning mark area, and a second opening is formed on the hard mask layer of the positioning mark area, the second opening is staggered with the first opening, and the depths of the first opening and the second opening are both less than the thickness of the hard mask layer, and the first opening and the second opening are used as positioning marks.
[0006] Further, in the positioning mark forming method, the depths of the first opening and the second opening are the same.
[0007] Further, in the positioning mark forming method, the widths of the first opening and the second opening are the same.
[0008] Further, in the positioning mark forming method, the cross-sectional shape of the first opening and the second opening is L-shaped or cross-shaped.
[0009] Further, in the positioning mark forming method, the longitudinal cross-sectional shape of the first opening and the second opening is rectangular.
[0010] Further, in the positioning mark forming method, it further includes:
[0011] A third lithography process and a third etching process are performed on the hard mask layer of the exposure region and the positioning mark area, and a third opening is formed on the hard mask layer of the positioning mark area, the third opening is staggered with the first opening and the second opening, and the depth of the third opening is less than the thickness of the hard mask layer.
[0012] Further, in the positioning mark forming method, the depths of the third opening, the first opening and the second opening are the same, and the widths of the third opening, the first opening and the second opening are the same.
[0013] Further, in the positioning mark forming method, the cross-sectional shape of the third opening is L-shaped or cross-shaped.
[0014] Further, in the positioning mark forming method, a polysilicon layer is formed on the exposure region and the scribe lane region, and the hard mask layer covers the polysilicon layer.
[0015] Further, in the positioning mark forming method, silicon dioxide is used as a filling material between the polysilicon layers.
[0016] According to some embodiments of the present application, the present application provides a positioning mark in one aspect, which is formed by any of the above methods.
[0017] The technical scheme provided by the embodiments of the present application has at least the following advantages: the first photoetching process and the first etching process are performed on the hard mask layer of the exposure area and the positioning mark area to form a first opening on the hard mask layer of the positioning mark area; the second photoetching process and the second etching process are performed on the hard mask layer of the exposure area and the positioning mark area to form a second opening on the hard mask layer of the positioning mark area, the second opening is staggered with the first opening in position, and the depths of the first opening and the second opening are both less than the thickness of the hard mask layer, the first opening and the second opening are used as positioning marks, in this way, the etching process is performed on different positions of the positioning marks on the same hard mask layer each time, the positioning marks at different positions are used to meet the positioning requirements in the patterning process, it is not necessary to repeatedly etch the same position of the hard mask layer, which avoids exposing the underlying material after multiple etching of the hard mask layer, and further avoids the profile abnormality of the underlying material caused by multiple etching, which is beneficial to improving the product yield. BRIEF DESCRIPTION OF DRAWINGS
[0018] One or more embodiments are illustrated by way of example in the drawings that are for illustrative purposes only, and not for the purposes of limitation of the embodiments, unless otherwise explicitly stated herein, the drawings in the drawings are not to scale; in order to more clearly illustrate the technical schemes in the embodiments of the present application or in the prior art, the drawings needed to be used in the embodiments will be briefly introduced below, obviously, the drawings in the following description can obtain other drawings without the premise of creating labor for those skilled in the art.
[0019] Figure 1 is a top view of a positioning mark area in the related art;
[0020] Figures 2A-2D is a cross-sectional schematic view of each step of the forming method of the positioning mark in the related art;
[0021] Figure 3 is a flowchart of the forming method of the positioning mark in the embodiments of the present application;
[0022] Figure 4 is a cross-sectional schematic view of the semiconductor substrate in the forming process of the positioning mark in the embodiments of the present application;
[0023] Figure 5 is a top view of a positioning mark area in the embodiments of the present application;
[0024] Figures 6A-6B is a cross-sectional schematic view of each step after the two photoetching processes and etching processes in the forming process of the positioning mark in the embodiments of the present application;
[0025] Figure 7 A top view of the semiconductor substrate after the second photoetching process and etching process in the forming process of the positioning mark of the embodiment of the present application;
[0026] Figure 8 A cross-sectional view after the third photoetching process and etching process in the forming process of the positioning mark of the embodiment of the present application;
[0027] Figure 9 A top view of the semiconductor substrate after the second photoetching process and etching process in the forming process of the positioning mark of the embodiment of the present application.
[0028] BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figures 1-2D In the figure, 100 is a semiconductor substrate, 101 is an exposure area, 102 is a scribe lane area, 103 is a positioning mark, 110 is a hard mask layer, and 120 is a polysilicon layer.
[0030] Figures 4-9 In the figure, 200 is a semiconductor substrate, 201 is an exposure area, 202 is a scribe lane area, 203 is a positioning mark area, 210 is a hard mask layer, and 220 is a polysilicon layer. DETAILED DESCRIPTION
[0031] The embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present application, many technical details are presented in order to make the reader better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0032] In the description of the embodiments of the present application, if technical terms contain “first” “second”, the technical terms “first” “second” and the like are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of “multiple” is more than two, unless otherwise explicitly and specifically limited. Similarly, “multiple groups” means more than two groups (including two groups), and “multiple pieces” means more than two pieces (including two pieces).
[0033] In this document, the reference to “embodiments” means that the specific features, structures or properties described in connection with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.
[0034] In the description of the embodiments of the present application, the term "and / or" is merely an association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of existence of A, existence of A and B, and existence of B. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.
[0035] Figure 3 A flowchart of a forming method of a positioning mark in an embodiment of the present application. The forming method of the positioning mark provided by the embodiment of the present application includes:
[0036] S11: providing a semiconductor substrate, the semiconductor substrate including an exposure area and a scribe lane area, the exposure area and the scribe lane area being formed with a hard mask layer, and the scribe lane area having a positioning mark area;
[0037] S12: performing a first lithography process and a first etching process on the hard mask layer of the exposure area and the positioning mark area, and forming a first opening on the hard mask layer of the positioning mark area;
[0038] S13: performing a second lithography process and a second etching process on the hard mask layer of the exposure area and the positioning mark area, and forming a second opening on the hard mask layer of the positioning mark area, the second opening being staggered with the first opening in position, and the depths of the first opening and the second opening both being less than the thickness of the hard mask layer, the first opening and the second opening being used as the positioning mark.
[0039] In this way, the positioning mark is etched at different positions on the same hard mask layer after each lithography process and etching process, the positioning marks at different positions are used to meet the positioning requirements in the patterning process, and it is not necessary to repeatedly etch at the same position of the hard mask layer, so that the exposure of the underlying material after multiple etching of the hard mask layer is avoided, and the profile abnormality problem of the underlying material caused by multiple etching is avoided, and the product yield is improved.
[0040] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.
[0041] As shown in FIG. 1, Figure 4 In step S11, a semiconductor substrate 200 is provided, the semiconductor substrate 200 including an exposure area 201 and a scribe lane area 202. In combination with FIG. 2, Figure 5As shown, the scribe lane region 202 has a positioning mark region 203. The semiconductor substrate 200 can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, and can be a die, a wafer after an epitaxial growth process, an aluminum nitride substrate, an aluminum oxide substrate, etc. The exposure region 201 can be a device region for forming semiconductor devices. The scribe lane region 202 is a narrow, blank isolation region between the exposure regions on the wafer.
[0042] Optionally, a hard mask layer 210 is formed on the exposure region 201 and the scribe lane region 202. The hard mask layer 210 is, for example, a silicon nitride layer. A polysilicon layer 220 is formed on the hard mask layer 210.
[0043] In step S12, a first lithography process and a first etching process are performed on the hard mask layer 210 of the exposure region 201 and the positioning mark region 203. Figure 6A As shown, a first opening C1 is formed on the hard mask layer of the positioning mark region 203.
[0044] Specifically, the first lithography process is performed to form a first patterned photoresist layer, and the first etching process is performed to etch the hard mask layer 210 using the first patterned photoresist layer as a mask, to form a first part of the pattern on the hard mask layer 210 of the exposure region 201, and to form the first opening C1 on the hard mask layer 210 of the positioning mark region 203.
[0045] In step S13, a second lithography process and a second etching process are performed on the hard mask layer 210 of the exposure region 201 and the positioning mark region 203. Figure 6B As shown, a second opening C2 is formed on the hard mask layer 210 of the positioning mark region 203, the second opening C2 is offset from the first opening C1, and the depths of the first opening C1 and the second opening C2 are both less than the thickness of the hard mask layer 210, the first opening C1 and the second opening C2 are used as positioning marks.
[0046] Specifically, the second lithography process is performed to form a second patterned photoresist layer, and the second etching process is performed to etch the hard mask layer 210 using the second patterned photoresist layer as a mask, to form a second part of the pattern on the hard mask layer 210 of the exposure region 201, and to form the second opening C2 on the hard mask layer 210 of the positioning mark region 203.
[0047] In this embodiment, two photolithography and etching processes are performed to form two openings. After the second photolithography and etching processes, the final hard mask layer pattern is formed on the hard mask layer 210 of the exposure area 201. The final hard mask layer pattern is formed by superimposing the partial pattern etched by the first photolithography and etching processes and the partial pattern etched by the second photolithography and etching processes.
[0048] In this embodiment, the positioning mark formed by the first opening C1 and the second opening C2 is a trench, and the trench stops on the hard mask layer 210. Furthermore, the trenches formed by the first etching process and the second etching process have the same height and are staggered in position to avoid repeated etching of the same location on the hard mask layer 210. The positioning requirement is met by using a positioning mark composed of two openings, and there is no need to repeatedly etch at the same location on the hard mask layer 210. This avoids exposing the underlying material after multiple etchings of the hard mask layer, thereby preventing contour abnormalities in the underlying material due to multiple etchings and improving product yield.
[0049] like Figure 6B As shown, the first opening C1 and the second opening C2 have the same depth, and the first opening C1 and the second opening C2 have the same width. Figure 7 As shown, the cross-sectional shapes of the first opening C1 and the second opening C2 are L-shaped or cross-shaped. The cross-sectional shape, i.e., the top-view shape, refers to the cross-sectional shape parallel to the wafer surface. For example... Figure 6B As shown, the longitudinal cross-sectional shape of the first opening C1 and the second opening C2 is rectangular. The longitudinal cross-sectional shape, i.e. the side cross-sectional shape, refers to the cross-sectional shape perpendicular to the wafer surface.
[0050] In another embodiment, when the hard mask layer pattern can consist of three part patterns, three photolithography and etching processes are required. After the second etching process forms the second opening C2, a third photolithography and third etching process can be performed on the hard mask layer 210 of the exposure area 201 and the positioning mark area 203, as follows. Figure 8 As shown, a third opening C3 is formed on the hard mask layer 210 of the positioning mark area 203. The third opening is offset from the first opening C1 and the second opening C2, and the depth of the third opening C3 is less than the thickness of the hard mask layer 210.
[0051] Specifically, a third photolithography process is performed to form a third patterned photoresist. The third patterned photoresist is used as a mask to perform a third etching process to etch the hard mask layer 210, forming a third partial pattern on the hard mask layer 210 in the exposure area 201, and forming a third opening C3 on the hard mask layer 210 in the positioning mark area 203.
[0052] The third opening C3 has the same depth as the first opening C1 and the second opening C2, and the third opening C3 has the same width as the first opening C1 and the second opening C2. Further, the first opening C1, the second opening C2 and the third opening C3 have a rectangular longitudinal cross-sectional shape. The third opening has an L-shaped or cross-shaped transverse cross-sectional shape.
[0053] Further, the first opening C1, the second opening C2 and the third opening C3 are located at the four corners of the exposure region 101. Preferably, the openings of the first opening C1, the second opening C2 and the third opening C3 are oriented towards the same exposure region 201. Further, the adjacent spacing between the first opening C1, the second opening C2 and the third opening C3 is the same.
[0054] In an embodiment, different exposure parameters can be used in each lithography process.
[0055] The method for forming the positioning mark provided in the embodiment provides a semiconductor substrate, the semiconductor substrate includes an exposure region and a scribe lane region, a hard mask layer is formed on the exposure region and the scribe lane region, and the scribe lane region has a positioning mark area; a first lithography process and a first etching process are performed on the hard mask layer of the exposure region and the positioning mark area, and a first opening is formed on the hard mask layer of the positioning mark area; a second lithography process and a second etching process are performed on the hard mask layer of the exposure region and the positioning mark area, and a second opening is formed on the hard mask layer of the positioning mark area, the second opening is staggered with the first opening, and the depth of the first opening and the second opening is less than the thickness of the hard mask layer, and the first opening and the second opening are used as positioning marks. In this way, the etching process is performed on different positions of the positioning mark on the same hard mask layer each time, the positioning demand in the patterning process is met by using the positioning marks at different positions, the hard mask layer does not need to be etched repeatedly at the same position, the exposure of the underlying material caused by etching the hard mask layer multiple times is avoided, the profile abnormality of the underlying material caused by etching the hard mask layer multiple times is avoided, and the yield of products is improved.
[0056] The embodiment of the present application also provides a positioning mark formed by the method provided in the embodiment. The positioning mark is located on a scribe lane region 202 of a semiconductor substrate 200, and the positioning mark includes a first opening C1 and a second opening C2 formed on a hard mask layer 210, the second opening C1 is staggered with the first opening C2, and the depth of the first opening C1 and the second opening C2 is less than the thickness of the hard mask layer 210. The positioning mark provided in the embodiment is formed at different positions on the same hard mask layer, the positioning demand in the patterning process is met by using the positioning marks at different positions, the hard mask layer does not need to be etched repeatedly at the same position, the exposure of the underlying material caused by etching the hard mask layer multiple times is avoided, the profile abnormality of the underlying material caused by etching the hard mask layer multiple times is avoided, and the yield of products is improved.
[0057] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be limited by the scope defined by the claims.
Claims
1. A method of forming a positioning mark, characterized by, The method comprises: providing a semiconductor substrate, the semiconductor substrate comprising an exposure region and a scribe lane region, a hard mask layer being formed on the exposure region and the scribe lane region, the scribe lane region having a positioning mark region thereon; performing a first lithography process and a first etching process on the hard mask layer of the exposure region and the positioning mark region, a first opening being formed on the hard mask layer of the positioning mark region; performing a second lithography process and a second etching process on the hard mask layer of the exposure region and the positioning mark region, a second opening being formed on the hard mask layer of the positioning mark region, the second opening being positionally offset from the first opening, and the first opening and the second opening each having a depth less than a thickness of the hard mask layer, the first opening and the second opening being used as positioning marks.
2. The method of claim 1, wherein The first opening and the second opening have the same depth.
3. The method of claim 1, wherein The first opening and the second opening have the same width.
4. The method of claim 1, wherein The first opening and the second opening have an L-shaped or cross-shaped cross-sectional shape.
5. The method of claim 1, wherein The first opening and the second opening have a rectangular longitudinal cross-sectional shape.
6. The method of claim 1, wherein The method further comprises: performing a third lithography process and a third etching process on the hard mask layer of the exposure region and the positioning mark region, a third opening being formed on the hard mask layer of the positioning mark region, the third opening being positionally offset from the first opening and the second opening, and the third opening having a depth less than a thickness of the hard mask layer.
7. The method of claim 6, wherein The third opening has the same depth as the first opening and the second opening, and the third opening has the same width as the first opening and the second opening.
8. The method of claim 6, wherein The third opening has an L-shaped or cross-shaped cross-sectional shape.
9. The method of claim 1, wherein A polysilicon layer is formed on the exposure region and the scribe lane region, and the hard mask layer covers the polysilicon layer.
10. A positioning mark, characterized by The method is formed by using any one of claims 1 to 9.