Memory controller, operating method thereof, memory system, and electronic system

Abstract

The invention discloses a memory controller and an operation method thereof, a storage system and an electronic system, and belongs to the technical field of storage. The memory controller includes: a storage device configured to store a firmware algorithm; the algorithm execution hardware comprises an operation expression, and the operation expression is obtained according to firmware algorithm configuration; and the processor is connected with the storage device and the algorithm execution hardware, and the processor is configured to call the algorithm execution hardware to execute the arithmetic expression to obtain an operation result of the firmware algorithm when the firmware algorithm is executed. According to the memory controller, the execution of the firmware algorithm can be realized through the combination of the arithmetic expression and the algorithm execution hardware, the execution of the firmware algorithm can be realized without preparing a special circuit, and the flexibility and the universality are relatively high. If the firmware algorithm needs to be updated, execution of the updated firmware algorithm can be realized only by reconfiguring the arithmetic expression included in the algorithm execution hardware according to the updated firmware algorithm, a circuit does not need to be changed, and the cost is relatively low.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory controller and its operating method, a storage system, and an electronic system. Background Technology

[0002] With the development of storage technology, storage systems are being used more and more widely. A storage system includes a memory controller, which can execute algorithms to obtain the results of those algorithms. Currently, the flexibility of memory controllers in executing algorithms still needs improvement. Summary of the Invention

[0003] This application provides a memory controller and its operating method, a memory system, and an electronic system. The technical solution is as follows:

[0004] On one hand, embodiments of this application provide a memory controller, the memory controller comprising:

[0005] The storage device is configured to store firmware algorithms;

[0006] Algorithm execution hardware, the algorithm execution hardware including an arithmetic expression, the arithmetic expression being obtained according to the firmware algorithm configuration; and

[0007] A processor is connected to the storage device and the algorithm execution hardware. The processor is configured to, when executing the firmware algorithm, call the algorithm execution hardware to execute the expression and obtain the calculation result of the firmware algorithm.

[0008] In one possible implementation, the algorithm execution hardware is bound to a configurable set of operations, which are obtained by configuring some or all of the configurable operations in the configurable set of operations according to the firmware algorithm.

[0009] In one possible implementation, the number of the operational expressions is at least one, and each operational expression includes a first operand, a second operand, operator information, output information, and operation chain information; wherein, the first operand and the second operand are two objects to be operated on; the operator information is used to indicate the operation rules between the first operand and the second operand; the output information is used to indicate the output method of the operation result of the first operand and the second operand; and the operation chain information is used to indicate the position of the any operational expression in at least one operational expression.

[0010] In one possible implementation, the memory controller is coupled to the memory, and the firmware algorithm is associated with the structure of the memory; at least one of the first operand, the second operand, the operator information, the output information, or the operation chain information is determined based on the structure of the memory.

[0011] In one possible implementation, the firmware algorithm is used to parse the physical address of the memory to obtain the components of the physical address, which is used to locate the storage space in the memory.

[0012] In one possible implementation, the number of components of the physical address of the memory and the number of the operation expressions are both N, with each of the N operation expressions corresponding one-to-one with the N components, where N is an integer not less than 2. The physical address of the memory is represented using binary values, and the N components are arranged sequentially from the least significant bit to the most significant bit of the binary value.

[0013] The second operand in the i-th operation of the N operations is the number of bits corresponding to the i-th component, and the number of bits corresponding to the i-th component is determined according to the structure of the memory; the operation rule indicated by the operator information in the i-th operation is shifting, which is used to shift the value of the number of bits corresponding to the i-th component from the low position of the first operand in the i-th operation to obtain the shifted value; the operation chain information in the i-th operation is used to indicate the position at the i-th bit; i is an integer not less than 1 and not greater than N;

[0014] Where i is not N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is output as the parsing result of the i-th component and the shifted value is output as the first operation object in the (i+1)-th operation; where i is N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is output as the parsing result of the i-th component.

[0015] When the value of i is 1, the first operand in the i-th operation is the binary value; when the value of i is not 1, the first operand in the i-th operation is the shifted value output by the (i-1)-th operation.

[0016] On the other hand, embodiments of this application provide an operation method for a memory controller, the memory controller including a storage device, algorithm execution hardware, and a processor, the storage device storing a firmware algorithm; the method includes:

[0017] Before executing the firmware algorithm, the calculation formula for the algorithm execution hardware is obtained according to the firmware algorithm configuration;

[0018] When the firmware algorithm is executed, the processor calls the algorithm execution hardware to execute the expression and obtain the calculation result of the firmware algorithm.

[0019] In one possible implementation, the algorithm execution hardware is bound to a configurable set of operations, which are obtained by configuring some or all of the configurable operations in the configurable set of operations according to the firmware algorithm.

[0020] In one possible implementation, the number of operational expressions is multiple, and each operational expression includes a first operand, a second operand, operator information, output information, and operation chain information; wherein, the first operand and the second operand are two objects to be operated on; the operator information is used to indicate the operation rules between the first operand and the second operand; the output information is used to indicate the output method of the operation result of the first operand and the second operand; and the operation chain information is used to indicate the position of any operational expression among multiple operational expressions.

[0021] In one possible implementation, the memory controller is coupled to the memory, and the firmware algorithm is associated with the structure of the memory; at least one of the first operand, the second operand, the operator information, the output information, or the operation chain information is determined based on the structure of the memory.

[0022] In one possible implementation, the firmware algorithm is used to parse the physical address of the memory to obtain the components of the physical address, which is used to locate the storage space in the memory.

[0023] In one possible implementation, the number of components of the physical address of the memory and the number of the operation expressions are both N, with each of the N operation expressions corresponding one-to-one with the N components, where N is an integer not less than 2. The physical address of the memory is represented using binary values, and the N components are arranged sequentially from the least significant bit to the most significant bit of the binary value.

[0024] The second operand in the i-th operation of the N operations is the number of bits corresponding to the i-th component, and the number of bits corresponding to the i-th component is determined according to the structure of the memory; the operation rule indicated by the operator information in the i-th operation is shifting, which is used to shift the value of the number of bits corresponding to the i-th component from the low position of the first operand in the i-th operation to obtain the shifted value; the operation chain information in the i-th operation is used to indicate the position at the i-th bit; i is an integer not less than 1 and not greater than N;

[0025] Where i is not N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is output as the parsing result of the i-th component and the shifted value is output as the first operation object in the (i+1)-th operation; where i is N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is output as the parsing result of the i-th component.

[0026] When the value of i is 1, the first operand in the i-th operation is the binary value; when the value of i is not 1, the first operand in the i-th operation is the shifted value output by the (i-1)-th operation.

[0027] On the other hand, embodiments of this application provide a storage system, the storage system including a memory and a memory controller coupled to the memory, the memory controller being any of the memory controllers described above.

[0028] In one possible implementation, the memory controller is configured to, when the operation result is associated with the operation of the memory, obtain the operation information of the memory based on the operation result, and send the operation information to the memory;

[0029] The memory is configured to receive the operation information and execute the operation corresponding to the operation information.

[0030] On the other hand, embodiments of this application provide an electronic system, the electronic system including a host and a storage system coupled to the host, the storage system including a memory and a memory controller coupled to the memory, the memory controller being any of the memory controllers described above.

[0031] In one possible implementation, the memory controller is configured to, when the operation result is associated with the operation of the memory, obtain the operation information of the memory based on the operation result, and send the operation information to the memory;

[0032] The memory is configured to receive the operation information and execute the operation corresponding to the operation information.

[0033] In one possible implementation, the memory controller is configured to send the computation result to the host if the computation result is associated with the host;

[0034] The host is configured to receive the calculation result. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of an electronic system provided in an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of the structure of a memory card provided in an embodiment of this application;

[0038] Figure 3 This is a schematic diagram of the structure of a solid-state drive provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of another electronic system provided in an embodiment of this application;

[0041] Figure 6 This is a schematic diagram of the structure of a memory controller provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram illustrating the binding relationship between execution hardware and a configurable set of operations provided in an embodiment of this application;

[0043] Figure 8 This is a schematic diagram of the composition structure of any operational expression provided in the embodiments of this application;

[0044] Figure 9 This is a schematic diagram of an arithmetic expression provided in an embodiment of this application;

[0045] Figure 10 This is a schematic diagram of the first operand in an arithmetic expression provided in an embodiment of this application;

[0046] Figure 11 This is a flowchart of an operation method of a memory controller provided in an embodiment of this application;

[0047] Figure 12 This is a schematic diagram of the structure of a storage system provided in an embodiment of this application;

[0048] Figure 13 This is a schematic diagram of another electronic system provided in an embodiment of this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. Although exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art. The drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the purpose of illustrating the embodiments of this application.

[0050] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with this application. Rather, they are merely examples consistent with some aspects of this application.

[0051] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “above something” but also includes “above something” or “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0052] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (one or more) another element or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0053] Figure 1 The illustration shows a schematic diagram of an electronic system provided in an embodiment of this application. The electronic system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0054] like Figure 1 As shown, the electronic system 100 includes a host 101 and a storage system 102 coupled to the host 101. The host 101 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 101 may be configured to send data to the storage system 102. Alternatively, the host 101 may be configured to receive data from the storage system 102.

[0055] The storage system 102 includes one or more memories 103 and a memory controller 104. The memory controller 104 is coupled to the memories 103 and is configured to control the memories 103. The memories 103 can be any type of memory. Optionally, the memories 103 are NAND (Not AND) flash memory, such as 3D NAND flash memory; or, the memories 103 are DRAM (Dynamic Random Access Memory), etc.

[0056] For example, memory controller 104 is also coupled to host 101. Memory controller 104 can manage data stored in memory 103 and communicate with host 101.

[0057] In one possible implementation, the memory controller 104 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0058] In one possible implementation, the memory controller 104 is designed to operate in a high duty cycle environment, such as a solid-state drive (SSD) or an embedded multi-media card (eMMC). SSDs or eMMCs are used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as for enterprise storage arrays.

[0059] The memory controller 104 can be configured to control the operation of the memory 103, such as read, erase, and program operations. The memory controller 104 can also be configured to manage various functions related to data stored or to be stored in the memory 103, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In one possible implementation, the memory controller 104 is further configured to process error correction codes (ECCs) regarding data read from or written to the memory 103. In this embodiment, the memory controller 104 is configured to obtain the computation result of a firmware algorithm, and then communicate with the memory 103 and / or the host 101 based on the computation result of the firmware algorithm.

[0060] The memory controller 104 can also perform any other suitable function, such as formatting the memory 103. The memory controller 104 can communicate with external devices (e.g., the host 101) according to a specific communication protocol. For example, the memory controller 104 can communicate with external devices through at least one of various interface protocols, such as USB, MMC (Multi Media Card), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, and NVMe (Non-Volatile Memory Express) protocols.

[0061] The memory controller 104 and one or more memories 103 can be integrated into various types of storage systems 102, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products.

[0062] For example, such as Figure 2As shown, the memory controller 104 and a single memory 103 can be integrated into the memory card 200. The memory card 200 may include PC cards (Personal Computer Memory Card International Association, PCMCIA, abbreviated as PC), CF cards, SmartMedia (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC (Reduced-Size MMC), MMCmicro (Micro Multimedia Card)), SD cards (SD, miniSD (Small Secure Digital Storage Card), microSD (Micro Secure Digital Storage Card), SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 200 may also include a connector for connecting the memory card 200 to a host computer (e.g., Figure 1 The memory card connector 201 is coupled to the host 101.

[0063] For example, such as Figure 3 As shown, the memory controller 104 and multiple memories 103 can be integrated into a solid-state drive (also referred to as a solid-state drive) 300. The solid-state drive 300 may also include a connection between the solid-state drive 300 and a host computer (e.g., ...). Figure 1 The solid-state drive connector 301 is coupled to the host 101. In one possible implementation, the storage capacity and / or operating speed of the solid-state drive 300 is greater than the storage capacity and / or operating speed of the memory card 200.

[0064] Figure 4 A schematic diagram of a memory provided in an embodiment of this application is shown. For example... Figure 4 As shown, the memory 103 includes a memory array 310 and peripheral circuitry 340 that is communicatively connected to the memory array 310.

[0065] The memory array 310 includes a plurality of memory strings 311 arranged in an array. The plurality of memory strings 311 are located on the bearing side of a substrate (not shown) and extend in a direction perpendicular to the bearing surface of the substrate. Exemplarily, the bearing surface of the substrate refers to the surface of the substrate used to bear the memory array 310.

[0066] Each memory string 311 includes multiple memory cells 312, which are stacked in a direction perpendicular to the substrate support surface. Each memory cell 312 has the function of storing data, and the stored data is determined by the number of electrons stored in the memory cell 312. The number of electrons stored in the memory cell 312 determines the magnitude of its threshold voltage; therefore, the threshold voltage of the memory cell 312 indicates the data it stores. The memory cell 312 is a floating-gate field-effect transistor or a charge-trap field-effect transistor.

[0067] For example, the storage unit 312 can be a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC), etc. SLC, MLC, TLC, and QLC can store 1, 2, 3, and 4 bits of data, respectively.

[0068] Each memory string 311 also includes an upper select transistor 313 and a lower select transistor 314. Upper select transistors 313 in different memory strings 311, at the same or similar height from the substrate bearing surface, are coupled to the same drain select line (DSL) 350. Lower select transistors 314 in different memory strings 311, at the same or similar height from the substrate bearing surface, are coupled to the same source select line (SSL) 360. The upper select transistors 313 and 314 are used to activate the selected memory string when reading, programming, or erasing memory cells. The upper select transistor 313 is also referred to as the top select gate (TSG), and the lower select transistor 314 is also referred to as the bottom select gate (BSG). Exemplarily, dummy cells (DCs) also exist between the upper select transistor 313 and the memory cell 312, and between the lower select transistor 314 and the memory cell 312.

[0069] One end of the storage string 311 is coupled to the bit line (BL) 320, and the other end of the storage string 311 is coupled to the source line (SL) 370.

[0070] Storage cells 312 in different storage strings 311 that are at the same or similar height from the substrate bearing surface are in the same layer. Multiple storage cells 312 in the same layer form a storage cell layer. That is, the storage array 310 includes multiple storage cell layers, and multiple word lines 330 are coupled to multiple storage cell layers respectively.

[0071] All memory strings 311 sharing the same set of word lines in memory array 310 form a memory block 31b. Each memory block 31b includes multiple memory pages, which are the smallest units for reading and programming (also known as writing), and the memory block 31b is the smallest unit for erasing.

[0072] In some embodiments, the source ends of each storage string 311 in the same storage block 31b are coupled to the same source line 370, which is also called a common source line (CSL). In other words, each storage string 311 in the same storage block 31b has an array common source (ACS). Here, the source end of the storage string 311 refers to the end of the storage string 311 used for coupling with the source line 370.

[0073] Peripheral circuitry 340 can be coupled to memory array 310 via drain select line 350, source select line 360, bit line 320, source line 370, and word line 330. Peripheral circuitry 340 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 310 by applying voltage and / or current signals to memory cells 312 via drain select line 350, source select line 360, bit line 320, source line 370, and word line 330, and by sensing voltage and / or current signals from memory cells 312.

[0074] The peripheral circuitry 340 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. The peripheral circuitry 340 can control the memory cells 312 in the selected memory string by controlling the voltage of the word line 330 coupled to the selected memory string and the voltage of the bit line 320 coupled to the selected memory string, thereby enabling operations such as erasing, programming, reading, or verification.

[0075] For example, storage system 102 can be implemented as a solid-state drive (SSD), and memory 103 can be implemented as a 3D NAND flash memory. In this case, the electronic system can be as follows: Figure 5 As shown. In Figure 5In an SSD, the components include a memory controller that communicates with the host computer and 3D NAND flash memory. The memory controller can read and write data in the 3D NAND flash memory. SSDs feature low latency, high performance, and low power consumption, and are gradually replacing traditional mechanical hard drives and SATA drives, becoming the more mainstream storage system. They are better able to adapt to the higher demands on data storage brought about by the development of information technology and the surge in user data.

[0076] With the development of storage technology, storage systems are being used more and more widely. A storage system includes a memory controller, which executes algorithms to obtain the results of those algorithms. An algorithm is a set of clear instructions for solving a problem; that is, given a certain set of inputs, an algorithm can obtain the required output within a finite amount of time.

[0077] In memory controllers (e.g., the memory controller in an SSD), for certain fixed algorithms that are particularly time-consuming, hardware (e.g., circuitry) is typically used to embed the algorithm to offload the CPU's computing power. In other words, in one embodiment, a circuit capable of executing the algorithm is fabricated within the memory controller, and the algorithm's computational results are obtained by running the circuit when the algorithm needs to be executed.

[0078] Fixed hardware circuit algorithms require the fabrication of specialized circuits, resulting in poor flexibility and immutability, which reduces versatility. If the algorithm needs updating, the circuit must be re-fabricated, increasing costs. Furthermore, unlike firmware, hardware cannot be modified multiple times after tape-out; once the chip is fabricated, even if the algorithm has problems, there's no way to recover. Especially since algorithms themselves iterate and are optimized, this can easily lead to repeated chip fabrication, increasing costs.

[0079] Based on this, embodiments of this application provide a memory controller that can improve the flexibility and versatility of algorithm execution while reducing costs. For example... Figure 6 As shown, the memory controller 60 provided in this embodiment includes a storage device 61, algorithm execution hardware 62, and a processor 63, with the processor 63 connected to the storage device 61 and the algorithm execution hardware 62. Exemplarily, this memory controller 60 can be... Figures 1 to 3 The memory controller 104 in the middle.

[0080] The storage device 61 is configured to store the firmware algorithm. The algorithm execution hardware 62 includes an expression, which is configured according to the firmware algorithm. The processor 63 is configured to call the algorithm execution hardware to execute the expression when executing the firmware algorithm, and obtain the result of the firmware algorithm.

[0081] Storage device 61 can be any hardware component with storage function within the memory controller 60. In this embodiment, the type of storage device 61 is not limited; for example, storage device 61 can be DRAM. In this embodiment, storage device 61 stores firmware algorithms. A firmware algorithm is an algorithm recorded in firmware (FW) used to implement any function. Firmware refers to the software in the memory controller 60 used to drive (or control) the hardware. In other words, in this embodiment, the algorithm is recorded in software, thereby solving the problems of poor maintenance and limited versatility caused by hardware-based algorithms.

[0082] This application does not limit the type of firmware algorithm. In some embodiments, the firmware algorithm may include, but is not limited to, algorithms for controlling the operation of the memory (e.g., reading, erasing, and programming), algorithms for managing data written to or read from the memory (e.g., bad block management algorithms, garbage collection algorithms, logical-to-physical address translation algorithms, wear leveling algorithms, error correction code algorithms, etc.), and algorithms for communicating with the host.

[0083] In some embodiments, the firmware algorithm can be an algorithm with a high update requirement. An algorithm with a high update requirement can be one that requires more than a certain number of updates within a reference time period. The reference time period and the number of updates threshold can be set based on experience or adjusted flexibly according to the application scenario, and this application embodiment does not limit them.

[0084] In an exemplary embodiment, the algorithm with high update requirements may be one associated with the memory structure. Such algorithms need to be updated as the memory structure changes, resulting in high update requirements. The memory structure refers to the structure of the memory array, which depends on the number of memory strings in the array, the number of memory cells in each memory string, and so on. For example, the algorithm associated with the memory structure may be an algorithm for resolving the physical address of the memory to obtain its components, where the physical address of the memory is the address used to locate storage space within the memory.

[0085] In an exemplary embodiment, algorithms with high update requirements can also be those whose final versions are not yet determined. Algorithms with undetermined final versions are not easily finalized in the short term and require later firmware optimization, thus leading to high update requirements. For example, an algorithm with an undetermined final version could be an algorithm that automatically searches for a random seed table. This algorithm automatically searches for a random seed in the random seed table. The random seed is used to randomize the data to be written to memory or to ensure the randomness of data read from memory.

[0086] The algorithm execution hardware 62 is the hardware within the memory controller 60 used to execute the firmware algorithm. The algorithm execution hardware 62 includes operational expressions configured according to the firmware algorithm, enabling subsequent execution of the firmware algorithm by executing these expressions. In other words, the algorithm execution hardware 62 is not a pre-prepared, fixed circuit, but rather a hardware component containing configurable operational expressions. Therefore, even if the firmware algorithm needs to be updated, only the operational expressions included in the algorithm execution hardware need to be reconfigured according to the updated firmware algorithm to execute the updated firmware algorithm, without requiring changes to the circuitry, thus reducing costs.

[0087] The processor 63 is a hardware component with processing capabilities in the memory controller 60. In this embodiment, the processor 63 is used to determine whether a firmware algorithm needs to be executed, and when it is determined that a firmware algorithm needs to be executed, it calls the algorithm execution hardware 62 to execute the pre-configured formula according to the firmware algorithm to obtain the calculation result of the firmware algorithm.

[0088] For example, the processor 63 may determine whether a firmware algorithm needs to be executed by: determining whether the execution conditions of the firmware algorithm are met; and if the execution conditions are met, determining that the firmware algorithm needs to be executed. The execution conditions of the firmware algorithm are related to the type of firmware algorithm, and this embodiment does not limit this. For example, the execution conditions of the firmware algorithm may include an instruction sent by the host carrying identification information of the firmware algorithm. For example, the execution conditions of the firmware algorithm may also include other components in the memory controller 60 outputting the data required to execute the firmware algorithm, or the memory controller 60 obtaining the data required to execute the firmware algorithm through communication with other devices (e.g., host, memory, etc.).

[0089] In an exemplary embodiment, the memory controller 60 has a Unify Compute Engine, which may refer to hardware with computing capabilities in the memory controller 60.

[0090] The algorithm execution hardware 62 is bound to some or all of the configurable arithmetic expressions among a plurality of configurable arithmetic expressions. Configurable arithmetic expressions refer to arithmetic expressions that can be flexibly set according to requirements. In this case, the arithmetic expressions included in the algorithm execution hardware 62 may refer to the arithmetic expressions obtained after configuring some or all of the configurable arithmetic expressions bound to the algorithm execution hardware 62 according to the firmware algorithm.

[0091] For example, the memory controller 60 may include multiple execution hardware devices capable of executing arithmetic expressions. A binding relationship is established between the multiple execution hardware devices and the multiple configurable arithmetic expressions. The number of configurable arithmetic expressions bound to different execution hardware devices may be the same or different; this embodiment does not limit this. This embodiment does not limit the binding relationship between the multiple execution hardware devices and the multiple configurable arithmetic expressions, as long as it ensures that each execution hardware device can perform its required task according to the bound configurable arithmetic expression. Algorithm execution hardware 62 can refer to any of the multiple execution hardware devices whose bound configurable arithmetic expressions can be used to execute firmware algorithms.

[0092] In other embodiments, the unified computing engine includes multiple configurable groups of operations, each group comprising multiple configurable operations. Different groups may contain the same or different numbers of configurable operations. Grouping the configurable operations improves the standardization of the unified computing engine's management of these operations.

[0093] The algorithm execution hardware 62 is bound to some or all of the configurable operation groups in a plurality of configurable operation groups; that is, the algorithm execution hardware 62 is bound to configurable operation groups. In this case, the operation groups included in the algorithm execution hardware 62 may refer to the operation groups obtained by configuring some or all of the configurable operation groups bound to the algorithm execution hardware 62 according to the firmware algorithm.

[0094] For example, the memory controller 60 may include multiple execution hardware devices capable of executing arithmetic expressions. A binding relationship is established between the multiple execution hardware devices and multiple configurable sets of arithmetic expressions. The number of configurable sets of arithmetic expressions bound to different execution hardware devices may be the same or different; this embodiment does not limit this. This embodiment does not limit the binding relationship between the multiple execution hardware devices and the multiple configurable sets of arithmetic expressions, as long as it ensures that each execution hardware device can perform its required tasks according to the bound configurable set of arithmetic expressions. Algorithm execution hardware 62 can refer to any execution hardware device among the multiple execution hardware devices whose configurable arithmetic expressions in the bound configurable set of arithmetic expressions can be used to execute firmware algorithms.

[0095] In some embodiments, the execution hardware may also be referred to as an IP (Intellectual Property) module, the configurable set of operations may also be referred to as a Compute Group, and the configurable operations may also be referred to as a ComputeLine.

[0096] For example, the memory controller 60 includes execution hardware A, execution hardware B, execution hardware C, and execution hardware D, and the unified computing engine includes 33 configurable operation groups (represented as configurable operation group 0, configurable operation group 1, configurable operation group 2, ..., configurable operation group 32). The binding relationship between the execution hardware and the configurable operation groups can be as follows: Figure 7 As shown. Hardware A is bound to configurable expression group 2, hardware B is bound to configurable expression group 0, hardware C is bound to configurable expression group 31, and hardware D is bound to configurable expression group 1. It should be noted that... Figure 7 The binding relationships shown are merely one example; the binding relationships between execution hardware and configurable sets of operations are not limited to this.

[0097] See also Figure 7 The firmware in the memory controller 60 can configure the configurable operations in the configurable operation groups. Different configurable operation groups can include completely different, partially the same, or completely identical configurable operations. For example, configurable operation group 0 includes configurable operation 0, configurable operation 1, configurable operation 2, and configurable operation 3.

[0098] For example, in the case where there is a binding relationship between multiple execution hardware and multiple configurable expressions, the firmware can determine the configurable expressions bound to the algorithm execution hardware 62 according to the binding relationship, and then configure all or part of the configurable expressions bound to the algorithm execution hardware 62 according to the firmware algorithm to obtain the expressions included in the algorithm execution hardware 62.

[0099] For example, in the case where there is a binding relationship between multiple execution hardware and multiple configurable formula groups, the firmware can determine the configurable formula group bound to the algorithm execution hardware 62 according to the binding relationship, and then configure all or part of the configurable formulas in the configurable formula group bound to the algorithm execution hardware 62 according to the firmware algorithm to obtain the formulas included in the algorithm execution hardware 62.

[0100] The process by which the firmware obtains the algorithm execution hardware based on the firmware algorithm configuration is related to the type of firmware algorithm. This application embodiment does not limit this, as long as it ensures that the calculation result of the firmware algorithm can be obtained by executing the calculation formula obtained after configuration.

[0101] In one possible implementation, the algorithm execution hardware 62 includes at least one set of operations, see [link to relevant documentation]. Figure 8Any operational expression includes a first operand, a second operand, operator information, output information, and operation chain information. The first and second operands are two objects to be operated on; the operator information indicates the operational rules between the first and second operands; the output information indicates how the result of the operation between the first and second operands is output; and the operation chain information indicates the position of any operational expression within multiple operational expressions. Expressing an operational expression using the first operand, second operand, operator information, output information, and operation chain information ensures the reliability of the operational expression.

[0102] The first operand can also be called the left-hand operand, which is to be operated on according to the rules of operation; the second operand can also be called the right-hand operand, which is to be operated on according to the rules of operation. For example, see Figure 8 Taking division as an example, in the expression A / B, A is the first operand and B is the second operand.

[0103] Operator information is used to indicate the operation rules between the first operand and the second operand. The operation rules are used to indicate how the first operand and the second operand should perform the operation. For example, the operation rules may include, but are not limited to, addition (+), subtraction (-), division ( / ), multiplication (*), AND (&), OR (|), XOR (^), left shift (<<), right shift (>>), negation (~), modulo (%), etc.

[0104] For example, different operation rules can be represented using different identifiers; that is, operator information can be represented using identifiers of operation rules. The identifiers of operation rules can be set based on experience or flexibly adjusted according to the application scenario; this application embodiment does not limit this. For example, such as... Figure 8 As shown, the operation rules indicated by the operator information include eight operation rules: addition (+), subtraction (-), division ( / ), multiplication (*), OR (|), modulo (%), XOR (^), and right shift (>>). The identifiers of the above eight operation rules are 000, 001, 010, 100, 101, 110, 011, and 111, respectively.

[0105] The output information is used to indicate the output method of the operation result of the first operand and the second operand. The output method includes, but is not limited to, directly outputting the final operation result of the expression, or using it as the input of the first or second operand of other expressions. Other expressions can refer to any one or more expressions other than the given expression, and this application embodiment does not limit this. For example, other expressions may include, but are not limited to: expressions located one position after the given expression, expressions located two positions after the given expression, etc. For example, multiple expressions can be divided into multiple expression groups according to the execution order, and other expressions may also include: the first expression in the expression group located one position after the given expression group, the first expression in the expression group located two positions after the given expression group, etc.

[0106] For example, different output methods can be represented by different identifiers; that is, output information can be represented by the identifier of the output method. The identifier of the output method can be set based on experience or flexibly adjusted according to the application scenario; this application embodiment does not limit this. For example, such as... Figure 8 As shown, the output information indicates five output modes: as the first operand input of the next operation, as the second operand input of the next operation, as the first operand input of the first operation in the next operation group, as the second operand input of the first operation in the next operation group, and output to a specific register (memory). These five output modes are identified as 000, 001, 010, 011, and 100, respectively. The specific register refers to the element used to store the final operation result of the operation, and it can be configured simultaneously with the operation.

[0107] The operation chain information is used to indicate the position of any operation in at least one operation, that is, to indicate which position of any operation is executed in at least one operation.

[0108] For example, different positions can be represented by different identifiers; that is, the operation chain information can be represented by the identifier of the position of the operation expression. The identifier of the position of the operation expression can be set based on experience or flexibly adjusted according to the application scenario, and this application embodiment does not limit this. For example, the position indicated by the operation chain information includes four positions: First, Middle, End, and Single, with identifiers of 00, 01, 10, and 11 respectively. Wherein, if the position indicated by the operation chain information is Single, it means that the number of operations is one.

[0109] For example, for any given expression, at least one of the first operand, second operand, operator information, output information, and operation chain information is configured by the firmware according to the firmware algorithm. If some of the information among the first operand, second operand, operator information, output information, and operation chain information is configured by the firmware according to the firmware algorithm, the remaining information refers to information that the given expression possessed before being configured according to the firmware algorithm. This information may refer to information that the given expression possesses by default, or information configured during a historical configuration process.

[0110] The configuration results of the first operand, the second operand, the operator information, the output information, and the operation chain information in the operation formula are related to the type of firmware algorithm, and this application embodiment does not limit this.

[0111] In one possible implementation, the memory controller 60 is coupled to the memory, and the firmware algorithm is associated with the memory structure. At least one of the first operand, the second operand, operator information, output information, or operation chain information is determined based on the memory structure. That is, the firmware algorithm may be an algorithm associated with the memory structure. In this case, at least one piece of information in the expression is determined based on the memory structure. Therefore, if the memory structure changes, the expression needs to be reconfigured to ensure that the configured expression is associated with the memory structure. Exemplarily, the memory structure refers to the structure of the memory array, which depends on the number of memory strings in the array, the number of memory cells in each memory string, etc. In some embodiments, the memory structure may also be referred to as memory granules.

[0112] In some embodiments, the structure of the memory may change continuously during the fabrication of the storage system, and the firmware algorithm associated with the memory structure also needs to be changed continuously. If the firmware algorithm is fixed to be executed by the circuit, it will lead to a decrease in the compatibility of the memory controller 60. Based on the method provided in the embodiments of this application, even if the structure of the memory changes, only the firmware algorithm needs to be updated, and then the arithmetic expression can be reconfigured according to the updated firmware algorithm. There is no need to re-fabricate the circuit, which is highly flexible and helps to save costs.

[0113] For example, since the firmware algorithm is recorded in the firmware, the firmware algorithm can be updated by updating the firmware. This application does not limit the method of updating the firmware. Any firmware update method can be used to update the firmware. For example, the firmware can be updated by uploading the firmware package through the device management service console; the firmware can also be updated through the update function built into the device's operating system, etc.

[0114] In an exemplary embodiment, where the firmware algorithm is associated with the structure of the memory, the firmware algorithm may be an algorithm for resolving the physical address of the memory to obtain the components of the physical address.

[0115] The physical address of a memory is used to locate storage space within the memory. The physical address of a memory is obtained by the memory controller 60 converting the logical address of the memory. That is, the process of resolving the physical address of a memory is performed after the memory controller 60 converts the logical address of the memory into a physical address. The logical address of a memory is the address used by a user or application to access data. It is the logical representation of data storage, allowing users to manage and access data at a higher level through the operating system and file system. The logical address does not directly correspond to a specific location in the memory, but is associated with the physical address through the algorithm of the memory controller 60 and a Logical-Physical Table (LPT). The physical address is the address of a specific location in the memory. It directly corresponds to the electronic location in the memory. The physical address refers to the exact location of the storage cell, which is directly accessed by electronic signals without any conversion or translation. In some embodiments, the process of the memory controller 60 resolving the physical address of the memory can be a mapping management process performed by the memory controller 60.

[0116] For example, a memory physical address comprises multiple components. Under different memory structures, the number of bits occupied by the same component in the memory physical address may differ. This could lead to the inability to accurately locate the storage space in the memory directly based on the physical address. Therefore, it is necessary to parse each component from the memory physical address to more accurately locate the storage space in the memory based on each component. In some embodiments, when a firmware algorithm is used to parse the memory physical address and obtain its components, the firmware algorithm can also be referred to as an algorithm for calculating the composition of the PAA (Physical Address).

[0117] Because the number of bits occupied by the same component in the physical address of memory may be different under different memory structures, different algorithms are needed to resolve the physical address of memory under different memory structures. That is, the firmware algorithm is associated with the memory structure.

[0118] In an exemplary embodiment, the physical address of the memory has N components and N operations, with each of the N operations corresponding to one of the N components. N is an integer not less than 2. The physical address of the memory is represented using binary numbers, and the N components are arranged sequentially from the least significant bit to the most significant bit of the binary number. The value of N can be flexibly set according to requirements; for example, N can be 5 or 8. Exemplarily, the order from the least significant bit to the most significant bit of the binary number refers to the order from the rightmost bit to the leftmost bit of the binary number.

[0119] In the i-th operation of N operations, the second operand is the number of bits corresponding to the i-th component, which is determined by the memory structure; the operator information in the i-th operation indicates the operation rule as shifting, which is used to shift the value of the number of bits corresponding to the i-th component from the low position of the first operand in the i-th operation to obtain the shifted value; the operation chain information in the i-th operation indicates the position at the i-th bit; i is an integer not less than 1 and not greater than N.

[0120] The number of bits corresponding to the i-th component refers to the number of bits occupied by the i-th component in the physical address. Depending on the memory structure, the number of bits corresponding to the i-th component may be the same or different. For example, the process of shifting the value of the number of bits corresponding to the i-th component from the low position of the first operand in the i-th expression can also be called the process of right-shifting the value of the number of bits corresponding to the i-th component.

[0121] When the value of i is not N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is output as the parsing result of the i-th component and the shifted value is output as the first operand in the (i+1)-th operation; when the value of i is N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is output as the parsing result of the i-th component.

[0122] When i is 1, the first operand in the i-th expression is a binary value; when i is not 1, the first operand in the i-th expression is the shifted value output by the (i-1)-th expression.

[0123] Next, we will further explain the N operational expressions mentioned above with specific examples.

[0124] Taking NAND flash memory as an example, the physical address of a memory consists of five components: AU (Allocate Unit), Page, Block, CH (Channel), and CE (Chip Enable). These five components are arranged sequentially from the least significant bit to the most significant bit of the physical address. In the current memory structure, the number of bits corresponding to component AU is 2 bits, component Page is 12 bits, component Block is 10 bits, component CH is 4 bits, and component CE is 3 bits.

[0125] The AU component in the physical address represents which AU within a memory page. AU is the name of each of the four parts after a NAND memory page is divided. The Page component in the physical address represents which page(s) within a memory block. A Page is the name of each memory page in NAND; a memory page is a virtual concept, not a physical one. For SLC, each memory cell contains 1 bit of information; therefore, reading the information stored in a layer of memory cells at the physical layer corresponds to reading the information of one Page. For MLC, each memory cell contains 2 bits of information; therefore, reading the information stored in a layer of memory cells at the physical layer corresponds to reading the information of two Pages.

[0126] The value of the Block component in the physical address indicates which Block in the NAND flash memory. The value of the CH component in the physical address indicates which group of physical pins in the NAND flash memory is responsible for receiving and transmitting data and commands. The value of the CE component in the physical address indicates which CE pin(s) in the NAND flash memory.

[0127] See Figure 9 The algorithm execution hardware 62 includes 5 operational expressions, namely operational expression 1 corresponding to component AU, operational expression 2 corresponding to component Page, operational expression 3 corresponding to component Block, operational expression 4 corresponding to component CH, and operational expression 5 corresponding to component CE.

[0128] For operation 1, the first operand is the binary value (A) representing the physical address; the second operand is 2; the operation rule indicated by the operator information is to shift two values ​​from the low position of the binary value (A) to obtain the shifted value (B); the operation chain information is used to indicate the first bit (represented by the identifier 01); the output information ( Figure 9 The output information 1) is used to indicate that the value shifted out by the shift is output as the analytical result (AU value) of component AU, and that the shifted value (B) is output as the first operand in the operation expression 2.

[0129] For operation 2, the first operand is the shifted value (B) output from operation 1; the second operand is 12; the operator information indicates the operation rule as shifting 12 values ​​from the lowest position of the shifted value (B) to obtain the shifted value (C); the operation chain information is used to indicate that it is in the 2nd position (represented by the identifier 02); the output information ( Figure 9 The output information 2) is used to indicate that the value shifted out by the shift will be output as the parsing result (Page value) of the component Page, and that the shifted value (C) will be output as the first operand in the operation 3.

[0130] For operation 3, the first operand is the shifted value (C) output from operation 2; the second operand is 10; the operator information indicates the operation rule as shifting 10 values ​​from the lowest position of the shifted value (C) to obtain the shifted value (D); the operation chain information is used to indicate that it is in the 3rd position (represented by the identifier 03); the output information ( Figure 9 The output information 3) is used to indicate that the value shifted out by the shift will be output as the parsing result (Block value) of the component Block, and that the shifted value (D) will be output as the first operand in the operation 4.

[0131] For operation 4, the first operand is the shifted value (D) output from operation 3; the second operand is 4; the operator information indicates that the operation rule is to shift 4 values ​​from the lowest position of the shifted value (D) to obtain the shifted value (E); the operation chain information is used to indicate that it is in the 4th position (represented by the identifier 04); the output information ( Figure 9 The output information 4) is used to indicate that the value shifted out by the shift will be output as the parsing result (CH value) of component CH, and that the shifted value (E) will be output as the first operand in expression 5.

[0132] For operation 5, the first operand is the shifted value (E) of the output of operation 4; the second operand is 3; the operation rule indicated by the operator information is to shift 3 values ​​out of the lower position of the shifted value (E) to obtain the shifted value (empty value); the operation chain information is used to indicate that it is in the 5th position (represented by the identifier 05); the output information ( Figure 9 The output information 5) is used to indicate that the value shifted out by the shifter will be output as the analytical result (CE value) of the component CE.

[0133] The relationships between the first operands (i.e., the values ​​A, B, C, D, and E) in the above five operations can be found in [reference needed]. Figure 10 Value A is a value that includes components AU, Page, Block, CH and CE. Component AU occupies 2 bits, component Page occupies 12 bits, component Block occupies 10 bits, component CH occupies 4 bits, and component CE occupies 3 bits.

[0134] Value B is the value obtained by shifting two values ​​from the lowest position of value A, including the components Page, Block, CH, and CE. Value C is the value obtained by shifting twelve values ​​from the lowest position of value B, including the components Block, CH, and CE. Value D is the value obtained by shifting ten values ​​from the lowest position of value C, including the components CH and CE. Value E is the value obtained by shifting four values ​​from the lowest position of value D, including the component CE. Figure 9 The operation shown can break down a large value A into its constituent element values ​​step by step. Since the number of bits occupied by each constituent element of value A varies with the memory structure, the process of parsing the constituent elements of value A can be achieved by using the configuration operation provided in this application embodiment.

[0135] In some embodiments, the firmware algorithm can be an algorithm associated with the memory structure, or it can be another algorithm with high update requirements. For example, the firmware algorithm can also be an algorithm whose final version is not yet determined, such as an algorithm for automatically finding the Randomizer Seed Table. This algorithm is not easy to solidify in the short term and needs to be combined with later firmware optimization. Executing this algorithm based on the memory controller 60 provided in the embodiments of this application can improve the flexibility and versatility of the algorithm execution, and also reduce the cost of updating the algorithm.

[0136] The memory controller 60 provided in this application embodiment supports software (firmware) definition of hardware (algorithm execution hardware) computation formulas. The firmware can dynamically configure the hardware computation formulas according to the algorithm, and the hardware executes the firmware-configured computation formulas sequentially to obtain the algorithm's computation result. This type of memory controller 60 can improve the feasibility of subsequent algorithm optimization. Compared with the hardware algorithm fixation scheme, the software-defined approach has better flexibility and helps reduce the cost consumption caused by repeated chip fabrication.

[0137] In this embodiment, the algorithm execution hardware includes an arithmetic expression configured according to the firmware algorithm, enabling the processor to obtain the computation result of the firmware algorithm by calling the algorithm execution hardware to execute the arithmetic expression. This type of memory controller can execute the firmware algorithm through the combination of the arithmetic expression and the algorithm execution hardware, achieving execution without the need for dedicated circuitry, thus offering high flexibility and versatility. Furthermore, if the firmware algorithm needs to be updated, execution can be achieved simply by reconfiguring the arithmetic expression included in the algorithm execution hardware according to the updated firmware algorithm, without requiring circuitry changes, resulting in lower costs.

[0138] This application provides an operation method for a memory controller. The memory controller includes a storage device, algorithm execution hardware, and a processor. The storage device stores firmware algorithms. This memory controller can... Figure 6 The memory controller 60 is located within the memory. See also... Figure 11 The operation method of the memory controller includes the following steps 1101 and 1102:

[0139] In step 1101, before executing the firmware algorithm, the calculation formula for the algorithm execution hardware is obtained according to the firmware algorithm configuration.

[0140] In step 1102, when executing the firmware algorithm, the processor calls the algorithm to execute the hardware execution formula to obtain the calculation result of the firmware algorithm.

[0141] In one possible implementation, the algorithm execution hardware is bound to a configurable set of operations, which are obtained by configuring some or all of the configurable operations in the configurable set of operations according to the firmware algorithm.

[0142] In one possible implementation, the number of operations is at least one, and each operation includes a first operand, a second operand, operator information, output information, and operation chain information; wherein, the first operand and the second operand are two objects to be operated on; the operator information is used to indicate the operation rules between the first operand and the second operand; the output information is used to indicate the output method of the operation result of the first operand and the second operand; and the operation chain information is used to indicate the position of any operation in at least one operation.

[0143] In one possible implementation, the memory controller is coupled to the memory, and the firmware algorithm is structurally associated with the memory; at least one of the first operand, the second operand, operator information, output information, or operation chain information is determined based on the memory structure.

[0144] In one possible implementation, the firmware algorithm is used to parse the physical address of the memory to obtain the components of the physical address, which is used to locate the storage space in the memory.

[0145] In one possible implementation, the physical address of the memory has N components and N operations, with each operation corresponding to one of the N components. N is an integer not less than 2. The physical address of the memory is represented using binary values, and the N components are arranged sequentially from the least significant bit to the most significant bit. The second operand in the i-th operation is the number of bits corresponding to the i-th component, which is determined according to the memory structure. The operator information in the i-th operation indicates a shift operation, which is used to shift the number of bits corresponding to the i-th component from the least significant bit of the first operand in the i-th operation to obtain the shifted value. The operation chain information in the i-th operation indicates the position at the i-th bit, where i is an integer not less than 1 and not greater than N.

[0146] Where i is not N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is the parsing result of the i-th component and the shifted value is the first operand in the (i+1)-th operation; where i is N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is the parsing result of the i-th component; where i is 1, the first operand in the i-th operation is a binary value; where i is not 1, the first operand in the i-th operation is the shifted value output by the (i-1)-th operation.

[0147] The description of the above-described memory controller operation method embodiments is the same as that of the above-described memory controller hardware embodiments. Figure 6 The illustrated embodiments show similar beneficial effects. For technical details not disclosed in the embodiments of the memory controller's operation method, please refer to the description of the hardware embodiments of the memory controller in this application for understanding.

[0148] This application provides a storage system, such as... Figure 12 As shown, the storage system 1200 includes a memory 1201 and a memory controller 1202 coupled to the memory 1201. The memory controller 1202 can be as described above. Figure 6 The memory controller 60 and memory 1201 can be the above-mentioned Figures 1 to 4 The memory 103 in the middle.

[0149] In one possible implementation, the memory controller 1202 is configured to, when the calculation result is associated with the operation of the memory 1201, obtain the operation information of the memory 1201 based on the calculation result, and send the operation information to the memory 1201. The memory 1201 is configured to receive the operation information and execute the operation corresponding to the operation information.

[0150] When the result of the firmware algorithm is associated with the operation of the memory 1201, the memory controller 1202 obtains the operation information of the memory 1201 based on the result of the firmware algorithm, and communicates with the memory 1201 based on the operation information of the memory 1201 to inform the memory 1201 of the operation to be performed.

[0151] The association between the firmware algorithm's calculation result and the operation of memory 1201 can be understood as the need to utilize the firmware algorithm's calculation result during the operation of memory 1201 (e.g., reading, programming, erasing, etc.). The operation information of memory 1201 is used to indicate the operation that memory 1201 needs to perform based on the calculation result. The method of obtaining the operation information of memory 1201 based on the calculation result is related to the type of firmware algorithm and the type of the firmware algorithm's calculation result, etc. This application embodiment does not limit this, as long as the memory 1201 can know what operation needs to be performed based on the operation information.

[0152] For example, the association between the firmware algorithm's calculation result and the operation of memory 1201 can mean that the firmware algorithm's calculation result is data that needs to be written into memory 1201. In this case, the way to obtain the operation information of memory 1201 based on the calculation result can be: using information including the calculation result and the address of the first storage space in memory 1201 as the operation information of memory 1201. After receiving this operation information, memory 1201 determines the first storage space according to the address of the first storage space and writes the calculation result into the first storage space.

[0153] For example, the association between the firmware algorithm's calculation result and the operation of memory 1201 can also mean that the firmware algorithm's calculation result includes the address of the second storage space containing the data to be read in memory 1201. In this case, the way to obtain the operation information of memory 1201 based on the calculation result can be: using the address of the second storage space as the operation information of memory 1201. After receiving this operation information, memory 1201 determines the second storage space according to the address of the second storage space, reads data from the second storage space, and feeds back the read data to memory controller 1202.

[0154] This application provides an electronic system, such as... Figure 13As shown, the electronic system 1300 includes a host 1301 and a storage system 1302 coupled to the host 1301. The storage system 1302 includes a memory 1303 and a memory controller 1304 coupled to the memory 1303. Exemplarily, the electronic system 1300 can be as described above. Figure 1 The electronic system 100 and the host 1301 can be the above-mentioned Figure 1 The host 101 and storage system 1302 can be the above-mentioned Figure 1 The storage system 102 and memory 1303 can be the above-mentioned Figures 1 to 4 The memory 103 and memory controller 1304 in the memory can be the above-mentioned Figure 6 The memory controller 60 in the middle.

[0155] In one possible implementation, the memory controller 1304 is configured to, when the calculation result is associated with the operation of the memory 1303, obtain the operation information of the memory 1303 based on the calculation result, and send the operation information to the memory 1303. The memory 1303 is configured to receive the operation information and execute the operation corresponding to the operation information.

[0156] When the result of the firmware algorithm is associated with the operation of the memory 1303, the memory controller 1304 obtains the operation information of the memory 1303 based on the result of the firmware algorithm, and communicates with the memory 1303 based on the operation information of the memory 1303 to inform the memory 1303 of the operation to be performed.

[0157] The association between the firmware algorithm's calculation result and the operation of memory 1303 can be understood as the firmware algorithm's calculation result being used during the operation of memory 1303 (e.g., reading, programming, erasing, etc.). The operation information of memory 1303 is used to indicate the operation that memory 1303 needs to perform based on the calculation result. The method of obtaining the operation information of memory 1303 based on the calculation result is related to the type of firmware algorithm and the type of the firmware algorithm's calculation result, etc. This application embodiment does not limit this, as long as the memory 1303 can know what operation needs to be performed based on the operation information.

[0158] For example, the association between the firmware algorithm's calculation result and the operation of memory 1303 can mean that the firmware algorithm's calculation result is data that needs to be written into memory 1303. In this case, the way to obtain the operation information of memory 1303 based on the calculation result can be: using information including the calculation result and the address of the first storage space in memory 1303 as the operation information of memory 1303. After receiving this operation information, memory 1303 determines the first storage space according to the address of the first storage space and writes the calculation result into the first storage space.

[0159] For example, the association between the firmware algorithm's calculation result and the operation of memory 1303 can also mean that the firmware algorithm's calculation result includes the address of the second storage space containing the data to be read in memory 1303. In this case, the way to obtain the operation information of memory 1303 based on the calculation result can be: using the address of the second storage space as the operation information of memory 1303. After receiving this operation information, memory 1303 determines the second storage space according to the address of the second storage space, reads data from the second storage space, and feeds back the read data to memory controller 1304.

[0160] In one possible implementation, the memory controller 1304 is configured to send the computation result to the host 1301 when the computation result is associated with the host. The host 1301 is configured to receive the computation result.

[0161] When the result of the firmware algorithm is associated with the host 1301, the memory controller 1304 sends the result to the host 1301 after obtaining the result of the firmware algorithm, so that the host 1301 can receive the result.

[0162] For example, associating the firmware algorithm's calculation result with the host 1301 can mean that the firmware algorithm's calculation result is obtained after executing the firmware algorithm according to the instructions sent by the host 1301. Alternatively, as an example, associating the firmware algorithm's calculation result with the host 1301 can mean that the host 1301 needs to utilize the firmware algorithm's calculation result for operation.

[0163] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0164] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A memory controller, characterized in that, The memory controller includes: The storage device is configured to store firmware algorithms; Algorithm execution hardware, the algorithm execution hardware including an arithmetic expression, the arithmetic expression being obtained according to the firmware algorithm configuration; and A processor is connected to the storage device and the algorithm execution hardware. The processor is configured to, when executing the firmware algorithm, call the algorithm execution hardware to execute the expression and obtain the calculation result of the firmware algorithm.

2. The memory controller according to claim 1, characterized in that, The algorithm execution hardware is bound to a configurable set of operations, which are obtained by configuring some or all of the configurable operations in the configurable set of operations according to the firmware algorithm.

3. The memory controller according to claim 1, characterized in that, The number of the operational expressions is at least one, and each operational expression includes a first operand, a second operand, operator information, output information, and operation chain information; Wherein, the first operand and the second operand are two objects to be operated on; the operator information is used to indicate the operation rules between the first operand and the second operand; the output information is used to indicate the output method of the operation result of the first operand and the second operand; the operation chain information is used to indicate the position of any operation expression in at least one operation expression.

4. The memory controller according to claim 3, characterized in that, The memory controller is coupled to the memory, and the firmware algorithm is associated with the structure of the memory; at least one of the first operand, the second operand, the operator information, the output information, or the operation chain information is determined based on the structure of the memory.

5. The memory controller according to claim 4, characterized in that, The firmware algorithm is used to parse the physical address of the memory to obtain the components of the physical address, which is used to locate the storage space in the memory.

6. The memory controller according to claim 5, characterized in that, The physical address of the memory has N components and N operations, with each of the N operations corresponding to one of the N components. N is an integer not less than 2. The physical address of the memory is represented by binary values, and the N components are arranged sequentially from the least significant bit to the most significant bit of the binary value. The second operand in the i-th operation of the N operations is the number of bits corresponding to the i-th component, and the number of bits corresponding to the i-th component is determined according to the structure of the memory; the operation rule indicated by the operator information in the i-th operation is shifting, which is used to shift the value of the number of bits corresponding to the i-th component from the low position of the first operand in the i-th operation to obtain the shifted value; the operation chain information in the i-th operation is used to indicate the position at the i-th bit; i is an integer not less than 1 and not greater than N; Where i is not N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is output as the parsing result of the i-th component and the shifted value is output as the first operand in the (i+1)-th operation; where i is N, the output information in the i-th operation is used to indicate that the value shifted out by the shift is output as the parsing result of the i-th component. When the value of i is 1, the first operand in the i-th operation is the binary value; when the value of i is not 1, the first operand in the i-th operation is the shifted value output by the (i-1)-th operation.

7. A method for operating a memory controller, characterized in that, The memory controller includes a storage device, algorithm execution hardware, and a processor; the storage device stores firmware algorithms; the method includes: Before executing the firmware algorithm, the calculation formula for the algorithm execution hardware is obtained according to the firmware algorithm configuration; When the firmware algorithm is executed, the processor calls the algorithm execution hardware to execute the expression and obtain the calculation result of the firmware algorithm.

8. A storage system, characterized in that, The storage system includes a memory and a memory controller coupled to the memory, wherein the memory controller is the memory controller described in any one of claims 1-6.

9. The storage system according to claim 8, characterized in that, The memory controller is configured to, when the calculation result is associated with the operation of the memory, obtain the operation information of the memory based on the calculation result, and send the operation information to the memory; The memory is configured to receive the operation information and execute the operation corresponding to the operation information.

10. An electronic system, characterized in that, The electronic system includes a host computer and a storage system coupled to the host computer. The storage system includes a memory and a memory controller coupled to the memory. The memory controller is the memory controller described in any one of claims 1-6.

11. The electronic system according to claim 10, characterized in that, The memory controller is configured to, when the calculation result is associated with the operation of the memory, obtain the operation information of the memory based on the calculation result, and send the operation information to the memory; The memory is configured to receive the operation information and execute the operation corresponding to the operation information.

12. The electronic system according to claim 10, characterized in that, The memory controller is configured to send the computation result to the host when the computation result is associated with the host; The host is configured to receive the calculation result.

Images