Integrated circuit device

Abstract

An integrated circuit device including a plurality of semiconductor patterns having different widths is provided. To minimize or reduce current leakage from a semiconductor pattern having a relatively small width to below a source / drain region, a lower thin film having a specific thickness may be selectively formed below the source / drain region corresponding to a narrow semiconductor pattern, thereby improving electrical reliability of the device. Further, an integrated circuit device including a plurality of semiconductor patterns having different widths is provided. To minimize or reduce current leakage from a semiconductor pattern having a relatively small width to below the source / drain region, a lower thin film may be selectively and thickly deposited below the source / drain region corresponding to the narrow semiconductor pattern, thereby improving electrical reliability of the device.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0113095 filed on August 22, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to integrated circuit devices. More specifically, this invention relates to integrated circuit devices including field-effect transistors. Background Technology

[0004] With the development of electronic technology, the demand for high integration of integrated circuit devices is increasing, and miniaturization is rapidly advancing. The miniaturization of integrated circuit devices leads to short-channel effects in transistors, which degrades the reliability of integrated circuit devices. To mitigate short-channel effects, integrated circuit devices with multi-gate structures, such as nanosheet transistors, have been proposed. Summary of the Invention

[0005] The present invention provides an integrated circuit device with improved operating characteristics and / or improved reliability.

[0006] Furthermore, the purpose of this invention is not limited to the above-described purposes, and other purposes not described herein will be clearly understood by those skilled in the art from the following description.

[0007] To achieve the above objectives, the present invention provides the following integrated circuit device.

[0008] According to one aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a fin-type active region protruding from a substrate and extending in a first direction; a first semiconductor pattern and a second semiconductor pattern spaced apart from each other in a second direction, the second direction intersecting the first direction, the first semiconductor pattern and the second semiconductor pattern being located above the fin-type active region; a gate line extending in the second direction, the gate line being located above the fin-type active region and surrounding the first semiconductor pattern and the second semiconductor pattern; a first source / drain region and a second source / drain region adjacent to the gate line above the fin-type active region, the first source / drain region being connected to the first semiconductor pattern, and the second source / drain region being connected to the second semiconductor pattern; and a lower thin film located on the fin-type active region and located below the first source / drain region in a third direction intersecting the first and second directions, wherein the second semiconductor pattern has a wider width in the second direction than the first semiconductor pattern.

[0009] According to another aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a fin-type active region protruding from a substrate and extending in a first direction; a first semiconductor pattern and a second semiconductor pattern spaced apart from each other in a second direction, the second direction intersecting the first direction, the first semiconductor pattern and the second semiconductor pattern being located above the fin-type active region; a gate line extending in the second direction above the fin-type active region and surrounding the first semiconductor pattern and the second semiconductor pattern; a first source / drain region and a second source / drain region adjacent to the gate line above the fin-type active region, the first source / drain region being connected to the first semiconductor pattern, and the second source / drain region being connected to the second semiconductor pattern; a first lower film located above the fin-type active region and below the first source / drain region; and a second lower film located above the fin-type active region and below the second source / drain region, wherein the second semiconductor pattern has a width greater than that of the first semiconductor pattern in the second direction, and the first lower film has a thickness greater than that of the second lower film in a third direction intersecting the first and second directions.

[0010] According to another aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a fin-type active region protruding from a substrate and extending in a first direction; a plurality of semiconductor patterns spaced apart from each other in a first direction and a second direction, the second direction intersecting the first direction, the plurality of semiconductor patterns being located above the fin-type active region; a gate line extending in the second direction above the fin-type active region and surrounding each of the plurality of semiconductor patterns; a plurality of source / drain regions adjacent to the gate line above the fin-type active region and respectively connected to the plurality of semiconductor patterns; and a lower thin film located above the fin-type active region and below at least one of the plurality of source / drain regions, wherein the width of a semiconductor pattern adjacent to a source / drain region overlapping with the lower thin film in the second direction is smaller than the width of another semiconductor pattern adjacent to a source / drain region not overlapping with the lower thin film in the second direction. Attached Figure Description

[0011] Some exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a schematic layout diagram illustrating an integrated circuit device according to some example embodiments;

[0013] Figures 2 to 9B This is a cross-sectional view illustrating a method of manufacturing an integrated circuit device according to some example embodiments; specifically, Figure 2 , Figure 3A , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 8A and Figure 9A Is along Figure 1 The cross-sectional view of the integrated circuit device corresponding to the section intercepted by line A1-A1', and Figure 3B , Figure 7B , Figure 8B and Figure 9B Is along Figure 1 A cross-sectional view of the integrated circuit device corresponding to the section intercepted by line A2-A2';

[0014] Figures 10 to 13B This is a cross-sectional view illustrating a method of manufacturing an integrated circuit device according to some example embodiments; specifically, Figure 10 , Figure 11A , Figure 12A and Figure 13A Is along Figure 1 The cross-sectional view of the integrated circuit device corresponding to the section intercepted by line A1-A1', and Figure 11B , Figure 12B and Figure 13B Is along Figure 1 A cross-sectional view of the integrated circuit device corresponding to the section intercepted by line A2-A2';

[0015] Figures 14 to 17B This is a cross-sectional view illustrating a method of manufacturing an integrated circuit device according to some example embodiments; and specifically, Figure 14 , Figure 15A , Figure 16A and Figure 17A Is along Figure 1 The cross-sectional view of the integrated circuit device corresponding to the section intercepted by line A1-A1', and Figure 15B , Figure 16B and Figure 17B Is along Figure 1 The cross-sectional view of the integrated circuit device corresponding to the section cut by line A2-A2'. Detailed Implementation

[0016] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes manufacturing or operational tolerances (e.g., ±10%) around said numerical value. Furthermore, when the terms “about” and “substantially” are used in conjunction with geometry, it is intended that the precision of the geometry is not required, but the degrees of freedom of the shape are within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified with “about” or “substantially,” it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around said numerical value or shape. When a range is specified, the range includes all values ​​within that range (such as increments of 0.1%).

[0017] It will be understood that elements and / or properties (e.g., structure, surface, orientation, etc.) that can be described as "perpendicular", "parallel", "coplanar" with respect to other elements and / or their properties (e.g., structure, surface, orientation, etc.) can be "perpendicular", "parallel", "coplanar" with respect to other elements and / or their properties, or can be "substantially perpendicular", "substantially parallel", "substantially coplanar" with respect to other elements and / or their properties, respectively.

[0018] A component and / or its characteristic that is “substantially perpendicular,” “substantially parallel,” or “substantially coplanar” relative to other components and / or their characteristics (e.g., structure, surface, orientation, etc.) will be understood as having a deviation of equal to or less than 10% (e.g., ±10% tolerance) in magnitude and / or angle relative to “perpendicular,” “parallel,” or “coplanar” relative to other components and / or their characteristics, respectively, within manufacturing tolerances and / or material tolerances.

[0019] In the following description, some exemplary embodiments are described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same elements, and repeated descriptions thereof are omitted.

[0020] Because this disclosure is subject to various modifications and has various exemplary embodiments, some exemplary embodiments are depicted in the accompanying drawings and described in detail in the detailed description. However, this is not intended to limit the scope to the depicted exemplary embodiments, and it should be understood that this disclosure covers all modifications, equivalents, and substitutions within the scope of the ideas and techniques disclosed herein. In describing some exemplary embodiments, detailed descriptions of relevant known techniques have been omitted where it was determined that such detailed descriptions might obscure the essential points of this disclosure.

[0021] Figure 1 This is a schematic layout diagram illustrating an integrated circuit device 100 according to some example embodiments. Figure 9A It is along Figure 1 A cross-sectional view of the integrated circuit device 100 taken by line A1-A1', and Figure 9B It is along Figure 1 A cross-sectional view of the integrated circuit device 100 taken by line A2-A2'.

[0022] Reference Figure 1 , Figure 9A and Figure 9BThe integrated circuit device 100 may include a transistor TR1 formed on a substrate 110, and the transistor TR1 may constitute a logic unit including a multi-bridge-channel field-effect transistor (MBCFET) device. In some example embodiments, the transistor TR1 may include a p-channel metal-oxide-semiconductor (PMOS) transistor or an n-channel metal-oxide-semiconductor (NMOS) transistor.

[0023] In some example embodiments, substrate 110 may include group IV semiconductors (such as Si and Ge), group IV-IV compound semiconductors (such as SiGe and SiC), or group III-V compound semiconductors (such as GaAs, InAs, and / or InP). Substrate 110 has a first surface 110F, and a plurality of fin-type active regions FA may protrude from the first surface 110F and extend along a first horizontal direction (X direction).

[0024] Device isolation film 112 may be disposed on the first surface 110F of substrate 110 and cover the underside of the sidewall of fin active region FA. Device isolation film 112 may fill the interior of device isolation trench 112T extending from the first surface 110F of substrate 110 into substrate 110 and may have a dual-layer structure, for example, an interface layer (not shown) and a buried insulating layer (not shown).

[0025] In some example embodiments, multiple semiconductor patterns NS may be spaced apart from each other in a vertical direction (Z direction) above the fin-type active region FA. In some example embodiments, the multiple semiconductor patterns NS may each include a group IV semiconductor (such as Si and / or Ge), a group IV-IV compound semiconductor (such as SiGe and / or SiC), or a group III-V compound semiconductor (such as GaAs, InAs, and / or InP).

[0026] Multiple semiconductor patterns NS may each have a relatively large width in the second horizontal direction (Y direction) and a relatively small thickness in the vertical direction (Z direction), and may have a shape such as a nanosheet. For example, as Figure 9A As shown, multiple semiconductor patterns NS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 spaced apart from each other in the vertical direction (Z direction) above the fin-type active region FA. However, the number of multiple semiconductor patterns NS is not limited to... Figure 9A The quantities shown. Each of the multiple semiconductor patterns NS can be used as a channel region.

[0027] In some example embodiments, each of the plurality of semiconductor patterns NS may have a width of about 5 nm to about 100 nm in the second horizontal direction (Y direction), and each of the plurality of semiconductor patterns NS may have a thickness of about 1 nm to about 10 nm in the vertical direction (Z direction), but the example embodiments are not limited thereto. In some example embodiments, at least one of the plurality of semiconductor patterns NS may have a different thickness in the vertical direction (Z direction) than the other semiconductor patterns NS.

[0028] In some example embodiments, a plurality of semiconductor patterns NS spaced apart from each other in the second horizontal direction (Y direction) may have different widths in the second horizontal direction (Y direction). For example, refer to Figure 9B The width of the semiconductor pattern NS formed on the left side in the second horizontal direction (Y direction) can be approximately 10 nm, and the width of the semiconductor pattern NS formed on the right side in the second horizontal direction (Y direction) can be approximately 30 nm. However, the inventive concept is not limited thereto, and Figure 9B This is just one example. The width of the semiconductor pattern NS in the second horizontal direction (Y direction) can include different values ​​ranging from about 5 nm to about 100 nm.

[0029] Multiple gate lines 120 may extend in a second horizontal direction (Y direction) to surround multiple semiconductor patterns NS, and may be spaced apart from each other in a first horizontal direction (X direction) by a first gate spacing CPP.

[0030] In some example embodiments, the multiple gate lines 120 may each comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof. For example, the gate lines 120 may include, but are not limited to, Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or combinations thereof. In some example embodiments, the multiple gate lines 120 may include a work function-containing metal layer (not shown) and a gap-filling metal film (not shown). The work function-containing metal layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and / or Pd. The gap-filling metal film may include a W film or an Al film. In some example embodiments, the multiple gate lines 120 may include a stacked structure of TiAlC / TiN / W, a stacked structure of TiN / TaN / TiAlC / TiN / W, or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W, but the example embodiments are not limited thereto.

[0031] In some example embodiments, each of the plurality of gate lines 120 may include a main gate 120M covering the uppermost semiconductor pattern NS and a sub-gate 120S located between two adjacent semiconductor patterns NS. For example, the main gate 120M may cover the upper surface of the third nanosheet N3, and the sub-gate 120S may be located between the fin active region FA and the first nanosheet N1, between the first nanosheet N1 and the second nanosheet N2, and between the second nanosheet N2 and the third nanosheet N3.

[0032] The gate insulating layer 122 may be located between the plurality of gate lines 120 and the plurality of semiconductor patterns NS. For example, the gate insulating layer 122 may be located between the uppermost semiconductor pattern NS and the main gate 120M of each of the plurality of gate lines 120, between the sub-gate 120S and each of the semiconductor patterns NS, and between the sub-gate 120S and the upper surface of the fin active region FA and / or the upper surface of the lower thin film 140.

[0033] In some example embodiments, the gate insulating layer 122 may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high-k dielectric film may include a metal oxide or a metal oxynitride. For example, high-k dielectric films that can be used as the gate insulating layer 122 may include, but are not limited to, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof.

[0034] External insulating spacers 124 may be located on the sidewalls of the main gate 120M of each of the plurality of gate lines 120. External insulating spacers 124 may be located at both ends of the uppermost semiconductor pattern NS, and each may be spaced apart from the gate line 120 with the gate insulating layer 122 located between the external insulating spacer 124 and the gate line 120. In some example embodiments, the external insulating spacer 124 may comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon carbonitride (SiC) x N y ), silicon dioxide (SiO2) x C y N z (or a combination thereof).

[0035] Multiple recesses RS1 and RS2 (or referred to as multiple recesses RS or first recess RS1 and second recess RS2) extending into the fin-type active region FA can be formed on both sides of multiple gate lines 120, and multiple source / drain regions 130 can be formed within the multiple recesses RS1 and RS2. The multiple source / drain regions 130 can be formed within the multiple recesses RS respectively, and can be connected to both ends of multiple semiconductor patterns NS.

[0036] In some example embodiments, the source / drain region 130 may include a buffer layer 132, a main semiconductor layer 134, and a capping layer 136. In some example embodiments, the buffer layer 132 may be located on the inner wall of each of the plurality of recesses RS and contact the plurality of semiconductor patterns NS. The main semiconductor layer 134 may fill the interior of each of the plurality of recesses RS and may have an upper surface located at a level higher than the uppermost semiconductor pattern NS. The capping layer 136 may cover the upper surface of the main semiconductor layer 134 and has a relatively small thickness.

[0037] In some example embodiments, the buffer layer 132 may be formed using a semiconductor material including a first element as a dopant. In some example embodiments, the first element may include at least one of fluorine, oxygen, argon, and / or nitrogen. In some example embodiments, the main semiconductor layer 134 may include at least one semiconductor material selected from SiGe, SiP, and / or SiGeB. The main semiconductor layer 134 may not include the first element as a dopant. In some example embodiments, the capping layer 136 may include a semiconductor material. For example, the capping layer 136 may include doped or undoped silicon. The capping layer 136 may cover the upper surface and sidewalls of the main semiconductor layer 134.

[0038] In some example embodiments, the lower thin film 140 may be formed beneath at least some of the plurality of source / drain regions 130. For example, see reference to Figure 9A At least a portion of the first recess RS1 may be filled with the lower thin film 140, and the other portion of the first recess RS1 may be filled with the active / drain region 130, but the interior of the second recess RS2 may be completely filled with the active / drain region 130.

[0039] In some example embodiments, the lower thin film 140 may be formed by an epitaxial process. In some example embodiments, the lower thin film 140 may comprise undoped Si, SiB, SiN, or a combination thereof. In this specification, the lower thin film 140 is illustrated as a single layer. However, this is merely an example, and it is clear that the lower thin film 140 may be formed as a multilayer.

[0040] In some example embodiments, for example, referring to Figure 17A and Figure 17BThe lower thin film 140 can be formed below all the plurality of source / drain regions 130. When the lower thin film 140 is formed in all the recesses RS1 and RS2, the thickness of the lower thin film 140 in the vertical direction (Z direction) can vary from one another depending on the width of the semiconductor pattern NS formed on the lower thin film 140 in the second horizontal direction (Y direction). For example, when the width of the semiconductor pattern NS in the second horizontal direction (Y direction) is relatively large, the thickness of the lower thin film 140 formed below the semiconductor pattern NS in the vertical direction (Z direction) can be less than when the width of the semiconductor pattern NS in the second horizontal direction (Y direction) is relatively small. The following describes in detail whether the lower thin film 140 is formed on the upper surface of the fin active region FA and its thickness.

[0041] A gate capping layer 126 may be disposed on multiple gate lines 120 and an external insulating spacer 124, and a passivation layer 142 covering the source / drain region 130 and an inter-gate insulating layer 144 may be formed between the multiple gate lines 120. In some example embodiments, the passivation layer 142 and the inter-gate insulating layer 144 may each comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon carbonitride (SiC) x N y ), silicon dioxide (SiO2) x C y N z (or a combination thereof).

[0042] Although not shown, a back-to-office (BEOL) structure may be disposed on the gate capping layer 126 and the inter-gate insulating layer 144. The BEOL structure may include contacts electrically connected to the source / drain regions 130 and / or the gate line 120, vias connected to the contacts, and metal lines connected to the vias.

[0043] In some example embodiments, a back-side power delivery network may also be formed on the bottom surface of the substrate 110, and connection structures (such as via contacts) may also be formed to connect the back-side power delivery network to the upper surface of the source / drain region 130 or to the lower surface of the source / drain region 130.

[0044] Typically, in multi-bridge channel field-effect transistor devices comprising multiple semiconductor patterns NS, forming gate lines around the multiple semiconductor patterns NS is a highly challenging process. Specifically, in the process of replacing sacrificial patterns between multiple semiconductor patterns with gate lines, electrical short circuits between the source / drain regions and the gate lines can occur. To address this, a method has been proposed to first form an epitaxial film under the source / drain regions before forming the source / drain regions. However, in devices comprising semiconductor patterns with varying horizontal thicknesses, current leakage, particularly under narrow semiconductor patterns, leads to device quality degradation.

[0045] However, according to some example embodiments, a thick epitaxial film is formed beneath a narrow semiconductor pattern, i.e., the thickness of the epitaxial film is formed differently depending on the horizontal width of the semiconductor pattern. Therefore, it is possible to prevent or reduce the possibility of electrical characteristic degradation and improve the electrical reliability of the semiconductor device.

[0046] Figures 2 to 9B This is a cross-sectional view illustrating a method of manufacturing an integrated circuit device 100 according to some example embodiments.

[0047] Specifically, Figure 2 , Figure 3A , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 8A and Figure 9A Is along Figure 1 The cross-sectional view of the integrated circuit device 100 corresponding to the cross section intercepted by line A1-A1', and Figure 3B , Figure 7B , Figure 8B and Figure 9B Is along Figure 1 The cross-sectional view of the integrated circuit device 100 corresponding to the section cut by line A2-A2'.

[0048] Reference Figure 2 A sacrificial layer 210 and a channel semiconductor layer PNS may be alternately and sequentially formed on the upper surface of the substrate 110. The stacked structure of the sacrificial layer 210 and the channel semiconductor layer PNS may be referred to as a channel semiconductor stack 210S.

[0049] In some example embodiments, the sacrificial layer 210 and the channel semiconductor layer PNS can be formed via an epitaxial process. In some example embodiments, the sacrificial layer 210 and the channel semiconductor layer PNS may comprise materials that are etch-selective relative to each other. For example, the sacrificial layer 210 and the channel semiconductor layer PNS may each comprise a single-crystal layer of a group IV semiconductor, a group IV-IV compound semiconductor, or a group II-IV compound semiconductor, and the sacrificial layer 210 and the channel semiconductor layer PNS may comprise different materials. In some example embodiments, the sacrificial layer 210 may comprise SiGe, and the channel semiconductor layer PNS may comprise single-crystal silicon.

[0050] In some example embodiments, the epitaxial process may include vapor phase epitaxy (VPE), chemical vapor deposition (CVD) processes (such as ultra-high vacuum (UHV) CVD), molecular beam epitaxy, or a combination thereof. During the epitaxial process, liquid or gaseous precursors may be used as precursors required to form the sacrificial layer 210 and the channel semiconductor layer PNS.

[0051] Reference Figure 3A and Figure 3B Subsequently, a hard mask pattern (not shown) extending to a specific length in the first horizontal direction (X direction) is formed on the uppermost channel semiconductor layer PNS. The hard mask pattern can then be used as an etching mask to etch the sacrificial layer 210, the channel semiconductor layer PNS, and the substrate 110. The stacked structure of the channel semiconductor layer PNS and the sacrificial layer 210 may have a line pattern shape extending in the first horizontal direction (X direction), and a device isolation trench 112T may be formed in the substrate 110 between the stacked line patterns of the channel semiconductor layer PNS and the sacrificial layer 210.

[0052] For example, the channel semiconductor layer PNS may include a first channel semiconductor layer PN1, a second channel semiconductor layer PN2, and a third channel semiconductor layer PN3 spaced apart from each other in a vertical direction (Z direction) above the first surface 110F of the substrate 110. The sacrificial layer 210 may be located between the upper surface of the substrate 110 and the first channel semiconductor layer PN1, between the first channel semiconductor layer PN1 and the second channel semiconductor layer PN2, and between the second channel semiconductor layer PN2 and the third channel semiconductor layer PN3.

[0053] The channel semiconductor layers PNS can extend in a first horizontal direction (X direction) and are spaced apart from each other in a second horizontal direction (Y direction). (See reference...) Figure 3BThe widths of the channel semiconductor layers PNS in the second horizontal direction (Y direction) can be different from each other. For example, the width of the left-side channel semiconductor layer PNS in the second horizontal direction (Y direction) can be a first width W1. Furthermore, the width of the right-side channel semiconductor layer PNS in the second horizontal direction (Y direction) can be a second width W2. In some example embodiments, the second width W2 can be greater than the first width W1. For example, the second width W2 can be greater than or equal to 30 nm (e.g., from about 30 nm to about 100 nm), and the first width W1 can be less than 30 nm (e.g., from about 30 nm to about 5 nm). In some example embodiments, the first width W1 can be about 10 nm, and the second width W2 can be about 30 nm, but the inventive concept is not limited thereto.

[0054] Subsequently, the interior of the device isolation trench 112T is filled with an insulating material, and the upper part of the insulating material is planarized. Thus, a device isolation film 112 filling the device isolation trench 112T can be formed. The fin-type active region FA can be defined in the substrate 110 through the device isolation film 112.

[0055] Subsequently, a sacrificial gate structure DG can be formed on the device isolation film 112 and the stacked line pattern of the channel semiconductor layer PNS and the sacrificial layer 210. Each of the sacrificial gate structures DG may include a sacrificial insulating layer pattern 222, a sacrificial gate line 224, a sacrificial gate spacer 226, and a sacrificial gate capping layer 228.

[0056] The sacrificial insulating layer pattern 222 may extend in a second horizontal direction (Y direction) and may be conformally formed on the upper surface and sidewalls of the stacked line pattern of the channel semiconductor layer PNS and the sacrificial layer 210, as well as on the upper surface of the device isolation film 112. In some example embodiments, the sacrificial insulating layer pattern 222 may include a material having etch selectivity with the sacrificial gate line 224, and may include at least one film selected, for example, from the group consisting of thermal oxides (silicon oxide) and / or silicon nitride.

[0057] The sacrificial gate line 224 may have a relatively large height on the sacrificial insulating layer pattern 222 to cover the stacked line pattern of the channel semiconductor layer PNS and the sacrificial layer 210. The upper surface of the sacrificial gate line 224 may have a flat horizontal plane. In some example embodiments, the sacrificial gate line 224 may comprise polysilicon, but the example embodiments are not limited thereto.

[0058] Sacrificial gate spacers 226 may be disposed on the sidewalls of the sacrificial gate line 224 and the sacrificial insulating layer pattern 222. In some example embodiments, the sacrificial gate spacers 226 may comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x Ny ), silicon carbonitride (SiC) x N y ), silicon dioxide (SiO2) x C y N z (or a combination thereof).

[0059] A sacrificial gate capping layer 228 may be disposed on the upper surface of the sacrificial gate line 224, and the two sidewalls of the sacrificial gate capping layer 228 may be covered by the sacrificial gate spacer 226. In some example embodiments, the sacrificial gate capping layer 228 may include a silicon nitride film.

[0060] Reference Figure 4 The stacked line patterns of the channel semiconductor layer PNS and the sacrificial layer 210, as well as a portion of the substrate 110, can be etched on both sides of the sacrificial gate structure DG, and thus, recesses RS1 and RS2 can be formed on both sides of the sacrificial gate structure DG. When recesses RS1 and RS2 are formed, the channel semiconductor layer PNS can be divided into multiple semiconductor patterns NS. For example, when recesses RS are formed, a structure in which multiple sacrificial layers 210 and multiple semiconductor patterns NS are alternately arranged can be formed on the fin active region FA.

[0061] The recesses RS1 and RS2 can be referred to as the first recess RS1 and the second recess RS2. The first recess RS1 and the second recess RS2 can be formed to the same depth and width using the same process.

[0062] In some example embodiments, such as Figure 4 As shown, recesses RS1 and RS2 may include sidewalls that extend continuously and are aligned with the two sidewalls of the sacrificial gate structure DG, for example, with the two sidewalls of the sacrificial gate spacer 226. For example, the sidewalls of each of the plurality of semiconductor patterns NS exposed by recesses RS1 and RS2 may be aligned with the sidewalls of the sacrificial gate spacer 226 and form a continuous sidewall profile.

[0063] Figure 4 Some example embodiments are shown, in which recesses RS1 and RS2 have substantially the same width over their entire height, and recesses RS1 and RS2 have vertical sidewall profiles. Therefore, the plurality of semiconductor patterns NS have substantially the same width in the first horizontal direction (X direction). However, in some example embodiments, the lower width of recesses RS1 and RS2 may be smaller than the upper width of recesses RS1 and RS2, and recesses RS1 and RS2 may have sloping sidewall profiles. Therefore, at least one of the plurality of semiconductor patterns NS (e.g., the lowermost semiconductor pattern NS or the first nanosheet N1) may have a larger width than the other semiconductor patterns NS.

[0064] Reference Figure 5 The sacrificial layer 210 exposed on the sidewalls of recesses RS1 and RS2 can be partially removed to form recesses EX. For example, the sacrificial layer 210 can be partially removed using a wet etching process or a dry etching process with etching conditions having selective etching characteristics relative to the sacrificial layer 210. In some example embodiments, each of the recesses EX may represent an inwardly recessed sidewall of the sacrificial layer 210 relative to the sidewalls of the plurality of semiconductor patterns NS, or may represent the space provided by the inwardly recessed sidewalls of the sacrificial layer 210 between semiconductor patterns NS that are adjacent to each other in the vertical direction (Z direction). Alternatively, in some example embodiments, the seed area of ​​silicon in the semiconductor patterns NS may be increased, and therefore, the semiconductor patterns NS may grow further than the sacrificial layer 210 in the first horizontal direction (X direction). As a result, recesses EX can be formed.

[0065] Reference Figure 6 A lower thin film 140 can be formed in the first recess RS1. The lower thin film 140 can be formed by an epitaxial process. The lower thin film 140 can have a first height h1 in the vertical direction (Z direction). For example, the first height h1 can be greater than or equal to 8 nm, but the inventive concept is not limited thereto. Figure 6 The diagram shows that the upper surface of the lower film 140 is at the same vertical height as the upper surface of the finned active region FA. However, this is merely an example, and the inventive concept is not limited thereto. In some exemplary embodiments, the upper surface of the lower film 140 may be at a vertical level lower than the upper surface of the finned active region FA (see [reference]). Figure 10 ).

[0066] The lower thin film 140 may comprise undoped Si, SiB, SiN, or combinations thereof. Although Figure 6 The lower film 140 is shown to be formed as a single layer, but the lower film 140 may be formed as a double layer or multiple layers.

[0067] Reference Figure 7A and Figure 7BSource / drain regions 130 can be formed within recesses RS1 and RS2. For example, source / drain regions 130 can be formed on a lower thin film 140 in the first recess RS1 by epitaxially growing semiconductor material from the surfaces of a plurality of semiconductor patterns NS, sacrificial layer 210, and substrate 110 exposed on the inner walls of the first recess RS1. Source / drain regions 130 can be formed in the second recess RS2 by epitaxially growing semiconductor material from the surfaces of a plurality of semiconductor patterns NS, sacrificial layer 210, and substrate 110 exposed on the inner walls of the second recess RS2. Source / drain regions 130 can be formed by sequentially forming a buffer layer 132, a main semiconductor layer 134, and a capping layer 136 on the inner walls of each of the recesses RS1 and RS2. For example, in some example embodiments, the main semiconductor layer 134 may contact the top surface of the lower thin film 140. In some example embodiments, in the second recess RS2, the buffer layer 132 may contact the sidewall of the substrate 110 defining the second recess RS2. In some example embodiments, the first recess RS1 may include a lower film 140, and the lower film may be omitted from the second recess RS2. However, as described below, the example embodiments are not limited thereto, and both the first recess RS1 and the second recess RS2 may include the lower film 140.

[0068] In some example embodiments, a buffer layer 132 may be formed on the inner walls of the recesses RS1 and RS2 to a thickness that does not completely fill the interior of the recesses RS1 and RS2. The buffer layer 132 may contact the surfaces of the plurality of semiconductor patterns NS, the sacrificial layer 210, and the substrate 110 exposed on the inner walls of the recesses RS1 and RS2.

[0069] In some example embodiments, the buffer layer 132 may be formed using a semiconductor material that includes a first element as a dopant. In some example embodiments, the first element may include at least one of fluorine, oxygen, argon, and / or nitrogen.

[0070] For example, the buffer layer 132 can be epitaxially grown by using the sidewalls of the semiconductor pattern NS exposed on the inner walls of the recesses RS1 and RS2, the sidewalls of the sacrificial layer 210 exposed on the inner walls of the recesses RS1 and RS2 (e.g., the exposed surface of the recess EX), and the upper surface of the substrate 110 exposed on the bottom of the recesses RS1 and RS2 (in the case of the second recess RS2) or the upper surface of the lower thin film 140 (in the case of the first recess RS1) as seed layers.

[0071] In some example embodiments, the main semiconductor layer 134 may have a relatively large thickness on the buffer layer 132 to fill the interior of the recesses RS1 and RS2. In some example embodiments, the upper surface of the main semiconductor layer 134 may be located at a higher level than the uppermost semiconductor pattern NS.

[0072] In some example embodiments, the main semiconductor layer 134 can be formed using at least one semiconductor material selected from SiGe, SiP, and SiGeB. The main semiconductor layer 134 can be epitaxially grown by using the inner wall of the buffer layer 132 as a seed layer.

[0073] In some example embodiments, the capping layer 136 may include a semiconductor material. For example, the capping layer 136 may include doped silicon or undoped silicon. The capping layer 136 may be formed to cover the upper surface and sidewalls of the main semiconductor layer 134 with a relatively small thickness.

[0074] Subsequently, a passivation layer 142 and an inter-gate insulating layer 144 may be formed to cover the sacrificial gate structure DG and the source / drain region 130. The passivation layer 142 may have a small thickness, and the inter-gate insulating layer 144 may have a relatively large height to fill the space between two adjacent sacrificial gate structures DG. The upper surface of the inter-gate insulating layer 144 may be coplanar with the upper surface of the sacrificial gate structure DG.

[0075] Reference Figure 8A and Figure 8B The sacrificial gate capping layer 228 can be removed by planarizing the upper surface of the sacrificial gate structure DG and the inter-gate insulating layer 144. The upper surface of the sacrificial gate line 224 can be exposed by the planarization process.

[0076] Subsequently, the sacrificial gate line 224 and the sacrificial insulating layer pattern 222 can be removed to form a gate space GSS. For example, the gate space GSS can be defined between two adjacent sacrificial gate spacers 226, and the sidewalls and top surfaces of the plurality of semiconductor patterns NS and the sidewalls of the sacrificial layer 210 can be exposed to the gate space GSS.

[0077] Subsequently, the multiple sacrificial layers 210 retained on the fin active region FA can be removed by the gate space (GSS), thereby partially exposing the multiple semiconductor patterns NS, the upper surface of the fin active region FA, and the upper surface of the lower thin film 140. The process for removing the multiple sacrificial layers 210 may include a wet etching process that utilizes the difference in etch selectivity between the sacrificial layers 210 and the multiple semiconductor patterns NS.

[0078] Reference Figure 9A and Figure 9BA gate insulating layer 122 can be formed on the surface exposed to the gate space GSS. Subsequently, gate lines 120 can be formed on the gate insulating layer 122 to fill the gate space GSS. For example, a work function conductive layer (not shown) can be conformally formed on the inner wall of the gate space GSS, and then a buried conductive layer (not shown) can be formed on the work function conductive layer. As a result, the gate space GSS can be filled. The upper portion of the buried conductive layer can then be planarized to expose the upper surface of the inter-gate insulating layer 144, thereby forming the gate lines 120.

[0079] In some example embodiments, a function control layer can be formed using Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlC, TiAlN, TaCN, TaC, TaSiN, or combinations thereof. A buried conductive layer can be formed using Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlC, TiAlN, TaCN, TaC, TaSiN, or combinations thereof.

[0080] Subsequently, the upper portions of the gate line 120, the gate insulating layer 122, and the sacrificial gate spacer 226 can be partially removed, and the gate capping layer 126 can be formed on the upper portion of the gate space GSS. Here, the remaining portion of the sacrificial gate spacer 226 can be referred to as the outer insulating spacer 124.

[0081] Through the above process, an integrated circuit device 100 can be formed.

[0082] To minimize or reduce current leakage from a narrow semiconductor pattern NS in the second horizontal direction (Y direction) to the source / drain region 130 below it, a lower thin film 140 of a certain thickness is selectively formed below the source / drain region 130 corresponding to the narrow semiconductor pattern NS. Therefore, the integrated circuit device 100 can have improved electrical reliability.

[0083] Figures 10 to 13B This is a cross-sectional view illustrating a method of manufacturing an integrated circuit device 100a according to some example embodiments. Specifically, Figure 10 , Figure 11A , Figure 12A and Figure 13A Is along Figure 1 The cross-sectional view of the integrated circuit device 100a corresponding to the cross section intercepted by line A1-A1', and Figure 11B , Figure 12B and Figure 13B Is along Figure 1 The cross-sectional view of the integrated circuit device 100a corresponding to the section cut by line A2-A2'.

[0084] Will understand, Figures 10 to 13B The integrated circuit device 100a is not in accordance with the reference. Figures 1 to 9B The described integrated circuit devices 100 are mutually exclusive, and elements with the same reference numerals represent the same components. Hereinafter, repeated descriptions of the same components are omitted, and the descriptions mainly focus on those related to... Figures 1 to 9B The difference between the integrated circuit device 100.

[0085] Figures 10 to 13B Some manufacturing processes of the integrated circuit device 100a can be compared with those of the reference. Figure 2 , Figure 3A , Figure 3B , Figure 4 and Figure 5 The manufacturing process of the described integrated circuit device 100 is performed in the same manner.

[0086] Reference Figure 10 ,exist Figure 5 As a result, the lower film 140 can partially fill the first recess RS1. The lower film 140 can be formed by an epitaxial process. The lower film 140 can have a first height h1' in the vertical direction (Z direction). The upper surface of the lower film 140 can be located at a vertical level lower than the upper surface of the fin-type active region FA.

[0087] The lower thin film 140 may comprise undoped Si, SiB, SiN, or combinations thereof. Although Figure 10 The lower film 140 is shown to be formed as a single layer, but the lower film 140 may be formed as a double layer or multiple layers.

[0088] Reference Figure 11A and Figure 11B Source / drain regions 130 can be formed within recesses RS1 and RS2. For example, source / drain regions 130 can be formed on a lower thin film 140 in the first recess RS1 by epitaxially growing semiconductor material from the surfaces of a plurality of semiconductor patterns NS, sacrificial layer 210, and substrate 110 exposed to the inner wall of the first recess RS1. Source / drain regions 130 can be formed in the second recess RS2 by epitaxially growing semiconductor material from the surfaces of a plurality of semiconductor patterns NS, sacrificial layer 210, and substrate 110 exposed to the inner wall of the second recess RS2. In some example embodiments, a buffer layer 132 in the first recess RS1 can extend between the main semiconductor layer 134 and the lower thin film 140. In some example embodiments, the buffer layer 132 can at least partially cover the sidewalls of the substrate 110 in the first recess RS1. In some example embodiments, the first buffer layer 132 can cover the exposed inner wall of the second recess RS2 defined by the substrate 110.

[0089] The source / drain region 130 can be formed by sequentially forming a buffer layer 132, a main semiconductor layer 134, and a capping layer 136 on the inner walls of each of the recesses RS1 and RS2. Subsequently, a passivation layer 142 and an inter-gate insulating layer 144 can be formed to cover the sacrificial gate structure DG and the source / drain region 130.

[0090] form Figure 11A and Figure 11B The method of forming the buffer layer 132, main semiconductor layer 134, capping layer 136, passivation layer 142 and gate insulating layer 144, and the constituent materials of each layer, may be the same as the method of forming the buffer layer 132, main semiconductor layer 134, capping layer 136, passivation layer 142 and gate insulating layer 144 of the integrated circuit device 100, and the constituent materials of each layer.

[0091] Because in Figure 11A In the cross-section taken along line A1-A1', the upper surface of the lower thin film 140 is located at a vertical horizontal position lower than the upper surface of the fin-type active region FA, therefore in Figure 11B In the cross-section taken along line A2-A2', the buffer layer 132 can be shown as exposed on the device isolation film 112. Figure 11B The section taken along line A2-A2' is shown as being located between the lower film 140 and the lowest sacrificial layer 210.

[0092] Reference Figure 12A and Figure 12B The sacrificial gate capping layer 228 can be removed by planarizing the upper surface of the sacrificial gate structure DG and the inter-gate insulating layer 144. The upper surface of the sacrificial gate line 224 can be exposed by the planarization process.

[0093] Subsequently, the sacrificial gate line 224 and the sacrificial insulating layer pattern 222 are removed to form the gate space GSS, and the plurality of sacrificial layers 210 retained on the fin active region FA are removed through the gate space GSS. Therefore, the plurality of semiconductor patterns NS, the upper surface of the fin active region FA, and the upper surface of the buffer layer 132 are partially exposed. During the above process, the lower thin film 140 may not be exposed by the buffer layer 132.

[0094] Reference Figure 13A and Figure 13BA gate insulating layer 122 can be formed on the surface exposed to the gate space GSS, and then a gate line 120 filling the gate space GSS can be formed on the gate insulating layer 122. Subsequently, the upper portion of the gate line 120, the gate insulating layer 122, and the sacrificial gate spacer 226 can be partially removed, and a gate capping layer 126 can be formed on the upper portion of the gate space GSS. Here, the remaining portion of the sacrificial gate spacer 226 can be referred to as the outer insulating spacer 124.

[0095] Through the above process, an integrated circuit device 100a can be formed.

[0096] Except that the upper surface of the lower thin film 140 formed in the first recess RS1 is located at a vertical level lower than the upper surface of the fin active region FA, the integrated circuit device 100a may have almost the same characteristics and effects as the integrated circuit device 100.

[0097] Figures 14 to 17B This is a cross-sectional view illustrating a method of manufacturing an integrated circuit device 100b according to some example embodiments. Specifically, Figure 14 , Figure 15A , Figure 16A and Figure 17A Is along Figure 1 The cross-sectional view of the integrated circuit device 100b corresponding to the cross section intercepted by line A1-A1', and Figure 15B , Figure 16B and Figure 17B Is along Figure 1 The cross section taken by line A2-A2' corresponds to the cross section of integrated circuit device 100b.

[0098] Will understand, Figures 14 to 17B The integrated circuit device 100b is not in accordance with the reference. Figures 1 to 9B The described integrated circuit devices 100 are mutually exclusive, and elements with the same reference numerals represent the same components. Hereinafter, repeated descriptions of the same components are omitted, and the descriptions mainly focus on those related to... Figures 1 to 9B The difference between the integrated circuit device 100.

[0099] Figures 14 to 17B Some manufacturing processes of the integrated circuit device 100b can be compared with those of the reference. Figure 2 , Figure 3A , Figure 3B , Figure 4 and Figure 5 The manufacturing process of the described integrated circuit device 100 is performed in the same manner.

[0100] Reference Figure 14 ,exist Figure 5As a result, the lower film 140 can partially fill each of the first recess RS1 and the second recess RS2. The lower film 140 can be formed by an epitaxial process. The lower film 140 formed in the first recess RS1 can have a first height h1 in the vertical direction (Z direction), and the lower film 140 formed in the second recess RS2 can have a second height h2 in the vertical direction (Z direction).

[0101] In some example embodiments, the first height h1 may be greater than the second height h2. For example, the first height h1 may be greater than or equal to 8 nm, and the second height h2 may be less than 8 nm. However, the inventive concept is not limited thereto.

[0102] To minimize or reduce current leakage from the semiconductor pattern NS, which has a different width in the second horizontal direction (Y direction), to the source / drain region 130 below, a lower thin film 140 disposed below the source / drain region 130 adjacent to the narrow semiconductor pattern NS is formed with a large thickness. Therefore, the integrated circuit device 100b can have improved electrical reliability. Thus, the first height h1 can be greater than the second height h2.

[0103] In some example embodiments, the lower film 140 formed in the first recess RS1 and the lower film 140 formed in the second recess RS2 may be formed simultaneously, or either of these lower films 140 may be formed first. In the case of forming the lower films 140 individually and sequentially, while the lower film 140 is formed first in one recess, the formation of an undesirable lower film in the other recess may be suppressed, for example, by means of a mask.

[0104] Figure 14 The upper surface of the lower thin film 140 formed in the first recess RS1 is shown to be coplanar with the upper surface of the fin active region FA, but this is only an example. As long as the relative relationship between the first height h1 and the second height h2 is satisfied, the upper surface of the lower thin film 140 can be located at a vertical level lower than the upper surface of the fin active region FA in the aforementioned integrated circuit device 100a.

[0105] The lower thin film 140 may comprise undoped Si, SiB, SiN, or combinations thereof. Although Figure 14 The lower film 140 is shown to be formed as a single layer, but the lower film 140 may be formed as a double layer or multiple layers.

[0106] Reference Figure 15A and Figure 15B Source / drain regions 130 can be formed within the recesses RS1 and RS2. For example, source / drain regions 130 can be formed on the lower thin film 140 by epitaxially growing semiconductor materials from the surfaces of multiple semiconductor patterns NS, sacrificial layer 210 and substrate 110 exposed to the inner walls of the recesses RS1 and RS2.

[0107] The source / drain region 130 can be formed by sequentially forming a buffer layer 132, a main semiconductor layer 134, and a capping layer 136 on the inner walls of each of the recesses RS1 and RS2. Subsequently, a passivation layer 142 and an inter-gate insulating layer 144 can be formed to cover the sacrificial gate structure DG and the source / drain region 130.

[0108] form Figure 15A and Figure 15B The method of forming the buffer layer 132, the main semiconductor layer 134, the capping layer 136, the passivation layer 142, and the gate insulating layer 144, as well as the constituent materials of each layer, may be the same as the method of forming the buffer layer 132, the main semiconductor layer 134, the capping layer 136, the passivation layer 142, and the gate insulating layer 144 in each of the integrated circuit devices 100 and 100a, as well as the constituent materials of each layer.

[0109] Because in Figure 15A In the cross-section taken along line A1-A1', the upper surface of the lower thin film 140 formed on the right side is located at a vertical level lower than the upper surface of the fin-type active region FA, therefore in Figure 15B In the cross-section taken along line A2-A2', the buffer layer 132 can be shown as exposed on the device isolation film 112. Figure 15B The section taken along line A2-A2' is shown as being between the lower film 140 and the lowest sacrificial layer 210. Although not shown separately, the buffer layer 132 can be used when the upper surface of the lower film 140 formed on the left is also located at a vertical level lower than the upper surface of the fin-type active region FA. Figure 15B The lower film 140 on both sides of the cross section of line A2-A2' is exposed.

[0110] Since the first depression RS1 and the second depression RS2 are formed to the same depth (see...) Figure 4 Therefore, it was formed in Figure 15B The lower films 140 on the left and right sides of the film may have the same vertical level on their lower surfaces.

[0111] Reference Figure 16A and 16B The sacrificial gate capping layer 228 can be removed by planarizing the upper surface of the sacrificial gate structure DG and the inter-gate insulating layer 144. The upper surface of the sacrificial gate line 224 can be exposed by the planarization process.

[0112] Subsequently, the sacrificial gate line 224 and the sacrificial insulating layer pattern 222 are removed to form the gate space GSS, and the plurality of sacrificial layers 210 retained on the fin active region FA are removed through the gate space GSS. Thus, the plurality of semiconductor patterns NS and the upper surface of the buffer layer 132 are partially exposed. During the above process, the lower thin film 140 may not be exposed by the buffer layer 132.

[0113] Reference Figure 17A and Figure 17B A gate insulating layer 122 can be formed on the surface exposed to the gate space GSS, and then a gate line 120 filling the gate space GSS can be formed on the gate insulating layer 122. Subsequently, the upper portion of the gate line 120, the gate insulating layer 122, and the sacrificial gate spacer 226 can be partially removed, and a gate capping layer 126 can be formed on the upper portion of the gate space GSS. Here, the remaining portion of the sacrificial gate spacer 226 can be referred to as the outer insulating spacer 124.

[0114] Through the above process, an integrated circuit device 100b can be formed.

[0115] Except that the thicknesses of the lower thin films 140 formed in the first recess RS1 and the second recess RS2 are different in the vertical direction (Z direction), the integrated circuit device 100b may have almost the same characteristics and effects as the integrated circuit device 100.

[0116] Although the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. An integrated circuit device, comprising: A fin-shaped active region that protrudes from the substrate and extends in a first direction; A first semiconductor pattern and a second semiconductor pattern spaced apart from each other in a second direction, the second direction intersecting the first direction, the first semiconductor pattern and the second semiconductor pattern being located above the fin active region; A gate line extending in the second direction, the gate line being located above the fin active region and surrounding the first semiconductor pattern and the second semiconductor pattern; A first source / drain region and a second source / drain region are located above the fin-type active region and adjacent to the gate line. The first source / drain region is connected to the first semiconductor pattern, and the second source / drain region is connected to the second semiconductor pattern. as well as The lower thin film is located on the finned active region and below the first source / drain region on a third direction intersecting the first and second directions. The second semiconductor pattern has a wider width than the first semiconductor pattern in the second direction.

2. The integrated circuit device as claimed in claim 1, wherein, The lower thin film includes undoped Si, SiB, SiN, or combinations thereof.

3. The integrated circuit device as claimed in claim 1, wherein, The vertical thickness of the lower film in the third direction is not less than 8 nm.

4. The integrated circuit device as claimed in claim 1, wherein, The upper surface of the lower film is at the same vertical level as the upper surface of the fin-shaped active region.

5. The integrated circuit device as claimed in claim 1, wherein, The upper surface of the lower film is located at a lower level than the upper surface of the fin-shaped active region.

6. The integrated circuit device as claimed in claim 1, wherein, The second semiconductor pattern has a width of 30 nm or more in the second direction.

7. The integrated circuit device as claimed in claim 1, wherein, The first semiconductor pattern has a width of less than 30 nm in the second direction.

8. The integrated circuit device as claimed in claim 1, wherein, The upper surface of the lower thin film is at least partially in contact with the first source / drain region.

9. The integrated circuit device as claimed in claim 1, wherein, The widths of the first semiconductor pattern and the second semiconductor pattern are equal in the first direction.

10. The integrated circuit device of claim 1, wherein, The first source / drain region and the second source / drain region each include a buffer layer, a main semiconductor layer, and a capping layer. The buffer layers of the first source / drain region and the second source / drain region are in contact with the first semiconductor pattern and the second semiconductor pattern, respectively. The main semiconductor layers of the first source / drain region and the second source / drain region are respectively located on the inner walls of the buffer layers of the first source / drain region and the second source / drain region, and The capping layers of the first source / drain region and the second source / drain region respectively cover the upper surface of the main semiconductor layer of the first source / drain region and the second source / drain region.

11. An integrated circuit device, comprising: A fin-shaped active region that protrudes from the substrate and extends in a first direction; A first semiconductor pattern and a second semiconductor pattern spaced apart from each other in a second direction, the second direction intersecting the first direction, the first semiconductor pattern and the second semiconductor pattern being located above the fin active region; A gate line that extends in the second direction above the fin-type active region and surrounds the first semiconductor pattern and the second semiconductor pattern; A first source / drain region and a second source / drain region are located above the fin-type active region and adjacent to the gate line. The first source / drain region is connected to the first semiconductor pattern, and the second source / drain region is connected to the second semiconductor pattern. The first lower film is located on the finned active region and below the first source / drain region; as well as The second lower film is located on the finned active region and below the second source / drain region. In the second direction, the second semiconductor pattern has a wider width than the first semiconductor pattern, and in a third direction intersecting the first and second directions, the first lower film has a thicker thickness than the second lower film.

12. The integrated circuit device of claim 11, wherein, The first lower film and the second lower film each comprise undoped Si, SiB, SiN or a combination thereof.

13. The integrated circuit device of claim 11, wherein, The lower surfaces of the first lower film and the second lower film have the same vertical horizontality.

14. The integrated circuit device of claim 11, wherein, The first lower film has a vertical thickness of not less than 8 nm, and the second lower film has a thickness of less than or equal to 8 nm in the third direction.

15. The integrated circuit device of claim 11, wherein, The second semiconductor pattern has a width of 30 nm or more in the second direction, and the first semiconductor pattern has a width of less than 30 nm in the second direction.

16. The integrated circuit device of claim 11, wherein, The upper surfaces of the first lower film and the second lower film are at least partially in contact with the first source / drain region and the second source / drain region, respectively.

17. The integrated circuit device of claim 11, wherein, The widths of the first semiconductor pattern and the second semiconductor pattern are equal in the first direction.

18. An integrated circuit device, comprising: A fin-shaped active region that protrudes from the substrate and extends in a first direction; Multiple semiconductor patterns are spaced apart from each other in a first direction and a second direction, the second direction intersecting the first direction, and the multiple semiconductor patterns are located above the fin active region; Gate lines that extend in the second direction above the fin-type active region and surround each of the plurality of semiconductor patterns; Multiple source / drain regions are located above the fin-type active region and adjacent to the gate line, and are respectively connected to the multiple semiconductor patterns; as well as The lower thin film is located above the finned active region and below at least one of the plurality of source / drain regions. The width of the semiconductor pattern adjacent to the source / drain region that overlaps with the lower thin film in the second direction is smaller than the width of another semiconductor pattern that is not adjacent to the source / drain region that overlaps with the lower thin film in the second direction.

19. The integrated circuit device of claim 18, wherein, The lower thin film includes undoped Si, SiB, SiN, or combinations thereof.

20. The integrated circuit device of claim 18, wherein, The lower films are located below all of the plurality of source / drain regions, and the vertical thicknesses of the lower films are different from each other.

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