Process method applied to semiconductor manufacturing process
By using multiple etching processes to remove the buffer layer and hard mask layer in semiconductor manufacturing, a protective layer is formed, which solves the problems of redundant areas and metal line short circuits caused by outward exposure and development, and improves the reliability and yield of products.
Patent Information
- Application Number
- CN202511784169.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-03-03
AI Technical Summary
In the semiconductor manufacturing process, redundant areas and short circuits in metal lines caused by outward exposure and development can affect product yield.
The buffer layer and hard mask layer of the target area are removed through multiple etching processes to form a protective layer to completely remove the hard mask layer residue. This process includes photolithography, dry etching and wet etching steps to form the desired pattern.
It improves the reliability and yield of semiconductor devices and solves the problem of hard mask layer residue caused by inward exposure and development.
Smart Images
Figure CN121604741A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a process method applied in semiconductor manufacturing. Background Technology
[0002] With the evolution of semiconductor integrated circuit manufacturing processes, at the 5-nanometer (nm) process node, the pitch width of metal lines in the back end of line (BEOL) process has been reduced to 28 nanometers. The pattern of this pitch needs to be realized by using a self-aligned quadruple patterning (SAQP) process through a photolithography machine.
[0003] Different regions on a wafer require different fabrication processes to form their patterns. Therefore, when fabricating a particular region, photolithography is used to open that region, allowing other regions to be covered by photoresist. For example, in back-end processes, some regions need to be formed using SADP (Self-aligned Double Patterning) and others using self-aligned double patterning (SADP). Thus, photolithography is used to open the SADP regions for the corresponding processes.
[0004] Due to overlay error (OVL), the area to be exposed needs to be "expanded" during the actual exposure process (i.e., the actual exposed pattern will be larger than the area to be exposed) to ensure that the area to be exposed is fully exposed. The following explanation uses the downstream process as an example to illustrate the outward expansion exposure and development.
[0005] refer to Figure 1 It shows a top view schematic diagram of the exposure and development extending outward along the X-axis. For example, as... Figure 1 As shown, region 101 is the area covered by photoresist, region 111 is the area opened by exposure and development after expanding outward in the X-axis direction, the area shown by the dashed line is the ideal exposure area, and the pattern 121 formed in region 111 is used to form metal lines. After the exposure and development of region 111 is opened outward in the X-axis direction, there is a risk of short circuit in the metal lines formed in pattern 121.
[0006] refer to Figure 2 It shows a top view schematic diagram after exposure and development extending outwards in the Y-axis direction. For example, as... Figure 2As shown, region 102 is the region covered by photoresist, region 112 is the region opened by exposure and development after expanding outward in the Y-axis direction, the region shown by the dashed line is the ideal exposure region, the pattern 122 formed in region 112 is used to form metal lines, after the exposure and development of region 122 is opened outward in the Y-axis direction, a redundant region 1221 will be formed.
[0007] As mentioned above, exposure and development through external expansion can lead to reduced yield (due to metal wire shorting) or the formation of redundant areas. Therefore, there is an urgent need to provide a new exposure and development process that can reduce the redundant areas after exposure and development while ensuring product yield. Summary of the Invention
[0008] This application provides a process method applied in semiconductor manufacturing, which can solve the problem of redundant regions formed by outward exposure and development in related technologies. The method includes:
[0009] The fourth buffer layer of the target area is removed by etching using photolithography. From a top view, the target area is located within the desired exposure area and its area is smaller than the area of the desired exposure area. The fourth buffer layer is formed on the third buffer layer, the third buffer layer is formed on the second buffer layer, the second buffer layer is formed on the first buffer layer, the first buffer layer is formed on the thin film layer, the thin film layer is formed above the substrate, and a patterned hard mask layer is formed in the third buffer layer.
[0010] Etching is performed to remove the third buffer layer of the target area, and a first groove is formed between the hard mask layers of the target area. During this etching process, the remaining photoresist is removed.
[0011] Etching is performed using the hard mask layer of the target area and the remaining fourth buffer layer as a mask. The etching stops at the first buffer layer, and a second groove is formed between the hard mask layers of the target area. During this etching process, the remaining fourth buffer layer is removed.
[0012] Remove the remaining third buffer layer;
[0013] A protective layer is formed on the exposed surface of the first buffer layer;
[0014] Etching is performed to remove the hard mask layer and the protective layer;
[0015] Using the second buffer layer as a mask, etching is performed to form a third groove in the first buffer layer. During this etching process, the remaining second buffer layer is removed.
[0016] In some embodiments, the etching process performed by photolithography to remove the fourth buffer layer in the target area includes:
[0017] Photoresist is covered on the fourth buffer layer, and the photoresist in the target area is removed by exposure and development in sequence.
[0018] Etching is performed to remove the fourth buffer layer of the target area.
[0019] In some embodiments, the hard mask layer includes a titanium oxide layer.
[0020] In some embodiments, the second buffer layer includes an LTO layer.
[0021] In some embodiments, the third buffer layer includes a SOC layer.
[0022] In some embodiments, the fourth buffer layer includes an ARC layer.
[0023] In some embodiments, the first buffer layer includes a silicon layer.
[0024] In some embodiments, forming a protective layer on the surface exposed by the first buffer layer includes:
[0025] Silicon oxide is formed as the protective layer in the area exposed by the first buffer layer through an oxidation reaction.
[0026] The technical solution of this application has at least the following advantages:
[0027] In the SAQP process of semiconductor devices, the target area is opened by photolithography. This target area is the area that is to be recessed within the target area. The third buffer layer is removed to expose the hard mask layer therein, forming a first groove. A second groove is formed between the patterned hard mask layers to expose the first buffer layer that needs to be etched at the bottom. A protective layer is formed in the area exposed by the first buffer layer, thereby removing the remaining hard mask layer and protective layer. Then, the desired pattern is etched in the first buffer layer. Since the hard mask layer can be completely removed by adjusting the etching parameters after the protective layer is formed, the problem of hard mask layer residue caused by recessed exposure and development is solved, which improves the reliability and yield of the device products. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0029] Figure 1 This is a top-view diagram showing the exposure and development process extending outwards along the X-axis.
[0030] Figure 2 This is a top view of the exposed and developed area extending outwards along the Y-axis.
[0031] Figure 3 This is a flowchart of a process method applied in semiconductor manufacturing, provided by an exemplary embodiment of this application;
[0032] Figures 4 to 12 This is a schematic diagram of the manufacturing process of a process method provided in an exemplary embodiment of this application. Detailed Implementation
[0033] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0036] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0037] refer to Figure 3 It illustrates a flowchart of a process method applied in semiconductor fabrication provided by an exemplary embodiment of this application, such as... Figure 3 As shown, the method includes:
[0038] Step S1: Etching is performed using photolithography to remove the fourth buffer layer of the target area. From a top-view perspective, the target area is located within the desired exposure area and its area is smaller than that of the desired exposure area. The fourth buffer layer is formed on the third buffer layer, the third buffer layer is formed on the second buffer layer, the second buffer layer is formed on the first buffer layer, the first buffer layer is formed on the thin film layer, the thin film layer is formed above the substrate, and a patterned hard mask layer is formed in the third buffer layer.
[0039] refer to Figure 4 It shows a top-view schematic diagram after the target area has been etched open; Reference Figure 5 It shows the edge after etching opens the target area. Figure 4 A cross-sectional view along the AA' direction. It should be noted that... Figure 4 and Figure 5 This is just an example, showing a partial area of the thin film layer on the substrate, and is not a completely one-to-one correspondence of the attached diagram.
[0040] For example, such as Figure 5 As shown, a thin film layer 210 is formed above a substrate (not shown in this embodiment). A first buffer layer 220 is formed on the thin film layer 210, a second buffer layer 230 is formed on the first buffer layer 220, a third buffer layer 250 is formed on the second buffer layer 230, and a fourth buffer layer 260 is formed on the third buffer layer 250. A patterned hard mask layer 240 is formed in the third buffer layer 250. Optionally, the top of the hard mask layer 240 is lower than the top of the third buffer layer 250. The second buffer layer 230, the hard mask layer 240, and the third buffer layer 250 contain different materials.
[0041] For example, such as Figure 4 As shown, viewed from above, the target area 200 is located within the desired exposure area. Figure 4 The target area 200 is located within the area indicated by the dashed line and its area is smaller than the area of the desired exposure area. Since the target area 200 is located within the desired exposure area and its boundary is recessed relative to the desired exposure area, this exposure and development method can be called "recessed".
[0042] Taking the application of this embodiment in a back-end process (in which the spacing between metal lines can be less than 30 nanometers) as an example, the thin film layer 210 may include a low-k insulating dielectric layer (a thin film layer made of a material with a dielectric constant k less than 4, for example, it may be a silicon dioxide (SiO2) layer or an oxygen-doped carbon silicon (ODC) layer), the first buffer layer 220 may include a silicon (Si) layer (which may be a polycrystalline silicon layer), the second buffer layer 230 may include a low-temperature oxide (LTO) layer, the hard mask layer 240 may include an oxide layer (for example, a titanium oxide (TiO) layer), the third buffer layer 250 may include a spin-on carbon (SOC) layer, and the fourth buffer layer 260 may include a metal anti-reflection coating (ARC) layer (for example, it may be a silicon layer).
[0043] For example, step S1 includes, but is not limited to: covering the fourth buffer layer 260 with photoresist 300, and removing the photoresist 300 of the target area 200 by exposure and development in sequence; performing etching to remove the fourth buffer layer 260 of the target area 200, and the etching stops at the third buffer layer 250.
[0044] Step S2: Etching is performed to remove the third buffer layer of the target area and form a first groove between the hard mask layers of the target area. During this etching process, the remaining photoresist is removed.
[0045] refer to Figure 6 This illustrates a cross-sectional view after the third buffer layer of the target area has been etched away. For example, as shown... Figure 6 As shown, the third buffer layer 250 of the target area 200 can be removed by a dry etching process, exposing the second buffer layer 230 of the target area 200. Since the hard mask layer 240 has a pattern, after the third buffer layer 250 filling the hard mask layer 240 is removed, the first groove 201 between the hard mask layers 240 of the target area is also exposed.
[0046] Step S3: Etching is performed using the hard mask layer of the target area and the remaining fourth buffer layer as a mask. The etching stops at the first buffer layer, and a second groove is formed between the hard mask layers of the target area. During this etching process, the remaining fourth buffer layer is removed.
[0047] refer to Figure 7 It shows a cross-sectional view after the second groove has been etched; Reference Figure 8 This illustrates a cross-sectional view after the remaining fourth buffer layer has been removed. For example, as shown... Figure 7As shown, etching can be performed using a dry etching process, stopping at the first buffer layer 220. A second groove 302 is formed between the hard masks 240 within the second buffer layer 230 of the target region 200. After the second groove 302 is formed, the remaining fourth buffer layer 260 can be thoroughly removed using a wet etching process. The effect after removal is as follows: Figure 8 As shown.
[0048] Step S4: Remove the remaining third buffer layer.
[0049] Step S5: A protective layer is formed on the exposed surface of the first buffer layer.
[0050] refer to Figure 9 This illustrates a cross-sectional view after a protective layer has been formed on the surface exposed by the first buffer layer. For example, as shown... Figure 9 As shown, the remaining third buffer layer 250 can be removed by a dry etching process, thereby forming a protective layer 221 on the exposed surface of the first buffer layer 220. If the first buffer layer 220 includes a silicon layer, oxygen (O2) can be introduced to form silicon oxide as the protective layer 221 in the exposed area of the first buffer layer 220 through an oxidation reaction.
[0051] Step S6: Etch to remove the hard mask layer and protective layer.
[0052] refer to Figure 10 This illustrates a cross-sectional view after etching away the hard mask layer and protective layer. For example, such as... Figure 10 As shown, the hard mask layer 240 and the protective layer 221 can be removed by dry etching. By adjusting the parameters in the dry etching process (e.g., at least one of the reaction gas, ion beam angle, gas flow rate, power, process chamber pressure, process chamber temperature, etc.), the selectivity ratio between the hard mask layer 240 and the second buffer layer 230 and the protective layer 221 can be adjusted so that the hard mask layer 240 and the protective layer 221 (since their thickness is smaller than that of the second buffer layer 230, they can be completely removed without causing the second buffer layer 230 to be over-etched) can be completely removed without causing the second buffer layer 230 to be over-etched.
[0053] Step S7: Using the second buffer layer as a mask, etching is performed to form a third groove in the first buffer layer. During this etching process, the remaining second buffer layer is removed.
[0054] refer to Figure 11 It shows a cross-sectional schematic diagram after the third groove is formed in the first buffer layer; Reference Figure 12 This illustrates a cross-sectional view after the remaining second buffer layer has been removed. For example, as shown... Figure 11As shown, a dry etching process can be used to form the third groove 203 in the first buffer layer. In subsequent processes, the first buffer layer 220 can be used as a mask for etching to form the final desired pattern in the thin film layer 210. After etching, the remaining second buffer layer 230 can be cleaned using a wet etching process to completely remove it. The effect after cleaning is as shown. Figure 12 As shown.
[0055] In related technologies, if exposure and development are performed using a recessed method, after opening the target area, etching is directly applied to the thin film layer. Then, a wet etching process is used to remove the second buffer layer and the hard mask layer. However, the hard mask layer under the photoresist layer is difficult to completely remove by wet etching, which affects the reliability of the device. In this embodiment, by etching multiple times to the first buffer layer, a protective layer is formed on the surface of the first buffer layer. Then, dry etching can more thoroughly remove the hard mask layer, solving the reliability problem caused by residual hard mask layers when using a recessed exposure and development method.
[0056] In summary, in the embodiments of this application, during the SAQP process of semiconductor devices, the target area is opened by photolithography. This target area is the area that is expected to be recessed within the target area. The third buffer layer is removed to expose the hard mask layer therein, forming a first groove. A second groove is formed between the patterned hard mask layers to expose the first buffer layer that needs to be etched at the bottom. A protective layer is formed in the area exposed by the first buffer layer, thereby removing the remaining hard mask layer and protective layer. Then, the required pattern is etched in the first buffer layer. Since the hard mask layer can be completely removed by adjusting the etching parameters after the protective layer is formed, the problem of hard mask layer residue caused by recessed exposure and development is solved, and the reliability and yield of the device product are improved.
[0057] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A process method applied in semiconductor fabrication, characterized in that, include: The fourth buffer layer of the target area is removed by etching using photolithography. From a top view, the target area is located within the desired exposure area and its area is smaller than the area of the desired exposure area. The fourth buffer layer is formed on the third buffer layer, the third buffer layer is formed on the second buffer layer, the second buffer layer is formed on the first buffer layer, the first buffer layer is formed on the thin film layer, the thin film layer is formed above the substrate, and a patterned hard mask layer is formed in the third buffer layer. Etching is performed to remove the third buffer layer of the target area, and a first groove is formed between the hard mask layers of the target area. During this etching process, the remaining photoresist is removed. Etching is performed using the hard mask layer of the target area and the remaining fourth buffer layer as a mask. The etching stops at the first buffer layer, and a second groove is formed between the hard mask layers of the target area. During this etching process, the remaining fourth buffer layer is removed. Remove the remaining third buffer layer; A protective layer is formed on the exposed surface of the first buffer layer; Etching is performed to remove the hard mask layer and the protective layer; Using the second buffer layer as a mask, etching is performed to form a third groove in the first buffer layer. During this etching process, the remaining second buffer layer is removed.
2. The method according to claim 1, characterized in that, The etching process, which removes the fourth buffer layer in the target area using photolithography, includes: Photoresist is covered on the fourth buffer layer, and the photoresist in the target area is removed by exposure and development in sequence. Etching is performed to remove the fourth buffer layer of the target area.
3. The method according to claim 2, characterized in that, The hard mask layer includes a titanium oxide layer.
4. The method according to claim 3, characterized in that, The second buffer layer includes an LTO layer.
5. The method according to claim 4, characterized in that, The third buffer layer includes the SOC layer.
6. The method according to claim 5, characterized in that, The fourth buffer layer includes the ARC layer.
7. The method according to claim 3, characterized in that, The first buffer layer includes a silicon layer.
8. The method according to claim 7, characterized in that, The formation of a protective layer on the surface exposed by the first buffer layer includes: Silicon oxide is formed as the protective layer in the area exposed by the first buffer layer through an oxidation reaction.