Grid mesh and preparation method thereof, ion source device and semiconductor equipment

Abstract

The invention provides a grid mesh, a preparation method thereof, an ion source device and semiconductor equipment, and relates to the technical field of semiconductors. The protective layers with uniform thickness and composition and stable performance are prepared on the surface of the grid mesh with grid mesh holes and the inner walls of the grid mesh holes, and the grid mesh using the protective layers effectively reduces particle pollution and / or trace element pollution introduced by the grid mesh in IBS and an ion beam etching process, stabilizes and prolongs the cycle time of a production process, and improves the production efficiency. And the production efficiency of the IBS and ion beam etching process is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a gate and its preparation method, an ion source device, and a semiconductor equipment. Background Technology

[0002] In the construction of ion sources that generate ion beams, the fabrication and quality control of the grid are crucial to the application of IBE (Ion Beam Etching) / FSE (Flexible Shaping Etch) in advanced process technologies.

[0003] Currently, the main types of gates include metal gates, graphite gates, and silicon gates. However, these gates can cause trace element contamination and / or particulate contamination during the manufacturing process.

[0004] Therefore, how to improve the grid to reduce or mitigate trace element pollution and / or particulate pollution is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above problems, this application provides a gate mesh and its fabrication method, an ion source device, and a semiconductor device, by preparing a protective layer with uniform thickness and composition and stable performance on the surface of the gate mesh having a distributed gate mesh aperture, and on the inner wall of the gate mesh aperture. The specific solution is as follows:

[0006] The first aspect of this application provides a method for preparing a grid, the method comprising:

[0007] A grid to be processed is provided, the grid having grid holes;

[0008] A protective layer is prepared on the surface of the grid to be treated and on the inner wall of the grid holes.

[0009] Preferably, in the above-described method for preparing the grid, the step of preparing a protective layer on the surface of the grid to be treated and on the inner wall of the grid openings includes:

[0010] A protective layer of carbon or silicon carbide material is prepared on the surface of the grid to be treated and on the inner wall of the grid holes.

[0011] Preferably, in the above-described method for preparing the grid, the step of preparing a protective layer on the surface of the grid to be treated and on the inner wall of the grid openings includes:

[0012] A protective layer is prepared on the surface of the grid to be treated and on the inner wall of the grid holes using an omnidirectional thin film deposition process.

[0013] Preferably, in the above-mentioned method for preparing the grid, the preparation of a protective layer on the surface of the grid to be treated and the inner wall of the grid holes based on the omnidirectional thin film deposition process includes:

[0014] A protective layer is prepared on the surface of the grid to be treated and on the inner wall of the grid holes using PECVD, ALD, CVD, or PIIP processes.

[0015] Preferably, in the above-described method for preparing the grid, when the grid to be processed is a metal grid, the preparation of a protective layer on the surface of the grid to be processed and the inner wall of the grid holes based on the omnidirectional thin film deposition process includes:

[0016] A protective layer is prepared on the surface of the metal grid and the inner wall of the grid holes based on one or a combination of the PECVD process, the ALD process, and the PIIP process.

[0017] Preferably, in the above-mentioned method for preparing the grid, the step of preparing a protective layer on the surface of the metal grid and the inner wall of the grid openings based on one or a combination of the PECVD process, the ALD process, and the PIIP process includes:

[0018] A protective layer is prepared on the surface of the metal grid and the inner wall of the grid holes in an environment with a temperature of less than 500°C, based on one or a combination of the PECVD process, the ALD process, and the PIIP process.

[0019] Preferably, in the above-mentioned method for preparing the grid, the step of preparing a protective layer on the surface of the metal grid and the inner wall of the grid holes based on one or a combination of the PECVD process, the ALD process, and the PIIP process at a temperature below 500°C includes:

[0020] In an environment with a temperature below 500°C, a protective layer with a thickness not exceeding 0.5 mm is prepared on the surface of the metal grid and the inner wall of the grid holes based on one or a combination of the PECVD process, the ALD process, and the PIIP process.

[0021] Preferably, in the above-mentioned method for preparing the grid, the step of preparing a protective layer on the surface of the metal grid and the inner wall of the grid holes based on one or a combination of the PECVD process, the ALD process, and the PIIP process at a temperature below 500°C includes:

[0022] In an environment with a temperature below 500°C, a protective layer with a thickness not exceeding 0.2 mm is prepared on the surface of the metal grid and the inner wall of the grid holes based on one or a combination of the PECVD process, the ALD process, and the PIIP process.

[0023] Preferably, in the above-described method for preparing the grid, when the grid to be treated is a graphite grid or a silicon carbide grid, the preparation of a protective layer on the surface of the grid to be treated and the inner wall of the grid holes based on the omnidirectional thin film deposition process includes:

[0024] A protective layer is prepared on the surface of the graphite grid or the silicon carbide grid and on the inner wall of the grid holes using the CVD process.

[0025] Preferably, in the above-described method for fabricating the grid, the step of preparing a protective layer on the surface of the graphite grid or the silicon carbide grid and on the inner wall of the grid openings using the CVD process includes:

[0026] Based on the CVD process, a protective layer with a thickness of at least 0.01 mm is prepared on the surface of the graphite grid or the silicon carbide grid and on the inner wall of the grid holes.

[0027] Preferably, in the above-described method for fabricating the grid, the step of preparing a protective layer on the surface of the graphite grid or the silicon carbide grid and on the inner wall of the grid openings using the CVD process includes:

[0028] Based on the CVD process, a protective layer with a thickness of at least 0.1 mm is prepared on the surface of the graphite grid or the silicon carbide grid and on the inner wall of the grid holes.

[0029] Preferably, in the above-mentioned method for preparing the grid, the thickness variation of the protective layer prepared by the omnidirectional thin film deposition process on the surface of the grid to be treated and the inner wall of the grid holes is less than 5% of the designed thickness of the protective layer.

[0030] Preferably, in the above-mentioned method for preparing the grid, the thickness variation of the protective layer prepared by the omnidirectional thin film deposition process on the surface of the grid to be treated and the inner wall of the grid holes is less than 1% of the designed thickness of the protective layer.

[0031] Preferably, in the above-described method for preparing the grid, the method further includes:

[0032] The grid with the protective layer is chemically cleaned.

[0033] Preferably, in the above-described method for preparing the grid, the chemical cleaning of the grid having the protective layer includes:

[0034] The grid with the protective layer is subjected to ultrasonic vibration treatment.

[0035] Preferably, in the above-mentioned method for preparing the grid, when the protective layer is a carbon material protective layer, the reaction gas used to form the carbon material protective layer includes a carbon-containing hydrocarbon chemical gas; the carbon-containing hydrocarbon chemical gas is one of C2H2, CH4, C2H4, and C3H8 or a mixture of at least two gases.

[0036] Preferably, in the above-described method for preparing the grid, when the protective layer is a silicon carbide material protective layer, the reaction gas used to form the silicon carbide material protective layer includes a silicon-containing reaction gas, wherein the silicon-containing reaction gas is SiH4 and / or SiCl4.

[0037] Preferably, in the above-described method for preparing the grid, when the protective layer is a silicon carbide material protective layer, the reaction gas used to form the silicon carbide material protective layer includes a carbon-containing hydrocarbon chemical gas; the carbon-containing hydrocarbon chemical gas is one of C2H2, CH4, C2H4, and C3H8 or a mixture of at least two gases.

[0038] Preferably, in the above-described method for preparing the grid, when the thickness of the protective layer to be prepared is greater than 5 μm, the surface roughness of the grid to be processed before preparing the protective layer is at least greater than 0.4 μm;

[0039] When the thickness of the protective layer to be prepared is greater than 30 μm, the surface roughness of the grid to be processed is at least greater than 2 μm before the protective layer is prepared.

[0040] A second aspect of this application provides a grid, which is obtained by the grid preparation method described in any one of the preceding claims.

[0041] A third aspect of this application provides an ion source device, the ion source device including the grid described above.

[0042] A fourth aspect of this application provides a semiconductor device, the semiconductor device including the gate described above.

[0043] Preferably, in the above-described semiconductor device, the semiconductor device is a semiconductor device that uses an ion source device.

[0044] By utilizing the above technical solutions, this application provides a gate and its preparation method, an ion source device, and a semiconductor device. By preparing a protective layer with uniform thickness and composition and stable performance on the surface of the gate with gate holes and on the inner wall of the gate holes, the use of the gate with the protective layer effectively reduces particulate contamination and / or trace element contamination introduced by the gate in IBS and ion beam etching processes, stabilizes and extends the cycle time of the production process, and increases the production efficiency of IBS and ion beam etching processes. Attached Figure Description

[0045] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0046] Figure 1 A schematic flowchart illustrating a method for fabricating a grid according to an embodiment of the present invention;

[0047] Figures 2-3 for Figure 1 A schematic diagram of a portion of the structure corresponding to the fabrication method of the grid shown;

[0048] Figure 4 A schematic flowchart of another method for preparing a grid according to an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of the cross-sectional microstructure of a carbon material protective layer with a thickness of approximately 50 micrometers deposited using a CVD process, provided as an embodiment of the present invention. Detailed Implementation

[0050] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0051] The Central Processing Unit (CPU), composed of semiconductor chips in an integrated circuit structure, is widely used in various everyday products such as medical devices, automobiles, and mobile phones, playing an increasingly important role in people's social lives. With the reduction of CPU feature size, the reduction of focal depth in photolithography equipment, and the trend towards 3D stacking of chip structures during the manufacturing process of very large-scale integrated circuits, more stringent requirements and challenges have been placed on the microscopic correction and planarization processes of the wafer chip morphology that form the CPU.

[0052] Currently, for devices with a minimum feature size of 0.35 micrometers or less, Chemical Mechanical Polishing (CMP) is the mainstream technology for achieving silicon wafer planarization. However, with the development of advanced technology nodes (above 22nm) and the emergence of new integration processes, such as the replacement of metal gates (RMGs), self-aligned contacts (SACs), and polysilicon aperture CMP, more challenges are posed to the thickness and morphological uniformity of chip structures (up to the nanometer or even angstrom level). Improper process control in CMP contact processing can lead to substrate defects, and particulate contamination induced by the polishing slurry, limiting its application and reducing yield. Furthermore, CMP technology currently cannot achieve high-precision planarization control at the nanometer or angstrom level, making it difficult to perform highly uniform and precise machining of replacement metal gates (RMGs) for Fin-FET nodes. These inherent drawbacks of CMP processes limit its application in advanced manufacturing processes where chip sizes are constantly shrinking.

[0053] In the past, ion beam shaping (IBS) techniques based on ion beam etching (IBE) and flexible shaping etching (FSE) for chip structures, such as micromachining and planarization, have provided new opportunities for precise control of chip thickness at the nanometer scale as the latest development in dry etching technology. This technology uses an ion source to bombard the wafer surface with neutral gas ions of a certain energy, removing or selectively removing surface material through physical sputtering. By optimizing the ion beam (energy, beam current density, and other parameters) during the process, the movement of colliding ions can be effectively controlled in the IBS process, achieving ultra-precision machining at the atomic level. By controlling the ion beam pulled out by the ion source during IBE / FSE, the incident angle of the bombarding ions can be adjusted, giving IBS a unique advantage in directional etching for surface micromachining, thereby achieving different etching rates at different incident ion angles on specific material surfaces. These characteristics enable IBS based on IBE / FSE technology to modify the surface roughness of chip patterns, truly achieving nanometer-level cross-wafer uniformity and flatness control (3σ < 15 Å within a 300mm wafer), meeting the stringent in-wafer uniformity targets of Fin-Fet and even GAA (Gate-All-Around) technologies. Furthermore, by adjusting the ion beam energy and angle, IBS can correct the shape and arrangement of EUV-generated chip patterns during EUV (Extreme Ultraviolet) patterning processes in chip manufacturing, replacing multiple EUV patterning processes, reducing the number of double or multiple EUV exposures, simplifying the processing flow of small-size, high-precision chips, and improving production efficiency. Therefore, IBE and FSE technologies are finding increasingly important applications in advanced manufacturing processes such as the miniaturization of advanced logic chip process nodes and the trend towards 3D memory chips.

[0054] However, based on the information described in the background art, the fabrication and quality control of the grid in the ion source structure for generating ion beams are crucial to the application of IBE / FSE in advanced process technologies. On one hand, the composition and function of the grid determine the beam current density, beam current distribution, and energy distribution of the energy-carrying ion beam formed by the ion source during IBE / FSE. On the other hand, the operational stability of the grid affects the working time cycle of the ion source and the efficiency with which the ion source maintains IBE / FSE. Furthermore, the selection and stability of the grid material are also crucial to particulate and trace element contamination in the IBE chamber.

[0055] Currently, Mo metal grids, widely used in ion sources, offer advantages such as good machinability, thermal stability, and stable service life, demonstrating excellent performance in ion beam processes based on Ar or Ar plus O2. However, in IBS processes using ion beams with specific energies (100eV-1200eV), the etching of the grid by the ion beam can induce trace amounts of Mo element contamination of the IBS process. This contamination becomes increasingly severe with the use of corrosive gases (such as Cl2, BCl3, HBr, CF4, CHF3, CH3F, C2H2, C2H4, and C3H8). These problems, including metal element contamination introduced by Mo grids, significantly limit the application of IBE technology in many critical process fabrications.

[0056] To mitigate trace metal contamination, high-purity graphite or silicon is used to fabricate the gate, replacing the Mo gate. While using high-purity graphite or silicon gates avoids introducing trace metal contamination, the ion beam's erosion of the gate during the IBS process, especially when using corrosive gases (such as Cl2, BCl3, HBr, CF4, CHF3, CH3F, C2H2, C2H4, and C3H8) to form the ion beam, can induce significant particulate contamination, affecting the normal operation of the IBS process. Furthermore, using sintered silicon carbide to fabricate the gate, due to the low purity of sintered silicon carbide, can also induce trace element contamination during both the IBS and ion beam etching processes.

[0057] In order to reduce or mitigate contamination from trace metal elements and particles, and to stabilize and extend the production cycle of IBS, it is urgent to develop and manufacture stable gates to improve their application in advanced chip manufacturing processes.

[0058] Based on this, this application provides a gate and its preparation method, an ion source device, and a semiconductor device. By preparing a protective layer with uniform thickness and composition and stable performance on the surface of the gate with gate holes and on the inner wall of the gate holes, the use of the gate with the protective layer effectively reduces particulate contamination and / or trace element contamination introduced by the gate in the IBS and ion beam etching processes, stabilizes and extends the cycle time of the production process, and increases the production efficiency of the IBS and ion beam etching processes.

[0059] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] refer to Figure 1 , Figure 1This is a schematic flowchart illustrating a method for fabricating a grid according to an embodiment of the present invention. The method for fabricating a grid according to an embodiment of the present invention includes:

[0061] S101: As Figure 2 and Figure 3 As shown, a grid 11 to be processed is provided, the grid 11 having grid holes 12.

[0062] Specifically, in this step, the grid 11 to be processed includes, but is not limited to, other forms of grids such as metal grids, graphite grids, silicon carbide grids, and silicon grids. Except for silicon carbide grids, the grid holes 12 of other grids can be prepared using different drilling techniques, such as mechanical drilling or laser drilling. Because silicon carbide grids have high hardness, the grid holes 12 of silicon carbide grids can be prepared using drilling techniques such as ultrasonic drilling or laser drilling.

[0063] To enhance the interfacial bonding between the gate 11 to be treated and the subsequently prepared protective layer 13, it is necessary to ensure that the surface roughness of the gate 11 to be treated increases appropriately with the increase of the thickness of the protective layer 13 before the preparation of the protective layer 13. In an optional embodiment of the present invention, when the thickness of the protective layer 13 to be prepared is greater than 5 μm, the surface roughness of the gate 11 to be treated before the preparation of the protective layer 13 is at least greater than 0.4 μm; when the thickness of the protective layer 13 to be prepared is greater than 30 μm, the surface roughness of the gate 11 to be treated before the preparation of the protective layer 13 is at least greater than 2 μm. This ensures a strong interfacial bonding between the gate 11 to be treated and the subsequently prepared protective layer 13, thereby improving the structural stability of the gate with the protective layer 13 and avoiding the risk of the protective layer falling off during the process.

[0064] S102: As Figure 3 As shown, a protective layer 13 is prepared on the surface of the grid 11 to be processed and on the inner wall of the grid holes 12.

[0065] Specifically, in this embodiment of the invention, since the grid made of carbon or silicon carbide does not introduce trace metal element contamination during the IBS process, and the grid made of carbon or silicon carbide has good electrical and thermal conductivity, the protective layer in this embodiment of the invention is a highly dense protective layer of carbon material or a protective layer 13 of silicon carbide material. That is, the protective layer 13 is prepared on the surface of the grid 11 to be treated and on the inner wall of the grid holes 12, including: preparing a protective layer 13 of carbon material or silicon carbide material on the surface of the grid 11 to be treated and on the inner wall of the grid holes 12.

[0066] A protective layer 13 is prepared on the surface of the grid 11 to be treated and the inner wall of the grid apertures 12 using a non-line-of-sight deposition thin film deposition process. In an optional embodiment of the present invention, the protective layer 13 is prepared on the surface of the grid 11 to be treated and the inner wall of the grid apertures 12 using a PECVD process, an ALD process, a CVD process, or a PIIP process.

[0067] In other words, this application employs advanced, comprehensive surface coating technology to deposit a high-purity, high-density carbon film or silicon carbide coating with uniform thickness and composition, and stable performance, as a protective layer 13, on the surface of a graphite, silicon, silicon carbide, or metal grid with distributed grid holes 12. By using the grid protected by the protective layer 13, particulate contamination and trace element contamination introduced by the ion source grid in the IBS and ion beam etching processes are effectively reduced, stabilizing and extending the cycle time of the production process, and increasing the production efficiency of the IBS and ion beam etching processes.

[0068] In an optional embodiment of the present invention, reference is made to... Figure 4 , Figure 4 This is a schematic flowchart illustrating another method for fabricating a grid according to an embodiment of the present invention. The method for fabricating a grid according to an embodiment of the present invention further includes:

[0069] S103: Perform chemical cleaning on the grid having the protective layer 13.

[0070] Specifically, in the embodiments of the present invention, although the surface coating preparation processes of the grid with protective layer 13 may differ, the thin film preparation process is completed in a vacuum chamber environment. The final chemical cleaning performed on the grid after it is removed from the coating chamber is mainly aimed at removing particles floating on the surface of protective layer 13. Therefore, in the embodiments of this application, the chemical cleaning of the grid is mainly based on ultrasonic vibration, avoiding the use of corrosive cleaning steps such as strong acids and strong alkalis.

[0071] In other words, the grid does not require any processing after being protected by a surface coating. It can be used directly after chemical cleaning to reduce particulate and trace element pollution.

[0072] The principles of PECVD, ALD, CVD, and PIIP processes will be briefly explained below.

[0073] Regarding CVD technology: One of the advanced all-around thin film deposition processes is Chemical Vapor Deposition (CVD), also known as thermochemical vapor deposition. CVD involves thermally decomposing reaction products at high temperatures (650℃-2500℃) to form high-vapor-pressure reaction gases. These gases condense on a substrate through a chemical reaction, forming numerous crystal nuclei. These nuclei aggregate into microcrystalline thin layers, which then continue to grow into a crystalline film. CVD offers advantages such as low investment, ease of continuous production, and simple operation. The basic condition for CVD in preparing silicon carbide films is heating the CVD reaction chamber to the silicon carbide film-forming temperature range, such as 1400℃-1800℃, and then introducing pyrolysis reaction gases with sufficient precursors (carbon and silicon sources). Commonly used silanes SiCl4 and SiH4 can provide silicon sources, while hydrocarbon gases CH4, C2H2, C2H4, and C3H8 can provide carbon sources. These reactive gases decompose at high temperatures to form silicon- and carbon-containing active components, which react on the substrate surface to form silicon carbide. Under the conditions of introducing C2H4 and CH4, the chemical reactions that form SiC during the CVD process are as follows.

[0074] SiH4(G) + CH4(G) = SiC(S) + 4H2(G)

[0075] Or 2SiH4(G) + C2H4(G) = 2SiC(S) + 6H2(G)

[0076] Here, S stands for Solid, and G stands for Gas, which represents gas.

[0077] Generally, by changing the flow rate of the reactant gas, the deposition temperature of the CVD process, and selecting substrates with different crystal structures, it is possible to prepare β-SiC phase films with complex face-centered cubic crystal structures, α-SiC phase films with close-packed hexagonal crystal structures, and dual-phase structures where β-SiC and α-SiC coexist. CVD-prepared silicon carbide films have the advantage of chemical purity greater than 99.999%, making them superhard materials second only to diamond and cubic boron nitride in hardness. It should be noted that this invention prioritizes the preparation of β-SiC phase films using the CVD process because the β-SiC phase structure exhibits more stable high-temperature chemical stability and better resistance to plasma etching than the α-SiC phase structure. Furthermore, by controlling the doping amounts of elements such as B, N, and P during the CVD process, the resistivity of the prepared silicon carbide film can be controlled, with a resistivity range from 0.1 Ω·cm to 1.0E8 Ω·cm.

[0078] For example, the resistivity of the prepared silicon carbide film is controlled by adjusting the doping amounts of elements such as B, N, and P during the CVD process. During the CVD silicon carbide coating preparation process, a gas containing nitrogen (e.g., N2), boron (e.g., boron trichloride and diborane), or phosphorus (e.g., phosphine, phosphorus trifluoride) is introduced to dope the deposited silicon carbide film with N, B, or P, thereby altering or controlling the resistivity of the formed silicon carbide coating. The resistivity of the silicon carbide coating ranges from 0.1 Ω·cm to 1.0E8 Ω·cm.

[0079] It should be noted that silicon carbide films prepared using CVD technology have the following advantages:

[0080] Advantage 1: High purity and high hardness; Advantage 2: Adjustable crystal structure and resistivity; Advantage 3: Capable of forming large-area films on flat substrates with a thickness of over 20mm; Advantage 4: Good corrosion resistance and plasma etching resistance; Advantage 5: Good thermal conductivity and thermal stability.

[0081] Based on ALD technology: One of the advanced all-around thin film deposition processes is atomic layer deposition (ALD). ALD involves the saturation chemisorption and reaction of precursor A with the substrate surface to form the first atomic layer. The remaining precursor A is then removed by purging. Precursor B is then introduced and re-chemisorbed onto the substrate surface, reacting with precursor A to form another pre-deposited layer. Byproducts and excess precursor B are removed by purging. This process is repeated cyclically to obtain the deposited thin film, and the film thickness is precisely controlled by the number of reaction cycles.

[0082] ALD (Alternating Layer Deposition) is a special chemical vapor deposition (CVD) process that grows films in single-atom-layer formations. The film growth process can generally be carried out in a low-temperature, low-pressure environment below 450°C. Unlike conventional CVD, the chemical precursor in ALD does not decompose before contacting the substrate surface. Instead, it undergoes a chemical decomposition reaction on the substrate surface after adsorption, and the resulting radicals uniformly cover the entire substrate surface, forming an atomic layer deposition. Therefore, by controlling the distribution of the reactive gas during ALD to ensure sufficient diffusion and contact of the chemical precursor with the component surface, and by allowing sufficient time for purging to remove any remaining precursors, ALD can form uniform multi-atom-layer stacked films on engineering components with complex geometries, the inner and outer walls of cylindrical tubes, and the inner surfaces of small pores. Because atomic-layer growth is achieved through the decomposition of the reactive precursor, ALD films have a dense structure, providing comprehensive surface coverage of the substrate component, and exhibiting excellent interfacial adhesion and thermal stability.

[0083] It should be noted that the ALD process and the resulting thin film have the following advantages:

[0084] Advantage 1: Low-temperature deposition forms dense films without pinholes; Advantage 2: It can form films over a large area on various substrate materials with complex shapes; Advantage 3: It can precisely control the composition and thickness of the film, and the thickness variation range can be increased from 1nm to more than 10um; Advantage 4: It has excellent film penetration, and the aspect ratio of the film can reach more than 1:200; Advantage 5: The film has good interfacial bonding and high thermal stability.

[0085] Regarding PIIP technology: One of the advanced omnidirectional thin film deposition processes is Plasma Immersion Ion Processing (PIIP). The principle of PIIP is to place the workpiece to be surface-treated within a coating chamber and connect it to a negatively biased power supply with pulsed functionality. When one or more external plasma generators within the PIIP reaction chamber ignite the reactive gases to form plasma, the workpiece is immersed and surrounded by the resulting plasma. Because the workpiece itself carries a pulsed negative bias, and due to variations in plasma density and its own bias voltage, the charged ions and active chemical radicals in the plasma surrounding the workpiece interact omnidirectionally with the workpiece surface. By adjusting the pulsed negative bias voltage of the workpiece itself according to the surface performance requirements of the workpiece, different modification treatments can be achieved on the workpiece surface. Under ultra-high pulse bias voltage (>30kV), all-round ion implantation (PIII) can be performed; within an appropriate bias voltage range (5kV-35kV), surface alloying or doping of the workpiece (Plasma Immersion Ion Alloying, PIIA) can be performed; under a lower negative bias voltage (<15kV), all-round coating on the workpiece surface (Plasma Immersion Ion Deposition, PIID) can be achieved; or under an even lower negative bias voltage (<1 kV), energetic ion bombardment cleaning (Plasma Immersion Ion Cleaning, PIIC) can be performed on the workpiece surface. Furthermore, since PIID is an all-around deposition of energetic ions on the workpiece surface under a lower negative bias voltage, PIID also has the function of Ion Beam Assisted Deposition (IBAD) and forms a dense thin film structure, and can be deposited on the workpiece surface at low temperature (<300℃).

[0086] PIIP (Polymerization Injection Process) offers numerous surface modification capabilities, enabling comprehensive surface treatment on a wide range of materials (metals, ceramics, plastics, etc.). Furthermore, the resulting film typically exhibits excellent interfacial adhesion due to the formation of a chemically mild interfacial transition layer on the workpiece surface. However, for small-diameter blind holes (<1 mm), PIIP often struggles to achieve uniform treatment on the inner surface of deep holes due to limitations imposed by gas diffusion and the formation of a plasma electric field distribution.

[0087] However, it should be noted that the thickness of the grid to be processed provided in this application is often less than 5 mm, and the diameter of the grid holes is at least greater than 1 mm. Therefore, using the PIIP process to prepare the protective layer will not result in the phenomenon that the inner walls of the grid holes cannot be effectively coated. This ensures that a high-purity, high-density carbon film or silicon carbide coating with uniform thickness and composition and stable performance can be deposited on the surface of the grid and the inner walls of the grid holes as a protective layer.

[0088] Based on PECVD technology, one of the advanced all-around thin film deposition processes is Plasma Enhanced Chemical Vapor Deposition (CVD). CVD is a method for preparing semiconductor thin films and other material thin films by using glow discharge to ionize the chemical vapor in a deposition chamber and then depositing the vapor on a substrate through chemical reactions. It enhances the activity of the chemical vapor reactants through plasma activation, increasing the surface reaction rate, and significantly reduces the film deposition temperature through high-energy ions. Under the action of plasma, the gas is dissociated in the chamber, forming a highly reactive substance containing gas molecules, high-energy ions, electrons, and active free radicals. On the deposition surface, not only are there conventional thermochemical reactions, but also complex plasma chemical reactions. The deposited film grows under the combined action of these two chemical reactions. The main methods for exciting glow discharge include: radio frequency excitation, DC high-voltage excitation, pulse excitation, and microwave excitation.

[0089] The main advantages of plasma-enhanced chemical vapor deposition are: low deposition temperature, minimal impact on the structure and physical properties of the substrate; fast deposition rate; good film thickness and composition uniformity; dense film structure with few pinholes; strong film adhesion; and wide range of applications, capable of preparing various metal films, inorganic films, and organic films, with extensive applications in semiconductor manufacturing, solar cells, coating technology, display panels, and other fields.

[0090] In an optional embodiment of the present invention, when the grid to be processed 11 is a metal grid, the preparation of a protective layer 13 on the surface of the grid to be processed 11 and the inner wall of the grid holes 12 based on the omnidirectional thin film deposition process includes:

[0091] A protective layer 13 is prepared on the surface of the metal grid and the inner wall of the grid holes 12 based on one or a combination of the PECVD, ALD, and PIIP processes. Optionally, the protective layer 13 is prepared on the surface of the metal grid and the inner wall of the grid holes 12 based on one or a combination of the PECVD, ALD, and PIIP processes at a temperature below 500°C. Optionally, a protective layer 13 with a thickness not exceeding 0.5 mm is prepared on the surface of the metal grid and the inner wall of the grid holes 12 based on one or a combination of the PECVD, ALD, and PIIP processes at a temperature below 500°C. Optionally, a protective layer 13 with a thickness not exceeding 0.2 mm is prepared on the surface of the metal grid and the inner wall of the grid holes 12 based on one or a combination of the PECVD, ALD, and PIIP processes at a temperature below 500°C.

[0092] When the gate 11 to be processed is a graphite gate or a silicon carbide gate, the preparation of a protective layer 13 on the surface of the gate 11 to be processed and the inner wall of the gate aperture 12 based on the omnidirectional thin film deposition process includes:

[0093] A protective layer 13 is prepared on the surface of the graphite grid or the silicon carbide grid and on the inner wall of the grid apertures 12 using the CVD process. Optionally, a protective layer 13 with a thickness of at least 0.01 mm is prepared on the surface of the graphite grid or the silicon carbide grid and on the inner wall of the grid apertures 12 using the CVD process. Optionally, a protective layer 13 with a thickness of at least 0.1 mm is prepared on the surface of the graphite grid or the silicon carbide grid and on the inner wall of the grid apertures 12 using the CVD process.

[0094] Specifically, in this embodiment of the invention, for gates made of different materials, corresponding omnidirectional coating processes can be adaptively employed to prepare the protective layer 13. Regarding the gate material, Mo metal has a high coefficient of thermal expansion, while Si has a low melting point. Therefore, when using CVD processes to perform surface coating on gates made of these materials, the CVD process often involves coating on the substrate material surface at temperatures between 950℃ and 1800℃, with the operating temperature close to or higher than the melting point of Si. This makes it difficult to achieve stable coating on Si material gate substrates. Furthermore, Mo's coefficient of thermal expansion is much higher than that of C and SiC materials. This causes the protective layer 13 of C material or SiC material deposited on the Mo gate surface during the CVD process to crack and peel off during the cooling process after coating due to the expansion effect of the Mo substrate and the C or SiC thin film. However, for grids with Mo or Si substrates, PECVD, ALD, and PIIP coating processes, or a combination of at least two of these processes, can be used to perform surface coating at substrate temperatures below 500°C. Since PECVD, ALD, and PIIP coating processes can be performed at lower temperatures, the requirements for coating equipment can be simplified, reducing production costs. However, coating processes performed at lower temperatures often have lower thin film growth rates, leading to longer coating cycle times and higher costs. Therefore, when using PECVD, ALD, and PIIP coating processes, or a combination of at least two of these coating processes, to prepare the protective layer 13 in this application, the thickness of the protective layer 13 on the surface of the metal grid and the inner wall of the grid holes 12 does not exceed 0.5 mm; preferably, when using PECVD, ALD, and PIIP coating processes, or a combination of at least two of these coating processes, to prepare the protective layer 13, the thickness of the protective layer 13 on the surface of the metal grid and the inner wall of the grid holes 12 does not exceed 0.2 mm, so as to ensure that the coating work is completed within a controllable coating process time.

[0095] For grids made of graphite or sintered silicon carbide, both have high melting points and similar coefficients of thermal expansion. Therefore, CVD (Continuous Chemical Deposition) can be used to deposit a protective layer 13 of carbon or silicon carbide onto the grid surface, allowing for sufficient thickness and high purity to be formed through high-temperature thermal decomposition. Compared to grids made of Mo metal, the risk of trace metal contamination introduced into the graphite and silicon carbide grids protected by the CVD-processed carbon or silicon carbide protective layer 13 is significantly reduced during the IBS (Integrated Metal Block) process. Therefore, when the protective layer 13 is prepared on a graphite grid or sintered silicon carbide grid using a CVD deposition process, the thickness of the protective layer 13 is at least greater than 0.01 mm on the surface of the graphite grid or sintered silicon carbide grid and on the inner wall of the grid holes 12. Preferably, when the protective layer 13 is prepared on a graphite grid or sintered silicon carbide grid using a CVD deposition process, the thickness of the protective layer 13 is at least greater than 0.1 mm on the surface of the graphite grid or sintered silicon carbide grid and on the inner wall of the grid holes 12, so as to ensure that the prepared grid can be processed for a sufficiently long time using processes such as IBS after being assembled with an ion source.

[0096] In an optional embodiment of the present invention, the thickness variation of the protective layer 13 prepared by the omnidirectional thin film deposition process on the surface of the grid 11 to be treated and the inner wall of the grid aperture 12 is less than 5% of the designed thickness of the protective layer 13. Optionally, the thickness variation of the protective layer 13 prepared by the omnidirectional thin film deposition process on the surface of the grid 11 to be treated and the inner wall of the grid aperture 12 is less than 1% of the designed thickness of the protective layer 13.

[0097] Specifically, in this embodiment of the invention, an omnidirectional coating process is used to uniformly coat the surface of the grid and the inner walls of the grid holes 12 on different material surfaces. Since the diameter of the grid holes 12 of the grid 11 to be treated provided in this application is at least greater than 1 mm, while the thickness of the grid 11 to be treated is often designed to be less than 5 mm, the omnidirectional coating in this embodiment of the invention can achieve a thickness variation of less than 5% of the designed thickness of the protective layer 13 on the grid surface and the inner walls of the grid holes 12; preferably, the thickness variation of the protective layer 13 prepared on the surface of the grid 11 to be treated and the inner walls of the grid holes 12 based on the omnidirectional thin film deposition process is less than 1% of the designed thickness of the protective layer 13.

[0098] refer to Figure 5 , Figure 5 This is a schematic diagram of the cross-sectional microstructure of a carbon material protective layer with a thickness of approximately 50 micrometers deposited using a CVD process, provided as an embodiment of the present invention. Figure 5As shown, the protective layer 13 of carbon material with a thickness of about 50 micrometers deposited by CVD process is microscopically magnified on the surface of graphite grid. Compared with graphite substrate, the protective layer 13 of carbon material deposited by CVD process has a very dense structure and a flat and smooth surface.

[0099] In summary, the present invention allows for sufficient dimensional variation in the thickness of the protective layer 13 when designing the grid. Therefore, when the surface-deposited film has a flat and smooth surface, no surface dimensional reprocessing is required for the film-covered protective grid, allowing for direct installation and use after chemical cleaning of the film-protected grid.

[0100] In an optional embodiment of the present invention, when the protective layer 13 is a carbon material protective layer 13, the reaction gas used to form the carbon material protective layer 13 includes a carbon-containing hydrocarbon chemical gas; the carbon-containing hydrocarbon chemical gas is one of C2H2, CH4, C2H4, C3H8 or a mixture of at least two gases.

[0101] When the protective layer 13 is a silicon carbide material protective layer 13, the reaction gas used to form the silicon carbide material protective layer 13 includes a silicon-containing reaction gas, which is SiH4 and / or SiCl4. The reaction gas used to form the silicon carbide material protective layer 13 includes a carbon-containing hydrocarbon chemical gas, which is one of C2H2, CH4, C2H4, and C3H8, or a mixture of at least two gases.

[0102] Specifically, the omnidirectional coating processes used in the embodiments of this invention, such as CVD, PECVD, ALD, and PIIP, share the common characteristic of relying on the thermal decomposition or plasma ionization decomposition of reactive gases to prepare the protective layer. In the deposition of the protective layer 13 of carbon material, preferred reactive gases include carbon-containing hydrocarbon chemical gases, such as ethylene (C2H2), methane (CH4), ethylene (C2H4), and propane (C3H8), etc. In the PECVD and PIIP processes, Ar or H2 can be used as the carrier gas in the thin film deposition process to maintain the stability of the plasma deposition process. In the deposition and preparation of the protective layer 13 of silicon carbide material, preferred Si-containing reactive gases include Saline (SiH4) and silicon chloride (SiCl4), which form silicon-containing active components through thermal decomposition or plasma ionization during thin film deposition. These components react with carbon-containing hydrocarbon chemical gases, such as ethylene (C2H2), methane (CH4), ethylene (C2H4), and propane (C3H8), through thermal decomposition to form carbon-containing active components. These react on the substrate surface to form the protective layer of silicon carbide material. Furthermore, hydrogen (H2) can also be used as a carrier gas during the CVD deposition of the protective layer of silicon carbide material.

[0103] In summary, most currently used Mo grids, graphite grids, and other grids made of other materials are formed through machining to create the final surface and inner surface of the grid holes. Surface damage to the grain structure caused by machining processes such as grinding can lead to particle and trace element contamination during the initial stages of IBS and ion beam etching processes, affecting production yield. In this embodiment of the invention, a protective layer 13 is prepared to protect the CIP grid. Because the protective layer has a surface with undamaged grain structure formed during the deposition process, particle and trace element contamination will not occur during the ion beam or plasma processes such as IBS.

[0104] It should be noted that this application specifically recommends using a protective layer 13 made of silicon carbide to protect the gate. Because silicon carbide gates prepared by CVD processes possess high purity, high hardness, and excellent resistance to plasma etching, CVD-prepared silicon carbide gate materials will not generate trace metal element contamination in related process applications such as IBE, FSE, IBD (Ion Beam Deposition), IBAD (Ion Beam Assisted Deposition), and Ion Implantation. This effectively eliminates the trace metal contamination problems caused by using Mo metal gates in IBS and IBE equipment, as well as the particulate contamination problems introduced by using graphite gates. Furthermore, even in process applications containing corrosive gases such as Cl, F, and Br, silicon carbide gates are less prone to forming non-volatile particulate contamination when etched. Combining these material properties, gates using a protective layer made of silicon carbide prepared by CVD processes can effectively improve process stability and increase production efficiency in related production processes such as IBE, FSE, IBD, IBAD, and Ion Implantation.

[0105] Based on the above embodiments of the present invention, another embodiment of the present invention also provides a grid, which is obtained by the grid preparation method described in any of the above embodiments.

[0106] Based on the above embodiments of the present invention, another embodiment of the present invention also provides an ion source device, the ion source device including the grid described in the above embodiments.

[0107] Based on the above embodiments of the present invention, another embodiment of the present invention also provides a semiconductor device, the semiconductor device including the gate described in the above embodiments.

[0108] The semiconductor equipment mentioned above includes semiconductor equipment and coating equipment that use ion source devices.

[0109] The foregoing has provided a detailed description of the grid and its preparation method, ion source device, and semiconductor equipment provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method of producing a grid, characterized by, The method for preparing the grid comprises: providing a grid to be processed, the grid to be processed having grid holes; preparing a protective layer on the surface of the grid to be processed and the inner wall of the grid holes.

2. The method of claim 1, wherein The method for preparing the protective layer on the surface of the grid to be processed and the inner wall of the grid holes comprises: preparing a protective layer of carbon material or silicon carbide material on the surface of the grid to be processed and the inner wall of the grid holes.

3. The method of claim 1-2, wherein The method for preparing the protective layer on the surface of the grid to be processed and the inner wall of the grid holes comprises: preparing the protective layer on the surface of the grid to be processed and the inner wall of the grid holes based on a full-area thin film deposition process.

4. The method of claim 3, wherein the grid is formed by a method comprising: The method for preparing the protective layer on the surface of the grid to be processed and the inner wall of the grid holes based on the full-area thin film deposition process comprises: preparing the protective layer on the surface of the grid to be processed and the inner wall of the grid holes based on a PECVD process, an ALD process, a CVD process or a PIIP process.

5. The method of claim 4, wherein the grid is formed by a method comprising: When the grid to be processed is a metal grid, the method for preparing the protective layer on the surface of the grid to be processed and the inner wall of the grid holes based on the full-area thin film deposition process comprises: preparing the protective layer on the surface of the metal grid and the inner wall of the grid holes based on one of the PECVD process, the ALD process, the PIIP process or a combination of at least two of the processes.

6. The method of claim 5, wherein the grid is formed by a method comprising: The method for preparing the protective layer on the surface of the metal grid and the inner wall of the grid holes based on one of the PECVD process, the ALD process, the PIIP process or a combination of at least two of the processes comprises: preparing the protective layer on the surface of the metal grid and the inner wall of the grid holes based on one of the PECVD process, the ALD process, the PIIP process or a combination of at least two of the processes at a temperature less than 500°C.

7. The method of claim 6, wherein the grid is formed by a method comprising: The method for preparing the protective layer on the surface of the metal grid and the inner wall of the grid holes based on one of the PECVD process, the ALD process, the PIIP process or a combination of at least two of the processes at a temperature less than 500°C comprises: preparing the protective layer on the surface of the metal grid and the inner wall of the grid holes based on one of the PECVD process, the ALD process, the PIIP process or a combination of at least two of the processes at a temperature less than 500°C, the thickness of the protective layer being not more than 0.5mm.

8. The method of claim 6, wherein the grid is formed by a method comprising: The method for preparing the protective layer on the surface of the metal grid and the inner wall of the grid holes based on one of the PECVD process, the ALD process, the PIIP process or a combination of at least two of the processes at a temperature less than 500°C comprises: preparing the protective layer on the surface of the metal grid and the inner wall of the grid holes based on one of the PECVD process, the ALD process, the PIIP process or a combination of at least two of the processes at a temperature less than 500°C, the thickness of the protective layer being not more than 0.2mm.

9. The method of claim 4, wherein the grid is formed by a method comprising: When the grid to be processed is a graphite grid or a silicon carbide grid, the protective layer is prepared on the surface of the grid to be processed and the inner wall of the grid hole by the all-around thin film deposition process, comprising: The protective layer is prepared on the surface of the graphite grid or the silicon carbide grid and the inner wall of the grid hole by the CVD process.

10. The method of claim 9, wherein the grid is prepared by a method comprising: The protective layer is prepared on the surface of the graphite grid or the silicon carbide grid and the inner wall of the grid hole by the CVD process, comprising: The protective layer is prepared on the surface of the graphite grid or the silicon carbide grid and the inner wall of the grid hole by the CVD process, comprising:

11. The method of claim 9, wherein the grid is prepared by a method comprising: The protective layer is prepared on the surface of the graphite grid or the silicon carbide grid and the inner wall of the grid hole by the CVD process, comprising: The protective layer is prepared on the surface of the graphite grid or the silicon carbide grid and the inner wall of the grid hole by the CVD process, comprising:

12. A method of producing a screen according to any one of claims 4 to 11, characterised in that, The protective layer is prepared on the surface of the graphite grid or the silicon carbide grid and the inner wall of the grid hole by the CVD process, comprising:

13. A method of producing a screen according to any one of claims 4 to 11, characterised in that, The thickness variation of the protective layer prepared on the surface of the grid to be processed and the inner wall of the grid hole by the all-around thin film deposition process is less than 5% of the designed thickness of the protective layer.

14. The method of claim 1, wherein The thickness variation of the protective layer prepared on the surface of the grid to be processed and the inner wall of the grid hole by the all-around thin film deposition process is less than 1% of the designed thickness of the protective layer. The method for preparing the grid further comprises:

15. The method of claim 14, wherein the grid is prepared by a method comprising: Chemical cleaning of the grid with the protective layer. The chemical cleaning of the grid with the protective layer, comprising:

16. The method of claim 2, wherein Ultrasonic oscillation treatment of the grid with the protective layer.

17. The method of claim 2, wherein When the protective layer is a carbon material protective layer, the reaction gas used to form the carbon material protective layer comprises a carbon-containing hydrocarbon chemical gas; the carbon-containing hydrocarbon chemical gas is one of C2H2, CH4, C2H4, C3H8 or a mixture of at least two gases.

18. The method of claim 2, wherein When the protective layer is a silicon carbide material protective layer, the reaction gas used to form the silicon carbide material protective layer comprises a silicon-containing reaction gas, and the silicon-containing reaction gas is SiH4 and / or SiCl4.

19. The method of claim 1, wherein When the protective layer is a silicon carbide material protective layer, the reaction gas used to form the silicon carbide material protective layer comprises a carbon-containing hydrocarbon chemical gas; the carbon-containing hydrocarbon chemical gas is one of C2H2, CH4, C2H4, C3H8 or a mixture of at least two gases. When the thickness of the protective layer to be prepared is greater than 5 μm, the surface roughness of the grid to be processed before preparing the protective layer is at least greater than 0.4 μm; 20. A screen, characterized by When the thickness of the protective layer to be prepared is greater than 30 μm, the surface roughness of the grid to be processed before preparing the protective layer is at least greater than 2 μm.

21. An ion source apparatus, comprising: The grid is obtained by the method for preparing the grid according to any one of claims 1-19.

22. A semiconductor device, comprising: The ion source device comprises the grid according to claim 20.

23. The semiconductor device of claim 22, wherein, The semiconductor device comprises the grid according to claim 20. The semiconductor device is a semiconductor device using an ion source device.

Images