Communication device and method for anti-jamming reconfigurable frequency hopping pattern

Abstract

The application discloses an anti-interference reconfigurable frequency hopping pattern communication device and method, relates to the technical field of wireless communication devices, and comprises a baseband module and an intermediate frequency processing module based on a field programmable gate array (FPGA), an AD conversion module, a DA conversion module, an up-conversion frequency mixer and a down-conversion frequency mixer connected with the baseband module and the intermediate frequency processing module based on the FPGA, and the device constitutes a transmitting chain and a receiving chain; the application has the beneficial effects that flexible frequency hopping pattern loading can be realized to adapt to communication between different devices, and the robustness of signal receiving is remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of wireless communication equipment technology, and more specifically, to a communication device and method with an anti-interference reconfigurable frequency hopping pattern. Background Technology

[0002] In the field of modern wireless communication technology, frequency hopping technology is widely used to combat interference, improve anti-interception capabilities, and enable multi-user access. Traditional frequency hopping communication equipment mostly uses fixed hardware, resulting in fixed functions and poor flexibility. With the development of software-defined radio technology, FPGA-based and digital processing-based solutions have gradually become mainstream, greatly enhancing their flexibility and reconfigurability.

[0003] For example, Chinese patent CN113472389B (hereinafter referred to as Document 1) discloses a "low-latency, configurable wireless fast frequency hopping system based on FPGA". This system also utilizes an FPGA to implement baseband signal processing, including RS encoding, DQPSK modulation, and digital frequency hopping, and configures parameters such as the frequency hopping table and keys via a host computer to achieve configurable frequency hopping communication. Its receiver processes the signal through a DDC, matched filtering, and frequency hopping synchronization module, and uses an AGC amplifier to control the gain of the received signal. However, Document 1 and the prior art still have some shortcomings:

[0004] 1. Lack of convenient system self-verification capability: After loading a new frequency hopping pattern or system parameters, File 1 requires actual wireless transceiver and peer equipment cooperation to verify its correctness. This process is cumbersome and not conducive to rapid debugging during the development phase and reliability verification before deployment.

[0005] 2. The power control mechanism is not precise enough: Document 1 mentions an AGC amplifier, which is an automatic gain control system. Its main purpose is to keep the amplitude of the receiver input signal within the optimal range of the AD conversion module to prevent signal clipping or excessive quantization noise. However, it is not a precise closed-loop power control system based on the target power value, especially at the transmitting end, where there is a lack of description of precise closed-loop control of the transmit power.

[0006] 3. Inadequate frequency offset correction mechanism: Frequency deviation between communication devices can severely affect demodulation performance. Document 1 mentions carrier synchronization, which is a standard demodulation step, but it does not disclose a clear closed-loop control mechanism that can actively compensate for and lock the system-level clock source frequency deviation.

[0007] Therefore, there is an urgent need in this field for a comprehensive communication device that not only enables high-performance frequency hopping communication, but also integrates convenient self-verification capabilities, precise adaptive power control, efficient bit error handling, and robust automatic frequency offset correction functions, so as to comprehensively improve the reliability, maintainability, and development efficiency of the system. Summary of the Invention

[0008] To overcome the shortcomings of the prior art, the present invention provides a high-performance anti-interference reconfigurable frequency hopping communication device and method that integrates internal self-loop verification, adaptive power control and automatic frequency offset control functions.

[0009] The technical solution adopted by this invention to solve its technical problem is: a communication device with anti-interference reconfigurable frequency hopping pattern, the improvement of which is that it includes a baseband module and an intermediate frequency processing module based on a field-programmable gate array (FPGA), an AD conversion module and a DA conversion module connected to the intermediate frequency processing module, and an up-conversion mixer and a down-conversion mixer connected to the baseband module. The AD conversion module is connected to the down-conversion mixer, and the up-conversion mixer is connected to the DA conversion module. The device constitutes a transmit link and a receive link; the device further includes:

[0010] The signal output from the up-conversion mixer in the transmit link is transmitted to the input of the down-conversion mixer in the receive link through an internal loop, so that the field-programmable gate array (FPGA) can perform self-loop testing and performance verification on the transmit and receive links.

[0011] The demodulation module within the FPGA is configured to estimate the frequency offset of the carrier frequency when receiving a signal and generate a frequency offset estimation signal. The FPGA also includes a frequency offset control module configured to fine-tune the frequency of the clock crystal oscillator that provides the operating clock for the FPGA, the AD conversion module, and the DA conversion module in a closed loop according to the frequency offset estimation signal, until the frequency offset estimation signal approaches zero.

[0012] In the above structure, the device further includes an adaptive power control mechanism, including a power detection circuit and a programmable attenuator connected to the transmit link and the receive link;

[0013] The field-programmable gate array (FPGA) is configured to: acquire the actual transmit or receive power value measured by the power detection circuit, compare it with the preset target power value, and automatically adjust the attenuation value of the programmable attenuator according to the comparison result, so as to stabilize the signal power near the target power value in a closed-loop manner.

[0014] In the above structure, the field-programmable gate array (FPGA) in the adaptive power control mechanism is configured to: decrease the attenuation value of the programmable attenuator when the actual power value is less than the target power value; and increase the attenuation value of the programmable attenuator when the actual power value is greater than the target power value.

[0015] In the above structure, the baseband module further includes a baseband serial port receiving module, a baseband data parsing module, a baseband processing module, a baseband serial port transmitting module, a baseband data packet assembly module, a frequency hopping control module, and a power adjustment module;

[0016] The baseband data parsing module, baseband data packet assembly module, frequency hopping control module, and power adjustment module are all connected to the baseband processing module. The baseband serial port receiving module is connected to the baseband data parsing module, and the baseband serial port transmitting module is connected to the baseband data packet assembly module.

[0017] The programmable attenuator includes a down-conversion attenuator circuit and an up-conversion attenuator circuit, and the power adjustment module is connected to the power detection circuit, the down-conversion attenuator circuit and the up-conversion attenuator circuit.

[0018] The frequency hopping control module is connected to the upconverter mixer and the downconverter mixer.

[0019] In the above structure, the intermediate frequency processing module further includes a channel decoding module;

[0020] The channel decoding module is configured to first perform RS decoding on the demodulated data to correct symbol errors in the data;

[0021] The channel decoding module is also configured to perform CRC verification on the data after RS ​​decoding;

[0022] The channel decoding module further includes a decision logic configured to: if the CRC check passes, determine that the data is correct and report it; if the CRC check fails, determine that the RS decoding was unsuccessful, mark the data as incorrect, and report the error status.

[0023] In the above structure, the intermediate frequency processing module further includes an intermediate frequency data packet assembly module, a demodulation module, an AD data acquisition module, an intermediate frequency data unpacking module, a channel coding module, a modulation module, an DA data transmission module, and an AD / DA configuration module;

[0024] The AD data acquisition module, demodulation module, channel decoding module, and intermediate frequency data packet assembly module are connected in sequence. The AD data acquisition module is connected to the AD conversion module, and the intermediate frequency data packet assembly module is connected to the baseband module.

[0025] The intermediate frequency data unpacking module, channel coding module, modulation module, and DA data transmission module are connected in sequence, and the intermediate frequency data unpacking module is connected to the baseband module, and the DA data transmission module is connected to the DA conversion module.

[0026] The frequency offset control module is connected to the demodulation module, and the AD / DA configuration module is connected to both the AD conversion module and the DA conversion module.

[0027] In the above structure, the field-programmable gate array (FPGA) performs self-loop testing and performance verification on the transmit and receive links, including:

[0028] After loading the new frequency hopping pattern, self-test data is sent through the internal loop to verify the correctness of the frequency hopping pattern, the modulation and demodulation function, and the link integrity, and the verification results are reported to the host computer.

[0029] The present invention also provides a method for a communication device with an anti-interference reconfigurable frequency hopping pattern, wherein the improvement is that the device includes a field-programmable gate array (FPGA), an AD conversion module, a DA conversion module, an up-conversion mixer, and a down-conversion mixer, and the method includes the following steps:

[0030] Self-loop verification steps: In response to the self-test command, self-test data is generated inside the device. This data is then passed through modulation, digital-to-analog conversion, and up-conversion in sequence. Finally, the up-converted signal is sent to the down-conversion mixer and AD conversion module through the internal loop for demodulation and data comparison to verify the correctness of the internal transceiver link.

[0031] Adaptive power control steps: During signal transmission or reception, the actual power on the signal path is detected in real time; the actual power is compared with a preset target power; and based on the comparison result, the attenuation value of the programmable attenuator on the signal path is automatically adjusted in a closed-loop manner to make the actual power approach the target power.

[0032] Automatic frequency offset control steps: When receiving and demodulating the signal, the carrier frequency offset of the received signal is periodically estimated; based on the estimated frequency offset value, the frequency of the clock crystal oscillator that provides the working clock for the FPGA, AD conversion module and DA conversion module is finely adjusted in a closed loop until the estimated frequency offset value converges to near zero.

[0033] Furthermore, the method also includes an error detection and repair step, which includes:

[0034] RS decoding is performed on the demodulated data to correct symbol errors present in the data;

[0035] Perform CRC check on the data after RS ​​decoding;

[0036] If the CRC check passes, the data is confirmed to be correct; if the CRC check fails, the RS decoding is determined to be unsuccessful, the data is marked as erroneous, and the error status is reported.

[0037] Furthermore, the adaptive power control step specifically includes: if the actual power is less than the target power, then the attenuation value is reduced; if the actual power is greater than the target power, then the attenuation value is increased.

[0038] The beneficial effects of the present invention are as follows: The communication device of the present invention with anti-interference reconfigurable frequency hopping pattern can realize flexible frequency hopping pattern loading to adapt to communication between different devices; through bit error detection correction and frequency offset adjustment, the anti-interference capability of the device can also be improved; in addition, through the adaptive power control mechanism, the robustness of signal reception is also significantly improved. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure of a communication device with an anti-interference reconfigurable frequency hopping pattern according to the present invention.

[0040] Figure 2 This is a schematic diagram of the data receiving process in this invention.

[0041] Figure 3 This is a schematic diagram of the data transmission process in this invention.

[0042] Figure 4 This is a schematic diagram of the power control process in this invention.

[0043] The diagram shows: Baseband module 10, Baseband serial port receiving module 101, Baseband data parsing module 102, Baseband processing module 103, Baseband serial port transmitting module 104, Baseband data packet assembly module 105, Frequency hopping control module 106, Power adjustment module 107, Intermediate frequency processing module 20, Intermediate frequency data packet assembly module 201, Channel decoding module 202, Demodulation module 203, AD data acquisition module 204, Intermediate frequency data unpacking module 205, Channel coding module 206, Modulation module 207, DA data transmitting module 208, AD / DA configuration module 209, Frequency offset control module 210, External RF circuit 30, AD conversion module 301, DA conversion module 302, Up-conversion mixer 303, Down-conversion mixer 304, Power detection circuit 305, Down-conversion attenuator circuit 307, Up-conversion attenuator circuit 306, Clock crystal oscillator 308. Detailed Implementation

[0044] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0045] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0046] This invention discloses a communication device with an anti-interference reconfigurable frequency hopping pattern, referring to... Figure 1 The diagram shown is a schematic of the device's structure. The device includes a baseband module 10 and an intermediate frequency (IF) processing module 20 based on a field-programmable gate array (FPGA), as well as corresponding external radio frequency (RF) circuitry 30. The external RF circuitry 30 includes an AD conversion module 301 and a DA conversion module 302 connected to the IF processing module 20, and an up-conversion mixer 303 and a down-conversion mixer 304 connected to the baseband module 10. The AD conversion module 301 is connected to the down-conversion mixer 304, and the up-conversion mixer 303 is connected to the DA conversion module 302. Furthermore, to better understand the technical solution of this invention, we will combine the baseband module 10, the IF processing module 20, and the external RF circuitry 30 with... Figure 1 A more detailed explanation will be provided.

[0047] The baseband module 10 includes a baseband serial port receiving module 101, a baseband data parsing module 102, a baseband processing module 103, a baseband serial port transmitting module 104, a baseband data packet assembly module 105, a frequency hopping control module 106, and a power adjustment module 107. The baseband data parsing module 102, the baseband data packet assembly module 105, the frequency hopping control module 106, and the power adjustment module 107 are all connected to the baseband processing module 103. The baseband serial port receiving module 101 is connected to the baseband data parsing module 102, and the baseband serial port transmitting module 104 is connected to the baseband data packet assembly module 105. The frequency hopping control module 106 is connected to the up-converter mixer 303 and the down-converter mixer 304.

[0048] Furthermore, the intermediate frequency (IF) processing module 20 also includes an IF data packet assembly module 201, a channel decoding module 202, a demodulation module 203, an AD data acquisition module 204, an IF data unpacking module 205, a channel coding module 206, a modulation module 207, a DA data transmission module 208, an AD / DA configuration module 209, and a frequency offset control module 210; the AD data acquisition module 204, demodulation module 203, channel decoding module 202, and IF data packet assembly module 201 are connected in sequence, and the AD data acquisition module 204 is connected to the AD conversion module 301. The intermediate frequency (IF) data packet assembly module 201 is connected to the baseband processing module 103 of the baseband module 10; the IF data unpacking module 205, the channel coding module 206, the modulation module 207, and the DA data transmission module 208 are connected in sequence, and the IF data unpacking module 205 is connected to the baseband processing module 103 of the baseband module 10, and the DA data transmission module 208 is connected to the DA conversion module 302; the frequency offset control module 210 is connected to the demodulation module 203, and the AD / DA configuration module 209 is connected to the AD conversion module 301 and the DA conversion module 302 respectively.

[0049] For the external radio frequency circuit 30, continue to combine Figure 1 As shown, it also includes a programmable attenuator and a power detection circuit 305. The programmable attenuator includes a down-conversion attenuator circuit 307 and an up-conversion attenuator circuit 306. The power adjustment module 107 is connected to the power detection circuit 305, the down-conversion attenuator circuit 307, and the up-conversion attenuator circuit 306. In addition, the down-conversion attenuator circuit 307 is connected to the down-conversion mixer 304 and the power detection circuit 305, respectively, and the up-conversion attenuator circuit 306 is connected to the up-conversion mixer 303 and the power detection circuit 305, respectively.

[0050] The specific functions of each of the above modules are explained in detail in this embodiment:

[0051] Baseband serial port receiving module 101: This module is mainly responsible for receiving message data sent by the host computer, that is, converting the serial serial port data into parallel 1-byte data according to the RS422 protocol at a specified baud rate, and then checking the CRC in the message. If it is correct, the data is sent to the baseband data parsing module 102; otherwise, the message is discarded.

[0052] Baseband data parsing module 102: This module is mainly responsible for parsing serial port data. It receives the message data output by the baseband serial port receiving module 101, parses the valid data in the message, such as frequency hopping patterns and frequency hopping information, data to be modulated, and modulation parameters, and sends it to the baseband processing module 103.

[0053] Baseband processing module 103: This module is mainly responsible for baseband message processing and data processing and forwarding. For message processing, this module first receives data output from the baseband data parsing module 102, then packages the data to be modulated along with modulation and demodulation parameters and forwards it to the intermediate frequency (IF) data unpacking module 205. Additionally, it receives messages from the IF data packaging module 201, extracts the demodulated data and demodulation status information, and forwards it to the baseband data packaging module 105. For data processing and forwarding, based on the saved frequency hopping pattern and frequency hopping position information, it parses the current frequency hopping frequency and sends it to the frequency hopping control module 106; simultaneously, it receives power information from the power adjustment module 107 and sends it to the baseband data unpacking module for information reporting.

[0054] Baseband data packet assembly module 105: Receives demodulated data, demodulation status, power information, etc. from baseband processing module 103, and assembles and sends them to baseband serial port transmission module 104.

[0055] Baseband serial port transmission module 104: Takes the messages sent by the baseband data packet assembly module 105, converts them from parallel to serial according to the RS422 protocol, and then sends them to the external host computer.

[0056] Frequency hopping control module 106: Receives frequency hopping information from baseband processing module 103, converts the frequency hopping point into SPI control commands, and sends them to downconverter mixer 304 to perform center frequency hopping.

[0057] Power adjustment module 107: Receives the transmit and receive power detected by power detection circuit 305, and controls the up and down converters based on the detected power to prevent the signal from being too weak or overflowing. Simultaneously, it returns the current power detection value to baseband processing module 103.

[0058] Intermediate frequency data unpacking module 205: parses the data packetized by baseband processing module 103, extracts the data to be modulated as well as modulation and demodulation parameters, etc. The modulation parameters are sent to modulation module 207, and the demodulation parameters are sent to demodulation module 203. The data to be modulated is first sent to channel coding module 206 for pre-modulation processing.

[0059] Channel coding module 206: Receives the data to be modulated sent by intermediate frequency data unpacking module 205, adds a frame header to the data to be modulated, and adds a CRC check code and RS encoding to the frame tail.

[0060] Modulation module 207: Receives and loads the modulation parameters sent by intermediate frequency data unpacking module 205, and receives the processed data to be modulated output by channel coding module 206. After the data is modulated, it outputs the modulated signal to DA data transmission module 208.

[0061] DA data transmission module 208: Receives the modulation signal output by modulation module 207, converts the signal data timing according to the data timing of DA conversion module 302, and then sends it to DA conversion module 302 for up-conversion.

[0062] AD data acquisition module 204: Receives data sent by AD conversion module 301, converts the data into signal data according to the timing of AD conversion module 301, and then sends it to demodulation module 203 for signal demodulation.

[0063] Demodulation module 203: Receives the signal to be demodulated from the AD data acquisition module 204, loads the demodulation parameters output by the intermediate frequency data unpacking module 205, and outputs the demodulated data to the channel decoding module 202 after demodulation. Additionally, during demodulation, it calculates the frequency offset between the receiving end and the local end based on the received signal and outputs the frequency offset value to the frequency offset control module 210.

[0064] Channel decoding module 202: Receives the demodulated data output by demodulation module 203 and inputs it into RS decoder for error correction. After decoding is completed, it performs CRC check on the data to confirm whether the decoding is successful, and outputs the CRC check result and the decoding result.

[0065] The intermediate frequency data packetization module 201: Packets the demodulated data output by the channel decoding module 202, the CRC check result, the RS decoding result, and the demodulation status output by the demodulation module 203, and sends them to the baseband processing module 103. Specifically, the channel decoding module 202 is configured to first perform RS decoding on the demodulated data to correct symbol errors in the data; the channel decoding module 202 is also configured to perform CRC check on the data after RS ​​decoding; the channel decoding module 202 also includes a decision logic, which is configured to: if the CRC check passes, determine that the data is correct and report it; if the CRC check fails, determine that the RS decoding was unsuccessful, mark the data as erroneous, and report the error status.

[0066] Frequency offset control module 210: Receives the frequency offset estimation signal calculated and output by demodulation module 203, and automatically fine-tunes the accuracy value of clock crystal 308, iterating multiple times until the frequency offset estimation signal approaches 0, and then completes frequency locking.

[0067] AD / DA configuration module 209: Controls the registers of AD / DA via SPI and initializes AD / DA, such as configuring parameters like clock, sampling rate, filter, center frequency, and gain control.

[0068] AD conversion module 301: Converts intermediate frequency signals into baseband signals, that is, converts the intermediate frequency analog signal after RF downconversion into a baseband digital signal and sends it to the field programmable gate array (FPGA).

[0069] DA conversion module 302: Converts baseband signals into intermediate frequency signals, that is, converts the baseband digital signals input from the field programmable gate array (FPGA) into intermediate frequency analog signals, and sends them to the upconverter mixer 303 for upconversion.

[0070] Upconverter mixer 303: Upconverts the intermediate frequency analog signal to the radio frequency according to the radio frequency center frequency set by the field programmable gate array (FPGA).

[0071] Downconversion mixer 304: Based on the RF center frequency set by the FPGA, it downconverts the RF analog signal to the intermediate frequency.

[0072] Down-conversion attenuator circuit 307: When an external signal is input, the power amplitude of the signal is controlled by the down-conversion attenuator circuit 307; the attenuation of the down-conversion attenuator circuit 307 is controlled by the field programmable gate array (FPGA).

[0073] Up-conversion attenuator circuit 306: After the signal is output from the up-conversion mixer 303, it passes through the up-conversion attenuator circuit 306 to control the power amplitude of the signal; the attenuation of the up-conversion attenuator circuit 306 is controlled by the field programmable gate array (FPGA).

[0074] Power detection circuit 305: In front of the signal input and output devices, another path is connected to the power detection circuit 305. Through this circuit, the power of the signal can be detected in real time and sent to the field programmable gate array (FPGA).

[0075] Combination Figure 1 As shown, we describe the loading process of the frequency hopping pattern in a communication device with an anti-interference reconfigurable frequency hopping pattern according to the present invention, specifically including the following steps:

[0076] Step 1: Send frequency hopping pattern message. The host computer sends the frequency hopping pattern loading message to the field programmable gate array (FPGA) via RS422 serial port.

[0077] Step 2: Perform frequency hopping pattern parsing. The baseband module 10 extracts the frequency hopping pattern in the message and performs CRC verification on the corresponding frequency hopping pattern.

[0078] Step 3: Save the frequency hopping pattern. After the verification is passed, the baseband module 10 writes the frequency hopping pattern into the RAM in the field programmable gate array (FPGA) for storage.

[0079] Step 4: Perform frequency hopping position transmission. The host computer sends the frequency hopping message to the field programmable gate array (FPGA) via the RS422 serial port.

[0080] Step 5: Extract the frequency hopping pattern. The baseband module 10 extracts the frequency hopping position in the message, and then uses the frequency hopping position as the address to read the corresponding frequency hopping pattern from the RAM.

[0081] Step 6: Perform frequency hopping. The baseband module 10 calculates the corresponding RF receiving center frequency and transmitting center frequency according to the frequency hopping pattern, and configures the mixer local oscillator frequency to complete the frequency hopping, thereby changing the up and down frequency.

[0082] This invention discloses a communication device with an anti-interference reconfigurable frequency hopping pattern. The device comprises a transmit link and a receive link. The device includes: transmitting the signal output from the up-conversion mixer 303 in the transmit link to the input of the down-conversion mixer 304 in the receive link via an internal loop, allowing the field-programmable gate array (FPGA) to perform self-loop testing and performance verification on the transmit and receive links. In this embodiment, this process is defined as an internal self-loop verification mechanism. The internal self-loop verification mechanism is used to send self-test data through the internal loop after loading a new frequency hopping pattern and verify the correctness of the frequency hopping pattern, modulation / demodulation functions, and link integrity, and reports the verification results to a host computer.

[0083] In this embodiment, a specific implementation of the internal self-loop verification mechanism is provided, the details of which are as follows:

[0084] Step 1: Initiate the self-test process. The host computer sends a self-test command, and after receiving it, the baseband module 10 enters the self-test preparation process.

[0085] Step 2: Send self-test data. After the baseband module 10 enters the self-test state, it sends the self-test data to the intermediate frequency processing module 20.

[0086] Step 3: Encode the self-test data. After receiving the self-test data, the intermediate frequency processing module 20 adds a frame header, CRC, and RS encoding fields to the data.

[0087] Step 4: Perform a self-loop modulation of the signal. After the grouped data is modulated, the output signal is up-converted through the DA conversion module 302 and the up-conversion mixer 303, and then looped back to the down-conversion mixer 304 and the AD conversion module 301 through the internal loop for down-conversion. Finally, the signal is acquired and received by the intermediate frequency processing module 20.

[0088] Step 5: Perform self-test result judgment. The acquired signal is demodulated, and the demodulated data undergoes CRC check and RS decoding in the intermediate frequency processing module 20. The CRC check result and decoding result are output and fed back to the baseband module 10. If the CRC check result and decoding result are normal, the baseband module 10 returns a self-test result to the host computer.

[0089] Based on the above, it can be understood that the receiving link, transmitting link, and internal loop are all defined according to the signal transmission process. For example, the receiving link includes a down-conversion mixer 304, an AD conversion module 301, an AD data acquisition module 204, a demodulation module 203, a channel decoding module 202, and an intermediate frequency data packet assembly module 201; the transmitting link includes an intermediate frequency data unpacking module 205, a channel coding module 206, a modulation module 207, an DA data transmission module 208, an DA conversion module 302, and an up-conversion mixer 303; and the internal loop, according to the internal self-loop verification mechanism, includes an up-conversion attenuator circuit 306, a down-conversion attenuator circuit 307, a power detection circuit 305, a power adjustment module 107, a baseband processing module 103, and a frequency hopping control module 106.

[0090] Combination Figure 2 As shown, we will describe in detail the data receiving process of a communication device with an anti-interference reconfigurable frequency hopping pattern according to the present invention. The specific process is as follows:

[0091] Step 1: Analog signal to digital signal conversion. After passing through the downconverter mixer 304, the radio frequency analog signal is converted into an intermediate frequency analog signal. Then, the AD conversion module 301 acquires the signal and converts it into a digital signal, which is then sent to the field programmable gate array (FPGA).

[0092] Step 2: Signal Acquisition. The Field Programmable Gate Array (FPGA) converts the input digital signal into usable digital signal data according to the timing of the digital signal in the AD conversion module 301, and then sends it to the demodulation module 203.

[0093] Step 3: Perform error detection and correction. After signal demodulation is completed, CRC check and RS decoding are performed on the demodulated data. Then, the check and decoding results, the decoded demodulated data, and the demodulation status output by demodulation module 203 are packaged together and sent to baseband processing module 103.

[0094] Step 4: Report serial port data. The baseband processing module 103 parses the required data and returns it to the host computer through the baseband serial port sending module 104.

[0095] Combination Figure 3As shown, we will describe in detail the data transmission process of a communication device with an anti-interference reconfigurable frequency hopping pattern according to the present invention. The specific process is as follows:

[0096] Step 1: Perform serial port data parsing. The host computer sends the data to be modulated through the baseband serial port receiving module 101, which is parsed and packetized by the baseband processing module 103 and sent to the intermediate frequency processing module 20.

[0097] Step 2: Encoding and Packet Assembly. After parsing the data, the intermediate frequency processing module 20 adds a frame header and CRC and RS encoding fields to the data to be modulated, and then sends it to the modulation module 207.

[0098] Step 3: Signal transmission. After the modulation module 207 outputs a signal, the field-programmable gate array (FPGA) converts the signal from digital data into a digital signal conforming to the DA timing, and then sends the signal to the DA conversion module 302.

[0099] Step 4: Convert the digital signal to an analog signal. The DA conversion module 302 converts the baseband digital signal into an intermediate frequency analog signal, which is then converted into a radio frequency analog signal by the up-conversion mixer 303, and finally sent to the outside.

[0100] Furthermore, the device also includes an adaptive power control mechanism, specifically including a power detection circuit 305 and a programmable attenuator connected to the transmit and receive links; wherein, the field-programmable gate array (FPGA) is configured to: acquire the actual transmit or receive power value measured by the power detection circuit 305, compare it with a preset target power value, and automatically adjust the attenuation value of the programmable attenuator according to the comparison result, thereby stabilizing the signal power near the target power value in a closed-loop manner. In this embodiment, the FPGA in the adaptive power control mechanism is configured to: decrease the attenuation value of the programmable attenuator when the actual power value is less than the target power value; and increase the attenuation value of the programmable attenuator when the actual power value is greater than the target power value. Figure 1 As shown, the programmable attenuator includes an up-conversion attenuator circuit 306 and a down-conversion attenuator circuit 307.

[0101] Combination Figure 4 As shown, we will describe in detail the power control process of a communication device with an anti-interference reconfigurable frequency hopping pattern according to the present invention, wherein the power control process at the transmitting end is as follows:

[0102] Step 1: Start power detection. When transmitting a signal, the power detection module first controls the power detection circuit 305 to start detecting the current transmission power.

[0103] Step 2: Perform power reading. The power detection module reads the current transmit power value and returns it to the baseband processing module 103, which then sends it to the host computer.

[0104] Step 3: Perform power adjustment. The power detection module compares the current transmit power with the target transmit power. If the signal power is too low, the attenuation value is appropriately reduced; if the signal power is too high, the attenuation value is appropriately increased, in order to achieve the target transmit power.

[0105] Continue to refer to Figure 4 As shown, it also includes the receiver power control process:

[0106] Step 1: Start power detection. When receiving signals, the power detection module first controls the power detection circuit 305 to start detecting the current received power level.

[0107] Step 2: Perform power reading. The power detection module reads the current received power value and returns it to the baseband processing module 103, which then sends it to the host computer.

[0108] Step 3: Perform power adjustment. The power detection module compares the current received power with the target received power. If the signal power is too low, the attenuation value is appropriately reduced; if the signal power is too high, the attenuation value is appropriately increased, in order to achieve the target received power.

[0109] Furthermore, the communication device with an anti-interference reconfigurable frequency hopping pattern according to the present invention also includes an automatic frequency offset control mechanism. The demodulation module 203 in the field-programmable gate array (FPGA) is configured to estimate the frequency offset value of the carrier frequency when receiving a signal and generate a frequency offset estimation signal. The FPGA also includes a frequency offset control module 210, configured to fine-tune the frequency of the clock crystal oscillator that provides the working clock for the FPGA, the AD conversion module 301, and the DA conversion module 302 in a closed loop according to the frequency offset estimation signal, until the frequency offset estimation signal approaches zero.

[0110] Specifically, in this embodiment, a specific implementation of the automatic frequency offset control mechanism is provided, including the following steps:

[0111] Step 1: Perform frequency offset estimation. When receiving the modulated signal, the demodulation module 203 periodically performs carrier recovery and outputs a real-time frequency offset estimation signal.

[0112] Step 2: Perform frequency compensation. Based on the output frequency offset estimation signal, fine-tune the DDS frequency word of the modulation and demodulation section clock shared by the FPGA and AD / DA configuration module 209 to compensate for the frequency deviation of the received signal.

[0113] Step 3: Closed-loop convergence. Repeat step 2 for multiple iterations until the frequency offset estimation signal approaches 0, thus locking the system frequency.

[0114] Based on the above, the communication device of the present invention, which provides an anti-interference reconfigurable frequency hopping pattern, can achieve flexible frequency hopping pattern loading to adapt to communication between different devices; through bit error detection and correction and frequency offset adjustment, the anti-interference capability of the device can also be improved; in addition, through an adaptive power control mechanism, the robustness of signal reception is also significantly improved. Moreover, the hardware circuit is simple, low in cost, and highly maintainable.

[0115] On the other hand, the present invention also provides a method for a communication device with an anti-interference reconfigurable frequency hopping pattern. This method is applied to the aforementioned device, therefore the structure of the device will not be described in detail in this embodiment. The method includes a self-loop verification step, an adaptive power control step, an automatic frequency offset control step, and a bit error detection and repair step.

[0116] The self-loop verification step includes: responding to a self-test command, generating self-test data internally, passing this data sequentially through modulation, digital-to-analog conversion, and up-conversion, and then sending the up-converted signal through an internal loop to the down-conversion mixer 304 and the AD conversion module 301 for demodulation and data comparison to verify the correctness of the internal transceiver link. Specifically, in this embodiment, the self-loop verification step includes:

[0117] Step 1: Self-test data generation and transmission. The baseband processing module 103 generates or calls preset self-test data (such as pseudo-random code) and sends it to the intermediate frequency processing module 20.

[0118] Step 2: Standard transmit link processing. The self-test data is processed by channel coding, modulation, DA conversion, and up-conversion mixer 303 to generate an analog signal in the radio frequency band. This process is completely consistent with normal data transmission.

[0119] Step 3: Internal Loopback. The up-converted signal is not sent to the antenna, but is directly fed into the input of the down-converter mixer 304 through an internal loop. This loop can be implemented by an RF switch controlled by a field-programmable gate array (FPGA).

[0120] Step 4: Standard Receiver Link Processing. The loopback signal undergoes a series of processes identical to normal reception, including down-conversion mixer 304, AD conversion module 301, demodulation, and channel decoding.

[0121] Step 5: Result Judgment. The baseband processing module 103 compares the demodulated and decoded self-test data with the original transmitted self-test data. Simultaneously, the intermediate frequency processing module 20 outputs the CRC check result and RS decoding result. If the data is completely consistent and the check / decoding status is normal, the self-test is considered passed, and a success status is returned to the host computer. Otherwise, a failure status and possible error information are returned.

[0122] The self-loop verification step allows the correctness of the entire transceiver signal chain (excluding antennas and space channels) to be fully verified in a controlled environment.

[0123] Furthermore, the adaptive power control step includes: detecting the actual power on the signal path in real time during signal transmission or reception; comparing the actual power with a preset target power; and automatically adjusting the attenuation value of the programmable attenuator on the signal path in a closed-loop manner based on the comparison result, so that the actual power approaches the target power. Specifically, in this embodiment, it includes transmit frequency control and receive frequency control.

[0124] Transmission frequency control steps:

[0125] Step 1: Before the signal passes through the up-conversion attenuation circuit, a portion of its power is coupled to the power detection circuit 305.

[0126] Step 2: The power detection circuit 305 converts the detected real-time power value into a digital signal and sends it to the field programmable gate array (FPGA).

[0127] Step 3: The power adjustment module and baseband processing module 103 in the FPGA compare the actual power value with the "target transmit power" set by the host computer.

[0128] Step 4: If the actual power is too low, the FPGA will control the up-conversion attenuator to reduce the attenuation; if the actual power is too high, the attenuation will be increased. This adjustment process continues until the actual power stabilizes within the allowable error range of the target power.

[0129] Receive power control steps:

[0130] Step 1: Similar to the transmitter, after the external signal enters the downconversion attenuation circuit, its power is monitored by the power detection circuit 305 before being sent to the downconversion mixer 304.

[0131] Step 2: The FPGA compares the detected received power with the set "target received power" and adjusts the attenuation value of the downconversion attenuation circuit accordingly to ensure that the signal amplitude sent to the ADC is neither overloaded nor too weak, and is always in the optimal dynamic range.

[0132] This closed-loop control based on target values ​​is more precise and flexible than traditional AGC.

[0133] Furthermore, the automatic frequency offset control step in this invention includes: periodically estimating the carrier frequency offset of the received signal during signal reception and demodulation; and fine-tuning the frequency of the clock crystal oscillator providing the operating clock for the FPGA, AD conversion module 301, and DA conversion module 302 based on the estimated frequency offset value, until the estimated frequency offset value converges to near zero. In this embodiment, the specific steps include:

[0134] Step 1: Frequency Offset Estimation. During reception, the demodulation module 203 within the FPGA continuously estimates the deviation between the center frequency and the local oscillator frequency of the received signal while executing the carrier recovery algorithm; this is the frequency offset estimation signal.

[0135] Step 2: Frequency Compensation. The demodulation module 203 outputs the frequency offset estimation signal to the frequency offset control module 210. The frequency offset control module 210 calculates a frequency adjustment amount based on the magnitude and polarity of the value.

[0136] Step 3: Closed-loop convergence. The frequency offset control module 210 applies this adjustment to the clock crystal that provides the clock reference for the entire digital and RF section. Specifically, this is typically achieved by fine-tuning the output frequency of the DDS (Direct Digital Synthesizer) driving the crystal. This adjustment is in the opposite direction to the estimated frequency offset, thus canceling it out.

[0137] This process (estimation -> compensation -> adjustment) iterates continuously until the frequency offset estimation signal output by the demodulation module 203 approaches 0. At this point, the system frequency reaches a locked state, and the frequencies of the transmitting and receiving parties are precisely aligned.

[0138] Furthermore, the present invention also includes a bit error detection and repair step, which includes:

[0139] Step 1: First, perform RS decoding, utilizing the powerful error correction capability of RS codes to correct burst or random symbol errors generated in the channel.

[0140] Step 2: Perform CRC check again on the data after RS ​​decoding.

[0141] Step 3: If the CRC check passes, it means that the data is complete and correct after RS ​​error correction.

[0142] Step 4: If the CRC check fails, it indicates that even after RS ​​decoding, there are still errors in the data that exceed its error correction capabilities. In this case, the system will determine the data as erroneous and report it to the upper layer, thus avoiding delivering data that "seems correct but is actually wrong" to the application and ensuring the final integrity of the data.

[0143] The present invention has the following advantages:

[0144] Firstly, it improves maintainability and development efficiency: Through an innovative internal self-loop verification mechanism, users can quickly and safely verify newly loaded frequency hopping patterns, modulation parameters, and the integrity of the entire transceiver link without relying on external devices or actual RF environments. This greatly simplifies the debugging process, shortens the development cycle, and ensures the correctness of critical device functions before deployment.

[0145] Secondly, it enhances the robustness of the communication link: the adaptive power control mechanism, through a closed-loop feedback of "measurement-comparison-adjustment," can precisely stabilize the power of transmitted and received signals at a preset target value. This not only compensates for power fluctuations caused by device aging and temperature changes, but also maintains the optimal signal-to-noise ratio in dynamic channels, significantly improving the stability and reliability of communication, and is more precise and proactive than traditional AGC control.

[0146] Thirdly, it enhances the ability to resist frequency offset interference: The automatic frequency offset control mechanism effectively combats frequency mismatch problems caused by crystal oscillator aging, temperature drift, or Doppler effect by compensating for system-level frequency deviations in real time through a closed loop. This mechanism ensures that the modem always operates in optimal condition, thereby significantly improving demodulation performance and communication success rate under non-ideal conditions.

[0147] Fourth, it improves the reliability of data transmission: Through the error detection and repair process that combines RS decoding and CRC check, this invention can not only correct a certain degree of channel errors, but also determine whether RS ​​decoding is successful through subsequent CRC check, avoiding the risk of introducing larger data errors due to RS decoding failure, and providing more reliable data for upper-layer applications.

[0148] Fifth, the system has high integration and controllable cost: This invention integrates the above-mentioned advanced functions into a hybrid architecture with FPGA as the core, making full use of the parallel processing capability and reconfigurability of FPGA, and achieving a huge improvement in functionality without significantly increasing hardware complexity and cost.

[0149] In summary, this invention combines three innovative closed-loop systems—internal self-loop verification, adaptive power control, and automatic frequency offset control—with an error handling process and integrates them onto a reconfigurable platform centered on a field-programmable gate array (FPGA), thus constructing a highly reliable, easy-to-maintain, and high-performance anti-interference communication solution.

[0150] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A communication device with an anti-interference reconfigurable frequency hopping pattern, characterized in that, The device includes a baseband module, an intermediate frequency (IF) processing module, an AD conversion module and a DA conversion module connected to the IF processing module, and an up-conversion mixer and a down-conversion mixer connected to the baseband module. The baseband module and IF processing module are based on a Field Programmable Gate Array (FPGA). The AD conversion module is connected to the down-conversion mixer, and the up-conversion mixer is connected to the DA conversion module. The device constitutes a transmit link and a receive link. The transmit link includes: an IF data unpacking module, a channel coding module, a modulation module, and a DA data transmission module within the IF processing module, as well as the DA conversion module and the up-conversion mixer. The receive link includes: the down-conversion mixer and the AD conversion module, as well as an AD data acquisition module, a demodulation module, a channel decoding module, and an IF data repackaging module within the IF processing module. The device further includes: transmitting the signal output from the up-conversion mixer in the transmit link to the input of the down-conversion mixer in the receive link through an internal loop, so as to allow the field-programmable gate array (FPGA) to perform self-loop testing and performance verification on the transmit and receive links; the FPGA performing self-loop testing and performance verification on the transmit and receive links includes: after loading a new frequency hopping pattern, sending self-test data through the internal loop and verifying the correctness of the frequency hopping pattern, the modulation and demodulation function, and the link integrity, and reporting the verification results to the host computer; The demodulation module within the FPGA is configured to estimate the frequency offset of the carrier frequency when receiving a signal and generate a frequency offset estimation signal. The FPGA also includes a frequency offset control module configured to fine-tune the frequency of the clock crystal oscillator that provides the operating clock for the FPGA, the AD conversion module, and the DA conversion module in a closed loop according to the frequency offset estimation signal, until the frequency offset estimation signal converges to zero, thereby achieving frequency locking.

2. The communication device with an anti-interference reconfigurable frequency hopping pattern according to claim 1, characterized in that, The device also includes an adaptive power control mechanism, comprising a power detection circuit and a programmable attenuator connected to the transmit link and the receive link; The field-programmable gate array (FPGA) is configured to: acquire the actual transmit or receive power value measured by the power detection circuit, compare it with the preset target power value, and automatically adjust the attenuation value of the programmable attenuator according to the comparison result, so as to stabilize the signal power within the allowable error range of the target power value in a closed-loop manner.

3. The communication device with an anti-interference reconfigurable frequency hopping pattern according to claim 2, characterized in that, The field-programmable gate array (FPGA) in the adaptive power control mechanism is configured to: decrease the attenuation value of the programmable attenuator when the actual power value is less than the target power value; and increase the attenuation value of the programmable attenuator when the actual power value is greater than the target power value.

4. The communication device with an anti-interference reconfigurable frequency hopping pattern according to claim 2, characterized in that, The baseband module also includes a baseband serial port receiving module, a baseband data parsing module, a baseband processing module, a baseband serial port transmitting module, a baseband data packet assembly module, a frequency hopping control module, and a power adjustment module; The baseband data parsing module, baseband data packet assembly module, frequency hopping control module, and power adjustment module are all connected to the baseband processing module. The baseband serial port receiving module is connected to the baseband data parsing module, and the baseband serial port transmitting module is connected to the baseband data packet assembly module. The programmable attenuator includes a down-conversion attenuator circuit and an up-conversion attenuator circuit, and the power adjustment module is connected to the power detection circuit, the down-conversion attenuator circuit and the up-conversion attenuator circuit. The frequency hopping control module is connected to the upconverter mixer and the downconverter mixer.

5. The communication device with an anti-interference reconfigurable frequency hopping pattern according to claim 1, characterized in that, The intermediate frequency processing module also includes a channel decoding module; The channel decoding module is configured to first perform RS decoding on the demodulated data to correct symbol errors in the data; The channel decoding module is also configured to perform CRC verification on the data after RS ​​decoding; The channel decoding module also includes a decision logic, which is configured to: if the CRC check passes, determine that the data is correct and report it; If the CRC check fails, the RS decoding is deemed unsuccessful, the data is marked as erroneous, and the error status is reported.

6. A communication device with an anti-interference reconfigurable frequency hopping pattern according to claim 5, characterized in that, The intermediate frequency (IF) processing module also includes an IF data packetization module, a demodulation module, an AD data acquisition module, an IF data unpacking module, a channel coding module, a modulation module, an DA data transmission module, and an AD / DA configuration module; The AD data acquisition module, demodulation module, channel decoding module, and intermediate frequency data packet assembly module are connected in sequence. The AD data acquisition module is connected to the AD conversion module, and the intermediate frequency data packet assembly module is connected to the baseband module. The intermediate frequency data unpacking module, channel coding module, modulation module, and DA data transmission module are connected in sequence, and the intermediate frequency data unpacking module is connected to the baseband module, and the DA data transmission module is connected to the DA conversion module. The frequency offset control module is connected to the demodulation module, and the AD / DA configuration module is connected to both the AD conversion module and the DA conversion module.

7. A method for a communication device applied to an anti-interference reconfigurable frequency hopping pattern, characterized in that, The device includes a field-programmable gate array (FPGA), an analog-to-digital converter (AD / DA) module, an up-conversion mixer, and a down-conversion mixer. The method includes the following steps: Self-loop verification steps: In response to the self-test command, self-test data is generated inside the device. This data is then passed through modulation, digital-to-analog conversion, and up-conversion in sequence. Finally, the up-converted signal is sent to the down-conversion mixer and AD conversion module through the internal loop for demodulation and data comparison to verify the correctness of the internal transceiver link. Adaptive power control steps: During signal transmission or reception, the actual power on the signal path is detected in real time; the actual power is compared with a preset target power value; and based on the comparison result, the attenuation value of the programmable attenuator on the signal path is automatically adjusted in a closed-loop manner to stabilize the actual power within the allowable error range of the target power value. Automatic frequency offset control steps: When receiving and demodulating the signal, the carrier frequency offset of the received signal is periodically estimated; based on the estimated frequency offset value, the frequency of the clock crystal oscillator that provides the working clock for the FPGA, AD conversion module and DA conversion module is finely adjusted in a closed loop until the estimated frequency offset value converges to zero, so as to achieve frequency locking.

8. The method for a communication device applied to an anti-interference reconfigurable frequency hopping pattern according to claim 7, characterized in that, The method also includes an error detection and repair step, which includes: RS decoding is performed on the demodulated data to correct symbol errors present in the data; Perform CRC check on the data after RS ​​decoding; If the CRC check passes, the data is confirmed to be correct; if the CRC check fails, the RS decoding is determined to be unsuccessful, the data is marked as erroneous, and the error status is reported.

9. A method for a communication device applied to an anti-interference reconfigurable frequency hopping pattern according to claim 7, characterized in that, The adaptive power control steps specifically include: if the actual power is less than the target power, then the attenuation value is reduced; if the actual power is greater than the target power, then the attenuation value is increased.

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