A transistor comprising a ladder structure, a manufacturing method and applications

Abstract

The application relates to a transistor containing a ladder structure, a drain electrode being a ladder structure with steps; a gate covering the surface of the high hole concentration structure layer and forming a Schottky contact with the high hole concentration structure layer; the drain electrode penetrating the passivation protective layer and the space on the upper surface of the barrier layer not covered by the high hole concentration structure layer in sequence, and extending into the channel layer, and the part extending into the channel layer presents a ladder structure with steps, the low step part facing one side of the high hole concentration structure layer, and the drain electrode and the barrier layer and the channel layer present an Ohmic contact.

Description

TECHNICAL FIELD

[0001] The present invention relates to a component of a semiconductor or other solid state device, and also to a process specifically applicable to the manufacture or treatment of a semiconductor or solid state device or component thereof. In particular, it relates to a transistor comprising a ladder structure, a method of manufacture and use. BACKGROUND

[0002] Gallium nitride transistor (GaN Transistor), also known as high electron mobility transistor (HEMT), is a third-generation wide bandgap semiconductor device based on gallium nitride (GaN) material. As a typical wide bandgap semiconductor material, gallium nitride has been widely used in civil fields such as automotive electronics, power electronics and 5G communication base stations. Not only that, its high switching frequency and high power density characteristics make it show irreplaceable application potential in high-end fields such as aerospace and satellite detection, becoming the key candidate material of core electronic devices in such fields.

[0003] However, aerospace and satellite detection equipment needs to work in a complex space environment for a long time, and there are a large number of high-energy particles (such as protons, electrons, heavy ions, etc.) in this environment, which will seriously affect the working reliability of gallium nitride devices and greatly limit their large-scale application in space. Research has shown that high-energy particle incidence will cause significant degradation of key electrical parameters such as output characteristics, transfer characteristics and transconductance of gallium nitride devices, and more seriously, it will directly cause damage to the internal structure of the device. Among them, single event effect is the main cause of the above problems and the core technical bottleneck restricting the space application of gallium nitride devices.

[0004] Specifically, the mechanism of single event effect is as follows: when high-energy particles in space enter the interior of the gallium nitride device, a large number of electron-hole pairs will be excited; under the action of the electric field inside the device, these carriers will collide and ionize, further generating more electron-hole pairs; this part of electron-hole pairs is collected by the device electrode through recombination, diffusion and drift, etc. Form a large instantaneous current, which may cause permanent damage between the drain and source, and even cause gate breakdown, resulting in complete failure of the device.

[0005] CN112951915A discloses a power device anti-single particle burnout reinforced structure electrode and a preparation method thereof. An N-type multi-buffer layer region structure is arranged in the drain electrode region of the semiconductor power device; a groove is formed at the source electrode and the neck region electrode, and a metal electrode is formed; an integrated transistor is arranged below the neck region; and an N-type field cutoff layer is arranged between the P-type body region and the drift region. The technical scheme of the application can greatly reduce the electric field peak value and collision ionization at the homojunction between the semiconductor power device drift region and the substrate, reduce the number of carriers generated due to avalanche multiplication caused by collision ionization, and greatly reduce the current density in the device, thereby reducing the heat generated due to current thermal effect, and significantly improving the SEB safe working voltage of the device. However, the effect of reducing single particle burnout is still not ideal.

[0006] CN112670341A discloses an enhanced power semiconductor device structure and a preparation method thereof. The device includes a heterojunction with 2DEG; a source electrode located above the heterojunction, a p-type gate with a stepped structure, and a drain electrode; and a gate electrode arranged on the p-type gate. At least part of the steps in the stepped structure is a thinned step extending from the step with the largest thickness of the p-type gate to the drain electrode side, the gate electrode is arranged on the step with the largest thickness of the p-type gate, and the thickness of the step with the largest thickness is arranged to be able to deplete the 2DEG in the heterojunction below the gate electrode. The technical scheme of the application reduces the difference in 2DEG density in the heterojunction below adjacent steps, especially the difference in 2DEG density in the heterojunction on the drain electrode side of the p-type gate and the heterojunction below the adjacent step, avoiding the problem that the breakdown voltage is reduced due to the existence of the interface with abrupt change of 2DEG density. In the invention, the gate is not processed, but an additional p-type gate structure covered by the gate is added, which is not the electrode structure of the gate. At the same time, the density difference needs to be considered, which greatly increases the processing difficulty and cost of the transistor.

[0007] In summary, developing more efficient anti-radiation performance gallium nitride device structure is the key to promoting the wide application of gallium nitride devices in aerospace and satellite detection fields, and has important research value and application prospect. SUMMARY

[0008] To solve the above technical problems, the present application provides a transistor containing a ladder structure, wherein the drain electrode is a ladder structure with steps.

[0009] The source electrode and the drain electrode are respectively located on two sides of the upper surface of the barrier layer which are not covered by the high hole concentration structure layer, the high hole concentration structure layer is a first high hole concentration structure layer covering the barrier layer and a second high hole concentration structure layer located on the first high hole concentration structure layer, the doping concentration of the first high hole concentration structure layer is less than the doping concentration of the second high hole concentration structure layer; the gate covers the surface of the high hole concentration structure layer and forms a Schottky contact with the second high hole concentration structure layer.

[0010] The drain electrode penetrates the passivation protection layer and the space on the upper surface of the barrier layer which is not covered by the high hole concentration structure layer in sequence and extends into the channel layer, and the part extending into the channel layer presents a stepped ladder structure, the low step part faces one side of the high hole concentration structure layer, and the drain electrode forms an ohmic contact with the barrier layer and the channel layer.

[0011] Further, in the transistor, the barrier layer covers the channel layer.

[0012] Further, the transistor further comprises a buffer layer covered by the channel layer.

[0013] Further, the transistor further comprises a substrate layer covered by the buffer layer.

[0014] Further, a passivation protection layer covering the barrier layer is further included, wherein the passivation protection layer covers the region on the upper surface of the barrier layer which is not covered by the source electrode, the drain electrode and the gate, and covers the region on the end surface of the barrier layer and part of the end surface of the channel layer which is not covered by other layers and should not be exposed.

[0015] Further, the source electrode penetrates the passivation protection layer and the barrier layer in sequence and extends into the channel layer, and the source electrode forms an ohmic contact with the barrier layer and the channel layer in contact.

[0016] Further, the substrate material is GaN, sapphire, Si, diamond or SiC substrate material.

[0017] Further, the buffer layer is made of one or more of GaN, AlGaN, InGaN and InAlN, and the thickness ranges from 50 nm to 10 μm.

[0018] Further, the channel layer is made of GaN, and the thickness ranges from 5 nm to 1 μm.

[0019] Further, the barrier layer is made of AlN, InN, AlGaN, InGaN or InAlN, and the thickness ranges from 5 nm to 1 μm.

[0020] Further, the first high hole concentration structure layer and the second high hole concentration structure layer are made of p-GaN, the thickness of the first high hole concentration structure layer or the second high hole concentration structure layer is 5-200 nm, and the doping concentration of the first high hole concentration structure layer or the second high hole concentration structure layer is 10 5 -10 22 / cm -3 .

[0021] Further, the thickness of the passivation protective layer is 20 nm-1 μm.

[0022] Further, the material of the passivation protective layer is SiO2, Si3N4, AlN, Al2O3, MgO, Sc2O3, TiO2, HfO2, BCB, ZrO2, Ta2O5 or La2O3.

[0023] Further, the material of the source electrode, the drain electrode and the gate electrode is Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN or any combination thereof; the combination includes combination and / or formation of alloy.

[0024] The application further provides a preparation method of the transistor comprising the ladder structure, which comprises:

[0025] The passivation protective layer is patterned according to the design scheme to form a third pattern penetrating through the passivation protective layer, the barrier layer and extending to the channel layer, and further a fifth pattern forming a step extending more to the channel layer is patterned on the side of the third pattern away from the high hole concentration structure layer, the third pattern corresponding to the low step part of the step and towards the side of the high hole concentration structure layer;

[0026] The drain electrode is integrally prepared in the third pattern and the fifth pattern, and after the preparation of the drain electrode, high-temperature alloy annealing is used to make the drain electrode form ohmic contact with the barrier layer and the channel layer.

[0027] Further, the preparation method further comprises: the passivation protective layer is patterned according to the design scheme to form a second pattern penetrating through the passivation protective layer, the barrier layer and exposing the channel layer;

[0028] The source electrode is prepared in the second pattern, and high-temperature alloy annealing is used to make the source electrode form ohmic contact with the barrier layer and the channel layer.

[0029] The application further provides a satellite power supply comprising the transistor comprising the ladder structure.

[0030] The application also provides a satellite comprising the satellite power supply.

[0031] The application has the advantages that:

[0032] The application achieves the purpose of relieving the edge electric field of the drain electrode by designing the ladder-shaped drain electrode structure, and the protruding part of the drain electrode extends to the step structure in the barrier layer and then to the channel layer. By adopting the structure of the application, the electric field strength is reduced from 6.5 MV / cm to 0.7 MV / cm, and the percentage of the reduction of the electric field strength is 89.23%, which can effectively reduce the edge electric field of the drain electrode and enhance the single-particle burnout effect resistance of the device.

[0033] In the prior art, in order to resist the single-particle burnout effect, an additional electrode is usually introduced to realize the timely collection of electron-hole pairs and inhibit the generation of transient large current. However, the application innovatively proposes to process the drain electrode, and the drain electrode of the application is designed with a special ladder-shaped step structure, which is different from the common processing method of increasing auxiliary structures. This makes the transistor prepared by the application not need complex processing steps, and does not need to pay attention to the density difference of different structure positions, and the processing process is simple, the processing difficulty is small, the processing cost is low, the yield is high, and it is conducive to large-scale popularization and application. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A transistor structure comprising a ladder-shaped structure of the application;

[0035] Figure 2 A base structure of a transistor comprising a ladder-shaped structure of the application;

[0036] Figure 3 A structure for forming a step pattern;

[0037] Figure 4 A structure for forming a first pattern;

[0038] Figure 5 A structure for forming a passivation protection layer;

[0039] Figure 6 A structure for forming a second pattern, a third pattern and a fourth pattern;

[0040] Figure 7 A structure for forming a fifth pattern;

[0041] Figure 8 A structure after processing of a source electrode and a drain electrode;

[0042] Figure 9A structure diagram after processing of the gate electrode;

[0043] Figure 10 A distribution diagram of electric field intensity of the transistor comprising the ladder structure according to the application;

[0044] Figure 11 A comparison diagram of simulation test of the transistor comprising the ladder structure according to the application.

[0045] The reference signs are:

[0046] 100-substrate, 200-buffer layer, 300-channel layer, 400-barrier layer, 501-first high hole concentration structure layer, 502-second high hole concentration structure layer, 503-first pattern, 600-passivation protection layer, 601-second pattern, 602-third pattern, 603-fourth pattern, 604-fifth pattern, 611-source electrode, 612-drain electrode, 613-gate, 401-taipat pattern. DETAILED DESCRIPTION

[0047] Figure 1 A diagram of the transistor comprising the ladder structure according to the application, wherein the drain electrode 612 is a ladder structure with steps;

[0048] The source electrode 611 and the drain electrode 612 are respectively located on two sides of the upper surface of the barrier layer 400 which is not covered by the high hole concentration structure layers 501 and 502, the high hole concentration structure layers are the first high hole concentration structure layer 501 covering the barrier layer 400 and the second high hole concentration structure layer 502 located on the first high hole concentration structure layer 501, the doping concentration of the first high hole concentration structure layer 501 is less than that of the second high hole concentration structure layer 502, and the gate 613 covers the surface of the high hole concentration structure layer and forms a Schottky contact with the second high hole concentration structure layer 502.

[0049] The drain electrode 612 penetrates the passivation protection layer 600 and the barrier layer 400 in sequence, and the part extending into the channel layer 300 presents a ladder structure with steps, the low step part is towards one side of the high hole concentration structure layers 501 and 502, and the drain electrode 612 is in ohmic contact with the barrier layer 400 and the channel layer 300.

[0050] The drain electrode 612 is close to the gate 613 on one side and presents a ladder shape, and the ladder structure is located in the channel layer 300; the ladder steps can be one-step, two-step or more.

[0051] The transistor comprising the ladder structure comprises: a substrate 100, a buffer layer 200, a channel layer 300, a barrier layer 400, high hole structure layers 501 and 502, a passivation protection layer 600, a source electrode 611, a drain electrode 612, and a gate 613; wherein the substrate layer 100, the buffer layer 200, the channel layer 300, and the barrier layer 400 are sequentially arranged from bottom to top, the high hole concentration layers 501 and 502 are arranged on the barrier layer 400, the passivation protection layer 600 covers the area on the upper surface of the barrier layer 400 which is not covered by the source electrode 611, the drain electrode 612, and the gate 613, and covers the area on the end surface of the barrier layer 400 and part of the end surface of the channel layer 300 which is not covered by other layers and should not be exposed.

[0052] The source electrode 611 sequentially penetrates the passivation protection layer 600, the barrier layer 400, and extends into the channel layer 300, and the source electrode 611 forms ohmic contact with the barrier layer 400 and the channel layer 300 in contact.

[0053] Specifically, the material of the passivation protection layer 600 is SiO2, Si3N4, AlN, Al2O3, MgO, Sc2O3, TiO2, HfO2, BCB, ZrO2, Ta2O5, or La2O3.

[0054] Specifically, the material of the source electrode 611, the drain electrode 612, and the gate 613 is Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN, or any combination thereof; the combination includes combination and / or formation of an alloy.

[0055] The preparation method of the transistor comprising the ladder structure of the present application comprises:

[0056] Wherein, Figure 2 The base structure of the transistor comprising the ladder structure of the present application is schematically shown as Figure 2 The buffer layer 200 is first grown on the substrate 100.

[0057] Preferably, the material of the substrate 100 is GaN, sapphire, Si, diamond, or SiC substrate material.

[0058] Preferably, the material of the buffer layer 200 is one or more of GaN, AlGaN, InGaN, and InAlN, and the thickness ranges from 50 nm to 10 μm.

[0059] The channel layer 300 is then grown on the buffer layer 200.

[0060] Preferably, the channel layer 300 is made of GaN and has a thickness ranging from 5 nm to 1 μm.

[0061] Then, a barrier layer 400 is grown on the channel layer 300.

[0062] Preferably, the barrier layer 400 is made of AlN, InN, AlGaN, InGaN, or InAlN, and its thickness ranges from 5 nm to 1 μm.

[0063] Further, a first high hole concentration structure layer 501 and a second high hole concentration structure layer 502 are sequentially grown on the barrier layer 400. Both the first high hole concentration structure layer 501 and the second high hole concentration structure layer 502 are made of p-GaN. The thickness of the first high hole concentration structure layer 501 or the second high hole concentration structure layer 502 is 5-200 nm, and the doping concentration of the first high hole concentration structure layer (501) or the second high hole concentration structure layer 502 is 10⁻⁶. 5 -10 22 / cm -3 .

[0064] Figure 3 The schematic diagram illustrating the stepped pattern shows that the previously grown substrate structure undergoes a first patterning process. Mesa patterns 401 are formed on both sides of the high-hole-concentration structural layers 501 and 502, the barrier layer 400, the channel layer 300, and the buffer layer 200. A partial step is formed at the buffer layer 200 in the mesa pattern 401; this step is to be covered by the passivation protective layer during subsequent processing to isolate it from other transistors. The processing employs ion implantation, photolithography, and plasma dry etching techniques to form the mesa pattern 401.

[0065] Figure 4 To form a structural schematic diagram of the first figure, as shown below Figure 4 As shown, the high hole concentration structure layers 501 and 502 are further patterned according to design requirements, removing portions to expose the barrier layer 400, and retaining portions of the first high hole concentration structure layer 501 and the second high hole concentration structure layer 502 to form a first pattern 503. The processing employs photolithography, plasma dry etching, or wet etching techniques to form the first pattern 503. The thickness of the first pattern 503 is the sum of the thicknesses of the first high hole concentration structure layer 501 and the second high hole concentration structure layer 502.

[0066] Figure 5 A schematic diagram of the structure forming the passivation protective layer, as shown below. Figure 5As shown, the passivation protective layer 600 is further processed on the aforementioned processed substrate structure to form a passivation protective layer 600 covering the mesa pattern 401, the first pattern 503 and other exposed parts. The processing process uses common processes such as deposition to form the passivation protective layer 600, for example, sputtering or chemical vapor deposition.

[0067] Specifically, the thickness of the passivation protective layer 600 is 20 nm-1 μm, and the manufacturing material can be SiO2, Si3N4, AlN, Al2O3, MgO, Sc2O3, TiO2, HfO2, BCB, ZrO2, Ta2O5 or La2O3, etc.

[0068] Figure 6 To form the structure schematic diagram of the second pattern, the third pattern and the fourth pattern, the passivation protective layer 600 is patterned according to the design scheme to form the second pattern 601 and the third pattern 602 which extend through the passivation protective layer 600 and the barrier layer 400 and reach the channel layer 300; and the fourth pattern 603 is exposed by patterning on the surface of the first pattern 503.

[0069] Figure 7 To form the structure schematic diagram of the fifth pattern, the third pattern 602 is further patterned to form the fifth pattern 604 which extends to the channel layer 300 and forms a step on the side of the third pattern 602 away from the high hole concentration structure layer 501 and 502, and the third pattern 602 corresponds to the low step part of the step and faces the side of the high hole concentration structure layer 501 and 502.

[0070] Figure 8 To form the structure schematic diagram of the processed source electrode and drain electrode, specifically, the processing process includes:

[0071] 1) Processing of the drain electrode

[0072] The drain electrode 612 is prepared in the third pattern 602 and the fifth pattern 604 according to the design scheme, and after the preparation of the drain electrode 612, high-temperature alloy annealing is used to form ohmic contact between the drain electrode 612 and the barrier layer 400 and the channel layer 300.

[0073] 2) Processing of the source electrode

[0074] The source electrode 611 is prepared in the second pattern 601 according to the design scheme, and after the preparation of the source electrode 611, high-temperature alloy annealing is used to form ohmic contact between the source electrode 611 and the barrier layer 400 and the channel layer 300.

[0075] Figure 9 To form the structure schematic diagram of the processed gate electrode, as shown inFigure 9 As shown, the gate 613 is processed as follows:

[0076] According to the design scheme, the gate 613 is prepared at the position of the exposed first pattern 503, and the gate 613 is consistent with the shapes of the high hole concentration structure layers 501 and 502 covered by the gate 613 and forms a Schottky contact.

[0077] Figure 10 For the simulation test results of the transistor structure containing the ladder-shaped structure of the present application, the red curve in the figure represents the transistor not containing the ladder-shaped structure of the present application, and the maximum electric field strength thereof is about 6.5 MV / cm, and the black curve represents the transistor containing the ladder-shaped structure of the present application, and the maximum electric field strength thereof is about 0.7 MV / cm.

[0078] Figure 11 For the comparison chart of the simulation test of the transistor structure containing the ladder-shaped structure of the present application, the black color represents that the test voltage of the drain electrode is 400 V, and the red color represents that the test voltage of the drain electrode is 450 V, and it can be seen from the figure that when the test voltage is 400 V, the electric field strength of the transistor containing the ladder-shaped structure of the present application near the drain electrode is very stable and does not suddenly increase obviously; when the test voltage is 450 V, the electric field strength of the transistor containing the ladder-shaped structure of the present application near the drain electrode suddenly increases, which proves that the drain electrode of the device is broken down at this voltage level, and the device fails.

[0079] It can be seen that the special ladder-shaped structure of the present application can effectively alleviate the electric field of the edge of the drain electrode by extending the step-shaped formation of the drain electrode metal structure to the communication channel layer 300, and it can be seen from the figure that compared with the defects of unstable structure, high processing difficulty, high cost, low service life and the like caused by adding other auxiliary structures on the gate or transistor in the prior art, the present application innovatively directly designs a special drain electrode structure, and the processing process is simpler compared with the technical solutions of many other auxiliary structures, so that the transistor structure and performance reliability are high, the cost is low, the yield is high, and it is more suitable for application scenarios in space environment.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and they should be covered in the scope of the claims of the present application.

Claims

1. A transistor comprising a ladder-shaped structure, characterized in that, The transistor comprising a ladder structure, wherein the drain electrode (612) is a ladder structure with steps; The source electrode (611) and drain electrode (612) are located on opposite sides of the upper surface of the barrier layer (400) that are not covered by the high hole concentration structure layers (501 and 502). The high hole concentration structure layers are a first high hole concentration structure layer (501) covering the barrier layer (400) and a second high hole concentration structure layer (502) located on the first high hole concentration structure layer (501). The doping concentration of the first high hole concentration structure layer (501) is less than that of the second high hole concentration structure layer (502). The gate electrode (613) covers the surface of the high hole concentration structure layer and forms a Schottky contact with the second high hole concentration structure layer. The thickness of the first high hole concentration structure layer (501) or the second high hole concentration structure layer (502) is 5-200 nm, and the doping concentration of the first high hole concentration structure layer (501) or the second high hole concentration structure layer (502) is 10 nm. 5 -10 22 / cm -3 ; The drain electrode (612) sequentially penetrates the passivation protection layer (600) and the space on the upper surface of the barrier layer (400) not covered by the high hole concentration structure layers (501 and 502), and extends into the channel layer (300). The portion extending into the channel layer (300) presents a stepped trapezoidal structure, with the lower step portion facing the side of the high hole concentration structure layers (501 and 502). The drain electrode (612) is in ohmic contact with the barrier layer (400) and the channel layer (300).

2. The transistor according to claim 1, characterized in that, In the transistor, the barrier layer (400) covers the channel layer (300).

3. The transistor according to claim 1, characterized in that, The transistor also includes a buffer layer (200) covered by the channel layer (300).

4. The transistor according to claim 3, characterized in that, The transistor also includes a substrate layer (100) covered by the buffer layer (200).

5. The transistor according to claim 2, characterized in that, It also includes a passivation protection layer (600) covering the barrier layer (400), wherein the passivation protection layer (600) covers the area on the upper surface of the barrier layer (400) that is not covered by the source electrode (611), drain electrode (612), and gate electrode (613), and covers the end face of the barrier layer (400) and part of the end face of the channel layer (300) that is not covered by other layers and should not be exposed.

6. The transistor according to claim 1, characterized in that, The source electrode (611) passes through the passivation protection layer (600) and the barrier layer (400) in sequence until it extends into the channel layer (300), and the source electrode (611) forms an ohmic contact with the barrier layer (400) and the channel layer (300) in contact with each other.

7. A method for fabricating a transistor comprising a ladder structure according to any one of claims 1-6, characterized in that, The method includes: According to the design scheme, the passivation protection layer (600) is patterned to form a third pattern (602) that runs through the passivation protection layer (600), the barrier layer (400) and extends to the channel layer (300). Further, on the side of the third pattern (602) away from the high hole concentration structure layer (501 and 502), a fifth pattern (604) that extends further towards the channel layer (300) and forms a step is patterned. The third pattern (602) corresponds to the lower part of the step and faces the side of the high hole concentration structure layer (501 and 502). In the third pattern (602) and the fifth pattern (604), the drain electrode (612) is integrally prepared. After the drain electrode (612) is prepared, it is annealed with a high-temperature alloy to form an ohmic contact with the barrier layer (400) and the channel layer (300).

8. The preparation method according to claim 7, characterized in that, The preparation method further includes: According to the design scheme, the passivation protection layer (600) is patterned to form a second pattern (601) that sequentially penetrates the passivation protection layer (600), the barrier layer (400) and exposes the channel layer (300). In the second pattern (601), a source electrode (611) is prepared and annealed with a high-temperature alloy to form an ohmic contact between the source electrode (611) and the barrier layer (400) and the channel layer (300).

9. A satellite power supply, characterized in that, Includes the transistor with a ladder structure as described in any one of claims 1-6.

10. A satellite, characterized in that, Includes the satellite power supply as described in claim 9.

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