Semiconductor device, power module, power conversion circuit, and vehicle

Abstract

The utility model discloses a semiconductor device, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged, the first surface is further provided with a source electrode groove, and the source electrode groove extends into the semiconductor body from the first surface; the source trench structure is located in the source trench and comprises a first insulating layer located on the inner wall of the source trench and a filling layer located on the side, away from the source trench, of the first insulating layer; the interlayer insulating layer is located on the first surface of the semiconductor body, the interlayer insulating layer comprises first sub-interlayer insulating layers, and the first sub-interlayer insulating layers cover the source trench structures and are arranged in one-to-one correspondence with the source trench structures; the ohmic contact layer is located on the side, away from the semiconductor body, of the interlayer insulating layer and covers the interlayer insulating layer and part of the first surface. According to the embodiment of the utility model, the source trench structure can be prevented from being excessively etched, and the electrical performance and the reliability of the semiconductor device can be improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Silicon carbide (SiC) trench gate metal-oxide-semiconductor field-effect transistors (MOSFETs) have advantages such as high current density, small cell spacing and fast switching speed, making them the main research focus of the next generation of SiC MOSFETs.

[0003] For SiC double-trench or multi-trench MOSFET structures, excessive etching may occur in the source trench structure during the fabrication of the insulating layer corresponding to the trench gate structure, which may affect the electrical performance and reliability of the semiconductor device. Utility Model Content

[0004] This invention provides a semiconductor device, a power module, a power conversion circuit, and a vehicle to solve the problem of structural damage within the source trench affecting the electrical performance and reliability of the semiconductor device.

[0005] In a first aspect, a semiconductor device is provided, comprising:

[0006] A semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other, the first surface further having a source trench, the source trench extending from the first surface into the semiconductor body;

[0007] A source trench structure is located inside the source trench, the source trench structure includes a first insulating layer located on the inner wall of the source trench and a filling layer located on the side of the first insulating layer away from the source trench;

[0008] An interlayer insulating layer is located on the first surface of the semiconductor body. The interlayer insulating layer includes a first sub-interlayer insulating layer, which covers the source trench structure and is disposed in a one-to-one correspondence with the source trench structure.

[0009] An ohmic contact layer is located on the side of the interlayer insulating layer away from the semiconductor body, covering the interlayer insulating layer and a portion of the first surface.

[0010] Optionally, the semiconductor body further includes: a well region and a first region, the first region being configured with a first conductivity type and located on the first surface, the well region being configured with a second conductivity type and located on the side of the first region away from the first surface, the first conductivity type and the second conductivity type being different;

[0011] And a second region, configured as a second conductivity type, located at the bottom and sidewalls of the source trench.

[0012] Optionally, along a direction perpendicular to the first surface to the second surface, the width of the first interlayer insulating layer is greater than or equal to the width of the source trench structure, and the width of the first interlayer insulating layer is less than the sum of the widths of the source trench structure and the second region.

[0013] Optionally, on the first surface, at least a portion of the second region is in contact with the ohmic contact layer.

[0014] Optionally, the ohmic contact layer may be made of nickel or aluminum.

[0015] Optionally, the first surface is further provided with a gate trench, the gate trench extending from the first surface into the semiconductor body;

[0016] The semiconductor device further includes a gate structure located inside the gate trench, comprising a second insulating layer located on the inner wall of the gate trench and a gate located on the side of the second insulating layer away from the gate trench; the material of the gate includes polysilicon.

[0017] The interlayer insulating layer further includes a second sub-interlayer insulating layer, which is disposed in the same layer as the first sub-interlayer insulating layer. The second sub-interlayer insulating layer covers the gate structure and is disposed in a one-to-one correspondence with the gate structure.

[0018] Optionally, the semiconductor device also includes:

[0019] The source electrode is located on the side of the ohmic contact layer away from the interlayer insulating layer;

[0020] The drain is located on the second surface of the semiconductor body.

[0021] Secondly, a power module is provided, comprising:

[0022] At least one semiconductor device as described in any embodiment of the first aspect;

[0023] A substrate for supporting the semiconductor device.

[0024] Thirdly, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction;

[0025] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the first aspect, the semiconductor device being electrically connected to the circuit board.

[0026] Fourthly, a vehicle is provided, including a load and a power conversion circuit as described in the third aspect, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0027] The semiconductor device provided in this embodiment of the invention has an interlayer insulating layer formed on the first surface of the epitaxial layer. The interlayer insulating layer includes a first dielectric portion, and the first dielectric portion is disposed in a one-to-one correspondence with the source structure disposed in the source trench. Furthermore, the orthogonal projection of the first dielectric portion onto the substrate covers the orthogonal projection of the source structure onto the substrate. This allows the first dielectric portion to protect the oxide layer in the source trench and the source structure of the polysilicon source, effectively preventing excessive etching of the source structure during the etching process to form the interlayer insulating layer, which could lead to losses and voids. This, in turn, improves the electrical performance and reliability of the semiconductor device.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a cross-sectional structural schematic diagram of a semiconductor device according to an embodiment of the present utility model;

[0031] Figure 2 This is a cross-sectional structural schematic diagram of another semiconductor device provided according to an embodiment of the present utility model;

[0032] Figure 3 This is a cross-sectional structural schematic diagram of another semiconductor device provided according to an embodiment of the present utility model;

[0033] Figure 4This is a schematic flowchart of a semiconductor device fabrication method according to an embodiment of the present invention;

[0034] Figures 5 to 11 yes Figure 4 Schematic diagrams of the cross-sectional structures of semiconductor devices corresponding to each step in the process. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0037] This utility model provides a semiconductor device. Figure 1 This is a cross-sectional structural diagram of a semiconductor device provided as an embodiment of the present invention. See also... Figure 1 The semiconductor device includes: a semiconductor body 110, a source trench structure 120, an interlayer insulating layer 130, and an ohmic contact layer 140.

[0038] The semiconductor body 110 includes a first surface 111 and a second surface 112 disposed opposite to each other. The first surface 111 is further provided with a source trench, which extends from the first surface 111 into the semiconductor body 110. A source trench structure 120 is located inside the source trench. The source trench structure 120 includes a first insulating layer 121 located on the inner wall of the source trench and a filling layer 122 located on the side of the first insulating layer 121 away from the source trench. An interlayer insulating layer 130 is located on the first surface 111 of the semiconductor body 110. The interlayer insulating layer 130 includes a first sub-interlayer insulating layer 131, which covers the source trench structure 120 and is disposed in a one-to-one correspondence with the source trench structure 120. An ohmic contact layer 140 is located on the side of the interlayer insulating layer 130 away from the semiconductor body 110 and covers the interlayer insulating layer 130 and part of the first surface 111.

[0039] Specifically, the semiconductor body 110 includes a substrate 100 and an epitaxial layer 101 stacked together. Exemplarily, the substrate 100 may include a SiC substrate with a high ion doping concentration, and the epitaxial layer 101 may be a SiC film with a low ion doping concentration. Both the substrate 100 and the epitaxial layer 101 have a first conductivity type, and the conductivity type of the film in the semiconductor device also includes a second conductivity type opposite to the first. Exemplarily, the first conductivity type may be N-type, then the second conductivity type is P-type; or, the first conductivity type may also be P-type, then the second conductivity type is N-type, without limitation. In this embodiment of the present invention, the structure of the semiconductor device provided by the present invention is described using an N-type first conductivity type and a P-type second conductivity type as an example.

[0040] The side of the epitaxial layer 101 away from the substrate 100 is the first surface 111 of the semiconductor body 110. A source trench extends from the first surface 111 into the interior of the semiconductor body 110, and the interior of the source trench is filled with a source trench structure 120. The source trench structure 120 includes a first insulating layer 121 disposed on the inner sidewall of the source trench and a filling layer 122 located on the side of the first insulating layer 121 away from the source trench. It should be noted that since the source trench is a process structure generated during the fabrication of the source trench structure 120 of the semiconductor device, therefore... Figure 1 The source trench is not shown in the figure.

[0041] An interlayer insulating layer 130 is disposed on the first surface 111 of the semiconductor body 110, and an ohmic contact layer 140 is disposed on the side of the interlayer insulating layer 130 away from the semiconductor body 110. The interlayer insulating layer 130 includes a first sub-interlayer insulating layer 131, which is disposed one-to-one above the source trench structure 120, such that the first sub-interlayer insulating layer 131 covers the orthogonal projection of the source trench structure 120 onto the substrate 100. This ensures that during the fabrication of the interlayer insulating layer 130, etching of the portion other than the retained first sub-interlayer insulating layer 131 will not cause damage to the source trench structure 120. In other words, the first sub-interlayer insulating layer 131 protects the source trench structure 120, effectively preventing over-etching of the first insulating layer 121 and the filling layer 122 in the source trench structure 120 during the etching process of forming the interlayer insulating layer 130, thereby improving the electrical performance and reliability of the semiconductor device.

[0042] The semiconductor device provided in this embodiment of the invention has an interlayer insulating layer disposed on a first surface of the semiconductor body. The interlayer insulating layer includes a first sub-interlayer insulating layer, which covers the source trench structure, and the source trench structures are disposed in a one-to-one correspondence. This allows the first sub-interlayer insulating layer to protect the source trench structure of the first insulating layer and the filling layer in the source trench, effectively preventing excessive etching of the source trench structure during the etching process to form the interlayer insulating layer, which could lead to losses and voids. This, in turn, improves the electrical performance and reliability of the semiconductor device.

[0043] Based on the above embodiments, Figure 2 This is a cross-sectional structural schematic diagram of another semiconductor device provided in this embodiment of the present invention. See also... Figure 2 Optionally, the semiconductor device further includes: a well region 180 and a first region 170, the first region 170 being configured with a first conductivity type and located on a first surface 111, the well region 180 being configured with a second conductivity type and located on the side of the first region 170 away from the first surface 111, the first conductivity type and the second conductivity type being different; and a second region 150, the second region 150 being configured with a second conductivity type and located at the bottom and sidewall of the source trench.

[0044] Specifically, both the first region 170 and the well region 180 extend from the first surface 111 into the interior of the semiconductor body 110, and the ion implantation depth of the well region 180 is greater than that of the first region 170. Among them, the well region 180 has a second conductivity type, the first region 170 has a first conductivity type, and the ion doping concentration of the first region 170 is relatively high and greater than the ion doping concentration of the semiconductor body 110; while the ion doping concentration of the well region 180 is relatively low and less than the ion doping concentration of the second region 150. The second region 150 is provided at the bottom and side walls of the periphery of the source trench structure 120. The conductivity type of the second region 150 is opposite to that of the semiconductor body 110 and has a second conductivity type, thereby forming a PN junction with the semiconductor body 110. The surface of the second region 150 is coplanar with the first surface 111, and the second region 150 contacts the ohmic contact layer 140 on the first surface 111, thereby forming a carrier transport channel of the semiconductor device.

[0045] Based on the above embodiments, continue to refer to Figure 2 , optionally, along the direction perpendicular to the first surface 111 to the second surface 112, the width of the first interlayer insulating layer 131 is greater than or equal to the width of the source trench structure 120, and the width of the first interlayer insulating layer 131 is less than the sum of the widths of the source trench structure 120 and the second region 150.

[0046] Exemplarily, the width of the first interlayer insulating layer 131 can be represented by D, the width of the source trench structure 120 can be represented by d1, and the width of the second region 150 on one side of the source trench structure 120 can be represented by d2. To ensure that the first interlayer insulating layer 131 completely covers the source trench structure 120 and protects the source trench structure 120 from being over-etched, the width D of the first interlayer insulating layer 131 should be at least equal to the width d1 of the source trench structure 120. To further reduce the possibility of the semiconductor device failing due to damage to the source trench structure 120, the width D of the first interlayer insulating layer 131 can be set to be greater than the width d1 of the source trench structure 120. Since the ohmic contact layer 140 on the side of the first interlayer insulating layer 131 away from the semiconductor body 110 needs to contact the second region 150 to form a carrier transport channel, the width D of the first interlayer insulating layer 131 cannot be too large. Exemplarily, in this embodiment, the width of the first interlayer insulating layer 131 is set to be less than the sum of the widths of the source trench structure 120 and the second regions 150 on both sides of the source trench structure 120, that is, D < d1 + 2d2. In this way, at least part of the second region 150 can be in contact with the ohmic contact layer 140 on the first surface 111, ensuring the normal electrical performance of the semiconductor device on the premise of protecting the source trench structure 120 from being damaged.

[0047] Based on the above embodiments, see below. Figure 2 Optionally, at least a portion of the second region 150 on the first surface 111 is in contact with the ohmic contact layer 140.

[0048] Specifically, since the first sub-interlayer insulating layer 131 in the interlayer insulating layer 130 completely covers the source trench structure 120, the ohmic contact layer 140 covering the surface of the interlayer insulating layer 130 is isolated from the source trench structure 120 by the first sub-interlayer insulating layer 131, so that the ohmic contact layer 140 does not directly contact the source trench structure 120; where the first sub-interlayer insulating layer 131 is not provided, the ohmic contact layer 140 can directly contact the first surface 111 to achieve carrier transport. Thus, the ohmic contact layer 140 can be formed by a single deposition of a chemically active metal material. For example, the material of the ohmic contact layer 140 includes nickel or aluminum. The first sub-interlayer insulating layer 131 can effectively prevent the formation of an alloy by contacting the source trench structure 120 with a more active metal material, which would lead to excessive consumption of the source trench structure 120 or even the formation of voids, thereby improving the reliability of the semiconductor device. Furthermore, using a more reactive metal material to prepare the ohmic contact layer 140 facilitates the formation of ohmic contacts, which helps to reduce the contact resistance between the second region 150 and the ohmic contact layer 140, thereby reducing the overall on-resistance of the semiconductor device.

[0049] Based on the above embodiments, see below. Figure 2 Optionally, the first surface 111 is further provided with a gate trench; the gate trench extends from the first surface 111 into the semiconductor body 110; the semiconductor device also includes a gate structure 160, which is located inside the gate trench and includes a second insulating layer 161 located on the inner wall of the gate trench and a gate 162 located on the side of the second insulating layer 161 away from the gate trench; the material of the gate 162 includes polysilicon;

[0050] The interlayer insulating layer 130 also includes a second sub-interlayer insulating layer 132, which is disposed on the same layer as the first sub-interlayer insulating layer 131. The second sub-interlayer insulating layer 132 covers the gate structure 160 and is disposed in a one-to-one correspondence with the gate structure 160.

[0051] Specifically, the semiconductor device provided in this embodiment of the present invention may include at least two source trenches, and the first surface 111 is further provided with at least one gate trench. The source trenches and gate trenches are arranged at intervals. Each gate trench is filled with a gate structure 160, wherein the gate structure 160 includes a second insulating layer 161 disposed on the inner wall of the gate trench and a gate 162 located on the side of the second insulating layer 161 away from the gate trench. For example, see... Figure 2This illustrates a configuration where a gate structure 160 and two source structures 120 are disposed on the first surface 111. It should be noted that, similar to the source trenches, the gate trenches are also process structures generated during the fabrication of the gate structure 160 of the semiconductor device; therefore, Figure 2 The gate trench is not shown.

[0052] At least one second sub-interlayer insulating layer 132 is provided in the interlayer insulating layer 130. Each second sub-interlayer insulating layer 132 is disposed in the same layer as each first sub-interlayer insulating layer 131. That is, each second sub-interlayer insulating layer 132 is disposed on the first surface 111 at a position corresponding to the gate structure 160, so that the second sub-interlayer insulating layer 132 covers the gate structure 160, thereby achieving insulation between the ohmic contact layer 140 covering the surface of the second sub-interlayer insulating layer 132 and the gate structure 160.

[0053] Based on the above embodiments, Figure 3 This is a cross-sectional structural schematic diagram of another semiconductor device provided in this embodiment of the present invention. See also... Figure 3 Optionally, the semiconductor device also includes:

[0054] The source electrode 190 is located on the side of the ohmic contact layer 140 away from the interlayer insulation layer 130;

[0055] Drain 200 is located on the second surface 112 of semiconductor body 110.

[0056] Specifically, a source electrode 190 is provided on the side of the ohmic contact layer 140 away from the interlayer insulating layer 130, and a drain electrode 200 is provided on the second surface 112 of the semiconductor body 110, thereby obtaining a complete semiconductor device.

[0057] This utility model embodiment also provides a method for fabricating a semiconductor device. Figure 4 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of this utility model. Figures 5 to 11 yes Figure 4 Schematic diagrams of the cross-sectional structures of the semiconductor devices corresponding to each step in the process. See also... Figures 4 to 11 The specific steps of this semiconductor device fabrication method include:

[0058] S110, a semiconductor body 110 is provided; the semiconductor body 110 includes a first surface 111 and a second surface 112 disposed opposite to each other.

[0059] For example, see Figure 5 The semiconductor body may include a substrate 100 and an epitaxial layer 101 stacked together. The substrate 100 may be an N-type heavily doped silicon carbide substrate, and an N-type lightly doped silicon carbide epitaxial layer is epitaxially grown on the surface of the substrate 100.

[0060] S120, ions of different conductivity types are implanted sequentially on the first surface 111 to form a first region 170 and a well region 180.

[0061] For example, see Figure 6 Ion implantation is performed using ions of a second conductivity type to form a well region; ion implantation is performed using ions of a first conductivity type to form a first region. The ion implantation depth in the first region is less than the ion implantation depth in the well region, and ions of the first conductivity type are not implanted at positions corresponding to the location of the source trench, thereby reducing fabrication costs to some extent.

[0062] For example, the semiconductor device may include an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. In this embodiment of the present invention, an N-type MOSFET semiconductor device is used as an example for explanation. If the first conductivity type is N-type, then the semiconductor body is an N-type semiconductor body, the well region 180 is a P-well region, and the first region 170 is an N+ doped region.

[0063] S130, a gate trench 163 and a source trench 123 are formed on the first surface 111.

[0064] For example, see Figure 7 The process involves etching from the first surface into the interior of the semiconductor body to form gate trenches and source trenches. The gate trenches and source trenches are spaced apart from each other.

[0065] S140, Ion implantation is performed on the semiconductor body 110 to form a second region 150; the second region 150 is disposed on the periphery of the source trench 123 and has a second conductivity type.

[0066] For example, see Figure 8 Ion implantation is performed from the first surface, corresponding to the periphery of the source trench, into the interior of the semiconductor body using ions of a second conductivity type, and the ion implantation depth is greater than the depth of the source trench, forming a second region.

[0067] S150, A gate structure 160 is formed inside the gate trench, and a source trench structure 120 is formed inside the source trench.

[0068] For example, see Figure 9An insulating material is deposited on the surface of the semiconductor device to form a second insulating layer 161 disposed on the inner wall of the gate trench and a first insulating layer 121 disposed on the inner wall of the source trench. Polysilicon material is deposited on the surface of the semiconductor device to form a gate 162 on the side of the second insulating layer 161 away from the gate trench and a filling layer 122 on the side of the first insulating layer 121 away from the source trench, thereby obtaining a gate structure 160 and a source trench structure 120.

[0069] S160, an interlayer insulating layer 130 is formed on the first surface 111.

[0070] For example, see Figure 10 An insulating material, such as silicon dioxide, is deposited on the first surface to form an insulating material layer. This insulating material layer is then etched to form an interlayer insulating layer. The interlayer insulating layer includes a first sub-interlayer insulating layer 131 and a second sub-interlayer insulating layer 132. The first sub-interlayer insulating layer 131 is configured to correspond one-to-one with each source trench structure, and the second sub-interlayer insulating layer 132 is configured one-to-one with each gate structure. This protects the source structures from damage and voids during the etching process, ensuring the electrical performance and reliability of the semiconductor device.

[0071] S170, An ohmic contact layer 140 is formed on the side of the interlayer insulating layer 130 away from the semiconductor body 110.

[0072] For example, see [link to previous article] Figure 10 An ohmic contact metal layer is formed by depositing a chemically reactive metal material, such as nickel or aluminum, on the surface of the interlayer insulating layer and then annealing it. At locations corresponding to the source trench and gate structures, the ohmic contact layer covers the surface of the interlayer insulating layer; at the interval between the source trench and gate structures, the ohmic contact layer contacts the first surface of the semiconductor body. In this way, the interlayer insulating layer isolates the source trench and gate structures from the ohmic contact layer, protecting them from direct contact. Therefore, the ohmic contact layer can be prepared using a chemically reactive metal material, making it easier for the ohmic contact layer to form ohmic contacts with the semiconductor material layer, improving the contact performance of the semiconductor device, and helping to reduce the overall on-resistance of the semiconductor device.

[0073] S180, a source electrode 190 is formed on the side of the ohmic contact layer 140 away from the interlayer insulation layer 130.

[0074] For example, see Figure 11 Metal material is deposited on the surface of the ohmic contact layer to form a source electrode with a flat surface.

[0075] S190, a drain 200 is formed on the second surface 112 of the semiconductor body 110.

[0076] For example, see [link to previous article] Figure 11 The second surface of the semiconductor body, i.e. the back side of the substrate, is thinned using chemical mechanical polishing (CMP). After thinning, a metal material is deposited on the second surface to form a smooth drain electrode.

[0077] The semiconductor device fabrication method provided in this embodiment of the invention forms an interlayer insulating layer on a first surface. This interlayer insulating layer includes a first sub-interlayer insulating layer corresponding to the source trench structure and a second sub-interlayer insulating layer corresponding to the gate structure. This allows the first and second sub-interlayer insulating layers to effectively protect the source trench structure and the gate structure, respectively. During the etching process to form the interlayer insulating layer, over-etching can effectively prevent damage or even voids in the source trench structure, thereby improving the electrical performance and reliability of the semiconductor device.

[0078] This invention provides a power module including a substrate and at least one semiconductor device provided in any of the embodiments of this invention, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of this power module including the semiconductor device provided in any of the embodiments of this invention will not be elaborated further here.

[0079] This invention provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device provided in any embodiment of this invention, and the semiconductor device is electrically connected to the circuit board.

[0080] Therefore, the power conversion circuit incorporates the beneficial effects of any of the semiconductor devices provided in the embodiments of the present invention, which will not be elaborated further here.

[0081] This invention also provides a vehicle including a load and a power conversion circuit as provided in any embodiment of this invention. The power conversion circuit is used to convert alternating current (AC) to direct current (DC), AC to AC, DC to DC, or DC to AC and then input the converted power to the load. Therefore, the beneficial effects of this vehicle including the power conversion circuit provided in any embodiment of this invention will not be elaborated further here.

[0082] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other, the first surface further having a source trench, the source trench extending from the first surface into the semiconductor body; A source trench structure is located inside the source trench, the source trench structure includes a first insulating layer located on the inner wall of the source trench and a filling layer located on the side of the first insulating layer away from the source trench; An interlayer insulating layer is located on the first surface of the semiconductor body. The interlayer insulating layer includes a first sub-interlayer insulating layer, which covers the source trench structure and is disposed in a one-to-one correspondence with the source trench structure. An ohmic contact layer is located on the side of the interlayer insulating layer away from the semiconductor body, covering the interlayer insulating layer and a portion of the first surface.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a well region and a first region, wherein the first region is configured with a first conductivity type and is located on the first surface, and the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface, wherein the first conductivity type and the second conductivity type are different; And a second region, configured as a second conductivity type, located at the bottom and sidewalls of the source trench.

3. The semiconductor device according to claim 2, characterized in that, Along a direction perpendicular to the first surface to the second surface, the width of the first interlayer insulating layer is greater than or equal to the width of the source trench structure, and the width of the first interlayer insulating layer is less than the sum of the widths of the source trench structure and the second region.

4. The semiconductor device according to claim 3, characterized in that, On the first surface, at least a portion of the second region is in contact with the ohmic contact layer.

5. The semiconductor device according to claim 1, characterized in that, The material of the ohmic contact layer includes nickel or aluminum.

6. The semiconductor device according to claim 1, characterized in that, The first surface is further provided with a gate trench, which extends from the first surface into the semiconductor body; The semiconductor device further includes a gate structure located inside the gate trench, comprising a second insulating layer located on the inner wall of the gate trench and a gate located on the side of the second insulating layer away from the gate trench; the material of the gate includes polysilicon. The interlayer insulating layer further includes a second sub-interlayer insulating layer, which is disposed in the same layer as the first sub-interlayer insulating layer. The second sub-interlayer insulating layer covers the gate structure and is disposed in a one-to-one correspondence with the gate structure.

7. The semiconductor device according to claim 6, characterized in that, Also includes: The source electrode is located on the side of the ohmic contact layer away from the interlayer insulating layer; The drain is located on the second surface of the semiconductor body.

8. A power module, characterized in that, include: At least one semiconductor device as described in any one of claims 1 to 7; A substrate for supporting the semiconductor device.

9. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 9, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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