Semiconductor integrated circuit in backside power distribution network architecture

Abstract

An integrated circuit includes: an insulating layer; a first conductive layer extending in a first direction in the insulating layer; a second conductive layer extending in the first direction in the insulating layer; a third conductive layer extending in the first direction in the insulating layer; a first standard cell in the insulating layer including a first cell boundary; and a second standard cell in which the first conductive layer overlaps the first cell boundary in a first direction, in which the second conductive layer is electrically connected to the first conductive layer, and configured to provide output pins that output signals converted to a plurality of voltage levels of the first standard cell, and in which the first conductive layer is electrically connected to the second conductive layer, and in which the second conductive layer is electrically connected to the second conductive layer. The third conductive layer is electrically connected to the first conductive layer and is configured to provide an input pin that receives a signal from the second standard cell.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0112880, filed with the Korean Intellectual Property Office on August 22, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to electronic devices. Specifically, this disclosure may relate to semiconductor integrated circuits in a back-end power distribution network architecture. Background Technology

[0003] Integrated circuits that process digital signals can be designed using standard cells. Functional circuits can be formed by setting up and wiring standard cells, enabling the integrated circuit to perform the required functions.

[0004] Meanwhile, with the increasing demand for high performance, high speed, and / or multifunctionality of integrated circuits, the integration density of integrated circuits is also increasing. As the integration level of integrated circuits continues to rise, various studies on back-side power distribution network architectures are actively underway. This architecture sets up a power distribution network on the back side of the substrate to route signals supplied to standard cells, thereby improving (e.g., minimizing) wiring congestion. Summary of the Invention

[0005] Embodiments of this disclosure may provide a semiconductor integrated circuit in a back-side power distribution network (BSPDN) architecture that can improve (e.g., reduce or minimize) wiring congestion and improve (e.g., optimize) the area of ​​the integrated circuit.

[0006] According to some embodiments, an integrated circuit may include: a substrate; an insulating layer on the substrate; a first conductive layer extending in the insulating layer along a first direction, wherein the first direction is parallel to an upper surface of the substrate; a second conductive layer extending in the same layer as the first conductive layer along the first direction; a third conductive layer extending in the insulating layer along the first direction; a first standard cell in the insulating layer, including a first cell boundary; and a second standard cell, wherein the first conductive layer overlaps with the first cell boundary in the first direction, wherein the second conductive layer is electrically connected to the first conductive layer and configured to provide an output pin that outputs a signal converted to a plurality of voltage levels of the first standard cell, and wherein the third conductive layer is electrically connected to the first conductive layer and configured to provide an input pin that receives a signal from the second standard cell.

[0007] According to some embodiments, an integrated circuit may include: a substrate; an insulating layer on the substrate; standard cells in the insulating layer, wherein cell boundaries of the standard cells extend along a first direction parallel to an upper surface of the substrate; pins located between cell boundaries in a second direction, the second direction being parallel to the upper surface of the substrate and intersecting the first direction, wherein the pins are configured to transmit signals converted into a plurality of voltage levels; and a conductive layer in the insulating layer and in the same layer as the pins, wherein the conductive layer overlaps with at least one cell boundary of the standard cells in the first direction, and wherein the conductive layer is electrically connected to the pins and is configured to transmit signals.

[0008] According to some embodiments, a semiconductor device may include: a substrate including a first cell region and a second cell region; a power distribution network (PDN) on a first surface of the substrate; a first insulating layer, wherein the first insulating layer includes: a first source / drain region electrically connected to the PDN via a back source / drain contact extending into the substrate through a second surface of the substrate opposite to the first surface; a second source / drain region electrically connected to a plurality of conductive layers via a first front source / drain contact and spaced apart from the first source / drain region in a first direction parallel to the first surface of the substrate; and a third source / drain region, through... The second front-side source / drain contact is electrically connected to a plurality of conductive layers, wherein a first source / drain region and a second source / drain region are disposed in a first cell region, and a third source / drain region is disposed in a second cell region; and a second insulating layer is disposed on the first insulating layer, wherein the second insulating layer comprises: a first conductive layer, which is the lowest conductive layer among a plurality of conductive layers, extends along a second direction parallel to a first surface of the substrate and perpendicular to a first direction, and is electrically connected to the first front-side source / drain contact; a second conductive layer, which is electrically connected to the second front-side source / drain contact; and a third conductive layer, which is electrically connected to the first conductive layer and the second conductive layer. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating a method for designing and manufacturing an integrated circuit according to some embodiments.

[0010] Figure 2 This is a layout diagram of an integrated circuit according to some embodiments.

[0011] Figure 3 This is a layout diagram of standard units according to some embodiments.

[0012] Figure 4 It is along Figure 3 A cross-sectional view of a standard element intercepted by line A-A'.

[0013] Figure 5 This is a layout diagram of an integrated circuit according to some embodiments.

[0014] Figure 6A This is a layout diagram of an integrated circuit according to some embodiments.

[0015] Figure 6B This is a layout diagram of an integrated circuit according to some embodiments.

[0016] Figure 7 It is along Figure 6A A cross-sectional view of the integrated circuit taken by line B-B'.

[0017] Figure 8 This is a layout diagram of an integrated circuit according to some embodiments.

[0018] Figure 9 This is a layout diagram of an integrated circuit according to some embodiments.

[0019] Figure 10 This is a layout diagram of an integrated circuit according to some embodiments.

[0020] Figure 11 This is a layout diagram of an integrated circuit according to some embodiments.

[0021] Figure 12 It is a layout diagram of an integrated circuit based on a comparative example.

[0022] Figure 13 The area reduction effect of an integrated circuit designed according to some embodiments is shown.

[0023] Figure 14 A design system for an integrated circuit according to some embodiments is illustrated schematically.

[0024] Figure 15 A semiconductor device according to some embodiments is shown. Detailed Implementation

[0025] In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings. The same reference numerals may be used for the same components in the drawings, and repeated descriptions of the same components may be omitted unless explicitly stated otherwise.

[0026] It should be understood that the embodiments described herein are intended to implement various features of this disclosure. These are merely examples and are not intended to be limiting. For example, the size of the components is not limited to the disclosed range or values ​​and can vary depending on process conditions and / or desired device characteristics. Furthermore, the following description of forming a first structure on or over a second structure can include embodiments where the first and second structures are formed in direct contact, and can also include embodiments where an additional structure is formed between the first and second structures so that the first and second structures are not in direct contact with each other. For simplicity and clarity, various structures can be drawn arbitrarily at different scales. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used to describe the relationship of one element or feature relative to another element or feature as shown in the accompanying drawings.

[0028] The accompanying drawings and descriptions should be considered illustrative in nature rather than restrictive. Unless explicitly stated otherwise, the same reference numerals may denote the same elements throughout the specification. In the flowcharts described with reference to the accompanying drawings in this specification, the order of operations may be changed, several operations may be combined, certain operations may be divided, and certain operations may be omitted.

[0029] In this description, expressions used in the singular can be interpreted as singular or plural unless explicitly expressed as “a” or “single.” While ordinal terms (such as “first” and “second”) may be used to describe a variety of components, these components are not limited to those terms. These terms are used only to distinguish one component from another.

[0030] Figure 1 This is a flowchart illustrating a method for designing and manufacturing an integrated circuit according to some embodiments.

[0031] Reference Figure 1 The method for designing and manufacturing integrated circuit 100 may include the steps of designing integrated circuit (S110) and manufacturing integrated circuit (S120).

[0032] The step of designing an integrated circuit (S110) may include generating a gate-level netlist 150, designing layout data for the circuit 160, and verifying it. This step can be performed in a design tool used to design and verify the integrated circuit.

[0033] The steps for designing an integrated circuit (S110) may include a logic synthesis step (S10) and a physical design step (S20). The logic synthesis step (S10) may refer to the step of generating a gate-level netlist 150 from RTL data 130. For example, an integrated circuit design tool (e.g., a logic synthesis tool) may perform logic synthesis to generate a gate-level netlist 150 (hereinafter referred to as a "netlist") from RTL data 130 written in a hardware description language (HDL) (such as VHSIC Hardware Description Language (VHDL) and Verilog). The gate-level netlist 150 may refer to a logical diagram representing the connection relationships between cells within the integrated circuit.

[0034] The physical design step (S20) may include a placement step (S21), a routing step (S23), and a verification step (S25). The integrated circuit design tool may receive the cell library 141 and technical documents 143 and perform each step based on them.

[0035] In the placement step (S21), standard cells can be set. For example, an integrated circuit design tool (e.g., a P&R tool) can set (e.g., locate or place) the standard cells used in the gate-level netlist 150. The integrated circuit design tool can set (e.g., locate or place) the standard cells along predefined rows based on information about the standard cells stored in the cell library 141. The cell library 141 may include layout information of the standard cells (such as the height, size, and geometry of the pattern forming the standard cells) and characteristic information of the standard cells (such as delay and leakage current).

[0036] Here, standard cells can include logic elements (such as AND, OR, inverters) and memory elements (such as flip-flops). Standard cells can be implemented using transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFETs, etc., but are not limited to these.

[0037] In the routing step (S23), the pins of the standard cells can be routed. For example, an integrated circuit design tool can connect the pins (electrically) of the standard cells set in the placement step (S21) based on the connection relationships of the standard cells in the gate-level netlist 150. The standard cells may include power pins for transmitting and receiving power supply voltage or ground voltage and signal pins for transmitting and receiving logic signals. In the following text, the pins of the standard cells may refer to signal pins.

[0038] An integrated circuit may include layers that electrically connect standard cells. Specifically, an integrated circuit may include layers in a third-party (e.g., Figure 3Layers stacked in the Z direction (as shown in the image). For example, a second layer can be formed on top of a first layer, which is the lowest layer among multiple layers. Furthermore, a third layer can be formed on top of the second layer. Each layer can be electrically connected via vias formed on that layer, and these layers and vias can electrically connect the pins of a standard cell. Multiple layers can intersect each other (e.g., in a third direction (e.g., ...). Figure 3 (The Z-direction) overlaps and extends.

[0039] For example, the first layer, which is the lowest layer among multiple layers, can be along a first direction (e.g., Figure 3 The second layer, formed on the first layer, extends along a second direction intersecting the first direction (e.g., the X direction in the first layer), and the second layer can extend along a second direction intersecting the first direction (e.g., the X direction in the first layer). Figure 3 The third layer formed on the second layer may extend in the first direction in the same (or similar) manner as the first layer, and the fourth layer formed on the third layer may extend in the second direction in the same (or similar) manner as the second layer. In the following, the first and third layers extending in the first direction may be referred to as horizontal layers, and the second and fourth layers extending in the second direction may be referred to as vertical layers. Each layer and via may include, but is not limited to, metal, conductive metal nitride, metal silicide, and / or combinations thereof (e.g., may be formed from metal, conductive metal nitride, metal silicide, and / or combinations thereof). In the following, the layer used to connect standard cells (electrically) may be referred to as a conductive layer or a metal layer.

[0040] An integrated circuit design tool can generate multiple metal layers based on information stored in technical document 143. Technical document 143 may include information about the multiple metal layers and multiple vias. For example, technical document 143 may define the names, widths, spacing, and areas of the metal layers and vias according to design rules. Technical document 143 may define the minimum and maximum widths of the first metal layer. In some embodiments, the integrated circuit design tool can generate first metal layers of various widths based on technical document 143 and use the first metal layers to electrically connect the pins of standard cells.

[0041] Multiple metal layers can be formed along multiple tracks formed on an integrated circuit. For example, a first metal layer can be formed along a first track extending in a first direction, a second metal layer can be formed along a second track extending in a second direction intersecting the first direction, and a third metal layer can be formed along a third track extending in the first direction. The first tracks extending in the first direction can be arranged in the second direction (e.g., arranged or spaced apart from each other) and can be parallel to each other. The second tracks extending in the second direction can be arranged in the first direction (e.g., arranged or spaced apart from each other) and can be parallel to each other. The third tracks extending in the first direction can be arranged in the second direction (e.g., arranged or spaced apart from each other) and can be parallel to each other. The first track and the third track can be the same or different.

[0042] In the routing step (S23), the integrated circuit design tool can create interconnection paths that connect the pins of standard cells and transmit and receive logic signals. Specifically, the integrated circuit design tool can form a first path by using multiple metal layers to connect a first pin of a first standard cell for transmitting and receiving logic signals to a second pin of a second standard cell for transmitting and receiving logic signals. This first path is an interconnection path between the first pin and the second pin. In some embodiments, the multiple metal layers forming the first path may include a first metal layer.

[0043] Integrated circuit design tools can generate layout data 160 that defines the standard cells and the generated multiple metal layers and vias. For example, the layout data 160 can have a format such as GDSII and can include geometric information of the cells as well as multiple metal layers and vias.

[0044] The verification step (S25) can be a step used to verify and modify the generated layout. Verification items may include, but are not limited to: Static Timing Analysis (STA), which verifies whether the layout meets the timing conditions of the design; Design Rule Check (DRC), which verifies whether the layout is correctly aligned with the design rules; Electronic Rule Check (ERC), which verifies whether the layout is correctly aligned and has no internal electrical disconnects; and Layout and Schematic (LVS), which verifies whether the layout matches the netlist.

[0045] The step of manufacturing an integrated circuit (S120) may include multiple steps for manufacturing a mask and forming a semiconductor package.

[0046] The step of manufacturing the integrated circuit (S120) may include performing optical proximity correction (OPC) and other processes on the layout data 160 generated in the step of designing the integrated circuit (S110) to generate mask data for forming various patterns of multiple metal layers, and a step of manufacturing a mask using the mask data. In the step of manufacturing the integrated circuit (S120), various types of exposure and etching processes may be (repeatedly) performed. These processes allow the sequential formation of patterns organized in the layout design on a silicon substrate.

[0047] Furthermore, in the step of manufacturing the integrated circuit (S120), a packaging process can be performed to mount the semiconductor device generated from the integrated circuit onto a PCB, and to mold the semiconductor device with a molding material. The packaging process can allow the use of multiple contact elements to flip or bond the semiconductor device to a substrate.

[0048] Figure 2 This is a layout diagram of an integrated circuit according to some embodiments.

[0049] Reference Figure 2 The integrated circuit 200 may include a plurality of standard cells SC, which include circuit patterns for forming various circuits. The plurality of standard cells SC may have the function of performing various logical functions. In an example embodiment, the plurality of standard cells SC may include or may be one of logic elements (such as AND, OR, inverters) and storage elements (such as latches, flip-flops, etc.). Additionally, although not shown herein, the integrated circuit 200 may also include physical units (such as padding cells).

[0050] A standard cell SC may include cell boundaries. The size of a standard cell SC may be determined by the cell boundaries. Specifically, a standard cell SC may be defined by cell boundaries, and integrated circuit design tools can identify the standard cell SC by using the cell boundaries. For example, the cell boundaries of a first standard cell 201 may include cell boundaries CB_X1 and CB_X2 in a first direction (e.g., the X direction) and cell boundaries CB_Y1 and CB_Y2 in a second direction (e.g., the Y direction) perpendicular to the first direction (e.g., the X direction). The cell boundaries of a second standard cell 202 may include cell boundaries CB_X3 and CB_X4 in a first direction (e.g., the X direction) and cell boundaries CB_Y3 and CB_Y4 in a second direction (e.g., the Y direction).

[0051] An integrated circuit design tool can pre-define multiple rows R1, R2, R3, R4, R5, and R6 extending along a first direction (e.g., the X direction) on the integrated circuit 200. The integrated circuit design tool can arrange multiple standard cells SC along the multiple rows R1, R2, R3, R4, R5, and R6. The multiple rows R1, R2, R3, R4, R5, and R6 can be regions where standard cells are arranged. Each of the multiple rows R1, R2, R3, R4, R5, and R6 can extend along the first direction (e.g., the X direction) and be arranged (e.g., arranged) along a second direction (e.g., the Y direction). The integrated circuit design tool can arrange multiple standard cells SC along the multiple rows R1, R2, R3, R4, R5, and R6. For example, a first standard cell 201 can be arranged along the first row R1, and a second standard cell 202 can be arranged along the second row R2 and the third row R3. Although Figure 2 The number of rows shown is six (6), but the number of rows can vary.

[0052] The heights of multiple standard units SC in the second direction (e.g., the Y direction) may be the same or different from each other. Specifically, the heights of the multiple standard units SC in the second direction (e.g., the Y direction) can be determined based on the length of the row in which the standard units are disposed in the second direction (e.g., the Y direction). For example, the height h of the first standard unit 201 in the second direction (e.g., the Y direction) may be equal to the length of the first row R1 in which the first standard unit 201 is disposed in the second direction (e.g., the Y direction). Hereinafter, such a standard unit may be referred to as a single-row unit. In some embodiments, the height 2h of the second standard unit 202 in the second direction (e.g., the Y direction) may be equal to the length of the multiple rows R2 and R3 in which the second standard unit 202 is disposed in the second direction (e.g., the Y direction). Hereinafter, such a standard unit may be referred to as a multi-row unit. However, multi-row units may include, but are not limited to, standard units with a unit height of 3h or higher.

[0053] Figure 2 An integrated circuit 200 is shown comprising six rows R1, R2, R3, R4, R5, and R6, but this is merely an example, and the integrated circuit 200 may include a different number of rows, and a row may include a different number of standard cells. Further details will be provided later. Figures 5 to 8 Region 210 describes integrated circuit 200.

[0054] Figure 3 This is a layout diagram of standard units according to some embodiments.

[0055] Reference Figure 3 Standard unit 300 is an integrated circuit (e.g., Figure 2One of the multiple standard units SC set in the integrated circuit 200), and the standard unit 300 in addition to Figure 3 In addition to the configuration, more configurations can be included.

[0056] Integrated circuit design tools can use cell libraries (e.g., Figure 1 The standard cell 300 generated from the cell library 141 in the database is used to design integrated circuits. The standard cell 300 may include a circuit pattern having a layout designed according to layout and routing (PnR) technology to perform at least one logic function. Specifically, the standard cell 300 may include a plurality of active regions F1, a gate line GL, a source / drain region 310, and a source / drain contact CA.

[0057] Reference Figure 3 The standard cell 300 may include a plurality of active regions F1. The plurality of active regions F1 may extend along a first direction (e.g., the X direction) and may be arranged (e.g., arranged or spaced apart from each other) along a second direction (e.g., the Y direction). The plurality of active regions F1 may be parallel to each other. Active patterns formed in the plurality of active regions F1 may intersect with gate lines GL (e.g., overlap with gate lines GL in a third direction) to form transistors.

[0058] Multiple gate lines GL can be disposed on multiple active regions F1. Each gate line GL can extend along a second direction (e.g., Y direction) intersecting a first direction (e.g., X direction). The multiple gate lines GL can overlap at least a portion of the multiple active regions F1 in the XY plane. The gate lines GL can comprise any conductive material (e.g., can be formed of any conductive material). Gate contacts CB can be disposed on the gate lines GL. The gate lines GL can be (electrically) connected to multiple metal layers within the integrated circuit 200 via the gate contacts CB.

[0059] Multiple source / drain regions 310 can be formed in multiple active regions F1, and multiple source / drain contacts CA can be formed in contact with the source / drain regions 310. The source / drain contacts CA can be (electrically) connected to some of the source / drain regions 310 formed in the multiple active regions F1. The source / drain contacts CA can extend from the multiple active regions F1 along a third direction (e.g., the Z direction). The source / drain contacts CA can (electrically) connect multiple metal layers within the integrated circuit 200 to the source / drain regions 310 via vias. Hereinafter, the source / drain contacts CA disposed from the multiple active regions F1 along a third direction (e.g., the Z direction) can be referred to as front-side source / drain contacts. According to some embodiments, the source / drain regions of the standard cell 300 can send and receive logic signals from multiple metal layers through the front-side source / drain contacts CA. According to some embodiments, among the source / drain regions 310 of the standard cell 300, the source / drain regions 310 (electrically) connected to the front-side source / drain contacts CA can correspond to signal pins of the standard cell 300.

[0060] The back-side source / drain contact DBC can be formed on opposite sides (e.g., opposite sides in a third direction (e.g., the Z direction)) of the front-side source / drain contact CA based on (relative to) multiple source / drain regions 310. The back-side source / drain contact DBC can be (electrically) connected to some of the source / drain regions 310 formed in multiple active regions F1. The back-side source / drain contact DBC can (electrically) connect multiple source / drain regions (e.g., source / drain regions 310) to the back-side conductive pattern described below. According to some embodiments, the source / drain regions 310 of the standard cell 300 can receive power supply voltage and / or ground voltage from the back-side conductive pattern through the back-side source / drain contact DBC. According to some embodiments, among the source / drain regions 310 of the standard cell 300, the source / drain regions 310 (electrically) connected to the back-side source / drain contact DBC can correspond to the power pins of the standard cell 300.

[0061] Each of the multiple source / drain regions 310 can be (electrically) connected to one of the front source / drain contact CA and the rear source / drain contact DBC.

[0062] Figure 4 It is along Figure 3 A cross-sectional view of a standard element intercepted by line A-A'.

[0063] Reference Figure 4The standard cell 400 includes a substrate insulating layer 410, an active region 420 on the substrate insulating layer 410, and an insulating layer 430 on the active region 420, and may include various patterns formed within each layer. Additionally, the standard cell 400 may include a back insulating layer 401 and a back conductive pattern 403 formed on (within) the back insulating layer 401. However, the structure of the standard cell 400 is not limited thereto. For example, the standard cell 400 may also include additional layers between each layer, or may not include some of the layers described above, or may include additional configurations formed in each layer, or may not include some configurations formed in each layer described above or later.

[0064] Reference Figure 4 The standard unit 400 may include a substrate insulating layer 410. The substrate insulating layer 410 may be a substrate or an insulating substrate. The substrate insulating layer 410 may include, for example, oxides, nitrides, oxynitrides and / or combinations thereof.

[0065] The standard cell 400 may include an active region 420. The active region 420 may be disposed on a first surface 413 of the substrate insulating layer 410 and may have a thickness in a third direction (e.g., the Z direction). Source / drain regions 421, 423, and 425 may be formed in the active region 420. The source / drain regions 421, 423, and 425 may be spaced apart from each other in a first direction (e.g., the X direction).

[0066] Standard cell 400 may include an insulating layer 430 on an active region 420. The insulating layer 430 may include a plurality of gate structures GS and source / drain contacts 432 and 434. The plurality of gate structures GS may be disposed on the active region 420. The plurality of gate structures GS may be spaced apart from each other in a first direction (e.g., the X direction) and may extend along a second direction (e.g., the Y direction). The gate structure GS may include a gate electrode 435 and a gate insulating layer 433. The gate insulating layer 433 may extend along a side surface of a gate spacer 431. The gate structure GS may be disposed between source / drain regions 421 and 423 and / or between source / drain regions 423 and 425 (in the first direction (e.g., the X direction)). The source / drain regions 421, 423, and 425 and the gate structure GS may form a transistor.

[0067] Source / drain contacts 432 and 434 may be spaced apart from each other in a first direction (e.g., the X direction) and may extend through the insulating layer 430 in a third direction (e.g., the Z direction) perpendicular to the first direction (e.g., the X direction) and the second direction (e.g., the Y direction). For example, source / drain contacts 432 and 434 may extend into the insulating layer 430 (in the third direction). Source / drain contacts 432 and 434 may make electrical contact with source / drain regions 423 and 425. For example, source / drain contacts 432 and 434 may (respectively) extend into source / drain regions 423 and 425. Source / drain contacts 432 and 434 may (electrically) connect multiple metal layers formed on the insulating layer 430 to source / drain regions 423 and 425. Source / drain regions 423 and 425 can receive electrical signals from other standard units and send electrical signals to other standard units, or provide electrical signals to other standard units, through source / drain contacts 432 and 434.

[0068] The standard unit 400 may include a back-side source / drain contact 411 that (electrically) connects the source / drain region 421 to the back-side conductive pattern 403. The back-side source / drain contact 411 may extend into the substrate insulating layer 410 and the active region 420 in a third direction (e.g., the Z direction) (e.g., penetrating the substrate insulating layer 410 and the active region 420). Accordingly, the back-side source / drain contact 411 may contact a portion of the source / drain region 421. In some embodiments, the back-side source / drain contact 411 may have a width that gradually narrows in a horizontal direction (e.g., a first direction and / or a second direction) from the second surface 415 of the substrate insulating layer 410 toward the source / drain region 421. That is, the back-side source / drain contact 411 may have a tapered shape in a third direction (e.g., the Z direction). The second surface 415 may be opposite to the first surface 413 in a third direction. For example, the first surface 413 and the second surface 415 may be the upper and lower surfaces of the substrate insulating layer 410, respectively. The back-side source / drain contact 411 may include, for example, metal, metal alloy, conductive metal nitride, conductive metal carbide and / or conductive metal oxide.

[0069] The standard unit 400 may include a back insulating layer 401. The back insulating layer 401 may be disposed on a second surface 415 of the base insulating layer 410. The upper surface of the back insulating layer 401 may contact a portion of the lower surface of the back source / drain contact 411. The back insulating layer 401 may include a back conductive pattern 403. The back conductive pattern 403 may include conductive patterns spaced apart in a third direction (e.g., the Z direction) and vias connecting (at least) two conductive patterns. In some embodiments, an externally supplied power supply voltage, etc., may be provided to the source / drain region 421 through the back conductive pattern 403 and the back source / drain contact 411. Specifically, the standard unit 400 may receive a power supply voltage, etc., from the outside through the back conductive pattern 403 and the back source / drain contact 411. Accordingly, according to some embodiments, the multiple metal layers formed on the insulating layer 430 of the standard unit 400 may not provide a power supply voltage, etc., to the standard unit 400. As used below, the terms “external configuration”, “external device”, “external power supply”, “external signal” or “external” are intended to refer broadly to devices, circuits, blocks, modules, power supplies and / or signals that reside externally (e.g., outside functional or physical boundaries) relative to a given circuit, block, module, system or device.

[0070] Meanwhile, although the standard cell 400 is shown as being formed as a FinFET, the active pattern formed on the active region 420 within the standard cell 400 can be formed in various shapes. For example, the standard cell 400 can be formed as a gate full-ring (GAA) transistor (where nanowires are surrounded by gate lines on the active region), or as a multi-bridge channel (MBC) transistor (where multiple nanosheets are stacked on the active region and gate lines surround the nanosheets), but is not limited thereto.

[0071] Figure 5 This is a layout diagram of an integrated circuit according to some embodiments. Specifically, integrated circuit 500 may correspond to... Figure 2 The integrated circuit region 210, and the standard cells of the integrated circuit 500 can be connected via a back conductive pattern (e.g., Figure 4 The back conductive pattern 403) and the back source / drain contact (e.g., Figure 4 The back-side source / drain contact 411 receives power supply voltage from the outside.

[0072] Reference Figure 5Multiple tracks with multiple metal layers disposed thereon can be defined on integrated circuit 500. For example, multiple tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 extending along a first direction (e.g., the X direction) can be defined on integrated circuit 500. Multiple tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 can extend along the first direction (e.g., the X direction) and be arranged (or spaced apart) along a second direction (e.g., the Y direction). Multiple tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 can be parallel to each other. The first metal layer M1 may be disposed along multiple tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11, which extend along a first direction (e.g., the X direction). For example, the first metal layer M1 may overlap with the multiple tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 extending along the first direction (e.g., the X direction) in a third direction (e.g., the Z direction).

[0073] In some embodiments, some of the multiple tracks T1, T6, and T11 may overlap with the boundaries CB_X1, CB_X2, and CB_X3 of the multiple standard units SC in a first direction (e.g., the X direction), and the remaining tracks T2, T3, T4, T5, T7, T8, T9, and T10 may be disposed between the boundaries CB_X1, CB_X2, and CB_X3 of the multiple standard units SC in the first direction (e.g., the X direction) (and disposed therebetween in a second direction (e.g., the Y direction)).

[0074] In some embodiments, the integrated circuit design tool may configure the first metal layer M1 to overlap with a plurality of tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11. For example, the first metal layer M1 included in the interconnect path through which logic signals of standard cells are transmitted may be disposed on tracks T1, T6, and T11 of the plurality of tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 that overlap with the boundaries CB_X1, CB_X2, and CB_X3 of the plurality of standard cells SC extending in a first direction (e.g., the X direction) (e.g., overlapping with the boundaries CB_X1, CB_X2, and CB_X3 in the first direction (e.g., the X direction)). In some embodiments, a first metal layer M1 corresponding to the pins of a plurality of standard cells SC may be disposed on tracks T2, T3, T4, T5, T7, T8, T9 and T10, which are disposed between the boundaries CB_X1 and CB_X2 or CB_X2 and CB_X3 extending along a first direction (e.g., the X direction) of the plurality of standard cells SC (disposed therebetween in a second direction (e.g., the Y direction)).

[0075] In some embodiments, the integrated circuit design tool may use a first metal layer M1 of a plurality of metal layers to generate the pins of a standard cell. Specifically, the integrated circuit design tool may generate source / drain contacts within the standard cell and on the active region F1 (e.g., Figure 4 The first metal layer M1, electrically connected to the source / drain contacts 432 and 434 in the first standard cell, serves as a pin of the standard cell. For example, among the plurality of first metal layers M1 on the first standard cell SC1, the first layer 501 may correspond to the input pin of the first standard cell SC1, and among the plurality of first metal layers M1 on the first standard cell SC1, the second layer 502 may correspond to the output pin of the first standard cell SC1. The first layer 501 corresponding to the input pin of the first standard cell SC1 may be arranged along the second track T2, and the second layer 502 corresponding to the output pin of the first standard cell SC1 may be arranged along the third track T3. In the following text, the first metal layer M1 corresponding to the pin of the standard cell may be referred to as the pin of the standard cell.

[0076] Here, each standard unit is shown overlapping with six tracks, but the number of tracks overlapping with each standard unit can vary. Furthermore, tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 according to this disclosure are tracks on which a first metal layer M1 is disposed; a second metal layer M2 can be disposed along a track extending in a second direction (e.g., the Y direction) perpendicular to the first direction (e.g., the X direction); and a third metal layer M3 can be disposed along a track extending in the same or different first direction (e.g., the X direction) as the track on which the first metal layer M1 is disposed, but its specific description is omitted herein.

[0077] Figure 6A and Figure 6B This is a layout diagram of an integrated circuit according to some embodiments. Specifically, Figure 6A and Figure 6B A first metal layer M1 disposed on an integrated circuit according to some embodiments is shown.

[0078] Reference Figure 6A Integrated circuit 600A may include multiple interconnect paths that directly (electrically) connect standard cells. For example, integrated circuit 600A may include a first path 610 that (electrically) connects pin P10 on the second track T2 of the first standard cell SC1 to pin P40 on the fourth track T4 of the fourth standard cell SC4. Integrated circuit 600A may include a second path 620 that (electrically) connects pin P11 on the third track T3 of the first standard cell SC1 to pin P30 on the fifth track T5 of the third standard cell SC3. Integrated circuit 600A may include a third path 630 that (electrically) connects pin P20 on the ninth track T9 of the second standard cell SC2 to pin P50 on the eighth track T8 of the fifth standard cell SC5. Each interconnect path may include multiple metal layers.

[0079] In some embodiments, integrated circuit design tools may use a first metal layer M1 to form interconnect paths, where the first metal layer M1 is the lowest layer among multiple layers. In this case, the first metal layer M1 of the interconnect path may be disposed on the track of pins without standard cells among multiple tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11. (Refer to...) Figure 6AIntegrated circuit design tools can place the first metal layer M1 of interconnect paths on the remaining tracks T1, T6, and T11, excluding those tracks T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 where standard cell pins are disposed. For example, the first path 610 may include second metal layers 611 and 615 (electrically connected) to pins P10 and P40, and a first metal layer 613 disposed on the first track T1. The second path 620 may include second metal layers 621 and 625 (electrically connected) to pins P11 and P30, and a first metal layer 623 disposed on the sixth track T6. The third path 630 may include second metal layers 631 and 635 (electrically connected) to pins P20 and P50, and a first metal layer 633 disposed on the eleventh track T11. In other words, the track on which the pins of the standard cell are formed and the track on which the first metal layer M1 included in the interconnect path are disposed can be different from each other. At the same time, different types of layers can be electrically connected to each other through vias V1.

[0080] In some embodiments, the integrated circuit design tool may place a first metal layer M1 within an interconnect path on one of a plurality of tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 that overlaps with the cell boundary of a standard cell in a first direction (X). The first track T1 and the sixth track T6 may overlap with the cell boundaries CB_X1 and CB_X2 of the first standard cell SC1 in the first direction (e.g., the X direction), respectively, and the eleventh track T11 may overlap with the cell boundary CB_X3 of the second standard cell SC2 in the first direction (e.g., the X direction).

[0081] In this way, the integrated circuit design tool can place the first metal layer M1 included in the interconnect path on the track of the pin where no standard cell is formed. The integrated circuit design tool can also place the first metal layer M1 included in the interconnect path on a track that overlaps with the cell boundary of the standard cell in a first direction (e.g., the X direction). According to some embodiments, by using the first metal layer M1 as the interconnect path, the integrated circuit can have the advantages of improving (e.g., reducing) wiring congestion and improving (e.g., optimizing or reducing) the size of the integrated circuit.

[0082] In some embodiments, the widths of the first metal layers M1 included in the interconnect path may be equal or different. Here, the width of the first metal layer M1 may refer to the width of the first metal layer M1 in a second direction (e.g., the Y direction).

[0083] For reference Figure 1As mentioned above, integrated circuit design tools can be based on technical documents (e.g., Figure 1 Multiple metal layers are generated according to the minimum and maximum widths of each metal layer as defined in technical document 143. (Refer to...) Figure 6A The first metal layer 613 included in the first path 610 may have a second width W2, and the first metal layer 623 included in the second path 620 may have a third width W3. The second width W2 and the third width W3 may be equal or different. The second width W2 and the third width W3 may be greater than (wider than) the first width W1 of the first metal layer M1 formed as a pin (e.g., pin P11) as a standard cell. Meanwhile, the fourth width W4 of the first metal layer 633 included in the third path 630 may be less than (narrower than) the second width W2 and the third width W3. The fourth width W4 may be equal to or greater than the first width W1. Integrated circuit design tools may use the first metal layer M1 with a relatively large (wider) width (e.g., W2 or W3) as an interconnect path to reduce the resistance of the interconnect path. In some embodiments, integrated circuit design tools may use the first metal layer M1 with a relatively small (narrower) width (e.g., W4) as an interconnect path to reduce the coupling capacitance of the interconnect path. Integrated circuit design tools can determine and generate the width of the first metal layer M1 of the interconnect path based on the characteristics of the interconnect path and the minimum and maximum widths of the first metal layer M1 as defined in technical document 143.

[0084] Meanwhile, the location of the first metal layer M1 included in the interconnect path is not limited thereto. In some embodiments, the first metal layer M1 included in the interconnect path may overlap in the XY plane with at least one cell boundary extending along a first direction (e.g., the X direction) among the cell boundaries of a plurality of standard cells included in the integrated circuit. In some embodiments, the location of the first metal layer M1 included in the interconnect path in a second direction (e.g., the Y direction) may be substantially the same as the location of at least one cell boundary extending along the first direction (e.g., the X direction) among the cell boundaries of a plurality of standard cells included in the integrated circuit in the second direction (e.g., the Y direction). (Refer to...) Figure 6B The first standard cell SC1 and the fourth standard cell SC4 of integrated circuit 600B can be interconnected via a fourth path 640. The fourth path 640 interconnects pin P10 of the first standard cell SC1 with pin P40 of the fourth standard cell SC4. The fourth path 640 can correspond to... Figure 6AThe first path 610. The fourth path 640 may include second metal layers 641 and 645 (electrically) connected to pins P10 and P40, and a first metal layer 643 disposed on the nth track Tn. The nth track Tn may be a track overlapping with the cell boundary CB_X6 of the sixth standard cell SC6 in the first direction (e.g., the X direction), the cell boundary CB_X7 of the seventh standard cell SC7 in the first direction (e.g., the X direction), and the cell boundary CB_X8 of the eighth standard cell SC8 in the first direction (e.g., the X direction).

[0085] In some embodiments, the first metal layer 643 may overlap with the cell boundary CB_X6 of the sixth standard cell SC6, the cell boundary CB_X7 of the seventh standard cell SC7, and / or the cell boundary CB_X8 of the eighth standard cell SC8 in the first direction (e.g., the X direction) among the plurality of standard cells included in the integrated circuit 600B. In some embodiments, the position of the first metal layer 643 in the second direction (e.g., the Y direction) may be the same as the position of the cell boundary CB_X6 of the sixth standard cell SC6, the cell boundary CB_X7 of the seventh standard cell SC7, and / or the cell boundary CB_X8 of the eighth standard cell SC8 in the first direction (e.g., the X direction) in the second direction (e.g., the Y direction) among the plurality of standard cells included in the integrated circuit 600B. Thus, there can be multiple interconnection paths connecting the pins of the standard cells.

[0086] Figure 7 It is along Figure 6A A cross-sectional view of the integrated circuit taken by line B-B'.

[0087] Reference Figure 7 The integrated circuit 700 may include a first unit region 791 and a second unit region 793. Here, the first unit region 791 corresponds to... Figure 6A The region of the fifth standard unit SC5, and the region of the second unit 793 corresponds to Figure 6A The region of the third standard unit SC3.

[0088] In some embodiments, the integrated circuit 700 may include a substrate insulating layer 710, an active region 720, and a plurality of insulating layers 730, 740, and 750 on the active region 720. The integrated circuit 700 may include a plurality of source / drain regions 721, 723, 725, and 727 formed in the active region 720, and a back-side source / drain contact 711 extending into the substrate insulating layer 710 and the active region 720 (e.g., penetrating the substrate insulating layer 710 and the active region 720) and contacting the source / drain region 721. The back-side source / drain contact 711 may be (electrically) connected to a back-side conductive pattern 703 within the back-side insulating layer 701. The source / drain regions 723 and 725 may be (electrically) connected to source / drain contacts 732 and 734 disposed on (within) the insulating layer 730 formed on the active region 720. The structure of the substrate insulating layer 710, the active region 720, and the multiple insulating layers 730 on the active region 720 of the integrated circuit 700 is similar to... Figure 4 The structure of the standard unit 400 is the same or similar, and therefore, a detailed description of it can be omitted.

[0089] In some embodiments, the integrated circuit 700 may include a via V0 and a plurality of first metal layers M1 disposed on an insulating layer 740 and electrically connected to a source / drain contact 734. The plurality of first metal layers M1 may be spaced apart from each other in a second direction (e.g., the Y direction). The plurality of first metal layers M1 may include pins P5 of a fifth standard unit SC5 and pins P3 of a third standard unit SC3. Some pins P3 and P5 may be electrically connected to the source / drain contact 734 through the via V0. The first width W1 of each pin P3 and P5 in the second direction (e.g., the Y direction) may be equal.

[0090] In some embodiments, the plurality of first metal layers M1 may include first metal layers 741, 743, and 745 within a plurality of interconnect paths. The first metal layers 741, 743, and 745 within the plurality of interconnect paths may be arranged at cell boundaries CB_X11, CB_X12, and CB_X13 extending along a first direction (e.g., the X direction) of standard cells SC3 and SC5. The widths W2, W3, and W4 of the first metal layers 741, 743, and 745 within the plurality of interconnect paths may be equal to or different from each other. The widths W2, W3, and W4 of the first metal layers 741, 743, and 745 within the plurality of interconnect paths may be greater than (wider than) the first width W1 of pin P.

[0091] In some embodiments, the first metal layers P3 and P5, which form the pins of the standard unit, and the first metal layers 741, 743, and 745 in the plurality of interconnect paths may be arranged on the same layer. A portion of the first metal layer M1 may be electrically connected to the second metal layer M2 through a via V1 disposed in the insulating layer 750. Although some metal layers M1 and M2 are shown herein, the integrated circuit 700 may include more upper metal layers (such as M3, M4, M5, etc., which may be disposed on M2, but are not shown).

[0092] Figure 8 This is a layout diagram of an integrated circuit according to some embodiments.

[0093] Reference Figure 8 The integrated circuit 800 may include multiple standard cells and multiple metal layers disposed on the integrated circuit 800. Each metal layer may be disposed along a predefined track. For example, the first metal layer M1 may be disposed along multiple tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 and T11 defined on the integrated circuit 800.

[0094] In some embodiments, the interconnect path may include multiple metal layers. For example, the interconnect path 810 connecting pin P11 of the first standard unit SC1 to pin P50 of the fifth standard unit SC5 (electrically) may include a second metal layer 801, a second metal layer 803, and a first metal layer 805 disposed in the sixth track T6. The metal layers may be electrically connected to each other via via V1. For example, the second metal layer 801 may be electrically connected to pin P11 of the first standard unit SC1 via via V1, the second metal layer 803 may be electrically connected to pin P50 of the fifth standard unit SC5 via via V1, and the first metal layer 805 may be electrically connected to the second metal layers 801 and 803 via via V1.

[0095] In some embodiments, the width of the first metal layer disposed on the track in the interconnect path can vary depending on the segment. Specifically, the first metal layer 805 disposed on the sixth track T6 in the interconnect path 810 can have a first width W1 in the first segment E1 and a second width W2 in the second segment E2. For example, integrated circuit design tools can determine different widths of the first metal layer 805 in each segment to reduce the resistance of the first metal layer 805 in the first segment E1 and improve the coupling capacitance with other layers adjacent to the first metal layer 805 in the second segment E2. The integrated circuit design tools can determine different widths of the first metal layer 805 in each segment by taking into account the characteristics of standard cells (e.g., first standard cell SC1) disposed adjacent to the first segment E1 and the characteristics of standard cells (e.g., fifth standard cell SC5) disposed adjacent to the second segment E2. The widths W1 and W2 of the first metal layer 805 can be specified in the technical documentation (…). Figure 1 The value between the minimum and maximum width of the first metal layer M1 as defined in technical document 143.

[0096] Figure 9 This is a layout diagram of an integrated circuit according to some embodiments. Figure 9 The configuration of the integrated circuit 900 and Figure 2 The configuration of the integrated circuit 200 is the same or similar, so any repeated descriptions can be omitted.

[0097] Integrated circuit design tools can arrange multiple standard cells SC along multiple rows R1, R2, R3, R4, R5, and R6 on an integrated circuit 900, which extend along a first direction (e.g., the X direction). The heights of the multiple standard cells SC in a second direction (e.g., the Y direction) can be equal or different. For example, the first standard cell SC1 can be a multi-row cell, and the second standard cell SC2 and the third standard cell SC3 can be single-row cells. (See below for reference.) Figure 10 and Figure 11 Provides a description of region 910 of integrated circuit 900.

[0098] Figure 10 and Figure 11 This is a layout diagram of an integrated circuit according to some embodiments. Specifically, integrated circuits 1000 and 1100 may correspond to integrated circuits (…). Figure 9 In region 910 of the 900), and the standard cells of integrated circuits 1000 and 1100 can receive power supply voltage from the outside through the back conductive pattern and the back source / drain contact, etc.

[0099] Reference Figure 10The integrated circuit 1000 may include a plurality of standard cells SC disposed along a plurality of rows R2 and R3 and a plurality of first metal layers M1 disposed along a plurality of tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 and T11. Some of the tracks T1, T6 and T11 on the integrated circuit 1000 may overlap with the cell boundaries of the plurality of standard cells in a first direction (e.g., the X direction). Specifically, the first track T1 may overlap with the cell boundary CB_10 of the first standard cell SC1 in the first direction (e.g., the X direction), the sixth track T6 may overlap with the cell boundary CB_12 of the second standard cell SC2 in the first direction (e.g., the X direction), and the eleventh track T11 may overlap with the cell boundary CB_11 of the first standard cell SC1 in the first direction (e.g., the X direction) and the cell boundary CB_13 of the second standard cell SC2 in the first direction (e.g., the X direction). Among the multiple tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 on the integrated circuit 1000, the positions of some tracks T1, T6, and T11 in the second direction (Y) may be the same as the positions of the cell boundaries (cell boundaries in the first direction (e.g., the X direction)) of multiple standard cells in the second direction (e.g., the Y direction). Specifically, the position of the first track T1 in the second direction (e.g., the Y direction) can be the same as the position of the cell boundary CB_10 of the first standard cell SC1 (extending along the first direction (e.g., the X direction)) in the second direction (e.g., the Y direction), the position of the sixth track T6 in the second direction (e.g., the Y direction) can be the same as the position of the cell boundary CB_12 of the second standard cell SC2 (extending along the first direction (e.g., the X direction)) in the second direction (e.g., the Y direction), and the position of the eleventh track T11 in the second direction (e.g., the Y direction) can be the same as the position of the cell boundary CB_11 of the first standard cell SC1 (extending along the first direction (e.g., the X direction)) and the cell boundary CB_13 of the second standard cell SC2 (extending along the first direction (e.g., the X direction) in the second direction (e.g., the Y direction).

[0100] In some embodiments, the first metal layer included in the interconnect path may be disposed on one of the plurality of tracks T1, T6, and T11 that overlap with the cell boundary of the standard cell in the first direction (e.g., the X direction). For example, the interconnect path 1020 connecting the first standard cell SC1 and the second standard cell SC2 (electrically) may include a first metal layer 1010 disposed on the sixth track T6, the first metal layer 1010 being positioned in the second direction (e.g., the Y direction) at the same position as the cell boundary CB_12 of the second standard cell SC2 extending along the first direction (e.g., the X direction) in the second direction (e.g., the Y direction). Meanwhile, the interconnect path 1020 that electrically connects the first standard cell SC1 and the second standard cell SC2 may include a first metal layer disposed in a track that overlaps with the cell boundary of a standard cell (extending along a first direction (e.g., the X direction) among a plurality of standard cells in the integrated circuit 1000, excluding the first standard cell SC1 and the second standard cell SC2, but is not limited thereto. In some embodiments, the track on which the first metal layer included in the interconnect path is disposed may be different from the track on which the pins of the standard cells are disposed. Specifically, the position of the first metal layer 1010 included in the interconnect path 1020 in the second direction (e.g., the Y direction) may be different from the position of the pins of the first standard cell SC1 and the second standard cell SC2 in the second direction (e.g., the Y direction).

[0101] In some embodiments, the width W1 of the first metal layer 1010 in the interconnect path 1020 may be different from the width W2 of the first metal layer as the pin output of the first standard unit SC1. Specifically, the width W1 of the first metal layer 1010 in the interconnect path 1020 may be greater than the width W2 of the first layer as the pin output of the first standard unit SC1. Therefore, the resistance of the interconnect path 1020 can be reduced.

[0102] Reference Figure 11 In some embodiments, the width of a first metal layer disposed on a track in an interconnect path can vary depending on the segment. Specifically, the first metal layer 1110 disposed on the sixth track T6 in interconnect path 1120 can have a first width W1 in the first segment E1 and a third width W3 in the second segment E2. For example, integrated circuit design tools can determine different widths of the first metal layer 1110 in each segment to reduce the resistance of the first metal layer 1110 in the first segment E1 and improve the coupling capacitance with layers adjacent to the first metal layer 1110 in the second segment E2. The widths W1 and W3 of the first metal layer 1110 can be specified in technical documents (e.g., Figure 1The value between the minimum and maximum width of the first metal layer M1 as defined in technical document 143.

[0103] Figure 12 It is a layout diagram of an integrated circuit based on a comparative example.

[0104] According to a comparative example, integrated circuit 1200 may include a plurality of standard cells arranged along a plurality of predefined rows R1 and R2 extending along a first direction (e.g., the X direction). The plurality of standard cells may include a plurality of pins arranged along a plurality of tracks.

[0105] According to a comparative example, integrated circuit 1200 may include a plurality of first metal layers 1210, 1220, and 1230 providing power supply voltage and ground voltage to a plurality of standard cells. The plurality of first metal layers 1210, 1220, and 1230 providing power supply voltage and ground voltage to the plurality of standard cells may be disposed as power rails at the cell boundaries of the plurality of standard cells (extending along a first direction (e.g., the X direction)). The plurality of first metal layers 1210, 1220, and 1230 may be disposed on rails T1, T6, and T11, which overlap with the cell boundaries of the plurality of standard cells (extending along the first direction (X)). The plurality of first metal layers 1210, 1220, and 1230 may extend along the first direction (e.g., the X direction) and be disposed (e.g., arranged or spaced apart from each other) along a second direction (e.g., the Y direction). Multiple first metal layers 1210, 1220 and 1230 can be parallel to each other.

[0106] According to the comparative example, the first metal layer M1 can be disposed on multiple tracks T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 within the integrated circuit 1200. For example, the pins of a standard cell are disposed on some tracks T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11, and power rails for providing power supply voltage and ground voltage to the standard cell are disposed on the remaining tracks T1, T6, and T11. Therefore, according to the comparative example, the integrated circuit design tool can use a third metal layer M3 and a fifth metal layer M5, in addition to the first metal layer M1, as horizontal layers within the interconnect path. (Refer to...) Figure 12The interconnect path 1240 that electrically connects the first standard cell SC1 and the second standard cell SC2 may include second metal layers 1241 and 1243 and a third metal layer 1242. According to a comparative example, since the number of metal layers that can be used as interconnect paths is limited, there is a problem that wiring congestion can easily occur, leading to an increase in the area of ​​the integrated circuit.

[0107] Figure 13 The area reduction effect of an integrated circuit designed according to some embodiments is shown.

[0108] Reference Figure 13 The first case, CASE 1, has an integrated circuit including power rails of the first metal layer M1, and the second case, CASE 2, has an integrated circuit that does not include power rails of the first metal layer M1. Specifically, in the first case, CASE 1, the integrated circuit does not use the first metal layer M1 as an interconnect path, while in the second case, CASE 2, the integrated circuit uses the first metal layer M1 as an interconnect path.

[0109] Looking at Design A, when the area of ​​Design A is 100% in Case 1, the area of ​​Design A is 96.4% in Case 2. Looking at Design B, when the area of ​​Design B is 100% in Case 1, the area of ​​Design B is 97% in Case 2.

[0110] In this way, by using the first metal layer M1 as the interconnect path for connecting standard cells instead of power rails, the area of ​​the integrated circuit can be reduced by about 3% or more.

[0111] Figure 14 A design system for an integrated circuit according to some embodiments is illustrated schematically.

[0112] The design system 1400 may include a storage device 1410, a design module 1430, a processor 1450, and an analysis module 1470. Figure 14 The design system 1400 can execute Figures 1 to 11 The design system 1400 is at least a portion of the integrated circuit design operations described in the method for designing integrated circuits. The design system 1400 can be implemented as an integrated device and therefore can be referred to as a design device. The design system 1400 can be provided as a dedicated device for designing integrated circuits, but it can also be a computer used to drive various simulation tools or design tools.

[0113] According to some embodiments, storage device 1410 may include a standard cell library 1411, a technical document 1412, and a design rule 1413. In some embodiments, the standard cell library 1411 may include layout information about standard cells, and the technical document 1412 may include information about multiple layers within an integrated circuit. The standard cell library 1411, technical document 1412, and design rule 1413 within storage device 1410 may be provided from storage device 1410 to design module 1430 and analysis module 1470. The number of cell libraries included in storage device 1410 may vary.

[0114] According to some embodiments, design module 1430 may receive standard cell library 1411, technical documents 1412, and design rules 1413 from storage device 1410 to perform... Figures 1 to 11 The design module 1430 performs integrated circuit design operations. In some embodiments, the design module 1430 may use a standard cell library 1411 to perform placement operations on standard cells and perform routing operations on the standard cells after generating multiple layers according to technical document 1412. According to some embodiments, the design module 1430 may use a first metal layer as an interconnect path, the first metal layer being the lowest metal layer among multiple metal layers. Specifically, the first metal layer may be disposed on the track of pins on which no standard cells are disposed. The track of pins on which no standard cells are disposed may overlap with the cell boundary of a standard cell in a first direction, or may overlap with the row on which standard cells are disposed. Here, the term "module" may refer to software, hardware (such as a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC)), or a combination of software and hardware.

[0115] Processor 1450 can be used by design module 1430 and analysis module 1470 to perform operations. For example, processor 1450 may include a microprocessor, application processor (AP), digital signal processor (DSP), graphics processing unit (GPU), etc. Although Figure 14 Only one processor 1450 is shown, but the design system 1400 may include multiple processors depending on the embodiment. The processor 1450 may also include cache memory to enhance operational capabilities.

[0116] Analysis module 1470 can be executed Figures 1 to 11 The layout generated by the design module 1430 is analyzed and verified during or after the design operation of the integrated circuit. In some embodiments, the analysis module 1470 may analyze and verify whether the standard cell and the multiple metal layers that electrically connect the standard cell meet the design rules based on the design rules 1413 received from the storage device 1410.

[0117] Figure 15 A semiconductor device according to some embodiments is shown.

[0118] Reference Figure 15 The semiconductor device 1500 may be a memory module comprising at least one stacked semiconductor chip 1530 and a system-on-a-chip (SOC) 1550 mounted on a packaging substrate 1510 (such as a printed circuit board).

[0119] An interposer layer 1520 may optionally be disposed on the packaging substrate 1510. The stacked semiconductor chip 1530 may be formed as a chip-on-a-chip (CoC). The stacked semiconductor chip 1530 may include at least one memory chip 1540 stacked on a buffer chip 1560 (such as a logic chip). The buffer chip 1560 and the at least one memory chip 1540 may be electrically connected to each other via through-silicon vias (TSVs). In some embodiments, the buffer chip 1560, the at least one memory chip 1540, and the system-on-a-chip 1550 may be connected via reference to Figures 1 to 11 The described layout method is used for design. Specifically, the signal pins of standard cells within the chip can be interconnected using the lowest metal layer among the metal layers, and the lowest metal layer can overlap with the cell boundary of the standard cell in a first direction. According to some embodiments, the semiconductor device 1500 can have a back-side power distribution network architecture. Accordingly, wiring congestion of the semiconductor device 1500 can be reduced, and its area can be utilized effectively. In some embodiments, the stacked semiconductor chip 1530 can be a high-bandwidth memory (HBM), for example, 500 GB / s to 1 Tb / s or higher.

[0120] While this disclosure has been described in conjunction with what is now considered to be actual embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.

Claims

1. An integrated circuit comprising: a substrate; an insulating layer on the substrate; a first conductive layer extending in a first direction in the insulating layer, wherein the first direction is parallel to an upper surface of the substrate; a second conductive layer extending in the first direction in the same layer as the first conductive layer; a third conductive layer extending in the first direction in the same layer as the first conductive layer; a first standard cell in the insulating layer, comprising a first cell boundary; and a second standard cell, wherein the first conductive layer overlaps the first cell boundary in the first direction, wherein the second conductive layer is electrically connected to the first conductive layer and is configured to provide an output pin that outputs a signal converted to a plurality of voltage levels of the first standard cell, and wherein the third conductive layer is electrically connected to the first conductive layer and is configured to provide an input pin that receives a signal from the second standard cell.

2. The integrated circuit of claim 1, wherein the first standard cell further comprises a second cell boundary extending in the first direction, and wherein the second conductive layer is located between the first cell boundary and the second cell boundary in a second direction that is parallel to the upper surface of the substrate and intersects the first direction.

3. The integrated circuit of claim 1, wherein the first conductive layer, the second conductive layer, and the third conductive layer are spaced apart from each other in a second direction that is parallel to the upper surface of the substrate and intersects the first direction.

4. The integrated circuit of claim 3, wherein the first standard cell further comprises a second cell boundary extending in the first direction, wherein the second standard cell comprises a third cell boundary and a fourth cell boundary extending in the first direction, and wherein the second conductive layer is located between the first cell boundary and the second cell boundary in the second direction, and the third conductive layer is located between the third cell boundary and the fourth cell boundary in the second direction.

5. The integrated circuit of claim 1, wherein a first width of the first conductive layer is different from a second width of the second conductive layer.

6. The integrated circuit of claim 5, wherein the first width of the first conductive layer is different from a third width of the third conductive layer.

7. The integrated circuit of claim 6, wherein the first width of the first conductive layer is greater than the second width of the second conductive layer and the third width of the third conductive layer.

8. The integrated circuit of claim 1, wherein the first conductive layer has a first width and a second width that is different from the first width.

9. The integrated circuit of claim 1, further comprising: a fourth conductive layer on the first conductive layer and the second conductive layer, wherein the fourth conductive layer electrically connects the first conductive layer with the second conductive layer; and a fifth conductive layer on the third conductive layer, wherein the fifth conductive layer electrically connects the third conductive layer with the second conductive layer. a fifth conductive layer over the first conductive layer and the third conductive layer, wherein the fifth conductive layer electrically connects the first conductive layer and the third conductive layer.

10. The integrated circuit of claim 9, further comprising: a sixth conductive layer under the second conductive layer, wherein the sixth conductive layer is configured to supply a power supply voltage to the first standard cell through a first source / drain pattern electrically connected to the second conductive layer and a second source / drain pattern spaced apart from the first source / drain pattern in the first direction.

11. The integrated circuit of claim 1, wherein the second standard cell further includes a third cell boundary extending in the first direction, wherein the third cell boundary is disposed at a same position as the first cell boundary of the first standard cell in a second direction parallel to an upper surface of the substrate and intersecting the first direction.

12. The integrated circuit of claim 11, further comprising: a third standard cell between the first standard cell and the second standard cell in the first direction.

13. The integrated circuit of claim 1, wherein the first standard cell and the second standard cell are adjacent in the first direction, and wherein the second conductive layer and the third conductive layer are spaced apart from each other in a second direction parallel to an upper surface of the substrate and intersecting the first direction.

14. An integrated circuit, comprising: a substrate; an insulating layer over the substrate; a standard cell in the insulating layer, wherein a cell boundary of the standard cell extends in a first direction parallel to an upper surface of the substrate; a pin between the cell boundaries in a second direction parallel to the upper surface of the substrate and intersecting the first direction, wherein the pin is configured to transmit a signal converted into a plurality of voltage levels; and a conductive layer in the insulating layer and in a same layer as the pin, wherein the conductive layer overlaps at least one of the cell boundaries of the standard cell in the first direction, and wherein the conductive layer is electrically connected to the pin and is configured to transmit the signal.

15. The integrated circuit of claim 14, wherein a first width of the conductive layer is different from a second width of the pin.

16. The integrated circuit of claim 14, wherein the first width of the conductive layer is greater than the second width of the pin.

17. The integrated circuit of claim 14, wherein the conductive layer has a first portion and a second portion in the first direction, has a first width in the first portion, and has a second width different from the first width in the second portion.

18. A semiconductor device, comprising: a substrate including a first cell region and a second cell region; a power distribution network (PDN) on a first surface of the substrate; a first insulating layer, wherein the first insulating layer includes: a first source / drain region electrically connected to the PDN through a back surface source / drain contact that extends into the substrate through a second surface of the substrate opposite the first surface; a second source / drain region electrically connected to the plurality of conductive layers through a first front surface source / drain contact and spaced apart from the first source / drain region in a first direction parallel to the first surface of the substrate; and a third source / drain region electrically connected to the plurality of conductive layers through a second front surface source / drain contact, wherein the first source / drain region and the second source / drain region are in the first cell region and the third source / drain region is disposed in the second cell region; and a second insulating layer on the first insulating layer, wherein the second insulating layer includes: a first conductive layer that is a lowest conductive layer among the plurality of conductive layers, extends along a second direction parallel to the first surface of the substrate and perpendicular to the first direction, and is electrically connected to the first front surface source / drain contact; a second conductive layer electrically connected to the second front surface source / drain contact; and a third conductive layer electrically connected to the first conductive layer and the second conductive layer.

19. The semiconductor device of claim 18, wherein the first cell region includes a first cell boundary extending in the second direction and a second cell boundary spaced apart from the first cell boundary in the first direction, and wherein the third conductive layer overlaps the second cell boundary.

20. The semiconductor device of claim 18, wherein a third width of the third conductive layer in the first direction is greater than a first width of the first conductive layer and a second width of the second conductive layer.

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