Method for manufacturing mask

Abstract

Disclosed is a method for manufacturing a mask using a laminate. The laminate may include: a silicon substrate; a first lower inorganic layer covering a lower surface of the silicon substrate; a second lower inorganic layer covering a lower surface of the first lower inorganic layer; a first upper inorganic layer covering the upper surface of the silicon substrate; and a second upper inorganic layer covering an upper surface of the first upper inorganic layer. The method may include the steps of: forming or providing a first opening; forming or disposing a first pattern portion and a second pattern portion; forming or providing a second opening overlapping the first opening by etching the silicon substrate through the first pattern portion and the second pattern portion; and removing the first lower inorganic layer, the second lower inorganic layer, and the first upper inorganic layer overlapping the second opening.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0120249, filed on September 4, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments of this disclosure relate to a method for manufacturing a mask. Background Technology

[0003] A display device is a device having organic light-emitting elements in a display area, wherein the organic light-emitting elements include pixel electrodes and a common electrode facing each other, and an organic light-emitting material between the pixel electrodes and the common electrode. A display device can be applied to one or more suitable electronic devices.

[0004] When manufacturing a display device (or electronic device) (e.g., when manufacturing a display device (or electronic device)), one or more suitable methods can be used to form or set the organic light-emitting material. For example, a deposition process utilizing a mask can be used. Summary of the Invention

[0005] One or more aspects of the embodiments of this disclosure relate to a method for manufacturing a mask with improved or enhanced reliability.

[0006] Additional aspects of the embodiments will be set forth in part in the description which follows, and in part will be apparent from the description or may be learned by practice of the presented embodiments.

[0007] A method for manufacturing a mask using a laminate according to one or more embodiments of the present disclosure may include the steps of: forming or providing a first opening that penetrates a second upper inorganic layer in a cell opening region and exposes the upper surface of the first upper inorganic layer; forming or providing a first patterned portion and a second patterned portion in the cell opening region, wherein the first patterned portion and the second patterned portion penetrate a first lower inorganic layer and the second lower inorganic layer and expose the lower surface of a silicon substrate, and wherein, if viewed in a plane (e.g., when viewed in a plane), the second patterned portion is obscured by the first patterned portion. The case portion surrounds; forming or setting a second opening superimposed on the first opening by etching a silicon substrate via a first pattern portion and a second pattern portion; and removing a first lower inorganic layer, a second lower inorganic layer and a first upper inorganic layer superimposed on the second opening, wherein the stack may include: a silicon substrate having monocrystalline silicon, the lower surface of the silicon substrate being a (100) plane; a first lower inorganic layer covering the lower surface of the silicon substrate; a second lower inorganic layer covering the lower surface of the first lower inorganic layer; a first upper inorganic layer covering the upper surface of the silicon substrate; and a second upper inorganic layer covering the upper surface of the first upper inorganic layer. If viewed in a plane (e.g., when viewed in a plane), each of the edges constituting the first pattern portion may be parallel to (e.g., substantially parallel to) the

[010] direction or the

[001] direction, and if viewed in a plane (e.g., when viewed in a plane), each of the edges constituting the second pattern portion may be parallel to (e.g., substantially parallel to) the

[011] direction or the

[01] direction. 1 ]direction.

[0008] According to one or more embodiments, if viewed on a plane (e.g., when viewed on a plane), the first pattern portion may include an outer edge and an inner edge, and each of the outer edge and the inner edge may have a rectangular shape (e.g., a generally rectangular shape).

[0009] According to one or more embodiments, when viewed on a plane (e.g., when viewed on a plane), the second pattern portion may be surrounded by the inner edge of the first pattern portion.

[0010] According to one or more embodiments, the second pattern portion may include a second-first pattern portion, in which the length of one side is equal to (e.g., substantially equal to) the length of the adjacent other side when viewed in a plane (e.g., when viewed in a plane).

[0011] According to one or more embodiments, the second pattern portion may include a second-second pattern portion, in which the length of one side is different from the length of the adjacent side when viewed in a plane (e.g., when viewed in a plane).

[0012] According to one or more embodiments, in the second pattern portion, the area of ​​each of one or more of the second pattern portions on the plane may be different from the area of ​​each of the remaining one or more of the second pattern portions on the plane.

[0013] According to one or more embodiments, the first lower inorganic layer and the first upper inorganic layer may include a first inorganic insulating (e.g., electrically insulating) material, and the second lower inorganic layer and the second upper inorganic layer may include a second inorganic insulating (e.g., electrically insulating) material.

[0014] According to one or more embodiments, the first inorganic insulating (e.g., electrical insulating) material may be silicon oxide, and the second inorganic insulating (e.g., electrical insulating) material may be silicon nitride.

[0015] According to one or more embodiments, in the step of forming or setting the second opening, the silicon substrate can be etched by wet etching.

[0016] According to one or more embodiments, the mask may be a deposition mask used to selectively deposit organic materials on a display substrate.

[0017] A method for manufacturing a mask using a laminate according to one or more embodiments of the present disclosure may include the steps of: forming or providing a first opening that penetrates a second upper inorganic layer in a cell opening region and exposes an upper surface of the first upper inorganic layer; forming or providing a first patterned portion and a second patterned portion in the cell opening region, wherein the first patterned portion and the second patterned portion penetrate a first lower inorganic layer and a second lower inorganic layer and expose a lower surface of a silicon substrate, and wherein, if viewed in a planar manner (e.g., when viewed in a planar manner), the second patterned portion is surrounded by the first patterned portion; removing if viewed in a planar manner (e.g., when viewed in a planar manner) For example, when viewed in a plane, a second lower inorganic layer is superimposed on the region surrounded by the first pattern portion; a second opening superimposed on the first opening is formed or provided by etching the silicon substrate via the first and second pattern portions; and the first lower inorganic layer and the first upper inorganic layer superimposed on the second opening are removed, wherein the stack may include: a silicon substrate having monocrystalline silicon, the lower surface of the silicon substrate being a (100) plane; a first lower inorganic layer covering the lower surface of the silicon substrate; a second lower inorganic layer covering the lower surface of the first lower inorganic layer; a first upper inorganic layer covering the upper surface of the silicon substrate; and a second upper inorganic layer covering the upper surface of the first upper inorganic layer. If viewed in a plane (e.g., when viewed in a plane), each of the edges constituting the first pattern portion may be parallel to (e.g., substantially parallel to) the

[010] direction or the

[001] direction, and if viewed in a plane (e.g., when viewed in a plane), each of the edges constituting the second pattern portion may be parallel to (e.g., substantially parallel to) the

[011] direction or the

[01] direction.1 ]direction.

[0018] According to one or more embodiments, if viewed on a plane (e.g., when viewed on a plane), the first pattern portion may include an outer edge and an inner edge, and each of the outer edge and the inner edge may have a rectangular shape (e.g., a generally rectangular shape).

[0019] According to one or more embodiments, if viewed on a plane (e.g., when viewed on a plane), the second pattern portion may be surrounded by the inner edge of the first pattern portion.

[0020] According to one or more embodiments, the second pattern portion may include a second-first pattern portion, in which the length of one side is equal to (e.g., substantially equal to) the length of the adjacent other side when viewed in a plane (e.g., when viewed in a plane).

[0021] According to one or more embodiments, the second pattern portion may include a second-second pattern portion, in which the length of one side is different from the length of the adjacent side when viewed in a plane (e.g., when viewed in a plane).

[0022] According to one or more embodiments, in the second pattern portion, the area of ​​each of one or more of the second pattern portions on the plane may be different from the area of ​​each of the remaining one or more of the second pattern portions on the plane.

[0023] According to one or more embodiments, the first lower inorganic layer and the first upper inorganic layer may include a first inorganic insulating (e.g., electrically insulating) material, and the second lower inorganic layer and the second upper inorganic layer may include a second inorganic insulating (e.g., electrically insulating) material.

[0024] According to one or more embodiments, the first inorganic insulating (e.g., electrical insulating) material may be silicon oxide, and the second inorganic insulating (e.g., electrical insulating) material may be silicon nitride.

[0025] According to one or more embodiments, in the step of forming or setting the second opening, the silicon substrate can be etched by wet etching.

[0026] According to one or more embodiments, the mask may be a deposition mask used to selectively deposit organic materials on a display substrate. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of embodiments of the subject matter of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the subject matter of this disclosure and, together with the description, serve to explain the principles of embodiments of the subject matter of this disclosure.

[0028] Figure 1 It is a plan view showing a mask according to one or more embodiments.

[0029] Figure 2 It is shown as follows Figure 1 The diagram shows an enlarged plan view of the opening region of one of the cells.

[0030] Figure 3 It is along Figure 2 The sectional view taken by line X1-X1' in the diagram.

[0031] Figures 4 to 20 This is a diagram illustrating a method for manufacturing a mask according to one or more embodiments.

[0032] Figures 21 to 25 This is a diagram illustrating a method of manufacturing a mask according to one or more embodiments.

[0033] Figures 26 to 30 This is a diagram illustrating a deposition process using a mask. Detailed Implementation

[0034] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. It should be noted that only the parts necessary for understanding operation according to the present disclosure are described in the following description, and descriptions of other parts may be omitted so as not to obscure the subject matter of the disclosure. In one or more embodiments, the present disclosure is not limited to the embodiments described herein and may be embodied in one or more suitable forms. However, the embodiments described herein are provided for explanation in more detail so that those skilled in the art can readily practice the spirit and scope of the present disclosure.

[0035] The same reference numerals are used for substantially the same components or elements in the figures, and redundant descriptions of substantially the same components or elements may not be provided.

[0036] The same reference numerals always denote the same elements. In one or more embodiments, the thickness, scale, and dimensions of elements may be exaggerated in the drawings for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations that the associated construction or arrangement may define.

[0037] Throughout this specification, if a first part is referred to as being connected to or joined to a second part (e.g., when the first part is referred to as being connected to or joined to a second part), this includes not only cases where the first and second parts are directly connected or joined, but also cases where the first and second parts are indirectly connected or joined through another element between them. The terminology used herein is for describing particular embodiments and is not intended to limit this disclosure. Throughout this specification, if a part includes a component (e.g., when a part includes a component), this means, unless the context clearly indicates otherwise, that it may further include other components, rather than excluding other components. At least one (species / manifestation) selected from X, Y, and Z and at least one (species / manifestation) selected from the group consisting of X, Y, and Z can be interpreted as one X, one Y, one Z, or any suitable combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). As used herein, the term "and / or" can include any suitable combination of one or more corresponding elements.

[0038] Although the terms “first” and / or “second” may be used herein to describe one or more elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the scope of this disclosure, the first element discussed herein may be referred to as the second element.

[0039] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” and / or “above” may be used herein. By doing so, as illustrated in the accompanying drawings, the relationship between one element or feature and another element or feature can be explained. Spatial relative terms are intended to include other orientations in use, operation, and / or manufacture, in addition to those depicted in the drawings. For example, if the device as illustrated in the drawings is flipped (e.g., when the device as illustrated in the drawings is flipped), the element depicted as “below” or “below” other elements or features is positioned “above” said other elements or features. Thus, in one or more embodiments, the term “below” may include both “above” and “below” orientations. In one or more embodiments, the device may be oriented in other directions (e.g., rotated 90 degrees or in other orientations). In one or more embodiments, the spatial relative terms used herein may be interpreted accordingly.

[0040] In this disclosure, it will be understood that if an element (or region, layer, and / or portion, etc.) is referred to as being "on" another element, "connected to," or "bonded to" another element (e.g., when an element (or region, layer, and / or portion, etc.) is referred to as being "on" another element, "connected to," or "bonded to" another element), then the element may be directly on, directly connected to, or directly bonded to said other element, or there may be intervening elements between these elements. Conversely, if an element is referred to as being "directly on" another element (e.g., when an element is referred to as being "directly on" another element), then there may be no intervening element.

[0041] It will be understood that if the terms “comprising / including” and / or “having or variations thereof” are used in this disclosure (e.g., when the terms “comprising / including” and / or “having or variations thereof” are used in this disclosure), it indicates the presence of the stated features, integrals, steps, actions, operations, elements, components, and / or groups thereof, but does not preclude the presence or addition of one or more other features, integrals, steps, actions, operations, elements, components, and / or groups thereof. Furthermore, the terms “comprising or variations thereof,” “including or variations thereof,” “having or variations thereof,” or similar terms include or support the terms “consisting of…” and “substantially consisting of…”, which indicate the presence of the stated features, integrals, steps, actions, operations, elements, and / or components, while other features, integrals, steps, actions, operations, elements, components, and / or groups thereof are absent or substantially absent.

[0042] One or more embodiments are described with reference to the accompanying drawings, which schematically illustrate preferred embodiments. In one or more embodiments, it should be understood that their shapes may vary depending on, for example, tolerances and / or manufacturing techniques. Therefore, the one or more embodiments disclosed herein should not be construed as limited to the specific shapes shown in the drawings. For example, it should be interpreted to include variations in shape due to manufacturing processes. Thus, the shapes shown in the drawings may not represent the actual shape of an area of ​​the device, and the embodiments of this disclosure are not limited thereto.

[0043] Figure 1 It is a plan view showing a mask according to one or more embodiments.

[0044] Reference Figure 1 The cell opening region (COA) can be set within the mask (MSK). Each cell opening region (COA) can be a region corresponding to a deposition target.

[0045] In each of the cell opening regions COA, the mask MSK may include an opening. In one or more embodiments, after the deposition target is aligned to correspond to (or superimpose with) the cell opening region COA, a deposition process can be performed using the mask MSK to selectively deposit deposition material on each of the deposition targets.

[0046] In one or more embodiments, the cell opening region COA may be arranged or configured to be separated from and / or spaced apart (e.g., spaced apart or separated) from each other along a first direction DR1 and a second direction DR2 perpendicular to (e.g., substantially perpendicular to) the first direction DR1. However, the arrangement of the cell opening region COA is not limited thereto. The cell opening region COA may be arranged or configured in one or more suitable forms.

[0047] Figure 2 It is shown as follows Figure 1 The diagram shows an enlarged plan view of the opening region of one of the cells. Figure 3 It is along Figure 2 The sectional view taken by line X1-X1' in the diagram.

[0048] In the following text, refer to Figure 2 and Figure 3 The description of the COA of a single cell opening region can be applied in a substantially similar (or similar) manner to, for example... Figure 1 Each of the cell opening regions COA shown.

[0049] Reference Figure 2 The mask MSK may include openings OPN arranged or disposed within the cell opening region COA. In one or more embodiments, the openings OPN may be arranged or disposed in a matrix along a first direction DR1 and a second direction DR2. For example, Figure 2 The diagram shows 49 open OPNs arranged or configured in a 7×7 matrix. However, the arrangement and number of open OPNs are not limited to this. Open OPNs can be arranged or configured in one or more suitable forms, and there can be more than 49 or fewer open OPNs.

[0050] Reference Figure 3 The mask MSK may include a silicon substrate WF, a first lower inorganic layer BIL1, a second lower inorganic layer BIL2, a first upper inorganic layer FIL1, and a second upper inorganic layer FIL2.

[0051] The silicon substrate WF may include silicon. The silicon substrate WF may include monocrystalline silicon. A first lower inorganic layer BIL1 may be below the silicon substrate WF. A second lower inorganic layer BIL2 may be below the first lower inorganic layer BIL1. A first upper inorganic layer FIL1 may be on the silicon substrate WF. A second upper inorganic layer FIL2 may be on the first upper inorganic layer FIL1. The first lower inorganic layer BIL1, the second lower inorganic layer BIL2, the first upper inorganic layer FIL1, and the second upper inorganic layer FIL2 may include inorganic insulating (e.g., electrically insulating) materials.

[0052] In one or more embodiments, the first lower inorganic layer BIL1 and the first upper inorganic layer FIL1 may include a first inorganic insulating (e.g., electrically insulating) material. The second lower inorganic layer BIL2 and the second upper inorganic layer FIL2 may include a second inorganic insulating (e.g., electrically insulating) material. The first inorganic insulating (e.g., electrically insulating) material may be a different type or kind of material from the second inorganic insulating (e.g., electrically insulating) material. For example, the first inorganic insulating (e.g., electrically insulating) material may be silicon oxide, and the second inorganic insulating (e.g., electrically insulating) material may be silicon nitride.

[0053] The second inorganic layer FIL2 may include a first opening OPN1. The first opening OPN1 may correspond to, as shown in reference... Figure 2 The described opening OPN. For example, the shape and arrangement of the first opening OPN1 in the plane can be substantially the same as the shape and arrangement of the opening OPN in the plane.

[0054] The first upper inorganic layer FIL1, the silicon substrate WF, the first lower inorganic layer BIL1, and the second lower inorganic layer BIL2 may include a second opening OPN2. The second opening OPN2 may be located within the cell opening region COA. The second opening OPN2 may be stacked with the first opening OPN1. In one or more embodiments, the stacked first opening OPN1 and second opening OPN2 can be understood as defining an opening OPN.

[0055] Figures 4 to 20 This is a diagram illustrating a method for manufacturing a mask according to one or more embodiments.

[0056] Reference Figure 4 The method for manufacturing a mask may include a first step (S1), a second step (S2), a third step (S3), a fourth step (S4), a fifth step (S5), a sixth step (S6), and a seventh step (S7).

[0057] The first step (S1) and the second step (S2) may be steps of forming or setting up a laminate. The third step (S3), the fourth step (S4), the fifth step (S5), the sixth step (S6) and the seventh step (S7) may be steps of manufacturing a mask using the laminate.

[0058] Reference Figure 5 A first lower inorganic layer BIL1 covering the lower surface of the silicon substrate WF and a first upper inorganic layer FIL1 covering the upper surface of the silicon substrate WF (S1) can be formed or disposed.

[0059] In one or more embodiments, the first lower inorganic layer BIL1 and the first upper inorganic layer FIL1 may comprise substantially the same material. For example, the first lower inorganic layer BIL1 and the first upper inorganic layer FIL1 may comprise silicon oxide.

[0060] Reference Figure 6 A second lower inorganic layer BIL2 covering the lower surface of the first lower inorganic layer BIL1 and a second upper inorganic layer FIL2 covering the upper surface of the first upper inorganic layer FIL1 can be formed or disposed (S2). In one or more embodiments, a laminate comprising a second lower inorganic layer BIL2, a first lower inorganic layer BIL1, a silicon substrate WF, a first upper inorganic layer FIL1, and a second upper inorganic layer FIL2 sequentially stacked along a third direction DR3 perpendicular to (e.g., substantially perpendicular to) the first direction DR1 and the second direction DR2.

[0061] In one or more embodiments, the second lower inorganic layer BIL2 and the second upper inorganic layer FIL2 may comprise substantially the same material. For example, the second lower inorganic layer BIL2 and the second upper inorganic layer FIL2 may comprise silicon nitride.

[0062] Refer again Figure 5 and Figure 6 The order in which the components constituting the laminate are formed or disposed can be changed. For example, a first upper inorganic layer FIL1 and a second upper inorganic layer FIL2 can be formed or disposed on a silicon substrate WF, and then a first lower inorganic layer BIL1 and a second lower inorganic layer BIL2 can be formed or disposed under the silicon substrate WF.

[0063] Figure 8 It is along Figure 7 The cross-sectional view taken by line Y1-Y1' in the diagram. (Refer to...) Figure 7 and Figure 8 Within the cell opening region COA, the first opening OPN1 can be formed or configured to penetrate the second upper inorganic layer FIL2 and expose the upper surface of the first upper inorganic layer FIL1 (S3). The first opening OPN1 can be formed or configured to have the same characteristics as referenced. Figure 2 The shape and / or arrangement corresponding to the described opening OPN.

[0064] In this step (S3), the second upper inorganic layer FIL2 can be patterned to form or set the first opening OPN1. The patterning of the second upper inorganic layer FIL2 can be performed, for example, by a dry etching method.

[0065] Figure 10 It is along Figure 9 The cross-sectional view taken by line Y2-Y2'. (Refer to...) Figure 9 and Figure 10 Within the cell opening region COA, the first pattern portion PTN1 and the second pattern portion PTN2 can be formed or configured to penetrate the first lower inorganic layer BIL1 and the second lower inorganic layer BIL2 and expose the lower surface of the silicon substrate WF (S4).

[0066] In this step (S4), etching can be performed in the direction of the rear surface (or lower surface) of the laminate to form or set the first patterned portion PTN1 and the second patterned portion PTN2. This etching can be, for example, dry etching. Figure 9 The rear surface (or lower surface) of the laminate is shown in the figure.

[0067] The silicon substrate WF may include monocrystalline silicon. In one or more embodiments, the lower surface of the silicon substrate WF may be a (100) plane. Figure 9 The crystal structure of the silicon substrate WF as the lower surface of the (100) plane is schematically shown.

[0068] If viewed in a plane (e.g., when viewed in a plane), the first pattern portion PTN1 may have a closed-loop shape. If viewed in a plane (e.g., when viewed in a plane), each of the edges constituting the first pattern portion PTN1 may be parallel to (e.g., substantially parallel to) the

[010] direction or the

[001] direction. In one or more embodiments, the

[010] direction may correspond to a direction based on, for example... Figure 9 The second direction DR2 of the (100) plane shown,

[001] can correspond to a direction based on, for example, Figure 9 The first direction DR1 of the (100) plane shown.

[0069] For example, if viewed in a plane (e.g., when viewed in a plane), the first patterned portion PTN1 may include an outer edge and an inner edge. The region between the outer edge and the inner edge of the first patterned portion PTN1 may be an area where the lower surface of the silicon substrate WF is exposed. Each of the outer edge and the inner edge of the first patterned portion PTN1 may have a rectangular shape (e.g., a generally rectangular shape) with sides parallel to (e.g., substantially parallel to) a first direction DR1 or a second direction DR2.

[0070] If viewed on a flat surface (e.g., when viewed on a flat surface), the second pattern portion PTN2 can be surrounded by the first pattern portion PTN1. For example, the second pattern portion PTN2 can be within the area surrounded by the inner edge of the first pattern portion PTN1.

[0071] If viewed in a plane (e.g., when viewed in a plane), each of the edges constituting the second pattern portion PTN2 can be parallel to (e.g., substantially parallel to) the

[011] direction or

[01] 1

[011] Direction. In one or more embodiments,

[011] direction may correspond to a first intermediate direction DRa, which is based on such Figure 9 The plane (100) shown is in the direction between the first direction DR1 and the second direction DR2, and the angle it forms with the first direction DR1 and the second direction DR2 is 45 degrees.

[01] 1 The direction can correspond to a second intermediate direction DRb, which is based on, for example, Figure 9 The (100) plane shown is perpendicular (e.g., substantially perpendicular) to the first intermediate direction DRa and the third direction DR3.

[0072] Each of the second pattern section PTN2 can be derived from, for example Figures 11 to 13 Implement by selecting any one of the one or more shapes shown.

[0073] Reference Figure 11 The diagram illustrates pattern portion PTN2a, part number 2-1. Pattern portion PTN2a may include a first side SS1a, a second side SS2a, a third side SS3a, and a fourth side SS4a. The first side SS1a and the third side SS3a may be parallel to (e.g., substantially parallel to) a first intermediate direction DRa, and the second side SS2a and the fourth side SS4a may be parallel to (e.g., substantially parallel to) a second intermediate direction DRb. The lengths of the first side SS1a, the second side SS2a, the third side SS3a, and the fourth side SS4a may be substantially the same.

[0074] Reference Figure 12 The diagram illustrates a second-2 pattern portion PTN2b according to one or more embodiments. The second-2 pattern portion PTN2b may include a first side SS1b, a second side SS2b, a third side SS3b, and a fourth side SS4b. The first side SS1b and the third side SS3b may be sides parallel to (e.g., substantially parallel to) a first intermediate direction DRa, and the second side SS2b and the fourth side SS4b may be sides parallel to (e.g., substantially parallel to) a second intermediate direction DRb. The length of each of the second side SS2b and the fourth side SS4b may be greater than the length of each of the first side SS1b and the third side SS3b.

[0075] Reference Figure 13 The diagram illustrates a second-2 pattern portion PTN2b' according to one or more embodiments. The second-2 pattern portion PTN2b' may include a first side SS1b', a second side SS2b', a third side SS3b', and a fourth side SS4b'. The first side SS1b' and the third side SS3b' may be sides parallel to (e.g., substantially parallel to) a first intermediate direction DRa, and the second side SS2b' and the fourth side SS4b' may be sides parallel to (e.g., substantially parallel to) a second intermediate direction DRb. The length of each of the first side SS1b' and the third side SS3b' may be greater than the length of each of the second side SS2b' and the fourth side SS4b'.

[0076] The second pattern part PTN2 can be used as shown in the reference. Figures 11 to 13 A suitable combination of one or more patterned parts of one or more shapes is used to achieve this.

[0077] For example, refer to Figure 9 Each of the second pattern portion PTN2 can be implemented as shown in the reference. Figure 11 The second-first patterned portion PTN2a is described. In one or more embodiments, the second patterned portion PTN2 may have substantially the same area on the plane.

[0078] For another example, see Figure 14 The second pattern part PTN2 can be obtained as shown in the reference. Figure 11 The 2-1 pattern portion PTN2a described, as shown in the reference... Figure 12 The 2-2 pattern portion PTN2b described and as shown in the reference Figure 13 The combination of the pattern portion PTN2b' described in section 2-2 is used to achieve this.

[0079] For another example, see Figure 15 The second pattern part PTN2 can be obtained as shown in the reference. Figure 11 The 2-1 pattern portion PTN2a described, as shown in the reference... Figure 12 The 2-2 pattern portion PTN2b described and as shown in the reference Figure 13 The second-2 pattern portion PTN2b' described is implemented by a combination of these. In one or more embodiments, the second-1 pattern portion PTN2a may include a pattern portion PTN2a_L having a relatively large area on the plane and a pattern portion PTN2a_S having a relatively small area on the plane.

[0080] For reference Figure 9 and Figures 11 to 15As described, the second pattern portion PTN2 can be implemented using one or more suitable combinations of pattern portions having one or more areas in a plane, having one or more arrangements in a plane, and having one or more shapes in a plane, provided that each of the edges constituting the second pattern portion PTN2 is parallel to (e.g., substantially parallel to) the

[011] direction or

[01] 1 The direction is sufficient.

[0081] Reference Figures 16 to 18 The silicon substrate WF can be etched by the first pattern portion PTN1 and the second pattern portion PTN2 to form or set the second opening OPN2 superimposed on the first opening OPN1 (S5). For example, this step (S5) may include step 5-1 (S5-1), step 5-2 (S5-2), and step 5-3 (S5-3).

[0082] Reference Figure 16 A wet etching process (S5-1) in which etchant ETC is sprayed toward the lower surface of the silicon substrate WF can be initiated. The etchant ETC can contact the lower surface of the silicon substrate WF exposed by the first patterned portion PTN1 and the second patterned portion PTN2.

[0083] Reference Figure 17 The silicon substrate WF can be etched using etchant ETC (S5-2). In one or more embodiments, because the lower surface of the silicon substrate WF is set as a (100) plane, and the first patterned portion PTN1 and the second patterned portion PTN2 have as referenced Figure 9 and Figures 11 to 15 The shape described is on a plane, so that etching of the silicon substrate WF can be performed in a set or specific direction (or in a set or specific shape).

[0084] For example, such as Figure 17 As shown, etching can be performed on the silicon substrate WF exposed by the first patterned portion PTN1 to give it an inverted trapezoidal (approximately inverted trapezoidal) cross-sectional shape. For example, as... Figure 17 As shown, etching can be performed on the silicon substrate WF exposed by the second pattern portion PTN2 to give it a rectangular (e.g., approximately rectangular) cross-sectional shape.

[0085] Reference Figure 18 After sufficient or appropriate etching time has elapsed, the etching of the silicon substrate WF can be completed, thereby forming or setting the second opening OPN2 (S5-3).

[0086] Refer again Figures 16 to 18Because the silicon substrate WF is etched in a set or specific direction (or in a set or specific shape) considering the crystal orientation of the silicon substrate WF, the shape of the first pattern portion PTN1 considering the crystal orientation on the plane, and the shape of the second pattern portion PTN2 considering the crystal orientation on the plane, the second opening OPN2 can be formed or set more efficiently or appropriately. For example, in the region where the second opening OPN2 is formed or set, the silicon substrate WF can be etched relatively uniformly by the pattern portions PTN1 and PTN2. In one or more embodiments, if etching is completed (e.g., when etching is completed) (S5-3), there may be substantially no residue of the silicon substrate WF on the lower surface of the first upper inorganic layer FIL1.

[0087] Reference Figure 19 and Figure 20 The first lower inorganic layer BIL1, the second lower inorganic layer BIL2, and the first upper inorganic layer FIL1 (S6 and S7) that are superimposed with the second opening OPN2 can be removed.

[0088] First, refer to Figure 19 The second lower inorganic layer BIL2, which is stacked with the second opening OPN2, can be removed (S6). The second upper inorganic layer FIL2 and the second lower inorganic layer BIL2 may include materials different from the first lower inorganic layer BIL1 and the first upper inorganic layer FIL1. For example, the second upper inorganic layer FIL2 and the second lower inorganic layer BIL2 may include silicon nitride, and the first lower inorganic layer BIL1 and the first upper inorganic layer FIL1 may include silicon oxide. In one or more embodiments, in this step (S6), the second lower inorganic layer BIL2, which has an etch rate different from that of the first lower inorganic layer BIL1 and the first upper inorganic layer FIL1, can be selectively etched and removed.

[0089] Subsequently, refer to Figure 20 The first lower inorganic layer BIL1 and the first upper inorganic layer FIL1, which are superimposed on the second opening OPN2, can be removed (S7). In this step (S7), the first lower inorganic layer BIL1 and the first upper inorganic layer FIL1, which have different etch rates than the second lower inorganic layer BIL2 and the second upper inorganic layer FIL2, can be selectively etched and removed. In one or more embodiments, in this step (S7), the second upper inorganic layer FIL2, which includes the first opening OPN1, can be substantially not removed by etching. For example, the reliability of the first opening OPN1 can be ensured.

[0090] Figures 21 to 25 This is a diagram illustrating a method of manufacturing a mask according to one or more embodiments.

[0091] Reference Figure 21The method for manufacturing a mask may include a first step (S1), a second step (S2), a third step (S3), a fourth step (S4), a fifth step (S5'), a sixth step (S6'), and a seventh step (S7').

[0092] In one or more embodiments, the first step (S1), the second step (S2), the third step (S3), and the fourth step (S4) may be as described in reference to Figures 5 to 15 The steps described are essentially the same. Therefore, no description of overlapping content will be provided.

[0093] Figure 23 It is along Figure 22 The sectional view taken along line Z1-Z1'. (Refer to...) Figure 22 and Figure 23 If viewed in a planar plane (e.g., when viewed in a planar plane), the second lower inorganic layer BIL2 can be removed in the region superimposed with the region surrounded by the first patterned portion PTN1 (S5'). In this step (S5'), the first lower inorganic layer BIL1 may not be substantially removed. In one or more embodiments, the first patterned portion PTN1 and the second patterned portion PTN2 may be retained on the lower surface of the exposed silicon substrate WF.

[0094] Reference Figure 24 The silicon substrate WF can be etched by the first patterned portion PTN1 and the second patterned portion PTN2 to form or set the second opening OPN2 superimposed on the first opening OPN1 (S6'). This step (S6') can be described as being in relation to a reference... Figures 16 to 18 The steps described (S5: S5-1, S5-2, and S5-3) are essentially the same. Therefore, no description of overlapping content will be provided.

[0095] Reference Figure 25 This allows for the removal of the first lower inorganic layer BIL1 and the first upper inorganic layer FIL1, which are superimposed on the second opening OPN2 (S7'). This step (S7') can be described as... Figure 20 The steps described (S7) are essentially the same. Therefore, no description of overlapping content will be provided.

[0096] Figures 26 to 30 This is a diagram illustrating a deposition process using a mask.

[0097] Reference Figure 26 The deposition process using a mask (MSK) may include a first step (A1), a second step (A2), a third step (A3), and a fourth step (A4).

[0098] Reference Figure 27 A mask MSK (A1) can be set on the display substrate DSUB, which serves as the deposition target.

[0099] The display substrate DSUB may include a substrate SUB, a pixel circuit layer PCL, a pixel electrode AE, and a pixel definition layer PDL.

[0100] The substrate SUB may include a silicon wafer substrate formed or disposed by a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0101] The pixel circuit layer (PCL) can be located on one surface of the substrate (SUB). Both the substrate (SUB) and the pixel circuit layer (PCL) can include circuit elements. For example, the substrate (SUB) and the pixel circuit layer (PCL) can include transistors (TFTs). Multiple transistors (TFTs) can be disposed within the substrate (SUB) and the pixel circuit layer (PCL).

[0102] A transistor TFT may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0103] The source region SRA and drain region DRA can be within the substrate SUB. A well WL formed or disposed by an ion implantation process can be provided or disposed within the substrate SUB, and the source region SRA and drain region DRA can be provided or disposed separately and / or spaced apart (e.g., spaced apart or separated) within the well WL. The region between the source region SRA and drain region DRA within the well WL can be defined as the channel region. The gate electrode GE can be stacked with the channel region between the source region SRA and drain region DRA and can be in the pixel circuit layer PCL. The gate electrode GE can be separated from the well WL or channel region by an insulating (e.g., electrically insulating) material such as the gate insulating layer GI. The gate electrode GE can include a conductive (e.g., electrically conductive) material.

[0104] The pixel circuit layer (PCL) may include multiple layers, including insulating (e.g., electrically insulating) layers and conductive (e.g., electrically conductive) patterns between the insulating (e.g., electrically insulating) layers. The conductive (e.g., electrically conductive) patterns may include, for example, a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via drain connections DRC that penetrate one or more insulating (e.g., electrically insulating) layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via source connections SRC that penetrate one or more insulating (e.g., electrically insulating) layers.

[0105] Pixel electrodes AE can be located on one surface of the pixel circuit layer PCL. Pixel electrodes AE can be individually connected to transistor TFTs. In one or more embodiments, each of the pixel electrodes AE can be referred to as an anode electrode.

[0106] The pixel defining layer (PDL) may be on one surface of the pixel circuit layer (PCL). The PDL may include pixel openings that expose portions of pixel electrodes (AEs). In one or more embodiments, the PDL may be between adjacent pixel electrodes (AEs).

[0107] The mask MSK can be aligned so that the first opening OPN1 is superimposed on the pixel electrode AE.

[0108] Reference Figure 28 The mask MSK can be moved relative to the display substrate DSUB, so that the second upper inorganic layer FIL2 contacts the pixel defining layer PDL (A2). In this step (A2), the first opening OPN1 can be stacked with the pixel electrode AE.

[0109] Reference Figure 29 Organic light-emitting material EL (A3) can be formed or deposited on the pixel electrode AE ​​within the pixel opening by selectively setting the deposition material using a mask MSK.

[0110] Reference Figure 30 The mask MSK (A4) can be removed. Thereafter, steps such as forming or setting a common electrode facing the pixel electrode AE ​​can be performed. In one or more embodiments, an electronic device including a display substrate DSUB can be provided.

[0111] According to a method for manufacturing a mask according to one or more embodiments of the invention, if the mask is manufactured (e.g., when manufacturing a mask), a method for manufacturing a mask with improved or enhanced reliability can be provided by using patterned portions that take into account the crystal orientation of the silicon substrate.

[0112] Although one or more embodiments of this disclosure have been described, it should be understood that this disclosure is not limited to these embodiments, but rather that one or more suitable changes and modifications can be made by those skilled in the art within the spirit and scope of this disclosure and its equivalents as claimed below.

Claims

1. A method for manufacturing a mask using a layer stack, wherein the layer stack comprising: a silicon substrate having a single crystal silicon, a lower surface of the silicon substrate being a (100) plane; a first lower inorganic layer covering the lower surface of the silicon substrate; a second lower inorganic layer covering a lower surface of the first lower inorganic layer; a first upper inorganic layer covering an upper surface of the silicon substrate; and a second upper inorganic layer covering an upper surface of the first upper inorganic layer, and wherein the method comprises the steps of: providing a first opening penetrating the second upper inorganic layer within a cell opening region and exposing the upper surface of the first upper inorganic layer; providing a first pattern portion and a second pattern portion within the cell opening region, wherein the first pattern portion and the second pattern portion penetrate the first lower inorganic layer and the second lower inorganic layer and expose the lower surface of the silicon substrate, and wherein the second pattern portion is surrounded by the first pattern portion when viewed in plan; providing a second opening superimposed with the first opening by etching the silicon substrate via the first pattern portion and the second pattern portion; and removing the first lower inorganic layer, the second lower inorganic layer, and the first upper inorganic layer superimposed with the second opening, wherein each of the sides constituting the first pattern portion is parallel to a [010] direction or a [001] direction when viewed in plan, and wherein, when viewed in plan, each of the sides constituting the second pattern portion is parallel to the [011] direction or the [01 1 ] direction.

2. The method of claim 1, wherein, the first pattern portion includes an outer edge and an inner edge when viewed in plan, wherein each of the outer edge and the inner edge has a rectangular shape, and wherein the second pattern portion is surrounded by the inner edge of the first pattern portion when viewed in plan.

3. The method of claim 1, wherein, the second pattern portion includes a 2-1 pattern portion in which a length of one side is equal to a length of an adjacent other side when viewed in plan.

4. The method of claim 1, wherein, the second pattern portion includes a 2-2 pattern portion in which a length of one side is different from a length of an adjacent other side when viewed in plan.

5. The method of claim 1, wherein, Among the second pattern portions, an area on a plane of each of one or more of the second pattern portions is different from an area on a plane of each of one or more of the remaining second pattern portions.

6. The method of claim 1, wherein, the first lower inorganic layer and the first upper inorganic layer comprise a first inorganic insulating material, wherein the second lower inorganic layer and the second upper inorganic layer comprise a second inorganic insulating material, wherein the first inorganic insulating material is silicon oxide, and wherein the second inorganic insulating material is silicon nitride.

7. The method of claim 1, wherein, In the step of providing the second opening, the silicon substrate is etched by wet etching.

8. A method for manufacturing a mask using a layer stack, wherein, The laminate includes: a silicon substrate having a single crystal silicon, a lower surface of the silicon substrate being a (100) plane; a first lower inorganic layer covering the lower surface of the silicon substrate; a second lower inorganic layer covering a lower surface of the first lower inorganic layer; a first upper inorganic layer covering an upper surface of the silicon substrate; a second upper inorganic layer covering an upper surface of the first upper inorganic layer, and wherein the method includes the steps of: providing a first opening penetrating the second upper inorganic layer within a cell opening region and exposing the upper surface of the first upper inorganic layer; providing a first pattern portion and a second pattern portion within the cell opening region, wherein the first pattern portion and the second pattern portion penetrate the first lower inorganic layer and the second lower inorganic layer and expose the lower surface of the silicon substrate, and wherein the second pattern portion is surrounded by the first pattern portion when viewed in plan; removing the second lower inorganic layer superimposed on an area surrounded by the first pattern portion when viewed in plan; providing a second opening superimposed on the first opening by etching the silicon substrate via the first pattern portion and the second pattern portion; and removing the first lower inorganic layer and the first upper inorganic layer superimposed on the second opening, wherein each of the sides constituting the first pattern portion is parallel to the [010] direction or the [001] direction when viewed in plan, and wherein, when viewed in plan, each of the sides constituting the second pattern portion is parallel to the [011] direction or the [01 1 ] direction.

9. The method of claim 8, wherein, the first pattern portion includes an outer edge and an inner edge when viewed in plan, wherein each of the outer edge and the inner edge has a rectangular shape, wherein the second pattern portion is surrounded by the inner edge of the first pattern portion when viewed in plan.

10. The method of claim 8, wherein, the first lower inorganic layer and the first upper inorganic layer include a first inorganic insulating material, wherein the second lower inorganic layer and the second upper inorganic layer include a second inorganic insulating material, wherein the first inorganic insulating material is silicon oxide, and wherein the second inorganic insulating material is silicon nitride.

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