Chip low-power consumption function verification method and device

Abstract

The application relates to a chip low-power function verification method and device. The method comprises the following steps: analyzing a low-power control instruction of a power state controller to generate an assertion verification signal; the low-power control instruction is used for instructing the power state controller to perform a target low-power operation on a target power domain in the same chip; during the execution process of the target low-power operation, a plurality of low-power control interface signals between the power state controller and the target power domain are collected; based on the assertion verification signal and a timing assertion strategy corresponding to the target low-power operation, the plurality of low-power control interface signals are subjected to timing verification to obtain a verification result. The timing assertion strategy for the same low-power operation is reused in the low-power function verification process of different power domains, independent verification components do not need to be respectively built for each power domain in the chip, the redundancy of verification code is significantly reduced, and the verification efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and in particular to a method and apparatus for verifying low-power chip functionality. Background Technology

[0002] Low-power design refers to minimizing the power consumption of the SoC (System on Chip) and extending the device's battery life while ensuring the SoC functions normally.

[0003] In low-power design verification based on UVM (Universal Verification Methodology Verification Method), it is necessary to build independent verification components for each power domain inside the SoC, resulting in code redundancy and low verification efficiency. Summary of the Invention

[0004] Therefore, it is necessary to provide a method and apparatus for verifying low-power functions of chips to address the above-mentioned technical problems, so as to realize the reuse of verification components in different power domains, reduce the amount of code, and improve verification efficiency.

[0005] In a first aspect, this application provides a method for verifying low-power functionality of a chip, comprising: parsing a low-power control instruction to a power state controller and generating an assertion verification signal; the low-power control instruction instructing the power state controller to perform a target low-power operation on a target power domain within the same chip; during the execution of the target low-power operation, acquiring multiple low-power control interface signals between the power state controller and the target power domain; and performing timing verification on the multiple low-power control interface signals based on the assertion verification signal and the timing assertion strategy corresponding to the target low-power operation to obtain a verification result.

[0006] In one embodiment, the method further includes: acquiring low-power control commands sent by the master control unit to the power state controller via an advanced peripheral bus.

[0007] In one embodiment, the step of acquiring multiple low-power control interface signals between the power state controller and the target power domain includes: acquiring multiple low-power control interface signals between the power state controller and the target power domain through a low-power hardware logic interface between the power state controller and the target power domain.

[0008] In one embodiment, the verification result includes timing verification success or timing verification failure; the timing verification of the plurality of low-power control interface signals based on the assertion verification signal and the timing assertion policy corresponding to the target low-power operation, to obtain the verification result, includes: responding to the assertion verification signal, initiating timing monitoring of the plurality of low-power control interface signals; if the timing changes of the signal state of each low-power control interface signal in multiple clock cycles all conform to the timing assertion policy corresponding to the target low-power operation, then the timing verification is determined to be successful; if the timing changes of the signal state of any low-power control interface signal in any clock cycle do not conform to the timing assertion policy, then the timing verification is determined to be failed.

[0009] In one embodiment, the target low-power operation includes a clock-off operation. The low-power control interface signals include a bus master stop request signal, a bus master stop response signal, a bus slave stop request signal, a bus slave stop response signal, a bus proxy enable signal, and a clock enable signal. The timing assertion strategy corresponding to the clock-off operation includes: after the rising edge of the current clock cycle when the assertion verification signal is valid, the bus master stop request signal becomes valid after at least a first number of clock cycles; after the bus master stop request signal becomes valid for at least a second number of clock cycles, the bus master stop response signal becomes valid; the bus master stop request signal and the bus... After the master device stop response signal is valid for a third number of clock cycles, the bus slave device stop request signal becomes valid; after the bus slave device stop request signal is valid for at least a fourth number of clock cycles, the bus slave device stop response signal becomes valid; after the bus slave device stop request signal and the bus slave device stop response signal are valid for a fifth number of clock cycles, the bus proxy enable signal becomes valid, and the bus master device stop request signal and the bus slave device stop request signal become invalid; after the bus proxy enable signal is valid, and the bus master device stop request signal and the bus slave device stop request signal become invalid, the clock enable signal becomes invalid.

[0010] In one embodiment, the target low-power operation includes a clock-on operation, and the low-power control interface signals include a bus proxy enable signal and a clock enable signal; the timing assertion strategy corresponding to the clock-on operation includes: after the rising edge of the current clock cycle when the assertion verification signal is valid, the bus proxy enable signal becomes invalid after at most the seventh number of clock cycles; after the bus proxy enable signal becomes invalid after at least the eighth number of clock cycles, the clock enable signal becomes valid.

[0011] In one embodiment, the target low-power operation includes a reset operation. The low-power control interface signals include a bus master stop request signal, a bus master stop response signal, a bus slave stop request signal, a bus slave stop response signal, a reset signal, a bus proxy enable signal, and a clock enable signal. The timing assertion strategy corresponding to the reset operation includes: after the rising edge of the current clock cycle when the assertion verification signal is valid, the bus master stop request signal becomes valid after at least the ninth clock cycle; after the bus master stop request signal becomes valid after at least the tenth clock cycle when the bus master stop request signal becomes valid, the bus master stop response signal becomes valid; after the bus master stop request signal and the bus master stop response signal become valid after the eleventh clock cycle when they are both valid, the bus slave... The device stop request signal is valid; after the bus slave device stop request signal is valid for at least the twelfth clock cycle, the bus slave device stop response signal is valid; after the bus slave device stop request signal and the bus slave device stop response signal are valid for at least the thirteenth clock cycle, the reset signal, the bus master device stop request signal, and the bus slave device stop request signal are invalid; after the reset signal, the bus master device stop request signal, and the bus slave device stop request signal are invalid for at least the fourteenth clock cycle, the bus proxy enable signal is valid; after the bus proxy enable signal is valid for at least the fifteenth clock cycle, the clock enable signal is valid; after the clock enable signal is valid for at least the sixteenth clock cycle, the reset signal is valid.

[0012] In one embodiment, the target low-power operation includes an exit reset operation, and the low-power control interface signals include a reset signal, a bus proxy enable signal, and a clock enable signal. The timing assertion strategy corresponding to the exit reset operation includes: after the rising edge of the current clock cycle in which the assertion verification signal is valid, the reset signal becomes invalid after at least the seventeenth clock cycle; after the reset signal becomes invalid for at least the eighteenth clock cycle, the bus proxy enable signal becomes invalid; after the bus proxy enable signal becomes invalid for at least the nineteenth clock cycle, the clock enable signal becomes valid; and after the clock enable signal becomes valid for at least the twentieth clock cycle, the reset signal becomes valid.

[0013] In one embodiment, the target low-power operation includes a power-off operation. The low-power control interface signals include a bus master stop request signal, a bus master stop response signal, a bus slave stop request signal, a bus slave stop response signal, a reset signal, a bus proxy enable signal, an isolation enable signal, a clock enable signal, a power-off enable signal, and a power-off response signal. The timing assertion strategy corresponding to the power-off operation includes: after the rising edge of the current clock cycle when the assertion verification signal is valid, the bus master stop request signal becomes valid after at least a twenty-first number of clock cycles; after the bus master stop request signal becomes valid after at least a twenty-second number of clock cycles; after the bus master stop request signal and the bus master stop response signal become valid after a twenty-third number of clock cycles; and after the bus slave stop request signal becomes valid after at least a twenty-fourth number of clock cycles. After the bus slave device stop request signal and the bus slave device stop response signal are valid for a twenty-fifth number of clock cycles, the reset signal, the bus master device stop request signal, and the bus slave device stop request signal become invalid; if the bus proxy enable signal is invalid, then after the bus proxy enable signal and the isolation enable signal are valid for a twenty-seventh number of clock cycles, the clock enable signal becomes invalid, and after the clock enable signal becomes invalid for a twenty-eighth number of clock cycles, the power-off enable signal becomes valid; or, if the valid state of the bus proxy enable signal and the invalid state of the clock enable signal are maintained for a twenty-ninth number of clock cycles, the isolation enable signal becomes valid for a thirtieth number of clock cycles, the power-off enable signal becomes valid; after the power-off enable signal becomes valid, the power-off response signal becomes valid; after the power-off enable signal and the power-off response signal are maintained valid for at least a thirty-first number of clock cycles, the reset signal becomes valid.

[0014] In one embodiment, the target low-power operation includes a power-on operation, and the low-power control interface signals include a reset signal, a power-off enable signal, a power-off response signal, a bus proxy enable signal, an isolation enable signal, and a clock enable signal. The timing assertion strategy corresponding to the power-on operation includes: after the rising edge of the current clock cycle in which the assertion verification signal is valid, the reset signal becomes invalid after at least the thirty-third clock cycle; after the reset signal becomes invalid for at least the thirty-fourth clock cycle, the power-off enable signal becomes invalid; after the power-off enable signal remains invalid for at least the thirty-fifth clock cycle, the power-off response signal becomes invalid; after the power-off response signal becomes invalid for at least the thirty-sixth clock cycle, the bus proxy enable signal and the isolation enable signal become invalid; after the bus proxy enable signal and the isolation enable signal become invalid for at least the thirty-seventh clock cycle, the clock enable signal becomes valid; and after the clock enable signal becomes valid for at least the thirty-eighth clock cycle, the reset signal becomes valid.

[0015] Secondly, this application also provides a chip low-power function verification device, comprising: a generation module, configured to parse low-power control instructions to a power state controller and generate assertion verification signals; the low-power control instructions are used to instruct the power state controller to perform a target low-power operation on a target power domain within the same chip; a acquisition module, configured to acquire multiple low-power control interface signals between the power state controller and the target power domain during the execution of the target low-power operation; and a verification module, configured to perform timing verification on the multiple low-power control interface signals based on the assertion verification signals and the timing assertion strategy corresponding to the target low-power operation, and obtain verification results.

[0016] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above method embodiments.

[0017] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above method embodiments.

[0018] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described method embodiments.

[0019] The aforementioned chip low-power function verification method and apparatus adopt an assertion-based verification approach. It automatically generates assertion verification signals by parsing low-power control instructions for the chip's power state controller. During the execution of the target low-power operation, it synchronously acquires multiple low-power control interface signals between the power state controller and the target power domain. Then, based on the assertion verification signals and a predefined timing assertion strategy corresponding to the target low-power operation, it performs automated timing verification on the low-power control interface signals. This allows timing assertion strategies for the same low-power operation to be reused in the low-power function verification process for different power domains, eliminating the need to build independent verification components for each power domain within the chip. This significantly reduces verification code redundancy and improves verification efficiency. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of a chip low-power function verification method in one embodiment;

[0022] Figure 2 This is a schematic diagram of the interaction of low-power control interface signals in one embodiment;

[0023] Figure 3 This is a timing diagram of the timing verification process corresponding to the clock-off operation in one embodiment;

[0024] Figure 4 This is a timing diagram of the timing verification process corresponding to the clock-opening operation in one embodiment;

[0025] Figure 5 This is a timing diagram of the timing verification process corresponding to the reset operation in one embodiment;

[0026] Figure 6 This is a timing diagram of the timing verification process corresponding to the exit reset operation in one embodiment;

[0027] Figure 7 This is a timing diagram of the timing verification process corresponding to the power-off operation in the normal state in one embodiment.

[0028] Figure 8 This is a timing diagram of the timing verification process corresponding to the reset or idle state power-off operation in one embodiment;

[0029] Figure 9This is a timing diagram of the timing verification process corresponding to the power-on operation in one embodiment;

[0030] Figure 10 This is a system architecture diagram of an implementation of a chip low-power function verification method in one embodiment;

[0031] Figure 11 This is a structural block diagram of a chip low-power function verification device in one embodiment;

[0032] Figure 12 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0035] In traditional low-power function verification processes for chips, it is typically necessary to build independent verification components for each power domain within the SoC, resulting in code redundancy and low verification efficiency. Therefore, in an exemplary embodiment, such as... Figure 1 As shown, this application provides a method for verifying the low-power functionality of a chip, which can be applied to verification equipment for verifying the functionality of a chip.

[0036] Specifically, the low-power function verification method for this chip includes the following steps.

[0037] Step 101: Parse the low-power control instructions to the power state controller and generate an assertion verification signal; the low-power control instructions are used to instruct the power state controller to perform a target low-power operation on the target power domain within the same chip.

[0038] First, the verification device can receive low-power control commands sent to the PSC (Power State Controller). The PSC is a hardware logic module that is connected to each power domain within the SoC and can independently control the power state of each power domain in the SoC in response to control commands from the main control unit such as the central controller or power management unit.

[0039] Low-power control instructions are a type of control instructions issued by the main control unit to the PSC. They carry key information such as the target power domain identifier and the target low-power operation type, and are used to instruct the PSC to perform the target low-power operation on the target power domain. This reduces the power consumption of the SoC while ensuring that the SoC functions normally, thereby realizing the low-power function of the SoC.

[0040] For example, the power domain within a SoC can include a normally-on power domain and a controllable power domain. The normally-on power domain needs to be constantly powered on, such as AD Ctrl (Analog-to-Digital Controller), DMA (Direct Memory Access Controller), and Timer. The controllable power domain can be completely powered off, such as DSP (Digital Signal Processor), SRIO (Serial RapidIO), and DDR (Double Data Rate SDRAM). The low-power operations supported by the normally-on power domain and the controllable power domain also differ. The normally-on power domain supports low-power operations such as clocking off, clocking on, resetting, and exiting reset, while the controllable power domain additionally supports low-power operations such as power-off and power-on. In this embodiment, the target power domain can be any normally-on power domain or a controllable power domain, and the target low-power operation can be any operation supported by the target power domain that can reduce SoC power consumption; no specific limitation is made.

[0041] After the verification device receives the low-power control command, it can parse and identify the target power domain and target low-power operation indicated in the command, and generate a precisely corresponding assertion verification signal (inst_enable) to initiate the subsequent timing verification process. The assertion verification signal is the triggering benchmark for timing verification; its effective state triggering will directly correlate with the start timing of the subsequent verification process, ensuring that the verification process is precisely synchronized with the execution process of the target low-power operation.

[0042] Step 102: During the execution of the target low-power operation, acquire multiple low-power control interface signals between the power state controller and the target power domain.

[0043] After receiving a low-power control command, the PSC can perform a target low-power operation on the target power domain. The target low-power operation does not directly and instantaneously change the power state of the target power domain, but is achieved through a series of strictly ordered low-power control interface signals.

[0044] For example, such as Figure 2 As shown, the low-power control interface signals may include, but are not limited to, the following signals.

[0045] Clock enable signal (clk_en): Issued by PSC (Power State Controller), synchronized with the clock signal (clk) issued by the phase-locked loop controller itself, and used to gate the clock of the target power domain;

[0046] Reset signal (module_resetn): Issued by PSC and synchronized with the global reset signal (rstn) issued by the reset controller itself, it is used to control the reset state of the target power domain.

[0047] Bus Master Stop Request Signal (switch_mreq): Issued by PSC, used to request the target power domain acting as the bus master to stop initiating new access requests;

[0048] Bus master device stop response signal (switch_mack): issued by the target power domain, used to confirm to the PSC that all initiated access requests have been processed when it is acting as a bus master device;

[0049] Bus slave device stop request signal (switch_sreq): issued by PSC, used to request the target power domain, which is a bus slave device, to stop receiving new access requests;

[0050] Bus slave device stop response signal (switch_sack): issued by the target power domain, used to confirm to the PSC that when it is a bus slave device, all received access requests have been responded to and completed;

[0051] Bus Proxy Enable Signal (bus_dummy_en): Issued by PSC, this signal enables a proxy module to take over its bus slave interface when the target power domain is unable to respond to bus access due to low-power operation.

[0052] Isolation enable signal (iso_en): issued by PSC, used to isolate the output port of the target power domain to a safe level before power is turned off;

[0053] Power-off enable signal (pg_en): Issued by PSC, used to control the power supply switch to the target power domain;

[0054] Power-off response signal (pg_ack): Issued by the power network, used to confirm to the PSC that the power state switching operation for the target power domain has been completed;

[0055] Digital Signal Processor Dedicated Bus Proxy Enable Signal (axi_rst_en): A signal dedicated to the DSP module, its function is similar to the bus proxy enable signal.

[0056] The verification device can acquire low-power control interface signals between the PSC and the target power domain during the execution of the target low-power operation by the PSC. The acquisition process must be synchronized with the execution timing of the target low-power operation to ensure that the acquired signals can completely and accurately reflect the interaction process between the power state controller and the target power domain, providing a data foundation for subsequent timing verification.

[0057] Step 103: Based on the assertion verification signal and the timing assertion strategy corresponding to the target low-power operation, perform timing verification on multiple low-power control interface signals to obtain the verification results.

[0058] In response to the assertion verification signal, the verification device can invoke the timing assertion strategy pre-bound to the target low-power operation to perform timing verification on the acquired low-power control interface signals. The timing assertion strategy is pre-defined according to the technical requirements of different low-power operations in the chip design rules, including the timing constraints of various low-power control interface signals, such as the handshake completion timing of request-response signal pairs, the fixed delay timing between different control stages, and the waiting timing from the enable signal taking effect to the execution signal action.

[0059] During the verification process, the generated assertion verification signal is used as the trigger reference. Starting from the rising edge of the clock cycle when the assertion verification signal is effectively triggered, the timing verification of each low-power control interface signal is performed to determine whether the effective / invalid state switching time and timing connection relationship of each low-power control interface signal meet the constraint requirements defined in the timing assertion strategy, so as to obtain the verification result.

[0060] The verification results indicate whether the PSC's execution of the target low-power operation in the target power domain conforms to the timing constraints on each low-power control interface signal defined in the timing assertion strategy, i.e., whether the execution timing of the target low-power operation conforms to the preset chip design rules. If the timing verification is successful, it indicates that the execution flow timing of the target low-power operation is compliant; if the timing verification fails, it indicates that the execution flow timing of the target low-power operation is non-compliant, which can further indicate that there is a timing risk in the low-power operation.

[0061] As can be seen from the above, the solution provided in this application adopts an assertion-based verification method. By parsing the low-power control instructions for the on-chip power state controller, assertion verification signals are automatically generated. During the execution of the target low-power operation, multiple low-power control interface signals between the power state controller and the target power domain are simultaneously collected. Then, based on the assertion verification signals and the predefined timing assertion strategy corresponding to the target low-power operation, the low-power control interface signals are automatically verified for timing. This allows the timing assertion strategy for the same low-power operation to be reused in the low-power function verification process for different power domains. There is no need to build independent verification components for each power domain on the chip, which significantly reduces the redundancy of verification code and improves verification efficiency.

[0062] In an exemplary embodiment, the method further includes: acquiring low-power control commands sent by the master control unit to the power state controller via an advanced peripheral bus.

[0063] In this exemplary embodiment, the verification device can acquire low-power control commands sent from the master control unit to the PSC via the APB (Advanced Peripheral Bus), thereby accurately capturing the source trigger signal of the target low-power operation and ensuring the consistency between the verification timing and the actual operation timing.

[0064] Among them, APB is a low-bandwidth, low-power general-purpose peripheral bus inside the SoC. It is the standard communication carrier between the main control unit and the power state controller. It has the characteristics of simple timing and high stability, and can adapt to the transmission requirements of low-speed control signals such as low-power control instructions.

[0065] In practice, the verification device can connect to the APB bus transmission link. When the main control unit transmits low-power control commands to the PSC via APB, the verification device can synchronously acquire these commands via APB. It should be noted that this acquisition step does not interfere with or modify the existing APB communication link, thus ensuring that normal command interaction between the main control unit and the PSC remains unaffected.

[0066] In an exemplary embodiment, step 102 involves acquiring multiple low-power control interface signals between the power state controller and the target power domain, including: acquiring multiple low-power control interface signals between the power state controller and the target power domain through a low-power hardware logic interface.

[0067] In this exemplary embodiment, in step 102, the low-power control interface signals can be collected through the low-power hardware logic interface between the PSC and the target power domain, thereby ensuring the integrity, timing consistency and transmission stability of the collected low-power control interface signals, and providing a reliable signal foundation for subsequent timing verification.

[0068] The low-power hardware logic interface (LPHLI) is a dedicated hardware channel within the SoC designed for low-power interaction between the Power Supply Controller (PSC) and various power domains. Verification devices can access the LPHLI. When the PSC initiates a low-power operation to the target power domain based on low-power control commands, the PSC and the target power domain can interact through this LPHLI to exchange a series of low-power control interface signals to achieve the target low-power operation. During the interaction, the verification device can synchronously acquire the low-power control interface signals through this LPHLI, ensuring that the acquired low-power control interface signals are completely synchronized in timing with the actual interaction process between the PSC and the target power domain, reducing latency deviations.

[0069] In an exemplary embodiment, the verification result includes timing verification success or timing verification failure; step 103 includes: in response to the assertion verification signal, starting timing monitoring of multiple low-power control interface signals; if the timing changes of the signal state of each low-power control interface signal in multiple clock cycles all conform to the timing assertion policy corresponding to the target low-power operation, then the timing verification is determined to be successful; if the timing changes of the signal state of any low-power control interface signal in any clock cycle do not conform to the timing assertion policy, then the timing verification is determined to be failed.

[0070] In this exemplary embodiment, the timing verification process uses the assertion verification signal as the trigger reference, and completes the verification by timing monitoring of the signal state of each low-power control interface signal and matching the strategy based on the timing assertion strategy, and finally outputs the verification result of timing verification success or timing verification failure.

[0071] Specifically, the assertion verification signal can be used as the start trigger signal for timing verification, to synchronously enable timing monitoring of various low-power control interface signals. The timing monitoring process uses the clock cycle as the smallest unit of time. Each clock cycle includes a rising edge and a falling edge. The rising edge refers to the instant when the clock signal (clk) transitions from a low level to a high level, and the falling edge refers to the instant when the clock signal transitions from a high level to a low level.

[0072] During timing monitoring, the signal status of each low-power control interface signal can be monitored over multiple clock cycles, and the signal status is compared with the timing assertion strategy corresponding to the predefined target low-power operation. The signal status of the assertion verification signal and each low-power control interface signal can be valid or invalid. Valid means that the signal has reached its agreed-upon operational level (in this embodiment, a high level is assumed to be the valid level), while invalid means that the signal has left the valid level state.

[0073] If the signal states of each low-power control interface signal meet the timing constraints of the timing assertion strategy within multiple clock cycles of low-power operation execution, and there is no timing deviation, then the timing verification can be directly determined to be successful. This indicates that the execution process of the target low-power operation is compliant at the timing level and will not cause operational abnormalities or chip functional failures due to signal interaction timing issues.

[0074] Conversely, if the signal state of any low-power control interface signal does not conform to the timing assertion strategy within any clock cycle, such as a low-power control interface signal failing to transition to an active state within the specified clock cycle, the signal state switching order of some low-power control interface signals being reversed, or the duration of the active state of a low-power control interface signal not meeting the requirements, then the timing verification can be determined to have failed.

[0075] This ensures that only the target low-power operation of the full timing assertion strategy can pass timing verification, which helps to quickly locate timing problems and improve the efficiency of low-power verification and the targeting of problem investigation.

[0076] In one implementation, the target low-power operation includes a clock-off operation, and the low-power control interface signals include a bus master stop request signal, a bus master stop response signal, a bus slave stop request signal, a bus slave stop response signal, a bus agent enable signal, and a clock enable signal.

[0077] The timing assertion strategy corresponding to the clock shutdown operation includes: after the rising edge of the current clock cycle when the assertion verification signal is valid, the bus master stop request signal becomes valid after at least a first number of clock cycles; after the bus master stop request signal becomes valid after at least a second number of clock cycles, the bus master stop response signal becomes valid; after the bus master stop request signal and the bus master stop response signal become valid after a third number of clock cycles, the bus slave stop request signal becomes valid; after the bus slave stop request signal becomes valid after at least a fourth number of clock cycles, the bus slave stop response signal becomes valid; after the bus slave stop request signal and the bus slave stop response signal become valid after a fifth number of clock cycles, the bus agent enable signal becomes valid, and the bus master stop request signal and the bus slave stop request signal become invalid; after the bus agent enable signal becomes valid, and the bus master stop request signal and the bus slave stop request signal become invalid, the clock enable signal becomes invalid after a sixth number of clock cycles when the bus agent enable signal becomes valid and the bus master stop request signal and the bus slave stop request signal become invalid.

[0078] In this implementation, such as Figure 3 As shown, the timing verification process corresponding to the clock shutdown operation includes: starting from the rising edge of the current clock cycle when the assertion verification signal is valid, within the first clock cycle to the first number of clock cycles after this starting point, the bus master device stop request signal can be valid in any of these clock cycles (corresponding to...). Figure 3 At moment ① (in the middle sequence), the bus interaction phase of the clock-off operation is officially started; subsequently, the bus master device stop request signal must remain valid for at least the second number of clock cycles before the bus master device stop response signal is valid, ensuring that the handshake interaction on the master device side is completed stably.

[0079] When the bus master stop request signal and the bus master stop response signal are both valid for a third number of clock cycles, the bus slave stop request signal becomes valid again (corresponding to...). Figure 3 At the moment of sequence number ②, the interaction process is extended to the slave device side; similarly, the bus slave device stop request signal must remain valid for at least the fourth number of clock cycles before the bus slave device stop response signal is valid, ensuring that the slave device completes state preparation.

[0080] After the bus slave stop request signal and the bus slave stop response signal have been simultaneously valid for five clock cycles, the bus agent enable signal becomes valid, and the bus master stop request signal and the bus slave stop request signal become invalid simultaneously (corresponding to...). Figure 3 At time ③ in the sequence, the bus interaction state was switched to the proxy state; and after the bus proxy enable signal was valid and the bus master stop request signal and the bus slave stop request signal were invalid for the sixth number of clock cycles, the clock enable signal was invalidated (corresponding to...). Figure 3 At time ④ in the middle, the timing sequence of the clock-off operation is now complete.

[0081] The address valid signal (avalid) and the address ready signal (aready) are handshake signals of the bus interface. The address valid signal is used to notify the slave device that the master device is ready to send a signal, and the address ready signal is used to notify the master device that the slave device is ready to receive a signal.

[0082] This ensures that every step of the clock shutdown operation conforms to the preset timing assertion strategy, avoiding functional abnormalities caused by bus chaos or improper clock shutdown timing. Furthermore, the specific number of clock cycles can be determined by the SoC's specific design specifications and is not limited. For example, the first to sixth cycles could be 4, 4, 2, 4, 2, 4 respectively.

[0083] In one implementation, the target low-power operation includes a clock-on operation, and the low-power control interface signals include a bus proxy enable signal and a clock enable signal.

[0084] The timing assertion strategies corresponding to the clock-on operation include: after the rising edge of the current clock cycle when the assertion verification signal is valid, the bus agent enable signal will be disabled after at most the seventh clock cycle; the clock enable signal will be valid after at least the eighth clock cycle when the bus agent enable signal is disabled.

[0085] In this implementation, such as Figure 4 As shown, the timing verification process corresponding to the clock-on operation includes: starting from the rising edge of the current clock cycle when the assertion verification signal is valid, within the first to the seventh clock cycle after this starting point, the bus agent enable signal can be disabled in any of these clock cycles (corresponding to...). Figure 4 The moment indicated by serial number ① marks the bus exiting the proxy state after the previous clock shutdown, preparing for subsequent clock recovery.

[0086] After the bus agent enable signal has been disabled for at least the eighth number of clock cycles, the clock enable signal switches to active (corresponding to...). Figure 4 At moment ② (in the middle sequence), the clock signal synchronously resumes the periodic clock pulses, which means that the clock-on operation is complete.

[0087] In this way, the timing assertion strategy reflects the timing constraint of exiting the agent state first and then restoring clock enable, ensuring a smooth and orderly switching between bus state and clock signal during clocking, and avoiding chip malfunctions caused by sudden clock recovery. The specific number of clock cycles can be determined by the SoC's specific design specifications and is not limited. For example, the seventh and eighth clock cycles can both be set to 4.

[0088] In one implementation, the target low-power operation includes a reset operation, and the low-power control interface signals include a bus master stop request signal, a bus master stop response signal, a bus slave stop request signal, a bus slave stop response signal, a reset signal, a bus proxy enable signal, and a clock enable signal.

[0089] The timing assertion strategy corresponding to the reset operation includes: after the rising edge of the current clock cycle when the assertion verification signal is valid, the bus master stop request signal becomes valid after at least the ninth clock cycle; after the bus master stop request signal becomes valid after at least the tenth clock cycle when the bus master stop request signal becomes valid, the bus master stop response signal becomes valid; after the bus master stop request signal and the bus master stop response signal become valid after the eleventh clock cycle when they both become valid, the bus slave stop request signal becomes valid; after the bus slave stop request signal becomes valid after at least the twelfth clock cycle when it becomes valid, the bus slave stop response signal becomes valid; after the bus slave stop request signal and the bus slave stop response signal become valid after the thirteenth clock cycle when they both become valid, the reset signal, the bus master stop request signal, and the bus slave stop request signal become invalid; after the fourteenth clock cycle when the reset signal, the bus master stop request signal, and the bus slave stop request signal become invalid, the bus agent enable signal becomes valid; after the bus agent enable signal becomes valid after at least the fifteenth clock cycle when it becomes valid, the clock enable signal becomes invalid; after the clock enable signal becomes invalid after at least the sixteenth clock cycle when it becomes invalid, the reset signal becomes valid.

[0090] In this implementation, such as Figure 5 As shown, the timing verification process corresponding to the reset operation includes: starting from the rising edge of the current clock cycle when the assertion verification signal is valid, within the first clock cycle to the ninth clock cycle after this starting point, the bus master device stop request signal can become valid in any of these clock cycles (corresponding to...). Figure 5 (At the moment indicated by serial number ①), ensure that the handshake interaction on the master device side is completed stably.

[0091] When the bus master stop request signal and the bus master stop response signal are both valid for eleven clock cycles, the bus slave stop request signal becomes valid again (corresponding to...). Figure 5 (At the moment of serial number ②); Similarly, after the bus slave device stops requesting the signal to be valid for at least the twelfth number of clock cycles, the bus slave device stops responding to the signal to be valid. At this point, the handshake on the slave device side is also completed, laying the groundwork for a stable bus state for the subsequent reset action.

[0092] After the bus slave stop request signal and the bus slave stop response signal have been valid for a total of thirteen clock cycles, the reset signal, the bus master stop request signal, and the bus slave stop request signal will synchronously become invalid (corresponding to...). Figure 5The moment indicated by number ③ in the sequence signifies the formal triggering of the reset operation; subsequently, after maintaining the current state for fourteen clock cycles, the bus proxy enable signal becomes valid (corresponding to...). Figure 5 At time ④ in the middle, the bus switches to the agent state.

[0093] The clock enable signal is deactivated after the bus proxy enable signal has been active for at least the fifteenth number of clock cycles (corresponding to...). Figure 5 At time ⑤ (in the middle sequence), the clock resumes operation; finally, after at least sixteen clock cycles since the clock enable signal became invalid, the reset signal becomes valid (corresponding to...). Figure 5 At time ⑥ (in the middle sequence), the state recovery of the entire reset process is completed.

[0094] This ensures that the reset operation completes the module reset while avoiding abnormal bus or clock switching. The specific number of clock cycles can be determined by the SoC's design specifications and is not limited. For example, the ninth and sixteenth cycles can be 4, 4, 2, 4, 2, 4, 4, 4, respectively.

[0095] In one implementation, the target low-power operation includes an exit reset operation, and the low-power control interface signals include a reset signal, a bus proxy enable signal, and a clock enable signal.

[0096] The timing assertion strategies corresponding to exiting the reset operation include: after the rising edge of the current clock cycle when the assertion verification signal is valid, the reset signal becomes invalid after at most seventeen clock cycles; after the reset signal becomes invalid for at least eighteen clock cycles, the bus agent enable signal becomes invalid; after the bus agent enable signal becomes invalid for at least nineteen clock cycles, the clock enable signal becomes valid; and after the clock enable signal becomes valid for at least twentieth clock cycles, the reset signal becomes valid.

[0097] In this implementation, such as Figure 6 As shown, the timing verification process corresponding to exiting the reset operation includes: starting from the rising edge of the current clock cycle when the assertion verification signal is valid, the reset signal can be invalidated in any of the following clock cycles from the first clock cycle to the seventeenth clock cycle (corresponding to...). Figure 6 The moment indicated by serial number ① marks the official start of the exit reset operation, and the module begins to leave the reset state.

[0098] After the reset signal remains in an inactive state for at least the eighteenth number of clock cycles, the bus proxy enable signal becomes inactive (corresponding to...). Figure 6 The moment indicated by serial number ② signifies that the bus proxy mode activated during the previous reset process has officially exited, clearing the state obstacles for the subsequent restoration of clock and module functions.

[0099] Subsequently, after the bus agent enable signal remains in an inactive state for at least the nineteenth number of clock cycles, the clock enable signal becomes active (corresponding to...). Figure 6 At moment ③ in the sequence, the clock signal synchronously resumed periodic clock pulses, indicating that the clock function has been started normally and the module has the hardware foundation to resume operation.

[0100] Finally, after the clock enable signal remains active for at least the twentieth number of clock cycles, the reset signal becomes active again (corresponding to...). Figure 6 At moment ④ in the middle, the entire process of exiting the reset operation is completed, and the module smoothly switches from the reset state to the normal working state.

[0101] This ensures a smooth transition of module states during the reset process, avoiding functional abnormalities caused by disordered signal interaction sequences. The specific number of clock cycles can be determined by the SoC's design specifications and is not limited. For example, the seventeenth and twentieth clock cycles can both be 4.

[0102] In one implementation, the target low-power operation includes a power-off operation, and the low-power control interface signals include a bus master stop request signal, a bus master stop response signal, a bus slave stop request signal, a bus slave stop response signal, a reset signal, a bus proxy enable signal, an isolation enable signal, a clock enable signal, a power-off enable signal, and a power-off response signal.

[0103] The timing assertion strategy corresponding to the power-off operation includes: after the rising edge of the current clock cycle when the assertion verification signal is valid, at most twenty-one clock cycles later, the bus master stop request signal becomes valid; after at least twenty-two clock cycles when the bus master stop request signal becomes valid, the bus master stop response signal becomes valid; after twenty-three clock cycles when both the bus master stop request signal and the bus master stop response signal become valid, the bus slave stop request signal becomes valid; after at least twenty-four clock cycles when the bus slave stop request signal becomes valid, the bus slave stop response signal becomes valid; after twenty-five clock cycles when both the bus slave stop request signal and the bus master stop response signal become valid, the reset signal, the bus master stop request signal, and the bus slave stop response signal become valid. The bus slave device stop request signal fails; if the bus agent enable signal is failed, then after the 26th clock cycle, the bus agent enable signal and the isolation enable signal become valid and effective; after the 27th clock cycle, the clock enable signal fails, and after the clock enable signal fails, the power-off enable signal becomes valid; or, if the bus agent enable signal is valid and the clock enable signal is failed, then after the 29th clock cycle, the isolation enable signal becomes valid and effective; after the 30th clock cycle, the power-off enable signal becomes valid; the power-off enable signal remains valid; after the 31st clock cycle, the power-off response signal becomes valid; when the power-off response signal becomes valid, the reset signal becomes valid.

[0104] In this implementation, the power-off operation includes two different cases: performing a power-off operation on the target power domain when it is in a fully functional operating state (normal state power-off operation) and performing a power-off operation on the target power domain when it is in a reset or idle state (reset or idle state power-off operation).

[0105] like Figure 7 and Figure 8 As shown, the timing verification process for power-off operations in normal state and power-off operations in reset or idle state includes: starting from the rising edge of the current clock cycle when the assertion verification signal is valid, within the first clock cycle to the twenty-first clock cycle after this starting point, the bus master device stop request signal can be valid in any of these clock cycles (corresponding to...). Figure 7 or Figure 8 (At the moment indicated by serial number ①), ensure that the bus handshake on the master device side is completed stably.

[0106] The bus master stop request signal becomes valid after at least twenty-two clock cycles. The bus master stop response signal becomes valid after twenty-three clock cycles of simultaneous validity of both the bus master stop request and response signals. Figure 7 or Figure 8(At the moment of serial number ②); Similarly, after the bus slave device stop request signal is valid for at least the 24th number of clock cycles, the bus slave device stop response signal is valid, and the bus handshake on the slave device side is also completed synchronously. At this time, the bus is in a stable stopped state.

[0107] After the bus slave stop request signal and the bus slave stop response signal are simultaneously valid for 25 clock cycles, the reset signal, the bus master stop request signal, and the bus slave stop request signal will synchronously become invalid (corresponding to...). Figure 7 or Figure 8 The moment indicated by number ③ marks the end of the bus interaction phase, and the target power domain enters the pre-power-off state reset phase.

[0108] against Figure 7 The normal power-off operation shown is in a state where the bus agent enable signal is disabled. After maintaining this state for 26 clock cycles, the bus agent enable signal and the isolation enable signal will become synchronously effective (corresponding to...). Figure 7 At time ④ in the sequence, the bus proxy mode was enabled and the power domain signal was isolated to avoid external signal interference during power-off; subsequently, after both remained valid for a full twenty-seven clock cycles, the clock enable signal was disabled (corresponding to...). Figure 7 At time ⑤, the clock stops running; after the clock enable signal fails for the 28th clock cycle, the power-off enable signal becomes active (corresponding to...). Figure 7 At moment ⑥ in the middle, the power outage process of the power domain is officially triggered.

[0109] against Figure 8 The reset or idle state power-off operation shown indicates that the bus agent enable signal is active and the clock enable signal is inactive. After maintaining this state for the 29th number of clock cycles, the isolation enable signal becomes active (corresponding to...). Figure 8 At time ④ in the sequence, the bus proxy mode was enabled and the power domain signal was isolated to avoid external signal interference during power-off; subsequently, after the isolation enable signal was effectively maintained for the thirtieth number of clock cycles, the power-off enable signal became effective (corresponding to...). Figure 8 At moment ⑤ in the middle, the power outage process of the power domain is officially triggered.

[0110] The power-off enable signal remains active until the power-off response signal becomes active, at which point the power-off response signal becomes active after the thirty-first clock cycle, indicating that the power module has received the power-off command. When both signals remain active for the thirty-second clock cycle, the reset signal becomes active (corresponding to...). Figure 7 The time of number ⑦ in the middle or Figure 8 At moment ⑥ (in the middle sequence), the entire power-off operation is now complete, and the target power domain has safely entered the power-off state.

[0111] This ensures a safe and orderly power-off process, preventing anomalies caused by power domain chaos. The specific number of clock cycles can be determined by the SoC's design specifications and is not limited. For example, the twenty-first and thirty-second cycles can be 4, 4, 2, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4 respectively, and the thirty-first cycle can also be any other value; there are no specific limitations.

[0112] In one implementation, the target low-power operation includes a power-on operation, and the low-power control interface signals include a reset signal, a power-off enable signal, a power-off response signal, a bus proxy enable signal, an isolation enable signal, and a clock enable signal.

[0113] The timing assertion strategy corresponding to the power-on operation includes: after the rising edge of the current clock cycle when the assertion verification signal is valid, the reset signal becomes invalid after at least the 33rd clock cycle; after the reset signal becomes invalid for at least the 34th clock cycle, the power-off enable signal becomes invalid; after the power-off enable signal remains invalid for at least the 35th clock cycle, the power-off response signal becomes invalid; after the power-off response signal becomes invalid for at least the 36th clock cycle, the bus proxy enable signal and the isolation enable signal become invalid; after the bus proxy enable signal and the isolation enable signal become invalid for at least the 37th clock cycle, the clock enable signal becomes valid; after the clock enable signal becomes valid for at least the 38th clock cycle, the reset signal becomes valid.

[0114] In this implementation, such as Figure 9 As shown, the timing verification process corresponding to the power-on operation includes: starting from the rising edge of the current clock cycle when the assertion verification signal is valid, within the first clock cycle to the thirty-third clock cycle after this starting point, the reset signal can be invalidated in any of these clock cycles (corresponding to...). Figure 9 The moment marked by serial number ① signifies the formal commencement of the power-on operation, and the target power domain begins to leave the initial reset state.

[0115] After the reset signal remains in an inactive state for at least the thirty-fourth clock cycle, the power-off enable signal becomes inactive (corresponding to...). Figure 9 At time ② in the middle, the power-off response signal is in an active state. Subsequently, the power-off enable signal remains inactive until the 35th clock cycle, at which point the power-off response signal becomes inactive, thus resetting the power state and laying the foundation for the subsequent power restoration of the target power domain.

[0116] After the power-off response signal remains in a failed state for at least the thirty-sixth clock cycle, the bus proxy enable signal and the isolation enable signal will simultaneously fail (corresponding to...). Figure 9 The moment indicated by number ③ signifies that the bus proxy mode and signal isolation function activated during the power-off phase have officially exited, and the signal link of the target power domain has returned to normal.

[0117] After both remain in a failed state for at least the thirty-seventh number of clock cycles, the clock enable signal becomes valid (corresponding to...). Figure 9 At time ④ in the sequence, the clock signal synchronously resumes periodic clock pulses, indicating that the clock function has been started normally and the target power domain has the hardware conditions to resume operation.

[0118] The reset signal becomes active after the clock enable signal remains active for at least the thirty-eighth number of clock cycles. Figure 9 At moment ⑤ in the middle, the entire power-on operation process is now complete, and the target power domain smoothly switches from a power-off state to a normal operating state.

[0119] This ensures a smooth and orderly transition between states during power-on, preventing functional abnormalities caused by chaotic signal interaction. The specific number of clock cycles can be determined by the SoC's design specifications and is not limited. For example, the 33rd to 38th cycles can all be 4, and the 35th cycle can also be any other value; there are no specific restrictions.

[0120] like Figure 10 The diagram shown is an implementation system architecture diagram of a chip low-power function verification method provided in this application embodiment, including an assertion verification layer deployed on the verification device and a low-power design layer of the chip to be verified.

[0121] The assertion verification layer includes low-power operation assertion components corresponding to different low-power functional modules, including but not limited to digital signal processor assertion components, high-speed serial interconnect interface assertion components, double data rate synchronous dynamic random access memory controller assertion components, analog-to-digital converter controller assertion components, timer assertion components, and direct memory access controller assertion components. For example, the digital signal processor assertion component includes assertion verification units designed for low-power operations such as power-off assertions, power-on assertions, clock-off assertions, clock-on assertions, reset assertions, and exit reset assertions for digital signal processors; the direct memory access controller assertion component includes assertion verification units designed for low-power operations such as clock-off assertions, clock-on assertions, reset assertions, and exit reset assertions for direct memory access controllers.

[0122] The low-power design layer is the actual low-power hardware architecture of the chip. The power state controller is responsible for managing the power states of different power domains, which include controllable power domains and normally-on power domains. The controllable power domain includes, but is not limited to, modules such as digital signal processors, high-speed serial interconnect interfaces, and double data rate synchronous dynamic random access memory controllers. The normally-on power domain includes, but is not limited to, modules such as analog-to-digital converter controllers, timers, and direct memory access controllers.

[0123] In the low-power design layer of the chip to be verified, the power state controller can receive low-power control instructions issued by the upper-level controller through the high-level peripheral bus, and realize the interaction of low-power control interface signals through the low-power hardware logic interface between each power domain. For example, the power state controller interacts with the digital signal processor through the digital signal processor low-power hardware logic interface, and the power state controller interacts with the direct memory access controller through the direct memory access controller low-power hardware logic interface.

[0124] Meanwhile, in the assertion verification layer of the verification device, low-power control commands issued by the upper-level controller can also be received through the high-level peripheral bus. Then, by parsing the low-power control commands, the target power domain indicated by them can be determined and an assertion verification signal can be generated.

[0125] Furthermore, during the execution of the target low-power operation by the chip to be verified, the verification device can acquire multiple low-power control interface signals between the power state controller and the target power domain through the low-power hardware logic interface between the power state controller and the target power domain. Based on the assertion verification signals and the timing assertion strategy corresponding to the target low-power operation, the device performs timing verification on the multiple low-power control interface signals to obtain the verification results.

[0126] The user data, data acquisition, and / or use involved in the embodiments of this application strictly comply with the laws, regulations, and industry standards of relevant countries and regions. The collection and acquisition of data involved in the embodiments of this application are all done in advance by actively prompting or prominently displaying information to inform users and obtaining authorization, or by obtaining full authorization from all parties. The processing, manipulation, forwarding, and use of data involved in the embodiments of this application are all carried out on the premise that the user or relevant party is fully informed and authorized. In implementing the various embodiments of this application, the types of data or information, scope of use, and usage scenarios that may be involved are informed to users or relevant parties and authorization is obtained through appropriate means. The specific methods of notification and authorization may vary according to actual circumstances, and this application is not limited in this regard. The processing of personal information involved in the embodiments of this application is carried out under the premise of having a legal basis (such as obtaining the consent of the personal information subject or being necessary for the performance of a contract), and is only processed within the prescribed or agreed scope. Sensitive personal information such as biometric information, medical and health information, financial account information, and precise location information involved in the embodiments of this application are all processed under the premise of having a specific purpose and sufficient necessity, and with the separate authorization and consent of the user or relevant party.

[0127] In some embodiments of this application, if the user or related party refuses to process personal information other than the information necessary for the basic functions, it will not affect the use of the basic functions of the embodiments of this application.

[0128] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0129] Based on the same inventive concept, this application also provides a chip low-power function verification device for implementing the chip low-power function verification method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the chip low-power function verification device provided below can be found in the limitations of the chip low-power function verification method described above, and will not be repeated here.

[0130] In one exemplary embodiment, such as Figure 11 As shown, a chip low-power function verification device is provided, which includes the following modules.

[0131] The generation module 201 is used to parse the low-power control instructions to the power state controller and generate an assertion verification signal; the low-power control instructions are used to instruct the power state controller to perform a target low-power operation on a target power domain within the same chip.

[0132] The acquisition module 202 is used to acquire multiple low-power control interface signals between the power state controller and the target power domain during the execution of the target low-power operation.

[0133] The verification module 203 is used to perform timing verification on the multiple low-power control interface signals based on the assertion verification signal and the timing assertion strategy corresponding to the target low-power operation, and obtain the verification result.

[0134] Each module in the aforementioned low-power function verification device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0135] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 12 As shown, the computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores measurement data and / or positioning information. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a low-power chip function verification method.

[0136] Those skilled in the art will understand that Figure 12 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0137] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in any of the above method embodiments.

[0138] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in any of the above method embodiments.

[0139] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0140] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0141] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0142] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0143] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A method for verifying the low-power functionality of a chip, characterized in that, The method includes: The low-power control instructions to the power state controller are parsed to generate an assertion verification signal; the low-power control instructions are used to instruct the power state controller to perform a target low-power operation on a target power domain within the same chip. During the execution of the target low-power operation, multiple low-power control interface signals between the power state controller and the target power domain are acquired; Based on the assertion verification signal and the timing assertion strategy corresponding to the target low-power operation, timing verification is performed on the multiple low-power control interface signals to obtain the verification result. The verification result includes timing verification success or timing verification failure; the timing verification of the multiple low-power control interface signals based on the assertion verification signal and the timing assertion strategy corresponding to the target low-power operation, to obtain the verification result, includes: In response to the assertion verification signal, timing monitoring of the plurality of low-power control interface signals is initiated; If the timing changes of the signal states of each of the low-power control interface signals in multiple clock cycles all conform to the timing assertion strategy corresponding to the target low-power operation, then the timing verification is deemed successful. If the timing change of the signal state of any of the low-power control interface signals in any clock cycle does not conform to the timing assertion strategy, then the timing verification is deemed to have failed.

2. The method according to claim 1, characterized in that, The acquisition of multiple low-power control interface signals between the power state controller and the target power domain includes: Multiple low-power control interface signals between the power state controller and the target power domain are acquired through the low-power hardware logic interface between the power state controller and the target power domain.

3. The method according to claim 1, characterized in that, The target low-power operation includes clock shutdown operation, and the low-power control interface signals include bus master stop request signal, bus master stop response signal, bus slave stop request signal, bus slave stop response signal, bus agent enable signal, and clock enable signal; The timing assertion strategy corresponding to the clock-off operation includes: After the rising edge of the current clock cycle when the assertion verification signal is valid, the bus master device stops requesting the signal to be valid after at most a first number of clock cycles; The bus master stop request signal becomes valid after at least a second number of clock cycles; The bus slave device stop request signal becomes valid after the bus master device stop request signal and the bus master device stop response signal have been valid for a third number of clock cycles. The bus slave device stop request signal becomes valid after at least the fourth number of clock cycles; After the bus slave device stop request signal and the bus slave device stop response signal are valid for a fifth number of clock cycles, the bus agent enable signal becomes valid, and the bus master device stop request signal and the bus slave device stop request signal become invalid. The clock enable signal deactivates after a sixth number of clock cycles when the bus agent enable signal is active and the bus master stop request signal and the bus slave stop request signal are inactive.

4. The method according to claim 1, characterized in that, The target low-power operation includes clock-on operation, and the low-power control interface signals include bus proxy enable signal and clock enable signal; The timing assertion strategy corresponding to the clock-opening operation includes: The bus agent enable signal will be deactivated after the rising edge of the current clock cycle when the assertion verification signal is valid, at most the seventh number of clock cycles. The clock enable signal becomes active after the bus agent enable signal has been disabled for at least the eighth number of clock cycles.

5. The method according to claim 1, characterized in that, The target low-power operation includes a reset operation, and the low-power control interface signals include a bus master stop request signal, a bus master stop response signal, a bus slave stop request signal, a bus slave stop response signal, a reset signal, a bus proxy enable signal, and a clock enable signal. The timing assertion strategy corresponding to the reset operation includes: After the rising edge of the current clock cycle when the assertion verification signal is valid, the bus master device stops requesting the signal to be valid after at most the ninth number of clock cycles. The bus master stop request signal becomes valid after at least the tenth number of clock cycles; The bus slave device stop request signal becomes valid after the bus master device stop request signal and the bus master device stop response signal have been valid for eleventh number of clock cycles. The bus slave device stops responding after at least twelfth clock cycle of the bus slave device stop request signal being valid; After the bus slave device stop request signal and the bus slave device stop response signal have been valid for thirteen clock cycles, the reset signal, the bus master device stop request signal, and the bus slave device stop request signal become invalid. The bus proxy enable signal becomes active fourteen clock cycles after the reset signal, the bus master stop request signal, and the bus slave stop request signal have failed. The clock enable signal becomes invalid after the bus proxy enable signal has been active for at least the fifteenth number of clock cycles. The reset signal becomes active after the clock enable signal has been disabled for at least the sixteenth number of clock cycles.

6. The method according to claim 1, characterized in that, The target low-power operation includes exiting the reset operation, and the low-power control interface signals include a reset signal, a bus proxy enable signal, and a clock enable signal. The timing assertion strategy corresponding to the exit reset operation includes: The reset signal becomes invalid after the rising edge of the current clock cycle when the assertion verification signal is valid, at most seventeen clock cycles later. The bus proxy enable signal fails after the reset signal fails for at least the eighteenth number of clock cycles. The clock enable signal becomes active after the bus proxy enable signal has been invalidated for at least the nineteenth number of clock cycles. The reset signal becomes active after the clock enable signal has been active for at least the twentieth number of clock cycles.

7. The method according to claim 1, characterized in that, The target low-power operation includes a power-off operation, and the low-power control interface signals include a bus master stop request signal, a bus master stop response signal, a bus slave stop request signal, a bus slave stop response signal, a reset signal, a bus agent enable signal, an isolation enable signal, a clock enable signal, a power-off enable signal, and a power-off response signal. The timing assertion strategy corresponding to the power-off operation includes: After the rising edge of the current clock cycle when the assertion verification signal is valid, the bus master device stops requesting the signal to be valid after at most twenty-first clock cycles; The bus master stop request signal becomes valid after at least twenty-two clock cycles; After the bus master stop request signal and the bus master stop response signal have been valid for twenty-third number of clock cycles, the bus slave stop request signal becomes valid. The bus slave device stops responding after the bus slave device stop request signal has been valid for at least the twenty-fourth number of clock cycles. After the bus slave device stop request signal and the bus slave device stop response signal have been valid for twenty-fifth clock cycles, the reset signal, the bus master device stop request signal, and the bus slave device stop request signal become invalid. If the bus proxy enable signal is in a disabled state, then after the twenty-sixth clock cycle, the bus proxy enable signal and the isolation enable signal become valid. After the twenty-seventh clock cycle, the clock enable signal becomes disabled. After the clock enable signal becomes disabled, after the twenty-eighth clock cycle, the power-off enable signal becomes valid. Alternatively, if the bus proxy enable signal is valid and the clock enable signal is in a disabled state, then after the twenty-ninth clock cycle, the isolation enable signal becomes valid. After the thirtieth clock cycle, the power-off enable signal becomes valid. After the power-off enable signal remains active for thirty-one clock cycles, the power-off response signal becomes active. The reset signal becomes valid when the power-off response signal is valid for the thirty-second number of clock cycles.

8. The method according to claim 1, characterized in that, The target low-power operation includes a power-on operation, and the low-power control interface signals include a reset signal, a power-off enable signal, a power-off response signal, a bus proxy enable signal, an isolation enable signal, and a clock enable signal. The timing assertion strategy corresponding to the power-on operation includes: The reset signal becomes invalid after the rising edge of the current clock cycle when the assertion verification signal is valid, at most the thirty-third number of clock cycles later. The power-off enable signal fails after the reset signal fails for at least the thirty-fourth number of clock cycles. After the power-off enable signal remains in an inactive state for at least the thirty-fifth number of clock cycles, the power-off response signal becomes inactive. The bus proxy enable signal and the isolation enable signal fail after the power-off response signal fails for at least the thirty-sixth number of clock cycles. The clock enable signal becomes active after the bus proxy enable signal and the isolation enable signal have been disabled for at least the thirty-seventh number of clock cycles. The reset signal becomes active after the clock enable signal has been active for at least the thirty-eighth number of clock cycles.

9. A chip low-power function verification device, characterized in that, The device includes: The generation module is used to parse the low-power control instructions to the power state controller and generate assertion verification signals; the low-power control instructions are used to instruct the power state controller to perform a target low-power operation on a target power domain within the same chip. The acquisition module is used to acquire multiple low-power control interface signals between the power state controller and the target power domain during the execution of the target low-power operation. The verification module is used to perform timing verification on the multiple low-power control interface signals based on the assertion verification signal and the timing assertion strategy corresponding to the target low-power operation, and obtain the verification result. The verification result includes successful timing verification or timing verification failure; the verification module is specifically used for: In response to the assertion verification signal, timing monitoring of the plurality of low-power control interface signals is initiated; if the timing changes of the signal state of each low-power control interface signal in multiple clock cycles all conform to the timing assertion strategy corresponding to the target low-power operation, the timing verification is determined to be successful; if the timing changes of the signal state of any low-power control interface signal in any clock cycle do not conform to the timing assertion strategy, the timing verification is determined to be unsuccessful.

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