SOT-MRAM device and preparation method thereof
By etching the magnetic tunnel junction stacked layer of the SOT-MRAM device stepwise and forming a protective layer, the problem of sidewall metal redeposition during the etching process was solved, thus improving the yield and reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-15
- Publication Date
- 2026-03-10
AI Technical Summary
During the etching process to form bits in SOT-MRAM devices, the redeposition of metal on the sidewalls of the magnetic tunnel junction (MTJ) causes bit short circuits, affecting the yield of SOT-MRAM devices.
By etching the magnetic tunnel junction stacked layer in the SOT-MRAM device stepwise, and forming a first protective layer when the etching stops on the barrier layer, the sidewall metal redeposition is avoided, and the reference layer and pinning layer are protected from ion damage.
It improves the yield of SOT-MRAM devices, reduces the occurrence of bit short circuits, and protects the critical layer structure from damage.
Smart Images
Figure CN121645894A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of magnetic memory technology, and in particular to a SOT-MRAM device and its fabrication method. Background Technology
[0002] Spin-orbit-moment magnetic random access memory (SOT-MRAM) has advantages such as non-volatility, fast read / write speed, long lifespan, and low power consumption, making it a memory device with great development potential. A bit in an SOT-MRAM device includes a spin-orbit-moment providing layer and a magnetic tunneling junction. During writing, current needs to be applied to the spin-orbit-moment providing layer; different directions of current are used to write different stored information.
[0003] However, during the etching process to form bits in SOT-MRAM devices, there is a problem of metal redeposition on the sidewalls of magnetic tunnel junctions (MTJs), which can lead to bit short circuits and affect the yield of SOT-MRAM devices. Summary of the Invention
[0004] To address the aforementioned issues, the SOT-MRAM device and its fabrication method provided by this invention involve stepwise etching of the magnetic tunnel junction stacked layer in the SOT-MRAM device, and forming a first protective layer when the etching stops on the barrier layer. This effectively avoids the problem of sidewall metal redeposition during the etching of the magnetic tunnel junction stacked layer, thereby improving the yield of the SOT-MRAM device.
[0005] In a first aspect, the present invention provides a method for fabricating a SOT-MRAM device, the method comprising:
[0006] A spin orbital layer, a magnetic tunnel junction stacked layer, and a hard mask layer are formed sequentially from bottom to top on the substrate. The magnetic tunnel junction stacked layer includes a free layer, a barrier layer, a reference layer, and a pinned layer stacked sequentially from bottom to top.
[0007] Patterned hard mask layer;
[0008] The magnetic tunnel junction stack is etched based on the patterned hard mask layer and stops on the barrier layer;
[0009] A first protective layer is deposited on the barrier layer, which covers the etched pinned layer and reference layer.
[0010] The first protective layer, barrier layer, and free layer are etched to form bits.
[0011] Optionally, the steps of etching the first protective layer, the barrier layer, and the free layer include:
[0012] The first protective layer, barrier layer, and free layer are etched, and the etching stops within ±2 nm of the upper surface of the spin orbital layer.
[0013] Optionally, the steps of etching the first protective layer, the barrier layer, and the free layer include:
[0014] The first protective layer, barrier layer, and free layer are etched, and the etching stops on the spin orbital layer to retain the portion of the first protective layer that is attached to the pinned layer and reference layer, forming a bit.
[0015] After etching the first protective layer, the barrier layer, and the free layer, the method further includes:
[0016] Clean the sidewalls of the first protective layer, barrier layer, and free layer after etching.
[0017] Optionally, the steps of etching the first protective layer, the barrier layer, and the free layer include:
[0018] The first protective layer, barrier layer, and free layer are etched according to the vertical portion of the first protective layer, and the etching stops on the free layer to preserve the bottom portion of the free layer;
[0019] The first protective layer, barrier layer, and free layer sidewalls, as well as the bottom portion of the free layer, are etched and cleaned, and the etching stops at the spin orbital layer to remove the bottom portion of the free layer, forming bits.
[0020] Optionally, after etching the first protective layer, the barrier layer, and the free layer, the method further includes:
[0021] A second protective layer is deposited on the spin orbital layer, which encapsulates the etched barrier layer and free layer.
[0022] Optionally, prior to the step of depositing the first protective layer on the barrier layer, the method further includes:
[0023] The exposed surfaces of the magnetic tunnel junction stack are subjected to oxidation treatment.
[0024] Optionally, after etching the first protective layer, the barrier layer, and the free layer, the method further includes:
[0025] The exposed surfaces of the anatomical units are oxidized.
[0026] Optionally, the pinning layer includes a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer stacked sequentially from bottom to top;
[0027] The spacer layer is made of insulating material, and the magnetization direction of the first ferromagnetic layer is opposite to that of the second ferromagnetic layer.
[0028] Optionally, the thickness of the first protective layer ranges from 5 nanometers to 20 nanometers;
[0029] The thickness of the barrier layer ranges from 0.5 nanometers to 2 nanometers.
[0030] In a second aspect, the present invention provides a SOT-MRAM device, which is fabricated using any of the methods described above.
[0031] The SOT-MRAM device and its fabrication method provided in this invention involve stepwise etching of the magnetic tunnel junction stacked layer in the SOT-MRAM device, forming a first protective layer when the etching stops at the barrier layer, and continuing to etch the remaining part of the magnetic tunnel junction stacked layer after the formation of the first protective layer. The first protective layer helps to isolate the reference layer and the free layer, reducing bit short circuits. It also protects the reference layer and the pinning layer from ion damage during the sidewall cleaning process. This effectively avoids the problem of sidewall metal redeposition during the etching of the magnetic tunnel junction stacked layer, thus improving the yield of the SOT-MRAM device. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a schematic flowchart illustrating a method for fabricating an SOT-MRAM device according to an embodiment of this application;
[0034] Figures 2 to 8 These are schematic cross-sectional views corresponding to various stages of fabrication of an SOT-MRAM device according to an embodiment of this application.
[0035] Figure label:
[0036] 1. Substrate; 2. Spin-orbit layer; 3. Magnetic tunnel junction stacked layer; 31. Free layer; 32. Barrier layer; 33. Reference layer; 34. Pinned layer; 4. Hard mask layer; 5. First protective layer; 6. Second protective layer; 7. Filler layer. Detailed Implementation
[0037] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0040] It should be noted that when an element is referred to as "fixedly connected" to another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.
[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.
[0042] Example 1
[0043] This embodiment provides a method for fabricating a SOT-MRAM device, see [link to documentation]. Figure 1 The method includes steps S101 to S105.
[0044] Step S101: A spin orbital layer 2, a magnetic tunnel junction stacked layer 3, and a hard mask layer 4 are sequentially formed from bottom to top on the substrate 1, and then combined with... Figure 2 .
[0045] The magnetic tunnel junction stacked layer 3 includes a free layer 31, a barrier layer 32, a reference layer 33, and a pinning layer 34 stacked sequentially from bottom to top; the free layer 31 is bonded to the spin orbital layer 2; necessary transistors and conductive lines are disposed on the substrate 1, which will not be described in detail in this embodiment.
[0046] In a further optional embodiment of this example, the thickness of the spin-orbit layer 2 ranges from 3 nanometers to 8 nanometers, such as 5 nanometers or 8 nanometers. The material of the spin-orbit layer 2 includes, but is not limited to, heavy metal materials and topological insulating materials; this embodiment does not specifically limit these materials.
[0047] The thickness of the barrier layer 32 ranges from 0.5 nanometers to 2 nanometers. Specifically, the thickness of the barrier layer 32 is 0.8 nanometers, 1 nanometer, 1.2 nanometers, 1.5 nanometers, or 1.8 nanometers, but is not limited thereto. The material of the barrier layer 32 includes, but is not limited to, at least one of oxides, nitrides, and oxynitrides, but this embodiment does not specifically limit this.
[0048] The spin direction of the reference layer 33 can be perpendicular or parallel, and it includes, but is not limited to, ferromagnetic metals, ferrimagnetic metals and their alloys, or superlattice structure materials composed of at least one of Co / Pt, Co / Pd and Co / Ni. This embodiment does not specifically limit this. The easy magnetization direction of the free layer 31 is parallel to the spin direction of the reference layer 33, and its material includes, but is not limited to, ferromagnetic metals, ferrimagnetic metals and their alloys.
[0049] The material of the hard mask layer 4 includes at least one of a metal mask or a dielectric mask. Metal masks include materials such as Ta, TaN, and TiN, while dielectric masks include materials such as SiOx and SiNx.
[0050] In a further optional embodiment of this embodiment, the pinning layer 34 includes a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer stacked sequentially from bottom to top.
[0051] The spacer layer is made of an insulating material, and the magnetization direction of the first ferromagnetic layer is opposite to that of the second ferromagnetic layer. The magnetization directions of the first and second ferromagnetic layers can be in-plane or out-of-plane. The materials of the first and second ferromagnetic layers include, but are not limited to, at least one of ferromagnetic and ferrimagnetic metals, or a superlattice structure material composed of at least one of Co / Pt, Co / Pd, and Co / Ni, or an artificial antiferromagnetic structure material formed by coupling heavy metals using the RKKY (Ruderman-Kittel-Kasuya-Yosida) model. The structure and function of this pinning layer 34 should be optimized and adjusted based on the function and structure of the SOT-MRAM device; this embodiment does not specifically limit this.
[0052] Step S102: Pattern the hard mask layer 4, and combine Figure 2 .
[0053] Step S103: Etch the magnetic tunnel junction stacked layer 3 according to the patterned hard mask layer 4, and stop at the barrier layer 32, combining... Figure 3 .
[0054] The etching method in step S103 can be ion beam etching or reactive ion etching, but is not limited to these. It is understood that the etching stopping at the barrier layer 32 includes, but is not limited to, any of the following etching scenarios.
[0055] Case 1: Etching stops at the upper surface of barrier layer 32.
[0056] Scenario 2: During the etching process, the barrier layer 32 was over-etched, that is, the etching stopped inside the barrier layer 32.
[0057] Step S104: Deposit the first protective layer 5 on the barrier layer 32, and combine Figure 4 .
[0058] The first protective layer 5 covers the etched pinning layer 34 and the reference layer 33.
[0059] In a further optional embodiment of this example, the thickness of the first protective layer 5 ranges from 5 nanometers to 20 nanometers. Specifically, the thickness of the first protective layer 5 is 6 nanometers, 8 nanometers, 10 nanometers, 15 nanometers, or 18 nanometers, etc., but is not limited thereto.
[0060] In a further optional embodiment of this embodiment, before step S104 and after step S103, the method further includes: oxidizing the exposed surface of the magnetic tunnel junction stacked layer 3.
[0061] It is understood that the oxidation process performed before step S104 and after step S103 includes, but is not limited to, introducing oxygen or oxygen plasma into the etching chamber, or removing the device etched in step S103 from the etching chamber and oxidizing the surface of the device with external air to form an oxide film on the surface of the device. The objects of this oxidation process include the sidewalls of the pinning layer 34 and the reference layer 33, as well as the upper surface of the barrier layer 32.
[0062] The specific implementation of the oxidation treatment of the exposed surface of the magnetic tunnel junction stack 3 is to oxidize the sidewalls of the hard mask layer 4, the pinning layer 34 and the reference layer 33, as well as the upper surface of the hard mask layer 4 and the barrier layer 32.
[0063] It should be noted that due to the non-uniformity of etching, when the etching stop barrier layer 32 is set on the upper surface, a portion of the bottom area of the reference layer 33 will not be completely etched during the actual etching process, which increases the probability of short circuits. After oxidation treatment, the material of the reference layer 33 becomes non-conductive, which can reduce the occurrence of short circuits between the reference layer 33 and the free layer 31, thereby improving the yield of SOT-MRAM devices.
[0064] Step S105: Etch the first protective layer 5, the barrier layer 32, and the free layer 31, and combine them. Figure 5 .
[0065] The etching method in step S105 can be ion beam etching or reactive ion etching, but is not limited to these. The bit includes a magnetic tunnel junction etched from the magnetic tunnel junction stack layer 3 and a spin orbital layer 2.
[0066] During the etching of the first protective layer 5, barrier layer 32, and free layer 31, the etching can stop within the free layer 31, or it can stop at the upper surface of the spin orbital layer 2, or the spin orbital layer 2 can be over-etched. In a further optional embodiment of this embodiment, the step of etching the first protective layer 5, barrier layer 32, and free layer 31 includes: etching the first protective layer 5, barrier layer 32, and free layer 31, and stopping the etching within a range of ±2 nm based on the upper surface of the spin orbital layer 2.
[0067] In a further optional embodiment of this embodiment, the step of etching the first protective layer 5, the barrier layer 32 and the free layer 31 includes: etching the first protective layer 5, the barrier layer 32 and the free layer 31, and stopping on the spin orbital layer 2, so as to retain the portion of the first protective layer 5 that is attached to the pinned layer 34 and the reference layer 44 to form a bit.
[0068] The process of etching the first protective layer 5 includes removing the horizontal portion of the first protective layer 5; the etching method in the step where the etching stops on the spin orbital layer 2 can be ion beam etching or reactive ion etching, but is not limited to these. It is understood that the etching stopping on the spin orbital layer 2 includes, but is not limited to, any of the following etching conditions.
[0069] Etching Case 1: Etching stops at the upper surface of spin orbital layer 2, combined with... Figure 5 .
[0070] Etching Scenario 2: During the etching process, the spin orbital layer 2 was over-etched, and the over-etching depth did not exceed 2 nanometers, meaning the etching stopped inside the spin orbital layer 2. Figure 6 .
[0071] In this embodiment, the etching of the first protective layer 5, barrier layer 32, and free layer 31 is etching case 1, that is, etching the first protective layer 5, barrier layer 32, and free layer 31, and stopping on the upper surface of the spin orbit layer 2. It can be understood that during the etching of the first protective layer 5, barrier layer 32, and free layer 31, and stopping on the spin orbit layer 2, specifically, the horizontal and vertical portions of the first protective layer 5 are removed to different degrees. Due to the influence of the etching angle, the removal rate of the horizontal portion of the first protective layer 5 is greater than that of the vertical portion. Thus, after stopping on the spin orbit layer 2, a portion of the vertical portion of the first protective layer 5 will be retained and stacked on top of the etched barrier layer 32 and free layer 31.
[0072] In a further optional embodiment of this embodiment, after etching the first protective layer 5, the barrier layer 32 and the free layer 31, the method further includes cleaning the sidewalls of the etched first protective layer 5, the barrier layer 32 and the free layer 31 and the upper surface of the spin orbital layer 2.
[0073] Understandably, in the semiconductor field, cleaning processes have a certain etching function. During the cleaning process of the sidewalls of the etched first protective layer 5, barrier layer 32, and free layer 31, as well as the upper surface of the spin orbital layer 2, it is permissible to appropriately over-etch the spin orbital layer 2, for example, not exceeding 2nm, to ensure good morphology and performance of the magnetic tunnel junction.
[0074] In this embodiment, a low-energy etching cleaning method is used during the cleaning of the sidewalls of the first protective layer 5, barrier layer 32, and free layer 31, as well as the upper surface of the spin orbital layer 2 after etching. The low-energy etching cleaning is a process that uses energy below 200 electron volts. Compared with the traditional etching process that uses energy above 500 electron volts, the low-energy etching cleaning method in this embodiment can not only clean the contaminants on the device surface, but also protect the device structure.
[0075] In a further optional embodiment of this embodiment, combined with Figure 7 After etching the first protective layer 5, the barrier layer 32 and the free layer 31, the method further includes depositing a second protective layer 6 on the spin orbital layer 2.
[0076] The second protective layer 6 covers the first protective layer 5, the hard mask layer 4, and the magnetic tunnel junction; the thickness of the material of the second protective layer 6 ranges from 5 nanometers to 20 nanometers, such as 6 nanometers, 8 nanometers, 10 nanometers, 15 nanometers, or 18 nanometers; the material of the second protective layer 6 is an insulating material, such as silicon nitride (SiNx), but is not limited to this.
[0077] Combination Figure 7 After depositing the second protective layer 6, the method further includes depositing a filling layer 7. The filling layer 7 covers the second protective layer 6; the material of the filling layer 7 is an insulating material, such as silicon oxide (SiOx), but is not limited to this. After forming the filling layer 7, the method further includes patterning the spin orbital layer 2, forming a top electrode and a top via, etc., to form a complete memory bit structure; this embodiment will not elaborate further on these aspects.
[0078] In a further optional embodiment of this embodiment, after the steps of etching the first protective layer 5, the barrier layer 32 and the free layer 31, and before the deposition of the second protective layer 6, the method further includes: oxidizing the surface of the bit exposed.
[0079] It is understood that the oxidation process performed after step S105 includes, but is not limited to, introducing oxygen or oxygen plasma into the etching chamber, or removing the device etched in step S105 from the etching chamber and oxidizing the surface of the device with external air to form an oxide film on the surface of the device. The objects of this oxidation process include: the sidewalls of the barrier layer 32 and the free layer 31, and the upper surface of the spin orbital layer 2.
[0080] The specific implementation of the oxidation treatment of the exposed surface of the ion is to oxidize the sidewalls of the first protective layer 5, the barrier layer 32 and the free layer 31, as well as the upper surface of the first protective layer 5, the hard mask layer 4 and the spin orbital layer 2.
[0081] Oxidizing the exposed surface of the bits oxidizes the residual metal on the sidewalls of the fabricated magnetic tunnel junction, making it non-conductive. This reduces the occurrence of short circuits between the reference layer 33 and the free layer 31, thereby improving the yield of SOT-MRAM devices.
[0082] The fabrication method of the SOT-MRAM device provided in this embodiment is simple to operate. It involves stepwise etching of the magnetic tunnel junction stacked layer 3 in the SOT-MRAM device, and forming a first protective layer 5 when the etching stops on the barrier layer 32. After the formation of the first protective layer 5, the remaining part of the magnetic tunnel junction stacked layer 3 is etched. The first protective layer 5 helps to isolate the reference layer 33 and the free layer 31, reducing bit short circuits. At the same time, it can also protect the reference layer 33 and the pinning layer 34 from ion damage during the sidewall cleaning process. In this way, the problem of sidewall metal redeposition during the etching of the magnetic tunnel junction stacked layer 3 can be effectively avoided, thus improving the yield of the SOT-MRAM device.
[0083] Example 2
[0084] Based on Example 1, this example provides a method for fabricating an SOT-MRAM device, which includes steps S201 to S210.
[0085] Step S201: A spin orbital layer 2, a magnetic tunnel junction stacked layer 3, and a hard mask layer 4 are sequentially formed from bottom to top on the substrate 1, and then combined with... Figure 2 .
[0086] Step S202: Pattern the hard mask layer 4, and combine Figure 2 .
[0087] Step S203: Etch the magnetic tunnel junction stacked layer 3 according to the patterned hard mask layer 4, stopping at the upper surface of the barrier layer 32, and combine... Figure 3 .
[0088] Step S204: The sidewalls of the pinning layer 34 and the reference layer 33, as well as the upper surface of the barrier layer 32, are subjected to oxidation treatment.
[0089] Step S205: Deposit the first protective layer 5 on the barrier layer 32, and combine Figure 4 .
[0090] Step S206: Etch the horizontal portion of the first protective layer 5, and continue etching the barrier layer 32 and the free layer 31 according to the vertical portion of the first protective layer 5, stopping at the upper surface of the spin orbital layer 2 to form a bit, and combine Figure 5 .
[0091] Step S207: Oxidize the sidewalls of the barrier layer 32 and the free layer 31, as well as the upper surface of the spin orbital layer 2.
[0092] Step S208: Clean the sidewalls of the barrier layer 32 and the free layer 31, as well as the upper surface of the spin orbital layer 2.
[0093] Step S209: Deposit a second protective layer 6 on the spin orbital layer 2, combining Figure 7.
[0094] Step S210: Deposit a filler layer 7 on the second protective layer 6, and combine Figure 7 .
[0095] Example 3
[0096] Based on Example 1, this example provides a method for fabricating an SOT-MRAM device, which includes steps S301 to S311.
[0097] Step S301: A spin orbital layer 2, a magnetic tunnel junction stacked layer 3, and a hard mask layer 4 are sequentially formed from bottom to top on the substrate 1, and then combined with... Figure 2 .
[0098] Step S302: Pattern the hard mask layer 4, and combine Figure 2 .
[0099] Step S303: Etch the magnetic tunnel junction stacked layer 3 according to the patterned hard mask layer 4, stopping at the upper surface of the barrier layer 32, and combine... Figure 3 .
[0100] Step S304: The sidewalls of the pinning layer 34 and the reference layer 33, as well as the upper surface of the barrier layer 32, are subjected to oxidation treatment.
[0101] Step S305: Deposit the first protective layer 5 on the barrier layer 32, and combine Figure 4 .
[0102] Step S306: Etch the horizontal portion of the first protective layer 5, and continue etching the barrier layer 32 and the free layer 31 according to the vertical portion of the first protective layer 5, stopping at the free layer 31 to retain the bottom portion of the free layer 31, combining... Figure 8 .
[0103] Step S307: Etch and clean the sidewalls of the first protective layer 5, the barrier layer 32, and the free layer 31, as well as the bottom portion of the free layer 31, and stop on the spin orbital layer 2 to remove the bottom portion of the free layer 31, forming bits, and combining. Figure 5 .
[0104] It should be noted that the etching and cleaning method in step S307 is the same as the cleaning process, and the etching function in the cleaning process is used to remove the bottom part of the free layer 31.
[0105] Step S308: Oxidize the sidewalls of the barrier layer 32 and the free layer 31, as well as the upper surface of the spin orbital layer 2.
[0106] Step S309: Clean the sidewalls of the barrier layer 32 and the free layer 31, as well as the upper surface of the spin orbital layer 2.
[0107] Step S310: Deposit a second protective layer 6 on the spin orbital layer 2, combining Figure 7 .
[0108] Step S311: Deposit a filler layer 7 on the second protective layer 6, and combine Figure 7 .
[0109] Example 4
[0110] This embodiment provides a SOT-MRAM device, which is fabricated using the method described in any one of Embodiments 1 to 3.
[0111] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0113] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method of fabricating an SOT-MRAM device, the method comprising: The method comprises: forming, on a substrate, a spin orbit layer, a magnetic tunnel junction stack layer and a hard mask layer in sequence from bottom to top, the magnetic tunnel junction stack layer comprising a free layer, a barrier layer, a reference layer and a pinned layer stacked in sequence from bottom to top; patterning the hard mask layer; etching the magnetic tunnel junction stack layer according to the patterned hard mask layer and stopping on the barrier layer; depositing a first protective layer on the barrier layer, the first protective layer covering the etched pinned layer and the reference layer; etching the first protective layer, the barrier layer and the free layer.
2. The method of claim 1, wherein, The step of etching the first protective layer, the barrier layer and the free layer comprises: etching the first protective layer, the barrier layer and the free layer and stopping within a range of ±2nm from the upper surface of the spin orbit layer.
3. The method of claim 1, wherein, The step of etching the first protective layer, the barrier layer and the free layer comprises: etching the first protective layer, the barrier layer and the free layer and stopping on the spin orbit layer to reserve a portion of the first protective layer that is in contact with the pinned layer and the reference layer, forming a bit; after the step of etching the first protective layer, the barrier layer and the free layer, the method further comprises: cleaning the sidewalls of the etched first protective layer, the barrier layer and the free layer.
4. The method of claim 1, wherein, The step of etching the first protective layer, the barrier layer and the free layer comprises: etching the first protective layer, the barrier layer and the free layer according to the vertical portion of the first protective layer and stopping on the free layer to reserve a bottom portion of the free layer; etching and cleaning the sidewalls of the first protective layer, the barrier layer and the free layer and the bottom portion of the free layer and stopping on the spin orbit layer to remove the bottom portion of the free layer, forming a bit.
5. The method of claim 1, wherein, after the step of etching the first protective layer, the barrier layer and the free layer, the method further comprises: depositing a second protective layer on the spin orbit layer, the second protective layer covering the etched barrier layer and the free layer.
6. The method of claim 1, wherein, before the step of depositing a first protective layer on the barrier layer, the method further comprises: performing an oxidation treatment on the exposed surface of the magnetic tunnel junction stack layer.
7. The method of claim 1, wherein, after the step of etching the first protective layer, the barrier layer and the free layer, the method further comprises: performing an oxidation treatment on the exposed surface of the bit.
8. The method according to any one of claims 1 to 7, characterized in that, the pinned layer comprises a first ferromagnetic layer, a spacer layer and a second ferromagnetic layer stacked in sequence from bottom to top; the spacer layer is made of an insulating material, and the magnetization direction of the first ferromagnetic layer is opposite to that of the second ferromagnetic layer.
9. The method according to any one of claims 1 to 7, characterized in that, the thickness of the first protective layer ranges from 5nm to 20nm; the thickness of the barrier layer ranges from 0.5nm to 2nm.
10. An SOT-MRAM device, characterized in that, The SOT-MRAM device is prepared by the method according to any one of claims 1 to 9.