Semiconductor memory device

Abstract

A semiconductor memory device includes: an active region spaced apart from a substrate in a vertical direction and extending in a first direction, the active region including a buried contact, a channel region, and a direct contact; a word line surrounding the channel region and extending in a second direction crossing the first direction; a capacitor including a first electrode including an electrode support portion connected to the buried contact and having a first width in the vertical direction and a main electrode portion integrally connected to the electrode support portion, the main electrode portion having a second width in the vertical direction, where the second width is greater than the first width; and an insulating pad surrounding the buried contact and the electrode support portion of the first electrode.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices, and more specifically, to semiconductor memory devices comprising a plurality of memory cells arranged in a three-dimensional manner. Background Technology

[0002] Due to advancements in electronic technology, the scaling down of semiconductor devices has progressed rapidly. This necessitates the miniaturization of memory cells. However, existing memory cells face limitations in maintaining high integration density and reliability. Therefore, semiconductor memory devices with structures that facilitate both miniaturization and high integration of memory cells are needed. Summary of the Invention

[0003] One or more embodiments provide a semiconductor memory device having a structure that, even when the area occupied by a plurality of memory cells arranged in three dimensions and the distance between the nodes of the capacitor are reduced due to miniaturization and high integration of the plurality of memory cells, the structure is able to eliminate the possibility of defects that may occur due to undesirable deformation of the electrodes of the capacitor during manufacturing and maximize the capacitance of the capacitor by sufficiently increasing the length of the electrodes of the capacitor.

[0004] According to one aspect of the embodiments, a semiconductor memory device includes: an active region spaced apart from a substrate in a vertical direction and extending in a first lateral direction, the active region including a buried contact, a channel region and a direct contact sequentially provided in the first lateral direction, wherein the first lateral direction is parallel to a main surface of the substrate; a word line surrounding the channel region of the active region and extending in a second lateral direction, wherein the second lateral direction is parallel to the main surface of the substrate and intersects the first lateral direction; a capacitor including a first electrode, the first electrode including an electrode support portion and a main electrode portion, the electrode support portion being connected to the buried contact of the active region and having a first width in a vertical direction, the main electrode portion being integrally connected to the electrode support portion and spaced apart from the buried contact in the first lateral direction, and the electrode support portion being between the main electrode portion and the buried contact, the main electrode portion having a second width in a vertical direction greater than the first width; and an insulating pad surrounding the buried contact and the electrode support portion of the first electrode.

[0005] According to another aspect of the embodiments, a semiconductor memory device includes: a memory cell block having a three-dimensional (3D) structure, the memory cell block including a plurality of memory cells repeatedly provided on a substrate in a first lateral direction, a second lateral direction and a vertical direction, wherein the first lateral direction and the second lateral direction intersect each other, and the vertical direction is perpendicular to the main surface of the substrate. The memory cell block includes: a plurality of active regions arranged on a substrate along lines extending in a vertical direction; a plurality of word lines, each of which surrounds a selected active region among the plurality of active regions and extends in a second lateral direction, the plurality of word lines overlapping each other in the vertical direction; a bit line extending in the vertical direction on the substrate, the bit line being connected to one side of each of the plurality of active regions; a plurality of capacitors, each of the plurality of capacitors including a first electrode connected to the other side of the selected active region among the plurality of active regions, the first electrode including an electrode support portion and a main electrode portion, the electrode support portion having a first width in the vertical direction, the main electrode portion being integrally connected to the electrode support portion and spaced apart from the selected active region in the first lateral direction, the electrode support portion being between the main electrode portion and the selected active region, the main electrode portion having a second width in the vertical direction greater than the first width; and a plurality of insulating pads, each of the plurality of insulating pads surrounding the selected active region among the plurality of active regions and the electrode support portion connected to the first electrode of the selected active region.

[0006] According to another aspect of the embodiments, a semiconductor memory device includes: an active region spaced apart from a substrate in a vertical direction and extending in a first lateral direction, the active region including a channel region, a buried contact, and a direct contact, the buried contact and the direct contact being spaced apart from each other in the first lateral direction and the channel region being between the buried contact and the direct contact, wherein the first lateral direction is parallel to the main surface of the substrate; a word line surrounding the channel region of the active region and extending in a second lateral direction, wherein the second lateral direction is parallel to the main surface of the substrate and intersects the first lateral direction; a gate dielectric film between the channel region of the active region and the word line; and a bit line connected to the direct contact of the active region. A contact; a capacitor including a first electrode connected to a buried contact of an active region, the first electrode including an electrode support portion and a main electrode portion, the electrode support portion having a first width in a vertical direction, the main electrode portion being integrally connected to the electrode support portion and spaced apart from the buried contact in a first transverse direction, the electrode support portion being between the main electrode portion and the buried contact, and the main electrode portion having a second width in a vertical direction, wherein the second width is greater than the first width; a metal silicide film between the first electrode of the capacitor and the buried contact of the active region; and an insulating pad surrounding the buried contact, the metal silicide film, and the electrode support portion of the first electrode. Attached Figure Description

[0007] The above and other aspects and features will become more apparent from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 It is a block diagram of a semiconductor memory device according to an embodiment;

[0009] Figure 2 This is a plan view of a semiconductor memory device according to an embodiment;

[0010] Figure 3 It is according to the implementation method along Figure 2 A cross-sectional view taken by line X1-X1';

[0011] Figure 4 According to the implementation method Figure 3 An enlarged cross-sectional view of part of the "EX1" region;

[0012] Figure 5 It is according to the implementation method along Figure 2 A cross-sectional view taken from line Y1-Y1';

[0013] Figure 6 It is according to the implementation method along Figure 4 Enlarged cross-sectional views of some components in the section intercepted by line Y2-Y2';

[0014] Figure 7 This is a cross-sectional view of a semiconductor memory device according to an embodiment;

[0015] Figure 8 According to the implementation method Figure 7 An enlarged cross-sectional view of part of the "EX2" region;

[0016] Figure 9 It is according to the implementation method along Figure 8 Enlarged cross-sectional views of some components in the section intercepted by line Y2-Y2';

[0017] Figure 10 This is a cross-sectional view of a semiconductor memory device according to an embodiment;

[0018] Figures 11 to 14 , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18 , Figure 19A , Figure 19B , Figures 20 to 31 , Figure 32A , Figure 32B , Figure 33A and Figure 33BThis is a diagram of a method for manufacturing a semiconductor memory device according to an embodiment, wherein... Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15A , Figure 16A , Figure 17A , Figure 18 and Figure 19A Each corresponds to the process sequence along the path. Figure 2 A cross-sectional view of a portion of the cross-section intercepted by line X1-X1'. Figure 15B , Figure 16B and Figure 17B Each corresponds to along Figure 2 A cross-sectional view of a portion of the section intercepted by line Y1-Y1'. Figure 19B yes Figure 19A An enlarged cross-sectional view of part of the "EXB" region. Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32A and Figure 33A Each corresponds to the process sequence. Figure 3 An enlarged cross-sectional view of the "EX1" region. Figure 32B and Figure 33B Each corresponds to the process sequence along the path. Figure 2 A cross-sectional view of a portion of the section intercepted by line Y2-Y2'; and

[0019] Figure 34 , Figure 35A , Figure 35B , Figure 36A and Figure 36B This is a diagram of a method for manufacturing a semiconductor memory device according to an embodiment, wherein... Figure 34 , Figure 35A and Figure 36A Each corresponds to the process sequence. Figure 7 An enlarged cross-sectional view of the "EX2" region. Figure 35B and Figure 36B Each corresponds to the process sequence along the path. Figure 2 A cross-sectional view of a portion of the section intercepted by line Y2-Y2'. Detailed Implementation

[0020] In the following, embodiments will be described in detail with reference to the accompanying drawings. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with this disclosure. It will be understood that when an element or layer is referred to as "on" another element or layer, "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to that other element or layer, or there may be an intervening element or layer. In contrast, when an element is referred to as "directly on" another element or layer, "directly connected to," or "directly attached to" another element or layer, there is no intervening element or layer. It will also be understood that even if a step or operation of a manufacturing apparatus or structure is described as being later than another step or operation, that step or operation may be performed later than that other step or operation, unless that other step or operation is described as being performed after that step or operation. In the accompanying drawings, the same reference numerals are used to denote the same elements, and repeated descriptions thereof will be omitted.

[0021] Figure 1 This is a block diagram of a semiconductor memory device 100 according to an embodiment.

[0022] Reference Figure 1 The semiconductor memory device 100 may include a memory cell array 11, a command decoder 12, an address buffer 13, an address decoder 14, a control circuit 15, a sense amplifier 16, and a data input / output (I / O) circuit 17.

[0023] The memory cell array 11 may include multiple memory cells MC. The memory cell array 11 may include multiple word lines WL, multiple bit lines BL, and multiple plate electrodes PL connected to the memory cells MC. The memory cell array 11 may include dynamic random access memory (DRAM) configured to sense the cell voltage Vcell stored as data in the memory cells MC.

[0024] The semiconductor storage device 100 can receive data DQ from an external device and output data DQ to an external device in response to a command CMD and an address ADDR received from an external device (such as a central processing unit (CPU) or a memory controller).

[0025] Each of the plurality of memory cells MC may include a cell transistor CT and a cell capacitor CC. The gate of the cell transistor CT may be connected to the word line WL. The first terminal of the cell transistor CT may be connected to the bit line BL. The second terminal of the cell transistor CT may be connected to the first terminal of the cell capacitor CC. The second terminal of the cell capacitor CC may be connected to the plate electrode PL. The memory cell MC may store a cell voltage Vcell with a specified data amplitude in the cell capacitor CC.

[0026] Command decoder 12 can determine the input command CMD by referring to the chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, and write enable signal / WE applied from an external device. Command decoder 12 can generate control signals corresponding to the command CMD. Command CMD may include activation command, read command, write command, and precharge command.

[0027] Address buffer 13 can receive address ADDR from an external device. Address ADDR may include word line addresses for addressing some of the plurality of word lines WL connected to memory cell array 11, bit line addresses for addressing some of the plurality of bit lines BL connected to memory cell array 11, and board line addresses for addressing some of the plurality of board electrodes PL connected to memory cell array 11. Address buffer 13 may send each of the word line addresses, bit line addresses, and board line addresses to address decoder 14.

[0028] Address decoder 14 may include word line decoder, bit line decoder, and board line decoder, which are respectively configured to select the word line WL, bit line BL, and board electrode PL of the memory cell MC to be accessed in response to the received address ADDR. The word line decoder can decode the word line address and activate the word line WL of the memory cell MC corresponding to the word line address. The bit line decoder can decode the bit line address and provide a bit line select signal BLS for selecting the bit line BL of the memory cell MC corresponding to the bit line address. The board line decoder can decode the board line address and provide a board line select signal PLS for selecting the board electrode PL of the memory cell MC corresponding to the board line address.

[0029] The control circuit 15 can control the sensing amplifier 16 under the control of the command decoder 12. The control circuit 15 can control the operation of the sensing amplifier 16 to detect the cell voltage Vcell of the memory cell MC. The control circuit 15 can control the sensing amplifier 16 to perform pre-charge operation, charge sharing operation, and sensing operation.

[0030] The sensing amplifier 16 can detect the charge stored as data in the storage cell MC. Furthermore, the sensing amplifier 16 can transmit the detected data DQ to the data I / O circuit 17, causing the detected data DQ to be output to the outside of the semiconductor storage device 100.

[0031] The data I / O circuit 17 can receive data DQ to be written to the memory cell MC from the outside and send the data DQ to the memory cell array 11. The data I / O circuit 17 can also output bit data detected by the sense amplifier 16 as read data.

[0032] Figures 2 to 6 This is a diagram of a semiconductor memory device 100 according to an embodiment. More specifically, Figure 2 This is a plan view of the semiconductor memory device 100 according to the embodiment. Figure 3 It is along Figure 2 The cross-sectional view taken by line X1-X1'. Figure 4 yes Figure 3 An enlarged cross-sectional view of part of the "EX1" region. Figure 5 It is along Figure 2 The cross-sectional view taken from line Y1-Y1'. Figure 6 It is along Figure 2 Enlarged cross-sectional views of some components taken from the section along line Y2-Y2'. See below for reference. Figures 2 to 6 The components of the semiconductor memory device 100 described herein may constitute a reference. Figure 1 A portion of the described storage cell array 11.

[0033] Reference Figures 2 to 6 The semiconductor memory device 100 may include a memory cell block CB, which includes a plurality of memory cells arranged repeatedly on the substrate 102 in a first lateral direction (X direction) and a second lateral direction (Y direction) that intersect each other (may be perpendicular to each other) and in a vertical direction (Z direction) perpendicular to the main surface 102M of the substrate 102.

[0034] At each of a plurality of vertical levels starting from substrate 102 in the vertical direction (Z direction), the memory cell block CB may include a plurality of active regions AC repeatedly arranged in a first lateral direction (X direction) and a second lateral direction (Y direction). Figure 3 and Figure 4 As shown, the plurality of active regions AC included in the memory cell block CB may include a plurality of active regions AC arranged on the substrate 102 along a line extending in the vertical direction (Z direction) and overlapping each other in the vertical direction (Z direction). In an embodiment, as Figure 3 and Figure 4As shown, each of the plurality of active regions AC included in the storage cell block CB may have a thickness in the vertical direction (Z direction), which is constant in the first lateral direction (X direction).

[0035] Each of the plurality of active regions AC may include a channel region 106A, a buried contact BC, and a direct contact DC, the buried contact BC and the direct contact DC being spaced apart from each other in a first lateral direction (X direction) with the channel region 106A between them. In each of the plurality of active regions AC, the buried contact BC, the channel region 106A, and the direct contact DC may be arranged sequentially in a straight line extending along the first lateral direction (X direction). In an embodiment, each of the plurality of active regions AC may have a thickness in the vertical direction (Z direction), which is substantially constant in the first lateral direction (X direction). In the plurality of active regions AC, the respective thicknesses of the buried contact BC, the channel region 106A, and the direct contact DC in the vertical direction (Z direction) may be the same or similar to each other. In an embodiment, each of the plurality of active regions AC may include a doped Si layer.

[0036] like Figure 2 , Figure 3 and Figure 4 As shown, at each of a plurality of vertical levels extending from substrate 102 in the vertical direction (Z direction), the memory cell block CB of semiconductor memory device 100 may include a plurality of word lines WL extending longitudinally in a second lateral direction (Y direction) parallel to the main surface 120M of substrate 102. The plurality of word lines WL may be spaced apart from each other in a first lateral direction (X direction), a second lateral direction (Y direction), and a vertical direction (Z direction). Each of the plurality of word lines WL may surround a channel region 106A and extend longitudinally in the second lateral direction (Y direction), the channel region 106A being a local region of a selected active region among the plurality of active regions AC included in the memory cell block CB. Figure 3 As shown, the multiple word lines WL included in the memory cell block CB may include multiple word lines WL arranged on the substrate 102 on lines extending in the vertical direction (Z direction) and overlapping each other in the vertical direction (Z direction).

[0037] In an embodiment, each of the plurality of word lines WL may include a metal, a conductive metal nitride, a metal silicide, doped polysilicon, or a combination thereof. For example, each of the plurality of word lines WL may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), tungsten (W), tungsten nitride (WN), cobalt (Co), aluminum (Al), nickel (Ni), titanium silicide (TiSi), titanium silicon nitride (TiSiN), tungsten silicide (WSi), tungsten silicon nitride (WSiN), tantalum silicide (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), cobalt silicide (CoSi), nickel silicide (NiSi), doped polysilicon, or a combination thereof, but is not limited thereto.

[0038] The gate dielectric film 130 may be located between the channel region 106A of the active region AC and the word line WL. In the first lateral direction (X direction), the width of each of the plurality of gate dielectric films 130 may be greater than the width of each of the plurality of word lines WL. In some embodiments, the gate dielectric film 130 may include a paraelectric material. For example, the gate dielectric film 130 may include silicon oxide, silicon nitride, silicon nitride, or combinations thereof. In other embodiments, the gate dielectric film 130 may include a high-k dielectric material. The high-k dielectric material may have a dielectric constant of about 10 to about 25. For example, the high-k dielectric material may include, but is not limited to, hafnium oxide, aluminum oxide, zirconium oxide, or combinations thereof. For example, each of the plurality of gate dielectric films 130 may include, but is not limited to, HfO2, Al2O3, ZrO2, or combinations thereof. In still other embodiments, the gate dielectric film 130 may include a combination of a paraelectric material and a high-k dielectric material.

[0039] like Figure 3 and Figure 4 As shown, the spaces of the plurality of word lines WL arranged on a line extending in the vertical direction (Z direction) can be filled by an insulating structure 129. The insulating structure 129 may include a silicon oxide film, a silicon nitride film, or a combination thereof.

[0040] like Figures 2 to 4As shown, the memory cell block CB of the semiconductor memory device 100 may include multiple bit lines BL extending longitudinally in the vertical direction (Z direction). On the substrate 102, each of the multiple bit lines BL may pass through the insulating structure 129 and extend longitudinally in the vertical direction (Z direction). Each of the multiple bit lines BL may be connected to one end of each of the multiple active regions AC included in the memory cell block CB that overlap each other in the vertical direction (Z direction). Each of the multiple bit lines BL may be connected to the direct contact DC of a selected active region among the multiple active regions AC.

[0041] In an embodiment, the direct contact DC included in the active region AC may include a doped silicon layer. For example, the direct contact DC may include a silicon layer doped with an n-type dopant. Each of the plurality of bit lines BL may include a metal, a conductive metal nitride, a metal silicide, doped polysilicon, or a combination thereof. For example, each of the plurality of bit lines BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Al, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, doped polysilicon, or a combination thereof, and is not limited thereto. In an embodiment, as Figure 3 As shown, each of the multiple bit lines BL may include a metal silicide film 152, a conductive pad 154, and a conductive plug 156, which are sequentially stacked on the surface of the active region AC that directly contacts DC. When in Figure 3 When viewed in the XY plane, the conductive plug 156 can be surrounded by a conductive pad 154, and both the conductive plug 156 and the conductive pad 154 can be surrounded by a metal silicide film 152. In an embodiment, the metal silicide film 152 may be omitted. In an embodiment, the metal silicide film 152 may include molybdenum silicide or titanium silicide, the conductive pad 154 may include TiN, and the conductive plug 156 may include W, but is not limited thereto.

[0042] like Figure 2 , Figure 3 and Figure 4 As shown, the memory cell block CB of the semiconductor memory device 100 may include a plurality of capacitors CAP respectively connected to the plurality of active regions AC. Each of the plurality of capacitors CAP may include a first electrode 186, a dielectric film 187, and a second electrode 188. The first electrode 186 of the capacitor CAP may be connected to a buried contact BC of a selected active region among the plurality of active regions AC. The dielectric film 187 may cover the surface of the first electrode 186. The second electrode 188 may cover the dielectric film 187 and be spaced apart from the first electrode 186, with the dielectric film 187 between the second electrode 188 and the first electrode 186.

[0043] like Figure 3 and Figure 4 As shown, the first electrode 186 of each of the plurality of capacitors CAP can be connected to the buried contact BC of the active region AC adjacent to it. The first electrode 186 may include an electrode support portion 186N and a main electrode portion 186W. The electrode support portion 186N may be adjacent to the buried contact BC of the active region AC. The main electrode portion 186W may be integrally connected to the electrode support portion 186N and spaced apart from the buried contact BC in a first lateral direction (X direction), with the electrode support portion 186N between them. In the vertical direction (Z direction), the electrode support portion 186N may have a first width VW1, and the main electrode portion 186W may have a second width VW2 greater than the first width VW1.

[0044] In each of the plurality of capacitors CAP, each of the electrode support portion 186N and the main electrode portion 186W of the first electrode 186 may have a cylindrical shape defining an internal space that accommodates a portion of the dielectric film 187. The outer surface of the electrode support portion 186N of the first electrode 186 may be spaced apart from the dielectric film 187, with an insulating film 174 between them. The outer surface of the main electrode portion 186W of the first electrode 186 may be in contact with the dielectric film 187.

[0045] The semiconductor memory device 100 may include an insulating pad 172 surrounding a buried contact BC, a buried insulating film 173 surrounding the insulating pad 172, and an insulating film 174 covering the surface of the buried insulating film 173 facing the dielectric film 187 and the second electrode 188. The insulating film 174 may include a portion contacting the electrode support portion 186N of the first electrode 186 and a portion contacting the buried insulating film 173. A portion of the insulating film 174 may surround the electrode support portion 186N of the first electrode 186. The insulating pad 172 may contact the electrode support portion 186N of the first electrode 186 and the buried contact BC. The insulating pad 172 may cover the sidewall of the word line WL. The portion of the insulating pad 172 surrounding the buried contact BC, the portion of the insulating film 174 surrounding the electrode support portion 186N of the first electrode 186, and the gate dielectric film 130 may be collinear with each other in a first lateral direction (X direction). In an embodiment, each of the insulating pad 172 and the insulating film 174 may include silicon oxide, and the buried insulating film 173 may include silicon nitride, but is not limited thereto.

[0046] The electrode support portion 186N of the first electrode 186 may protrude further than the dielectric film 187 toward the buried contact BC of the active region AC in the first lateral direction (X direction). The electrode support portion 186N of the first electrode 186 and the buried contact BC of the active region AC may be surrounded by an insulating pad 172.

[0047] A metal silicide film 184 may be located between the electrode support portion 186N of the first electrode 186 and the buried contact BC of the active region AC. The metal silicide film 184 may contact each of the electrode support portion 186N and the buried contact BC. The metal silicide film 184 may be surrounded by an insulating pad 172 together with the electrode support portion 186N and the buried contact BC. The metal silicide film 184 may include, but is not limited to, titanium silicide, tantalum silicide, cobalt silicide, molybdenum silicide, or tungsten silicide. The first electrode 186 of the capacitor CAP may be electrically connected to the buried contact BC of the active region AC via the metal silicide film 184. In an embodiment, the metal silicide film 184 may be omitted. In this case, the electrode support portion 186N included in the first electrode 186 of the capacitor CAP may contact the buried contact BC of the active region AC. The second electrode 188 of the capacitor CAP may be spaced apart from the active region AC and cover the surface of the first electrode 186.

[0048] like Figure 2 As shown, in the top view, the plurality of capacitors CAP can be adjacent to and arranged on a line extending along a second lateral direction (Y direction) of the plurality of word lines WL and the plurality of active regions AC. As used herein, the top view represents a view from the XY plane. In the top view, each of the plurality of active regions AC can be located in the first lateral direction (X direction) between each of its adjacent bit lines BL and capacitors CAP. Figure 2 and Figure 3 As shown, the multiple bit lines BL can be spaced apart from the multiple capacitors CAP in the first lateral direction (X direction), and the multiple word lines WL are between them.

[0049] In each of the plurality of capacitors CAP, the electrode support portion 186N and the main electrode portion 186W of the first electrode 186 may be integrally connected to each other and comprise the same material. In each of the plurality of capacitors CAP, the electrode support portion 186N and the main electrode portion 186W in the first electrode 186 and each of the second electrodes 188 may comprise a metal film, a conductive metal oxide film, a conductive metal nitride film, a conductive metal nitride film, or a combination thereof. In embodiments, each of the first electrode 186 and the second electrode 188 may include molybdenum (Mo), tungsten (W), ruthenium (Ru), platinum (Pt), iridium (Ir), cobalt (Co), tin (Sn), titanium (Ti), Ti nitride, Ti oxide, Ti oxide, niobium (Nb), Nb nitride, Nb oxide, Nb oxide, tungsten (W) nitride, vanadium (V) nitride, V oxide, molybdenum (Mo) nitride, Mo oxide, ruthenium (Ru) oxide, strontium-ruthenium (SrRu) oxide, cobalt (Co) nitride, Co oxide, Co oxide, tin (Sn) nitride, Sn oxide, Sn oxide, or combinations thereof. For example, each of the first electrode 186 and the second electrode 188 may include titanium nitride (TiN), niobium nitride (NbN), cobalt nitride (CoN), tin oxide (SnO2), or combinations thereof. In other embodiments, each of the first electrode 186 and the second electrode 188 may include tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), vanadium (V), vanadium nitride (VN), molybdenum (Mo), molybdenum nitride (MoN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), strontium ruthenium oxide (SrRuO3, SRO), iridium (Ir), iridium oxide (IrO2), platinum (Pt), platinum oxide (PtO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), (La,Sr)CoO3 (LSCo), or combinations thereof. However, the constituent materials of each of the first electrode 186 and the second electrode 188 are not limited to the examples described above.

[0050] The dielectric film 187 may comprise a silicon oxide film, a high-k dielectric film, or a combination thereof. In embodiments, the dielectric film 187 may comprise a metal oxide, which includes at least one metal selected from hafnium (Hf), zirconium (Zr), aluminum (Al), niobium (Nb), cerium (Ce), lanthanum (La), tantalum (Ta), and titanium (Ti). In embodiments, the dielectric film 187 may have a single film structure comprising a high-k dielectric film. In other embodiments, the dielectric film 187 may have a multilayer structure comprising a plurality of high-k dielectric films sequentially stacked on the first electrode 186. The high-k dielectric film may comprise, but is not limited to, HfO2 films, ZrO2 films, Al2O3 films, Y2O3 films, Sc2O3 films, La2O3 films, Ta2O5 films, Nb2O5 films, CeO2 films, TiO2 films, GeO2 films, SrTiO3 films, BaSrTiO3 films, or combinations thereof. In other embodiments, the dielectric film 187 may comprise an oxide of at least one metal selected from Ti, Nb, Ta, Sn, and Mo, or a nitride of at least one metal selected from Ti, Nb, Ta, Sn, and Mo. For example, the dielectric film 187 may comprise Ti oxide, Ti nitride, Nb oxide, Nb nitride, Ta oxide, Ta nitride, Sn oxide, Sn nitride, Mo oxide, Mo nitride, or combinations thereof. In still other embodiments, the dielectric film 187 may comprise a ferroelectric film comprising at least one oxide selected from hafnium (Hf), silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), and strontium (Sr). The ferroelectric film may comprise a hafnium-based oxide, such as hafnium oxide (HfO), zirconium hafnium oxide (HZO), hafnium titanium oxide, or hafnium silicon oxide. The ferroelectric film may further comprise dopants as needed. The dopant may include, but is not limited to, at least one element selected from silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), scandium (Sc), strontium (Sr), magnesium (Mg), and barium (Ba).

[0051] In each of the plurality of capacitors CAP, a dielectric film 187 may cover both the inner and outer surfaces of the main electrode portion 186W of the first electrode 186. Each of the inner and outer surfaces of the main electrode portion 186W may be in contact with the dielectric film 187. The dielectric film 187 may cover the inner surface of the electrode support portion 186N of the first electrode 186, but not the outer surface. The inner surface of the electrode support portion 186N may be in contact with the dielectric film 187, and the outer surface of the electrode support portion 186N may be in contact with the insulating pad 172. The outer surface of the electrode support portion 186N may be spaced apart from the dielectric film 187, with an insulating film 174 positioned between them.

[0052] The electrode support portion 186N of the first electrode 186 can be aligned and collinear with the buried contact BC, the channel region 106A, and the direct contact DC included in the active region AC in the first lateral direction (X direction). In the vertical direction (Z direction), the first width VW1 of the electrode support portion 186N can be substantially equal to the third width VW3 of the active region AC.

[0053] The gate dielectric film 130 may be located between the channel region 106A and the word line WL of the active region AC, and may surround the channel region 106A. The first width VW1 of the electrode support portion 186N of the first electrode 186 may be less than the fourth width VW4, which is the maximum width of the gate dielectric film 130 in the vertical direction (Z direction). The fourth width VW4 may be defined by the outer surface of the gate dielectric film 130.

[0054] like Figure 6 As shown, when viewed in the YZ plane, the cross-section of the main electrode portion 186W of the first electrode 186 can have a quadrilateral closed-loop shape with rounded corners. The dielectric film 187 can contact each of the inner and outer surfaces of the main electrode portion 186W of the first electrode 186. A portion of the second electrode 188 can fill the portion of the first electrode 186 defined by the dielectric film 187 within the internal space of the first electrode 186, and another portion of the second electrode 188 can cover the outer surface of the first electrode 186 with the dielectric film 187 between them.

[0055] like Figure 2 and Figure 3 As shown, the memory cell block CB of the semiconductor memory device 100 may further include a plate electrode 190. The plate electrode 190 may correspond to a reference. Figure 1 The plate electrode PL is described. (e.g.) Figure 3As shown, the plate electrode 190 may include a central portion 190A and a plurality of finger portions 190B. The central portion 190A may extend longitudinally in a vertical direction (Z direction) on the substrate 102. The plurality of finger portions 190B may protrude from the central portion 190A in a first lateral direction (X direction). Each of the plurality of finger portions 190B of the plate electrode 190 may overlap with the main electrode portion 186W of the first electrode 186 of the capacitor CAP in the vertical direction (Z direction). The plurality of finger portions 190B of the plate electrode 190 may not overlap with the electrode support portion 186N of the first electrode 186 of the capacitor CAP in the vertical direction (Z direction). The plurality of finger portions 190B of the plate electrode 190 may be spaced apart from the main electrode portion 186W of the first electrode 186 in the vertical direction (Z direction), with the dielectric film 187 and the second electrode 188 of the capacitor CAP located between them. Multiple capacitors CAP located on both sides of a plate electrode 190 in the first lateral direction (X direction) can share the single plate electrode 190. The plate electrode 190 may include a metal film, a conductive metal oxide film, a conductive metal nitride film, a conductive metal nitride film, a semiconductor film, or a combination thereof. In embodiments, the plate electrode 190 may include Ti, Ti nitride, Ti oxide, Ti nitride, Nb, Nb nitride, Nb oxide, Nb nitride, Co, Co nitride, Co oxide, Co nitride, Sn, Sn nitride, Sn oxide, Sn nitride, silicon germanium (SiGe), or a combination thereof. For example, plate electrode 190 may include, but is not limited to, titanium nitride (TiN), niobium nitride (NbN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), vanadium (V), vanadium nitride (VN), molybdenum (Mo), molybdenum nitride (MoN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), platinum (Pt), silicon germanium (SiGe), or combinations thereof.

[0056] Figures 7 to 9 This is a diagram of a semiconductor memory device 200 according to an embodiment. More specifically, Figure 7 This is a cross-sectional view of a portion of the semiconductor memory device 200, corresponding to the view along... Figure 2 The cross section intercepted by line X1-X1'. Figure 8 yes Figure 7 An enlarged cross-sectional view of part of the "EX2" region. Figure 9 It is along Figure 8 Enlarged cross-sectional views of some components taken from the section along line Y2-Y2'. See below for reference. Figures 7 to 9 The components of the semiconductor memory device 200 described can form a reference. Figure 1 This is a portion of the described storage cell array 11. Figures 7 to 9In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 2 to 6 Since the same elements are used in the same way, repeated descriptions of them are omitted.

[0057] Reference Figures 7 to 9 The memory cell block CB2 of the semiconductor memory device 200 can have the same characteristics as the one already referenced. Figures 2 to 6 The memory cell block CB of the described semiconductor memory device 100 has a substantially identical configuration. However, the memory cell block CB2 of the semiconductor memory device 200 may include a plurality of capacitors CAP2 respectively connected to a plurality of active regions AC. Each of the plurality of capacitors CAP2 may include a first electrode 286, a dielectric film 287, and a second electrode 288. The first electrode 286 of the capacitor CAP2 may be connected to a buried contact BC of a selected active region among the plurality of active regions AC. The first electrode 286, dielectric film 287, and second electrode 288 of each of the plurality of capacitors CAP2 may each have substantially the same configuration as those already referenced. Figures 2 to 4 The first electrode 186, dielectric film 187, and second electrode 188 are described with the same configuration. However, the first electrode 286 of each of the plurality of capacitors CAP2 may include an electrode support portion 286N and a main electrode portion 286W. The electrode support portion 286N may be adjacent to the buried contact BC of the active region AC. The main electrode portion 286W may be integrally connected to the electrode support portion 286N and spaced apart from the buried contact BC in a first lateral direction (X direction), with the electrode support portion 286N between them. In the vertical direction (Z direction), the electrode support portion 286N may have a first width VW21, and the main electrode portion 286W may have a second width VW22 greater than the first width VW21.

[0058] In each of the plurality of capacitors CAP2, each of the electrode support portion 286N and the main electrode portion 286W of the first electrode 286 may have an internally filled column shape. The outer surface of the electrode support portion 286N of the first electrode 286 may be spaced apart from the dielectric film 287 with the insulating film 174 between them, and the outer surface of the main electrode portion 286W of the first electrode 286 may be in contact with the dielectric film 287.

[0059] like Figure 9 As shown, when viewed in the YZ plane, the cross-section of the first electrode 286 can have a quadrilateral shape with rounded corners. The dielectric film 287 can contact the outer surface of the first electrode 286. The second electrode 288 can cover the outer surface of the first electrode 286, with the dielectric film 287 positioned between them.

[0060] Figure 10 This is a cross-sectional view of the semiconductor memory device 300 according to the embodiment. Figure 10The diagram shows a cross-sectional configuration of a portion of the semiconductor memory device 300, corresponding to the section along... Figure 2 The cross section intercepted by line X1-X1'. See below for reference. Figure 10 The components of the semiconductor memory device 300 described can form a reference. Figure 1 This is a portion of the described storage cell array 11. Figure 10 In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 2 to 6 Since the same elements are used in the same way, repeated descriptions of them are omitted.

[0061] Reference Figure 10 The memory cell block CB3 of the semiconductor memory device 300 can substantially have the same characteristics as those already referenced. Figures 2 to 6 The semiconductor memory device 100 described has the same configuration as the memory cell block CB. However, the memory cell block CB3 of the semiconductor memory device 300 may include a plurality of capacitors CAP3 respectively connected to a plurality of active regions AC. Each of the plurality of capacitors CAP3 may include a first electrode 386, a dielectric film 187, and a second electrode 188. The first electrode 386 of the capacitor CAP3 may be connected to a buried contact BC of a selected active region among the plurality of active regions AC. The first electrode 386 of each of the plurality of capacitors CAP3 may have substantially the same configuration as the referenced... Figures 2 to 4 The first electrode 186 described has the same configuration. However, the first electrode 386 of each of the plurality of capacitors CAP3 may include an electrode support portion 386N and a main electrode portion 386W. The electrode support portion 386N may be adjacent to the buried contact BC of the active region AC. The main electrode portion 386W may be integrally connected to the electrode support portion 386N and spaced apart from the buried contact BC in a first lateral direction (X direction), with the electrode support portion 386N between them. In the vertical direction (Z direction), the electrode support portion 386N may have a first width VW31, and the main electrode portion 386W may have a second width VW32 greater than the first width VW31.

[0062] In each of the plurality of capacitors CAP3, the electrode support portion 386N of the first electrode 386 may have an internally filled cylindrical shape, and the main electrode portion 386W of the first electrode 386 may have a cylindrical shape defining an internal space that accommodates a portion of the dielectric film 187 and a portion of the second electrode 188. The outer surface of the electrode support portion 386N of the first electrode 386 may be spaced apart from the dielectric film 187 with an insulating film 174 between them, and the outer surface of the main electrode portion 386W of the first electrode 386 may be in contact with the dielectric film 187.

[0063] In reference Figures 1 to 10In the described semiconductor memory devices 100, 200, and 300, the first electrodes 186, 286, and 386 of capacitors CAP, CAP2, and CAP3 may each include electrode support portions 186N, 286N, and 386N, and main electrode portions 186W, 286W, and 386W. The electrode support portions 186N, 286N, and 386N may each be connected to a buried contact BC of the active region AC and have a first width VW1 in the vertical direction (Z direction). The main electrode portions 186W, 286W, and 386W may each be integrally connected to the electrode support portions 186N, 286N, and 386N, and each may be spaced apart from the buried contact BC in a first lateral direction (X direction), with the electrode support portions 186N, 286N, and 386N located between them. The main electrode portions 186W, 286W, and 386W may each have a second width VW2 in the vertical direction (Z direction) that is greater than the first width VW1. The electrode support portions 186N, 286N, and 386N of the first electrodes 186, 286, and 386 can each have a structure surrounded by an insulating pad 172 together with the buried contact BC of the active region AC. Therefore, the positions of the electrode support portions 186N, 286N, and 386N, which are portions of the first electrodes 186, 286, and 386 respectively, can each be fixed by the insulating pad 172. Therefore, even when the lengths of the first electrodes 186, 286, and 386 in the first lateral direction (X direction) of capacitors CAP, CAP2, and CAP3 are increased to improve capacitance, undesirable deformations (such as tilting, bending, or collapse of the first electrodes 186, 286, and 386) and defects caused by undesirable deformations can be prevented during the manufacture of semiconductor memory devices 100, 200, and 300. Therefore, the semiconductor memory devices 100, 200, and 300 according to the embodiments can maximize the capacitance of capacitors CAP, CAP2, and CAP3 within a limited area. Furthermore, the semiconductor memory devices 100, 200, and 300 according to the embodiments can have improved performance without inefficiently increasing the area occupied by the plurality of memory cells in the memory cell blocks CB, CB2, and CB3, and provide a structure that is conducive to high integration.

[0064] Figures 11 to 33B This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment. More specifically, Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15A , Figure 16A , Figure 17A , Figure 18 and Figure 19A Each corresponds to the process sequence along the path. Figure 2 A cross-sectional view of a portion of the section intercepted by line X1-X1'. Figure 15B , Figure 16B and Figure 17B Each corresponds to along Figure 2 A cross-sectional view of a portion of the section intercepted by line Y1-Y1'. Figure 19B yes Figure 19A An enlarged cross-sectional view of part of the "EXB" region. Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32A and Figure 33A Each corresponds to the process sequence. Figure 3 A magnified cross-sectional view of the "EX1" region. Figure 32B and Figure 33B Each corresponds to the process sequence along the path. Figure 2 A cross-sectional view of a portion of the section intercepted by line Y2-Y2'. (Refer to...) Figures 11 to 33B Description of manufacturing reference Figures 2 to 6 An example of a method for describing a semiconductor memory device 100. Figures 11 to 36B In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 2 to 6 Since the same elements are used in the same way, repeated descriptions of them are omitted.

[0065] Reference Figure 11 Multiple sacrificial layers 104 and multiple active layers 106 may be stacked alternately one after another on the main surface 102M of the substrate 102 in the vertical direction (Z direction). In an embodiment, each of the multiple sacrificial layers 104 and the multiple active layers 106 may each comprise a semiconductor material. In an embodiment, each of the multiple sacrificial layers 104 may comprise an undoped SiGe layer or a SiGe layer doped with carbon (C) atoms, and each of the multiple active layers 106 may comprise a Si layer. In the vertical direction (Z direction), the thickness T1 of each of the multiple active layers 106 may be less than the thickness T2 of each of the multiple sacrificial layers 104. In an embodiment, the thickness T2 of each of the multiple sacrificial layers 104 may be at least three times the thickness T1 of each of the multiple active layers 106, but is not limited thereto.

[0066] Reference Figure 12A silicon oxide film 108 and a silicon nitride film 109 can be sequentially formed on a stacked structure including the plurality of sacrificial layers 104 and the plurality of active layers 106, and a mask pattern MP1 can be formed on the silicon nitride film 109. The mask pattern MP1 may include a plurality of first openings OP1. In an embodiment, the mask pattern MP1 may include a photoresist pattern, and the plurality of first openings OP1 may correspond to openings in the photoresist pattern, but are not limited thereto. Subsequently, by using the mask pattern MP1 as an etching mask, the silicon nitride film 109 and the silicon oxide film 108 can be sequentially etched through the plurality of first openings OP1. Subsequently, the stacked structure including the plurality of sacrificial layers 104 and the plurality of active layers 106 can be etched, thus forming a plurality of holes H1 in the stacked structure to expose the substrate 102.

[0067] A portion of the plurality of sacrificial layers 104 can be removed through the plurality of first openings OP1 and the plurality of holes H1. As a result, the plurality of active layers 106 can protrude in a first lateral direction (X direction) between the remaining portions of the plurality of sacrificial layers 104.

[0068] Reference Figure 13 ,exist Figure 12 In the resulting structure, a first insulating pad 121 may be formed to conformally cover the surfaces exposed through the plurality of holes H1, and a second insulating pad 122 may be formed to conformally cover the first insulating pad 121. A buried insulating film 123 may be formed to fill the remaining space defined by the second insulating pad 122 in the plurality of holes H1. In an embodiment, the first insulating pad 121 may comprise silicon oxide, the second insulating pad 122 may comprise silicon nitride, and the buried insulating film 123 may comprise silicon oxide.

[0069] The mask pattern MP1, silicon nitride film 109, and silicon oxide film 108 can be removed using a chemical mechanical polishing (CMP) process. This results in a flat top surface where the active layers 106 located at the vertical level furthest from the substrate 102 are exposed. Subsequently, silicon oxide film 108A and silicon nitride film 109A can be formed on the resulting structure.

[0070] Reference Figure 14 A mask pattern MP2 can be formed on the silicon nitride film 109A. The mask pattern MP2 may include a second opening OP2. The second opening OP2 may be located at the junction of the silicon nitride film 109A and the silicon nitride film 109A. Figure 12The positions of the plurality of first openings OP1 in the mask pattern MP1 shown are offset in the first lateral direction (X direction). In an embodiment, the mask pattern MP2 may include a photoresist pattern, and the second opening OP2 may correspond to an opening in the photoresist pattern, but is not limited thereto.

[0071] By using the mask pattern MP2 as an etching mask, the stacked structure including the plurality of sacrificial layers 104 and the plurality of active layers 106 can be etched through the second opening OP2. Therefore, a hole H2 can be formed in the stacked structure to expose the substrate 102.

[0072] Reference Figure 15A and Figure 15B ,exist Figure 14 In the resulting structure, the plurality of sacrificial layers 104 exposed through the plurality of holes H2 can be removed. During the removal of the plurality of sacrificial layers 104, corresponding portions of the plurality of active layers 106 may be consumed. Thereafter, a third insulating pad 125 and a fourth insulating pad 126 can be formed to conformally cover the plurality of holes (see reference 102). Figure 14 The surfaces of the plurality of active layers 106 exposed at H2. A buried insulating film 127 may be formed to fill the remaining space defined by the fourth insulating pad 126 of the plurality of holes H2. In an embodiment, the third insulating pad 125 may comprise silicon oxide, the fourth insulating pad 126 may comprise silicon nitride, and the buried insulating film 127 may comprise silicon oxide. The mask pattern MP2 may be removed using a CMP process to expose the top surface of the silicon nitride film 109A.

[0073] Reference Figure 16A and Figure 16B You can refer to it after it has been executed. Figure 15A and Figure 15B The described process forms a mask pattern MP3 on the resulting structure. The mask pattern MP3 may include a plurality of third openings OP3. The mask pattern MP3 may include a photoresist pattern, and the plurality of third openings OP2 may correspond to openings in the photoresist pattern, but are not limited thereto.

[0074] Subsequently, using the mask pattern MP3 as an etching mask, the silicon nitride film 109A and the silicon oxide film 108A can be etched sequentially through the plurality of third openings OP3. Then, the buried insulating film 123, the second insulating pad 122 and the first insulating pad 121 can be removed sequentially to form a plurality of holes H3 exposing the plurality of active layers 106 and the substrate 102.

[0075] Reference Figure 17A and Figure 17B It can be seen from Figure 16A and Figure 16BThe resulting structure removes the mask pattern MP3 to expose the top surface of the silicon nitride film 109A. Next, a gate dielectric film 130 can be formed to conformally cover the surfaces exposed by the plurality of holes H3, a conductive layer can be formed to cover the surface of the gate dielectric film 130, and a protective pattern can be formed to cover desired portions of the conductive layer. Subsequently, by using the protective pattern as an etching mask, the exposed portions of the conductive layer can be selectively removed, thus forming a plurality of conductive patterns WLMs for forming multiple word lines. The remaining space of the plurality of holes H3 exposing the plurality of conductive patterns WLMs can then be filled by an insulating structure 129. The insulating structure 129 may include a silicon oxide film, a silicon nitride film, or a combination thereof. In an embodiment, the insulating structure 129 may include silicon oxide pads, silicon nitride pads, and a silicon oxide film stacked sequentially on the surface of the gate dielectric film 130 and the surface of the plurality of conductive patterns WLMs for filling. The top surface of the silicon nitride film 109A may be exposed around the insulating structure 129.

[0076] Reference Figure 18 After it has been implemented with reference Figure 17A and Figure 17B In the structure obtained by the described process, multiple bit lines BL can be formed to pass through a portion of the insulating structure 129 in the vertical direction (Z direction). Each of the multiple bit lines BL can be formed to contact multiple active layers 106 arranged on the line extending in the vertical direction (Z direction). To form the multiple bit lines BL, multiple vertical vias can be formed to pass through a portion of the insulating structure 129 in the vertical direction (Z direction). The multiple active layers 106 arranged on the line extending in the vertical direction (Z direction) can be exposed through the multiple vertical vias. A dopant can be doped into each of the multiple active layers 106 exposed through the multiple vertical vias to form a direct contact DC. Subsequently, a metal silicide film 152, a conductive pad 154, and a conductive plug 156 can be sequentially formed within the multiple vertical vias. The dopant can include p-type or n-type impurity ions. For example, the dopant can include boron (B), phosphorus (P), or arsenic (As), but is not limited thereto. The silicon nitride film 109A and the silicon oxide film 108A can be removed using a CMP process. Subsequently, a flat top surface can be formed, on which the plurality of active layers 106 located at the vertical level furthest from the substrate 102 are exposed.

[0077] Reference Figure 19A and Figure 19B It can form a mask pattern 160 to cover the reference that has already been applied to it. Figure 18 The structure obtained from the described process. Mask pattern 160 may include a fourth opening OP4. In the view from above, the position of the fourth opening OP4 may be... Figure 14 The second opening OP2 shown is in the same or similar position. The mask pattern 160 may include a silicon nitride film, and the fourth opening OP4 may correspond to an opening in the silicon nitride film.

[0078] Buried insulating film 127, fourth insulating pad 126 and third insulating pad 125 (refer to) Figure 18 The exposed portions of the multiple active layers 106, multiple gate dielectric films 130, and substrate 102 can be removed through the fourth opening OP4. Therefore, a hole H4 can be formed exposing these multiple active layers 106, multiple gate dielectric films 130, and substrate 102. Subsequently, the exposed portions of the multiple gate dielectric films 130 can be partially removed through the hole H4 to expose the multiple conductive patterns WLM. The exposed portions of the multiple conductive patterns WLM can be etched to form multiple word lines WL from the multiple conductive patterns WLM. As a result, as... Figure 19B As shown in the enlarged view, the insulating structure 129 can be exposed inside the hole H4 around the word line WL surrounding the active layer 106.

[0079] Reference Figure 20 An insulating pad 172 can be formed to conformally cover the surfaces of each of the plurality of word lines WL, the plurality of gate dielectric films 130, and the insulating structure 129 exposed within the aperture H4. Subsequently, a buried insulating film 173 can be formed on the insulating pad 172 to partially fill the corresponding spaces between the plurality of active layers 106. The buried insulating film 173 can be formed to surround a portion of each of the plurality of active layers 106, with the insulating pad 172 positioned between them. Portions of the plurality of active layers 106 and portions of the insulating pad 172 covering the plurality of active layers 106 can protrude beyond the sidewalls of the buried insulating film 173 within the aperture H4 in a first lateral direction (X direction).

[0080] Reference Figure 21 ,exist Figure 20 In the resulting structure, the portion of the insulating liner 172 exposed inside the hole H4 can be removed to expose a portion of each of the plurality of active layers 106.

[0081] Reference Figure 22 ,exist Figure 21 In the resulting structure, an insulating film 174 can be formed to conformally cover each of the exposed surfaces of the plurality of active layers 106, the exposed surface of the insulating pad 172, and the exposed surface of the buried insulating film 173 among the surfaces exposed by the aperture H4. In an embodiment, the insulating film 174 may comprise a silicon oxide film.

[0082] Reference Figure 23 ,exist Figure 22 On the resulting structure, a first silicon nitride liner 175A can be formed to conformally cover the insulating film 174.

[0083] Reference Figure 24 ,exist Figure 23 A silicon oxide film can be formed in the resulting structure to fill the pore H4, and a portion of the silicon oxide film can be removed to form a silicon oxide pattern 176 that exposes a portion of the first silicon nitride liner 175A.

[0084] Reference Figure 25 ,exist Figure 24 In the resulting structure, a silicon nitride plug 175P can be formed to fill the hole H4.

[0085] Reference Figure 26 It can be seen from Figure 25 The resulting structure removes a portion of the silicon nitride plug 175P. Therefore, a second silicon nitride liner 175B can be formed including the remaining portion of the silicon nitride plug 175P, and a portion of the first silicon nitride liner 175A can be exposed within the orifice H4 through the second silicon nitride liner 175B. The exposed first silicon nitride liner 175A can be removed. The remaining first silicon nitride liner 175A and second silicon nitride liner 175B can form a silicon nitride liner structure 175 surrounding the silicon oxide pattern 176.

[0086] Reference Figure 27 ,exist Figure 26 In the resulting structure, a portion of the insulating film 174 can be removed through the aperture H4, thus allowing space SP to be formed around the plurality of active layers 106. This portion of the insulating film 174 can be removed using a wet etching process or an isotropic dry etching process. During the removal of the insulating film 174, the amount of insulating film 174 removed can be controlled such that a portion of the insulating film 174 remains between the active layer 106 and the first silicon nitride pad 175A.

[0087] Reference Figure 28 It can be referenced from what has already been executed. Figure 27 The structure obtained by the described process removes a portion of each of the plurality of active layers 106 exposed through the aperture H4. Therefore, a plurality of electrode spaces EP can be formed adjacent to the plurality of active layers 106, the width of which in the vertical direction (Z direction) is defined by the first silicon nitride pad 175A, the insulating film 174, and the insulating pad 172. By incorporating dopant into the plurality of active layers 106 via the aperture H4 and the plurality of electrode spaces EP, buried contacts BC can be formed in each of the plurality of active layers 106, thus forming the plurality of active regions AC. In embodiments, the dopant may include p-type or n-type impurity ions. For example, the dopant may include boron (B), phosphorus (P), or arsenic (As), but is not limited thereto.

[0088] The width of each of the plurality of electrode spaces EP defined by the insulating film 174 and the insulating pad 172 in the vertical direction (Z direction) may be smaller than the width of each of the plurality of electrode spaces EP defined by the first silicon nitride pad 175A in the vertical direction (Z direction).

[0089] Reference Figure 29 A metal silicide film 184 can be formed on the surface of each of the plurality of active regions AC exposed in the plurality of electrode spaces EP. In an embodiment, the formation of the metal silicide film 184 may include forming a metal-silicon composite layer by vapor deposition of metal and silicon on the surface of each of the plurality of active regions AC and silicide formation of the metal-silicon composite layer by using a thermal annealing process or an annealing process.

[0090] Reference Figure 30 A conductive layer 186L can be formed to conformally cover the surfaces exposed by the aperture H4 and the plurality of electrode spaces EP. The material constituting the conductive layer 186L can be the same as the material constituting the first electrode 186 already described above.

[0091] Reference Figure 31 The portion of the conductive layer 186L outside the plurality of electrode spaces EP can be removed to form a plurality of first electrodes 186. Each of the plurality of first electrodes 186 may include an electrode support portion 186N and a main electrode portion 186W. The electrode support portion 186N may be adjacent to the buried contact BC of the active region AC. The main electrode portion 186W may be integrally connected to the electrode support portion 186N and spaced apart from the buried contact BC in a first lateral direction (X direction), with the electrode support portion 186N between them.

[0092] Reference Figure 32A and Figure 32B It can be referenced from what has already been executed. Figure 31 The described process results in a structure that removes the silicon nitride pad structure 175 and the silicon oxide pattern 176. Therefore, the outer surface of the main electrode portion 186W of each of the plurality of first electrodes 186 can be exposed.

[0093] Reference Figure 33A and Figure 33B ,exist Figure 32A and Figure 32B In the resulting structure, a dielectric film 187 can be formed to conformally cover the exposed surface of the main electrode portion 186W of each of the plurality of first electrodes 186 and the exposed surface of the insulating film 174.

[0094] After that, as Figures 2 to 4 As shown, a second electrode 188 covering a dielectric film 187 and a plate electrode 190 can be formed sequentially, thus enabling the fabrication of... Figures 2 to 6 The semiconductor memory device 100 shown.

[0095] Figures 34 to 36B This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment. More specifically, Figure 34 , Figure 35A and Figure 36A Each corresponds to the process sequence. Figure 7 An enlarged cross-sectional view of the area "EX2". Figure 35B and Figure 36B Each corresponds to the process sequence along the path. Figure 2 A cross-sectional view of a portion of the section intercepted by line Y2-Y2'. (Refer to...) Figures 34 to 36B The manufacturing process has been described in reference to Figures 7 to 9 An example of a method for describing a semiconductor memory device 200. Figures 34 to 36B In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 2 to 9 Since the same elements are used in the same way, repeated descriptions of them are omitted.

[0096] Reference Figure 34 , can execute reference Figures 11 to 29 The described process. Subsequently, in Figure 29 In the resulting structure, a first electrode 286 can be formed to fill each of the plurality of electrode spaces EP. The first electrode 286 may include an electrode support portion 286N and a main electrode portion 286W. The electrode support portion 286N may be adjacent to the buried contact BC of the active region AC. The main electrode portion 286W may be integrally connected to the electrode support portion 286N and spaced apart from the buried contact BC in a first lateral direction (X direction), with the electrode support portion 286N between them.

[0097] Reference Figure 35A and Figure 35B It can be referenced from what has already been executed. Figure 34 The described process results in a structure that removes the silicon nitride pad structure 175 and the silicon oxide pattern 176. Therefore, the outer surface of each of the plurality of first electrodes 286 can be exposed.

[0098] Reference Figure 36A and Figure 36B ,exist Figure 35A and Figure 35B In the resulting structure, a dielectric film 287 can be formed to conformally cover the exposed surface of each of the plurality of first electrodes 286 and the exposed surface of the insulating film 174.

[0099] After that, as Figure 7 and Figure 8 As shown, a second electrode 288 covering a dielectric film 287 and a plate electrode 190 can be formed sequentially, thus enabling the fabrication of... Figures 7 to 9 The semiconductor memory device 200 shown.

[0100] In order to manufacture Figure 10 The semiconductor memory device 300 shown can perform the same operation as the referenced one. Figures 11 to 33B The described process is similar to that of a conventional process. However, in reference... Figure 30 and Figure 31 In the described process, a plurality of first electrodes 386 may be formed in place of the plurality of first electrodes 186. Each of the plurality of first electrodes 386 may be formed including an electrode support portion 386N and a main electrode portion 386W. The electrode support portion 386N may be adjacent to the buried contact BC of the active region AC. The main electrode portion 386W may be integrally connected to the electrode support portion 386N and spaced apart from the buried contact BC in a first lateral direction (X direction), with the electrode support portion 386N between them. To form the plurality of first electrodes 386, in reference to Figure 30 During the formation of the conductive layer 186L, the portion of the electrode space EP defined by the insulating film 174 and the insulating pad 172 can be completely filled by the conductive layer 186L to obtain an electrode support portion 386N with a column shape. The conductive layer 186L can conformally cover the exposed surface in the portion of the electrode space EP defined by the first silicon nitride pad 175A to obtain a main electrode portion 386W with a cylindrical shape.

[0101] Subsequently, a reference operation can be performed on the obtained structure. Figures 32A to 36B The described process allows for the manufacture of... Figure 10 The semiconductor memory device 300 shown.

[0102] Although it has been referenced Figures 11 to 36B Describes manufacturing Figures 2 to 10 The methods of the semiconductor memory devices 100, 200, and 300 shown are illustrated, but it will be understood that within the scope of this disclosure, methods can be applied by referring to... Figures 11 to 36B The described process is modified and altered in various ways to manufacture it. Figures 2 to 10 Semiconductor memory devices 100, 200, and 300, as well as semiconductor memory devices with various modified structures, are shown.

[0103] Although various aspects of the embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0104] This application claims priority to Korean Patent Application No. 10-2024-0126175, filed on September 13, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: An active region is spaced apart from the substrate in a vertical direction and extends in a first lateral direction. The active region includes a buried contact, a channel region and a direct contact provided sequentially in the first lateral direction, wherein the first lateral direction is parallel to the main surface of the substrate. The word line extends around the channel region of the active region in a second lateral direction, wherein the second lateral direction is parallel to the main surface of the substrate and intersects the first lateral direction. A capacitor includes a first electrode, the first electrode including an electrode support portion and a main electrode portion, the electrode support portion being connected to the buried contact of the active region and having a first width in the vertical direction, the main electrode portion being integrally connected to the electrode support portion and spaced apart from the buried contact in the first lateral direction, the electrode support portion being between the main electrode portion and the buried contact, and the main electrode portion having a second width in the vertical direction greater than the first width; as well as An insulating pad surrounds the buried contact and the electrode support portion of the first electrode.

2. The semiconductor memory device of claim 1, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. Each of the electrode support portion and the main electrode portion of the first electrode has a cylindrical shape that defines an internal space for accommodating a portion of the dielectric film. The outer surface of the electrode support portion of the first electrode is spaced apart from the dielectric film, and an insulating film is located between the outer surface of the electrode support portion and the dielectric film. The outer surface of the main electrode portion of the first electrode is in contact with the dielectric film.

3. The semiconductor memory device of claim 1, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. Each of the electrode support portion and the main electrode portion of the first electrode has an internally filled column shape. The outer surface of the electrode support portion of the first electrode is spaced apart from the dielectric film, and an insulating film is located between the outer surface of the electrode support portion and the dielectric film. The outer surface of the main electrode portion of the first electrode is in contact with the dielectric film.

4. The semiconductor memory device of claim 1, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. The electrode support portion of the first electrode has an internally filled column shape. The main electrode portion of the first electrode has a cylindrical shape that defines an internal space accommodating a portion of the dielectric film and a portion of the second electrode. The outer surface of the electrode support portion of the first electrode is spaced apart from the dielectric film, and an insulating film is located between the outer surface of the electrode support portion and the dielectric film. The outer surface of the main electrode portion of the first electrode is in contact with the dielectric film.

5. The semiconductor memory device of claim 1, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode, and The electrode support portion of the first electrode protrudes further into the buried contact than the dielectric film in the first lateral direction.

6. The semiconductor memory device of claim 1, further comprising a metal silicide film between the electrode support portion and the buried contact of the first electrode, the metal silicide film contacting each of the electrode support portion and the buried contact. The metal silicide film is surrounded by the insulating pad.

7. The semiconductor memory device of claim 1, wherein the electrode support portion and the main electrode portion comprise the same material.

8. The semiconductor memory device of claim 1, further comprising a bit line extending longitudinally in a vertical direction on the substrate, the bit line being connected to the direct contact of the active region. The bit line is spaced apart from the capacitor in the first lateral direction, and the word line is between the bit line and the capacitor.

9. The semiconductor memory device of claim 1, further comprising a gate dielectric film between the channel region and the word line in the active region, the gate dielectric film surrounding the channel region. The first width of the electrode support portion is less than the maximum width of the gate dielectric film in the vertical direction, and the maximum width of the gate dielectric film is defined by the outer surface of the gate dielectric film.

10. The semiconductor memory device of claim 1, wherein the electrode support portion, the buried contact, the channel region and the direct contact are aligned with each other and collinear in the first lateral direction.

11. A semiconductor memory device, comprising: A storage cell block with a three-dimensional structure includes a plurality of storage cells repeatedly provided on a substrate in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction and the second lateral direction intersect each other, and the vertical direction is perpendicular to the main surface of the substrate. The storage cell block includes: Multiple active regions are arranged on the substrate along a line extending in the vertical direction; Multiple word lines, each of which surrounds a selected active region among the multiple active regions and extends in the second lateral direction, the multiple word lines overlapping each other in the vertical direction; Bit lines extend on the substrate in the vertical direction and are connected to one side of each of the plurality of active regions; A plurality of capacitors, each of the plurality of capacitors including a first electrode connected to the other side of a selected active region among the plurality of active regions, the first electrode including an electrode support portion and a main electrode portion, the electrode support portion having a first width in the vertical direction, the main electrode portion being integrally connected to the electrode support portion and spaced apart from the selected active region in the first lateral direction, the electrode support portion being between the main electrode portion and the selected active region, the main electrode portion having a second width in the vertical direction greater than the first width; and A plurality of insulating pads, each of the plurality of insulating pads surrounding a selected active region of the plurality of active regions and the electrode support portion of the first electrode connected to the selected active region.

12. The semiconductor memory device of claim 11, wherein each of the plurality of capacitors further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. Each of the electrode support portion and the main electrode portion of the first electrode has a cylindrical shape that defines an internal space for accommodating a portion of the dielectric film. The outer surface of the electrode support portion of the first electrode is spaced apart from the dielectric film, and an insulating film is located between the outer surface of the electrode support portion and the dielectric film. The outer surface of the main electrode portion of the first electrode is in contact with the dielectric film.

13. The semiconductor memory device of claim 11, wherein each of the plurality of capacitors further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. Each of the electrode support portion and the main electrode portion of the first electrode has a column shape. The outer surface of the electrode support portion of the first electrode is spaced apart from the dielectric film, and an insulating film is located between the outer surface of the electrode support portion and the dielectric film. The outer surface of the main electrode portion of the first electrode is in contact with the dielectric film.

14. The semiconductor memory device of claim 11, wherein each of the plurality of capacitors further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. The electrode support portion of the first electrode has a column shape. The main electrode portion of the first electrode has a cylindrical shape that defines an internal space accommodating a portion of the dielectric film and a portion of the second electrode. The outer surface of the electrode support portion of the first electrode is spaced apart from the dielectric film, and an insulating film is located between the outer surface of the electrode support portion and the dielectric film. The outer surface of the main electrode portion of the first electrode is in contact with the dielectric film.

15. The semiconductor memory device of claim 11, further comprising a metal silicide film between the electrode support portion of the first electrode and selected active regions among the plurality of active regions, the metal silicide film contacting the electrode support portion and each of the selected active regions. The metal silicide film is surrounded by a selected insulating pad from the plurality of insulating pads.

16. The semiconductor memory device of claim 11, wherein the first width of the electrode support portion is equal to the third width of the selected active region in the vertical direction.

17. A semiconductor memory device, comprising: An active region is spaced apart from the substrate in a vertical direction and extends in a first lateral direction. The active region includes a channel region, a buried contact, and a direct contact. The buried contact and the direct contact are spaced apart from each other in the first lateral direction, and the channel region is between the buried contact and the direct contact. The first lateral direction is parallel to the main surface of the substrate. The word line extends around the channel region of the active region in a second lateral direction, wherein the second lateral direction is parallel to the main surface of the substrate and intersects the first lateral direction. A gate dielectric film is located between the channel region and the word line in the active region; Bit lines are connected to the direct contact of the active region; A capacitor includes a first electrode connected to the buried contact of the active region, the first electrode including an electrode support portion and a main electrode portion, the electrode support portion having a first width in the vertical direction, the main electrode portion being integrally connected to the electrode support portion and spaced apart from the buried contact in the first transverse direction, the electrode support portion being between the main electrode portion and the buried contact, and the main electrode portion having a second width in the vertical direction, wherein the second width is greater than the first width; A metal silicide film is placed between the first electrode of the capacitor and the buried contact of the active region. as well as An insulating pad surrounds the buried contact, the metal silicide film, and the electrode support portion of the first electrode.

18. The semiconductor memory device of claim 17, wherein the electrode support portion, the buried contact, the channel region and the direct contact are aligned with each other and collinear in the first lateral direction.

19. The semiconductor memory device of claim 17, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. The outer surface of the electrode support portion of the first electrode is spaced apart from the dielectric film, and an insulating film is located between the outer surface of the electrode support portion and the dielectric film. The outer surface of the main electrode portion of the first electrode is in contact with the dielectric film.

20. The semiconductor memory device of claim 17, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. Each of the electrode support portion and the main electrode portion of the first electrode of the capacitor comprises a conductive metal nitride, a conductive metal oxide, a conductive metal oxide nitride, a metal, or a combination thereof. The dielectric film includes HfO2 film, ZrO2 film, Al2O3 film, Y2O3 film, Sc2O3 film, La2O3 film, Ta2O5 film, Nb2O5 film, CeO2 film, TiO2 film, GeO2 film, SrTiO3 film, BaSrTiO3 film, or combinations thereof.

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