Semiconductor memory device

Abstract

A semiconductor memory device includes: a substrate having an upper surface; an active region spaced apart from the substrate in a vertical direction perpendicular to an upper surface of the substrate and extending in a first lateral direction parallel to the upper surface of the substrate; a word line at least partially surrounding the active region and extending in a second lateral direction parallel to the upper surface of the substrate and perpendicular to the first lateral direction; a capacitor including a first electrode connected to the active region; and an insulating ring protruding from the first electrode of the capacitor toward the word line in the first lateral direction, the insulating ring surrounding a portion of the active region and including a metal element.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device, and more specifically, to a semiconductor memory device comprising a plurality of memory cells arranged in a three-dimensional manner. Background Technology

[0002] Due to advancements in electronic technology, the scaling down of semiconductor devices has progressed rapidly in recent years. This necessitates the miniaturization of memory cells. However, typical memory cells have limitations in maintaining high integration density and reliability. Therefore, there is a need to develop semiconductor memory devices with structures that facilitate both miniaturization and high integration of memory cells.

[0003] The information in this background section was already known or derived by the inventors before or during the implementation of embodiments of this application, or it is technical information acquired during the implementation of embodiments. Therefore, it may contain information that does not form prior art already known to the public. Summary of the Invention

[0004] One or more example embodiments provide a semiconductor memory device having a structure that enables the capacitance of a capacitor in a limited area to be maximized by preventing the capacitor from tilting or collapsing.

[0005] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the embodiments presented.

[0006] According to one aspect of an exemplary embodiment, a semiconductor memory device includes: a substrate having an upper surface; an active region spaced apart from the substrate in a vertical direction perpendicular to the upper surface of the substrate and extending in a first lateral direction parallel to the upper surface of the substrate; a word line at least partially surrounding the active region and extending in a second lateral direction parallel to the upper surface of the substrate and perpendicular to the first lateral direction; a capacitor including a first electrode connected to the active region; and an insulating ring projecting from the first electrode of the capacitor toward the word line in the first lateral direction, the insulating ring surrounding a portion of the active region and including a metallic element.

[0007] According to one aspect of an exemplary embodiment, a semiconductor memory device having a three-dimensional (3D) structure includes: a substrate having a upper surface; and a memory cell block on the substrate, the memory cell block including: a plurality of active regions arranged in rows in a vertical direction perpendicular to the upper surface of the substrate; a plurality of word lines, each of the plurality of word lines at least partially surrounding a corresponding active region of the plurality of active regions and extending in a second lateral direction parallel to the upper surface of the substrate; bit lines extending in a vertical direction on the substrate, the bit lines being connected to a first side of each of the plurality of active regions; a plurality of capacitors, each of the plurality of capacitors including a first electrode connected to a second side of a corresponding active region of the plurality of active regions, the second side being opposite to the first side; and a plurality of insulating rings arranged in rows in a vertical direction, each of the plurality of insulating rings projecting from the first electrode of the corresponding capacitor toward the corresponding word line of the plurality of word lines in a first lateral direction parallel to the upper surface of the substrate and perpendicular to the second lateral direction, each insulating ring surrounding a portion of the corresponding active region of the plurality of active regions, wherein each of the plurality of insulating rings includes a metal element.

[0008] According to one aspect of an exemplary embodiment, a semiconductor memory device includes: a substrate having an upper surface; an active region extending in a first lateral direction parallel to the upper surface of the substrate and spaced apart from the substrate in a vertical direction perpendicular to the upper surface of the substrate, the active region including a channel region, a buried contact, and a direct contact, wherein the buried contact and the direct contact are spaced apart from each other in the first lateral direction and the channel region is between the buried contact and the direct contact; a word line at least partially surrounding the channel region of the active region and extending in a second lateral direction parallel to the upper surface of the substrate and perpendicular to the first lateral direction; a gate dielectric film between the channel region of the active region and the word line; a bit line connected to the direct contact of the active region; a capacitor including a first electrode connected to the buried contact of the active region; a metal silicide film between the first electrode of the capacitor and the buried contact of the active region; and an insulating ring including a first portion contacting the first electrode of the capacitor, a second portion surrounding the metal silicide film, and a third portion surrounding a portion of the buried contact, the insulating ring including a metal element, wherein the gate dielectric film is aligned with and collinear with the insulating ring in the first lateral direction. Attached Figure Description

[0009] The above and other aspects, features and advantages of certain exemplary embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 It is a block diagram of a semiconductor memory device according to one or more embodiments;

[0011] Figure 2It is a plan view of a semiconductor memory device according to one or more embodiments;

[0012] Figure 3 It is based on one or more implementation methods along Figure 2 A cross-sectional view taken by line X1-X1';

[0013] Figure 4 It is based on one or more implementation methods. Figure 3 An enlarged cross-sectional view of part of the "EX1" region;

[0014] Figure 5 It is based on one or more implementation methods along Figure 2 A cross-sectional view taken from line Y1-Y1';

[0015] Figure 6A It is based on one or more implementation methods along Figure 4 An enlarged cross-sectional view of the line Y2-Y2';

[0016] Figure 6B It is based on one or more implementation methods along Figure 4 An enlarged cross-sectional view of the line Y3-Y3';

[0017] Figure 7 It is a cross-sectional view of a semiconductor memory device according to one or more embodiments;

[0018] Figure 8 It is based on one or more implementation methods. Figure 7 An enlarged cross-sectional view of part of the "EX2" region;

[0019] Figure 9 It is based on one or more implementation methods along Figure 8 An enlarged cross-sectional view of the line Y2-Y2';

[0020] Figure 10 It is a cross-sectional view of a semiconductor memory device according to one or more embodiments;

[0021] Figures 11 to 36B A diagram illustrating a method of manufacturing a semiconductor memory device according to one or more embodiments; and

[0022] Figures 37 to 39B This is a diagram of a method for manufacturing a semiconductor memory device according to one or more embodiments. Detailed Implementation

[0023] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto, but can be implemented in various other forms.

[0024] As used here, expressions such as "at least one of..." modify the entire column of elements when preceding them, without modifying any individual elements within that column. For example, the expression "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0025] It will be understood that when an element or layer is referred to as being "above" another element or layer, "over" another element or layer, "on" another element or layer, "below" another element or layer, "under" another element or layer, "below" another element or layer, "connected to" another element or layer, or "attached to" another element or layer, it can be directly above, directly above, directly on, directly below, directly below, directly connected to, or directly attached to another element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly above" another element or layer, "directly above" another element or layer, "directly on" another element or layer, "directly below" another element or layer, "directly under" another element or layer, "directly connected to" another element or layer, or "directly linked to" another element or layer, there is no intermediate element or layer.

[0026] As used herein, the term “cover” may indicate complete or partial coverage of a corresponding surface and variations thereof, and the term “surround” may indicate complete or partial surrounding of a component and variations thereof, without specifically limiting the amount of coverage or surrounding.

[0027] Figure 1 This is a block diagram of a semiconductor memory device 100 according to one or more embodiments.

[0028] refer to Figure 1 The semiconductor memory device 100 may include a memory cell array 11, a command decoder 12, an address buffer 13, an address decoder 14, a control circuit 15, a sense amplifier 16, and a data input / output (I / O) circuit 17.

[0029] The memory cell array 11 may include multiple memory cells MC. The memory cell array 11 may include multiple word lines WL, multiple bit lines BL, and multiple plate electrodes PL connected to the memory cells MC. The memory cell array 11 may include dynamic random access memory (DRAM) configured to sense the cell voltage Vcell stored as data in the memory cells MC.

[0030] The semiconductor storage device 100 can receive data DQ from and output data DQ to an external device in response to a command CMD and an address ADDR received from an external device (e.g., a central processing unit (CPU) or a memory controller).

[0031] Each of the multiple memory cells MC may include a cell transistor CT and a cell capacitor CC. The gate of the cell transistor CT may be connected to the word line WL. The first terminal of the cell transistor CT may be connected to the bit line BL. The second terminal of the cell transistor CT may be connected to the first terminal of the cell capacitor CC. The second terminal of the cell capacitor CC may be connected to the plate electrode PL. The memory cell MC may store a cell voltage Vcell with a specified data value in the cell capacitor CC.

[0032] Command decoder 12 can determine the input command CMD by referring to the chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, and write enable signal / WE applied from an external device. Command decoder 12 can generate control signals corresponding to the command CMD. Command CMD may include activation command, read command, write command, and precharge command.

[0033] Address buffer 13 can receive address ADDR applied from an external device. Address ADDR may include word line addresses for addressing some of the multiple word lines WL connected to memory cell array 11, bit line addresses for addressing some of the multiple bit lines BL connected to memory cell array 11, and board line addresses for addressing some of the multiple board electrodes PL connected to memory cell array 11. Address buffer 13 can transmit each of the word line addresses, bit line addresses, and board line addresses to address decoder 14.

[0034] Address decoder 14 may include word line decoder, bit line decoder, and board line decoder, which are respectively configured to select the word line WL, bit line BL, and board electrode PL of the memory cell MC to be accessed in response to the received address ADDR. The word line decoder can decode the word line address and activate the word line WL corresponding to the memory cell MC at the word line address. The bit line decoder can decode the bit line address and provide a bit line select signal for selecting the bit line BL of the memory cell MC corresponding to the bit line address. The board line decoder can decode the board line address and provide a board line select signal for selecting the board electrode PL of the memory cell MC corresponding to the board line address.

[0035] The control circuit 15 can control the sensing amplifier 16 under the control of the command decoder 12. The control circuit 15 can control the operation of the sensing amplifier 16 to detect the cell voltage Vcell of the memory cell MC. The control circuit 15 can control the sensing amplifier 16 to perform pre-charge operation, charge sharing operation, and sensing operation.

[0036] The sensing amplifier 16 can detect the charge stored as data in the memory cell MC. Furthermore, the sensing amplifier 16 can transmit the detected data DQ to the data I / O circuit 170, so that the detected data DQ is output to the outside of the semiconductor memory device 100.

[0037] The data I / O circuit 17 can receive data DQ to be written to the memory cell MC from the outside and transmit the data DQ to the memory cell array 11. The data I / O circuit 17 can output the bit data detected by the sense amplifier 16 as read data to the outside.

[0038] Figures 2 to 6B This is a diagram of a semiconductor memory device 100 according to one or more embodiments. More specifically, Figure 2 It is a plan view of a semiconductor memory device 100 according to one or more embodiments. Figure 3 It is along Figure 2 The cross-sectional view taken by line X1-X1'. Figure 4 yes Figure 3 An enlarged cross-sectional view of part of the "EX1" region. Figure 5 It is along Figure 2 The cross-sectional view taken from line Y1-Y1'. Figure 6A It is along Figure 4 An enlarged cross-sectional view of the line Y2-Y2'. Figure 6B It is along Figure 4 An enlarged cross-sectional view of the section intercepted by line Y3-Y3'. See below for reference. Figures 2 to 6B The components of the semiconductor memory device 100 described herein may constitute a reference. Figure 1 A portion of the described storage cell array 11.

[0039] refer to Figures 2 to 6B The semiconductor memory device 100 may include a memory cell block CB containing a plurality of memory cells, which are repeatedly arranged on the substrate 102 in a first lateral direction (X direction) and a second lateral direction (Y direction) perpendicular to each other and in a vertical direction (Z direction) perpendicular to the upper surface 102M of the substrate 102.

[0040] Multiple vertical levels (such as) spaced apart from the substrate 102 in the vertical direction (Z direction) Figure 3 At each of the vertical hierarchies VL1, VL2, and VL3, the storage cell block CB may include multiple active regions AC, which are repeatedly arranged in the first lateral direction (X direction) and the second lateral direction (Y direction). Figure 3 As shown, the plurality of active regions AC included in the memory cell block CB may include a plurality of active regions AC arranged in a row in the vertical direction (Z direction) and positioned above each other in the vertical direction (Z direction) on the substrate 102. In one or more embodiments, as Figure 3 and Figure 4 As shown, each of the multiple active regions AC included in the storage cell block CB can have a thickness in the vertical direction (Z direction), which is constant in the first lateral direction (X direction).

[0041] Each of the plurality of active regions AC may include a channel region 106A and a buried contact BC and a direct contact DC spaced apart from each other in a first lateral direction (X direction), with the channel region 106A located therebetween. In each of the plurality of active regions AC, the buried contact BC, the channel region 106A, and the direct contact DC may be arranged sequentially in a straight line in the first lateral direction (X direction). In one or more embodiments, each of the plurality of active regions AC may have a height in a vertical direction (Z direction) that is substantially constant in the first lateral direction (X direction). In the plurality of active regions AC, the corresponding heights of the buried contact BC, the channel region 106A, and the direct contact DC in the vertical direction (Z direction) may be the same or similar to each other. In one or more embodiments, each of the plurality of active regions AC may include a doped Si layer.

[0042] like Figure 2 , Figure 3 and Figure 4As shown, at each of a plurality of vertical layers spaced apart from the substrate 102 in the vertical direction (Z direction), the memory cell block CB of the semiconductor memory device 100 may include a plurality of word lines WL extending longitudinally in a second lateral direction (Y direction) parallel to the upper surface 102M of the substrate 102. The plurality of word lines WL may be spaced apart from each other in the first lateral direction (X direction), the second lateral direction (Y direction), and the vertical direction (Z direction). Each of the plurality of word lines WL may surround a channel region 106A and extend longitudinally in the second lateral direction (Y direction), the channel region 106A being a local region of one of a plurality of active regions AC included in the memory cell block CB. Figure 3 As shown, multiple word lines WL contained in the memory cell block CB can be arranged in a row on the substrate 102 in the vertical direction (Z direction) and positioned above each other in the vertical direction (Z direction).

[0043] In one or more embodiments, each of the plurality of word lines WL may include a metal, a conductive metal nitride, a metal silicide, doped polysilicon, or a combination thereof. For example, each of the plurality of word lines WL may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), tungsten (W), tungsten nitride (WN), cobalt (Co), aluminum (Al), nickel (Ni), titanium silicide (TiSi), titanium silicon nitride (TiSiN), tungsten silicide (WSi), tungsten silicon nitride (WSiN), tantalum silicide (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), cobalt silicide (CoSi), nickel silicide (NiSi), doped polysilicon, or a combination thereof, but is not limited thereto.

[0044] The gate dielectric film 130 may be located between the channel region 106A of the active region AC and the word line WL. In the first lateral direction (X direction), the width of each of the plurality of gate dielectric films 130 may be greater than the width of each of the plurality of word lines WL. In one or more embodiments, the gate dielectric film 130 may include a paraelectric material. For example, the gate dielectric film 130 may include silicon oxide, silicon nitride, silicon nitride, or combinations thereof. In one or more embodiments, the gate dielectric film 130 may include a high-k dielectric material. The high-k dielectric material may have a dielectric constant of about 10 to about 25. For example, the high-k dielectric material may include, but is not limited to, hafnium oxide, aluminum oxide, zirconium oxide, or combinations thereof. For example, each of the plurality of gate dielectric films 130 may include, but is not limited to, HfO2, Al2O3, ZrO2, or combinations thereof. In yet another embodiment, the gate dielectric film 130 may include a combination of a paraelectric material and a high-k dielectric material.

[0045] like Figure 3 and Figure 4 As shown, the corresponding spaces of multiple word lines WL arranged in a row in the vertical direction (Z direction) can be filled by the insulating structure 129. The insulating structure 129 may include a silicon oxide film, a silicon nitride film, or a combination thereof.

[0046] like Figures 2 to 4 As shown, the memory cell block CB of the semiconductor memory device 100 may include multiple bit lines BL extending longitudinally in the vertical direction (Z direction). On the substrate 102, each of the multiple bit lines BL may pass through the insulating structure 129 and extend longitudinally in the vertical direction (Z direction). Each of the multiple bit lines BL may be connected to one end of each of the multiple active regions AC included in the memory cell block CB that are located above each other in the vertical direction (Z direction). Each of the multiple bit lines BL may be connected to a direct contact DC of one of the multiple active regions AC.

[0047] In one or more embodiments, the direct contact DC included in the active region AC may include a doped silicon layer. For example, the direct contact DC may include a silicon layer doped with an n-type dopant. Each of the multiple bit lines BL may include a metal, a conductive metal nitride, a metal silicide, doped polysilicon, or a combination thereof. For example, each of the multiple bit lines BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Al, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, doped polysilicon, or a combination thereof, and is not limited thereto. In one or more embodiments, as Figure 3 As shown, each of the multiple bit lines BL may include a metal silicide film 152, a conductive pad 154, and a conductive plug 156, which are sequentially stacked on the surface of the active region AC that directly contacts DC. When in Figure 3 When viewed in the XY plane, the conductive plug 156 may be surrounded by a conductive pad 154, and both the conductive plug 156 and the conductive pad 154 may be surrounded by a metal silicide film 152. In one or more embodiments, the metal silicide film 152 may be omitted. In one or more embodiments, the metal silicide film 152 may include molybdenum silicide or titanium silicide, the conductive pad 154 may include TiN, and the conductive plug 156 may include W, but is not limited thereto.

[0048] like Figure 2 , Figure 3 and Figure 4As shown, the memory cell block CB of the semiconductor memory device 100 may include multiple capacitors CAP respectively connected to multiple active regions AC. Each of the multiple capacitors CAP may include a first electrode 186, a dielectric film 187, and a second electrode 188. The first electrode 186 of the capacitor CAP may be connected to a buried contact BC of one of the multiple active regions AC.

[0049] like Figure 3 and Figure 4 As shown, a metal silicide film 184 may be located between the first electrode 186 of the capacitor CAP and the buried contact BC of the active region AC. The metal silicide film 184 may include, but is not limited to, titanium silicide, tantalum silicide, cobalt silicide, molybdenum silicide, or tungsten silicide. The first electrode 186 of the capacitor CAP may be electrically connected to the buried contact BC of the active region AC via the metal silicide film 184. In one or more embodiments, the metal silicide film 184 may be omitted. In this case, the first electrode 186 of the capacitor CAP may contact the buried contact BC of the active region AC. The second electrode 188 of the capacitor CAP may be spaced apart from the active region AC and cover the surface of the first electrode 186. A dielectric film 187 of the capacitor CAP may be located between the first electrode 186 and the second electrode 188.

[0050] like Figure 2 As shown, in the top view, multiple capacitors CAP can be adjacent to multiple word lines WL and multiple active regions AC, and can be arranged in a row in the second lateral direction (Y direction). As used herein, the top view can indicate a view from the XY plane. In the top view, each of the multiple active regions AC can be located in the first lateral direction (X direction) between its adjacent bit line BL and capacitor CAP. Figure 2 and Figure 3 As shown, multiple bit lines BL can be spaced apart from multiple capacitors CAP in the first lateral direction (X direction), and multiple word lines WL are located in between.

[0051] In each of the plurality of capacitors CAP, each of the first electrode 186 and the second electrode 188 may include a metal film, a conductive metal oxide film, a conductive metal nitride film, a conductive metal nitride film, or a combination thereof. In one or more embodiments, each of the first electrode 186 and the second electrode 188 may include molybdenum (Mo), tungsten (W), ruthenium (Ru), platinum (Pt), iridium (Ir), cobalt (Co), tin (Sn), titanium (Ti), Ti nitride, Ti oxide, Ti nitride, niobium (Nb), Nb nitride, Nb oxide, Nb nitride, tungsten (W) nitride, vanadium (V) nitride, V oxide, molybdenum (Mo) nitride, molybdenum (Mo) oxide, ruthenium (Ru) oxide, strontium-ruthenium (SrRu) oxide, cobalt (Co) nitride, Co oxide, Co nitride, tin (Sn) nitride, Sn oxide, Sn nitride, or a combination thereof. For example, each of the first electrode 186 and the second electrode 188 may include titanium nitride (TiN), niobium nitride (NbN), cobalt nitride (CoN), tin oxide (SnO2), or combinations thereof. In one or more embodiments, each of the first electrode 186 and the second electrode 188 may include tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), vanadium (V), vanadium nitride (VN), molybdenum (Mo), molybdenum nitride (MoN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), strontium ruthenium oxide (SrRuO2). 3, (SRO), iridium (Ir), iridium oxide (IrO2), platinum (Pt), platinum oxide (PtO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), (La,Sr)CoO3 (LSCo), or combinations thereof. However, the constituent materials of each of the first electrode 186 and the second electrode 188 are not limited to the examples described above.

[0052] The dielectric film 187 may comprise a silicon oxide film, a high-k dielectric film, or a combination thereof. In one or more embodiments, the dielectric film 187 may comprise a metal oxide, which includes at least one metal selected from hafnium (Hf), zirconium (Zr), aluminum (Al), niobium (Nb), cerium (Ce), lanthanum (La), tantalum (Ta), and titanium (Ti). In one or more embodiments, the dielectric film 187 may have a single-film structure comprising a high-k dielectric film. In one or more embodiments, the dielectric film 187 may have a multilayer structure comprising a plurality of high-k dielectric films sequentially stacked on the first electrode 186. The high-k dielectric film may comprise, but is not limited to, HfO2 film, ZrO2 film, Al2O3 film, Y2O3 film, Sc2O3 film, La2O3 film, Ta2O5 film, Nb2O5 film, CeO2 film, TiO2 film, GeO2 film, SrTiO3 film, BaSrTiO3 film, or a combination thereof. In one or more embodiments, the dielectric film 187 may comprise an oxide of at least one metal selected from Ti, Nb, Ta, Sn, and Mo, or a nitride of at least one metal selected from Ti, Nb, Ta, Sn, and Mo. For example, the dielectric film 187 may comprise Ti oxide, Ti nitride, Nb oxide, Nb nitride, Ta oxide, Ta nitride, Sn oxide, Sn nitride, Mo oxide, Mo nitride, and combinations thereof. In yet another embodiment, the dielectric film 187 may comprise a ferroelectric film comprising at least one oxide selected from hafnium (Hf), silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), and strontium (Sr). The ferroelectric film may comprise hafnium-based oxides, such as hafnium oxide (HfO), hafnium zirconium oxide (HZO), hafnium titanium oxide, and hafnium silicon oxide. The ferroelectric film may further comprise dopants as needed. The dopant may include, but is not limited to, at least one element selected from silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), scandium (Sc), strontium (Sr), magnesium (Mg), and barium (Ba).

[0053] like Figure 3 , Figure 4 and Figure 6A As shown, the first electrode 186 of each of the plurality of capacitors CAP can have a cylindrical shape defining an internal space that accommodates a portion of a dielectric film 187 and a portion of a second electrode 188. The dielectric film 187 can cover both the inner and outer surfaces of the first electrode 186. Figure 6AAs shown, when viewed in the YZ plane, the cross-section of the first electrode 186 can have a rectangular closed-loop shape with rounded corners. The dielectric film 187 can contact each of the inner and outer surfaces of the first electrode 186. A portion of the second electrode 188 can fill the portion of the interior space of the first electrode 186 defined by the dielectric film 187, and another portion of the second electrode 188 can cover the outer surface of the first electrode 186 with the dielectric film 187 therebetween.

[0054] like Figure 3 and Figure 4 As shown, the memory cell block CB of the semiconductor memory device 100 may include a plurality of metal insulating rings (STLs). In the memory cell block CB of the semiconductor memory device 100, the plurality of metal insulating rings (STLs) may be arranged in a row in the vertical direction (Z direction).

[0055] Each of the plurality of metal-insulating ring STLs may protrude in a first lateral direction (X direction) from a first electrode 186 of one of the plurality of capacitors CAP toward a corresponding word line WL of the plurality of word lines WL and an adjacent gate dielectric film 130. Each of the plurality of metal-insulating ring STLs may surround a buried contact BC, which is part of one of the plurality of active regions AC. Figure 6B As shown, when viewed in the YZ plane, the cross-section of each of the multiple metal-insulating ring STLs can have a rectangular closed-loop shape with rounded corners.

[0056] like Figure 4 As shown, each of the plurality of metal-insulating ring STLs may include a first portion of the first electrode 186 of the contact capacitor CAP, a second portion surrounding a metal silicide film 184, and a third portion surrounding a portion of the buried contact BC. One of the plurality of gate dielectric films 130 may be aligned and collinear with one of the plurality of metal-insulating ring STLs in a first lateral direction (X direction). The metal silicide film 184 may be surrounded by one of the plurality of metal-insulating ring STLs, and the outer surface of the metal silicide film 184 may contact said one of the plurality of metal-insulating ring STLs.

[0057] like Figure 4As specifically shown, the dielectric film 187 of the capacitor CAP may have a surface that contacts the metal-containing insulating ring STL. The semiconductor memory device 100 may include an insulating pad 172 surrounding the buried contact BC, a buried insulating film 173 surrounding the insulating pad 172 and the metal-containing insulating ring STL, and an oxide pad 174S covering the surfaces of the buried insulating film 173 facing the dielectric film 187 and the second electrode 188. The insulating pad 172 may surround the buried contact BC and contact the surface closest to the word line WL and the gate dielectric film 130 in the first lateral direction (X direction) surrounding the metal-containing insulating ring STL. The insulating pad 172 may cover the sidewalls of the word line WL. The portion of the insulating pad 172 surrounding the buried contact BC may be collinear with the metal-containing insulating ring STL in the first lateral direction (X direction). In one or more embodiments, each of the insulating pad 172 and the oxide pad 174S may include silicon oxide, and the buried insulating film 173 may include silicon nitride, but is not limited thereto.

[0058] The oxide pad 174S may surround at least a portion of the metal-insulating ring STL. In the first lateral direction (X direction), the width of the oxide pad 174S may be smaller than the width of the metal-insulating ring STL. For example, in... Figure 4 As can be seen in the portion "EX1A" shown in dashed lines, the dielectric film 187 may include a protrusion 187P projecting toward the word line WL and the gate dielectric film 130 in a first lateral direction (X direction). The protrusion 187P of the dielectric film 187 may be located between the oxide pad 174S and the metal-containing insulating ring STL. The protrusion 187P of the dielectric film 187 may contact each of the oxide pad 174S and the metal-containing insulating ring STL. In the oxide pad 174S, at least a portion of the surface facing the metal-containing insulating ring STL may be spaced apart from the metal-containing insulating ring STL in a vertical direction (Z direction), with the protrusion 187P of the dielectric film 187 located therebetween.

[0059] In one or more embodiments, each of the plurality of metal-containing insulating ring STLs may include a crystalline metal oxide. For example, each of the plurality of metal-containing insulating ring STLs may include, but is not limited to, HfO2, ZrO2, Ta2O5, Nb2O5, TiO2, La2O3, or combinations thereof.

[0060] Each of the dielectric film 187 of the capacitor CAP and the metal-containing insulating ring STL may include a metal oxide. In this case, in one or more embodiments, the dielectric film 187 of the capacitor CAP may include a metal element of the same type as the metal element included in the metal-containing insulating ring STL. For example, when the metal-containing insulating ring STL includes HfO2, the dielectric film 187 may include a hafnium oxide film, such as an HfO2 film.

[0061] like Figure 2 and Figure 3 As shown, the memory cell block CB of the semiconductor memory device 100 may further include a plate electrode 190. The plate electrode 190 may correspond to a reference. Figure 1 The plate electrode PL is described. (e.g.) Figure 3 As shown, the plate electrode 190 may include a central portion 190A and a plurality of finger portions 190B. The central portion 190A may extend longitudinally in a vertical direction (Z direction) on the substrate 102. The plurality of finger portions 190B may protrude from the central portion 190A in a first lateral direction (X direction). Each of the plurality of finger portions 190B of the plate electrode 190 may overlap with the first electrode 186 of the capacitor CAP in the vertical direction (Z direction). The plurality of finger portions 190B of the plate electrode 190 may be spaced apart from the first electrode 186 of the capacitor CAP in the vertical direction (Z direction), with the dielectric film 187 and the second electrode 188 of the capacitor CAP therebetween. A plurality of capacitors CAP located on both sides of a plate electrode 190 in the first lateral direction (X direction) may share the single plate electrode 190. The plate electrode 190 may include a metal film, a conductive metal oxide film, a conductive metal nitride film, a conductive metal oxide nitride film, a semiconductor film, or a combination thereof. In one or more embodiments, the plate electrode 190 may include Ti, Ti nitride, Ti oxide, Ti oxide nitride, Nb, Nb nitride, Nb oxide, Nb oxide nitride, Co, Co nitride, Co oxide, Co oxide, Sn, Sn nitride, Sn oxide, Sn oxide, silicon germanium (SiGe), or combinations thereof. For example, the plate electrode 190 may include titanium nitride (TiN), niobium nitride (NbN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), vanadium (V), vanadium nitride (VN), molybdenum (Mo), molybdenum nitride (MoN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), platinum (Pt), silicon germanium (SiGe), or combinations thereof, but is not limited thereto.

[0062] Figures 7 to 9 This is a diagram of a semiconductor memory device 200 according to one or more embodiments. More specifically, Figure 7This is a cross-sectional view of a portion of the semiconductor memory device 200, corresponding to the view along... Figure 2 The cross section intercepted by line X1-X1'. Figure 8 yes Figure 7 An enlarged cross-sectional view of part of the "EX2" region. Figure 9 It is along Figure 8 An enlarged cross-sectional view of line Y2-Y2' is shown below. (See below for reference.) Figures 7 to 9 The components of the semiconductor memory device 200 described herein may constitute a reference. Figure 1 This is a portion of the described storage cell array 11. Figures 7 to 9 In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 2 to 6B Since the same elements are used in the same way, their repeated descriptions can be omitted.

[0063] refer to Figures 7 to 9 The memory cell block CB2 of the semiconductor memory device 200 can have the same characteristics as the referenced memory cell block CB2. Figures 2 to 6B The memory cell block CB of the described semiconductor memory device 100 has a substantially identical configuration. However, the memory cell block CB2 of the semiconductor memory device 200 may include a plurality of capacitors CAP2 respectively connected to a plurality of active regions AC. Each of the plurality of capacitors CAP2 may include a first electrode 286, a dielectric film 287, and a second electrode 288. The first electrode 286 of the capacitor CAP2 may be connected to a buried contact BC of one of the plurality of active regions AC. The first electrode 286, dielectric film 287, and second electrode 288 of each of the plurality of capacitors CAP2 may respectively and have the same configuration as referenced. Figures 2 to 4 The first electrode 186, dielectric film 187, and second electrode 188 described are substantially the same configuration. However, the first electrode 286 of each of the plurality of capacitors CAP2 may have a columnar shape with a filled interior.

[0064] As in Figure 8 As can be seen from the portion "EX2A" shown in dashed lines, the dielectric film 287 may include protrusions 287P projecting toward the word line WL and the gate dielectric film 130 in the first lateral direction (X direction). The protrusions 287P of the dielectric film 287 may be located between the oxide pad 174S and the metal-containing insulating ring STL. The protrusions 287P of the dielectric film 287 may contact each of the oxide pad 174S and the metal-containing insulating ring STL. In the oxide pad 174S, at least a portion of the surface facing the metal-containing insulating ring STL may be spaced apart from the metal-containing insulating ring STL in the vertical direction (Z direction), with the protrusions 287P of the dielectric film 287 located therebetween.

[0065] like Figure 9As shown, when viewed in the YZ plane, the cross-section of the first electrode 286 can have a rectangular shape with rounded corners. The dielectric film 287 can contact the outer surface of the first electrode 286. The second electrode 288 can cover the outer surface of the first electrode 286, with the dielectric film 287 disposed therebetween.

[0066] Figure 10 This is a cross-sectional view of a semiconductor memory device 300 according to one or more embodiments. Figure 10 The diagram shows a cross-sectional configuration of a portion of the semiconductor memory device 300, corresponding to the section along... Figure 2 The cross section intercepted by line X1-X1'. See below for reference. Figure 10 The components of the semiconductor memory device 300 described herein may constitute a reference. Figure 1 This is a portion of the described storage cell array 11. Figure 10 In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 2 to 6B Since the same elements are used in the same way, their repeated descriptions can be omitted.

[0067] refer to Figure 10 The memory cell block CB3 of the semiconductor memory device 300 can substantially have the same characteristics as the referenced memory cell block CB3. Figures 2 to 6B The memory cell block CB of the semiconductor memory device 100 described has the same configuration. However, the memory cell block CB3 of the semiconductor memory device 300 may include an oxide pad 374S covering the surface of the buried insulating film 173 facing the dielectric film 387 and the second electrode 188, and a plurality of capacitors CAP3 respectively connected to a plurality of active regions AC.

[0068] In the memory cell block CB3 of the semiconductor memory device 300, each of the plurality of capacitors CAP3 may include a first electrode 186, a dielectric film 387, and a second electrode 188. Detailed configurations of the first electrode 186 and the second electrode 188 of the capacitors CAP3 can be found in reference [reference needed]. Figure 2 , Figure 3 and Figure 6A The configuration is the same as described. The dielectric film 387 of capacitor CAP3 can have essentially the same characteristics as the reference. Figure 2 , Figure 3 and Figure 6A The dielectric film 187 described has the same configuration. However, the dielectric film 387 of capacitor CAP3 may not include the portion protruding between the oxide pad 374S and the metal-containing insulating ring STL. The oxide pad 374S may at least partially surround the metal-containing insulating ring STL. In the first lateral direction (X direction), the width of the oxide pad 374S may be smaller than the width of the metal-containing insulating ring STL. The oxide pad 374S may include, but is not limited to, silicon oxide.

[0069] As in Figure 10 As can be seen in the dashed section “EX3”, the surface of the oxide pad 374S facing the metal-insulating ring STL can contact the outer surface of the metal-insulating ring STL.

[0070] refer to Figures 1 to 10 The described semiconductor memory devices 100, 200, and 300 may include a metal-insulating ring STL that protrudes from the first electrodes 186 and 286 of capacitors CAP, CAP2, and CAP3 in a first lateral direction (X direction) and surrounds a portion of the buried contact BC of the active region AC. During the manufacturing process of semiconductor memory devices 100, 200, and 300, the metal-insulating ring STL can advantageously control the effective length of the first electrodes 186 and 286 to a constant level. Therefore, semiconductor memory devices 100, 200, and 300 according to one or more embodiments can provide a structure that maximizes the capacitance of capacitors CAP, CAP2, and CAP3 even when the area occupied by the plurality of memory cells arranged in a three-dimensional manner is reduced due to the miniaturization and high integration of the plurality of memory cells. Furthermore, semiconductor memory devices 100, 200, and 300 according to one or more embodiments can have improved performance without inefficiently increasing the area occupied by the plurality of memory cells in the memory cell blocks CB, CB2, and CB3, and provide a structure that facilitates high integration.

[0071] Figures 11 to 36B This is a diagram illustrating a method of manufacturing a semiconductor memory device according to one or more embodiments. More specifically, Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15A , Figure 16A , Figure 17A , Figure 18 and Figure 19A Each is based on the process sequence and along Figure 2 A cross-sectional view of the portion of the area corresponding to the section cut by line X1-X1'. Figure 15B , Figure 16B and Figure 17B Each is along Figure 2 A cross-sectional view of a portion of the area corresponding to the section cut by line Y1-Y1'. Figure 19B yes Figure 19A An enlarged cross-sectional view of part of the "EXB" region. Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 , Figure 34 , Figure 35A and Figure 36A Each is based on the process sequence and Figure 3 An enlarged cross-sectional view of an example of the region corresponding to "EX1". Figure 35B and Figure 36B Each is based on the process sequence and along Figure 4 A cross-sectional view of an example region corresponding to the section intercepted by line Y2-Y2'. (Reference) Figures 11 to 36B For reference Figures 2 to 6B An example of a manufacturing method for the described semiconductor memory device 100 will be described. Figures 11 to 36B In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 2 to 6B Since the same elements are used in the same way, their repeated descriptions can be omitted.

[0072] refer to Figure 11 Multiple sacrificial layers 104 and multiple active layers 106 can be alternately stacked on the upper surface 102M of the substrate 102 in the vertical direction (Z direction). In one or more embodiments, the multiple sacrificial layers 104 and multiple active layers 106 may each comprise a semiconductor material. In one or more embodiments, each of the multiple sacrificial layers 104 may comprise an undoped SiGe layer or a SiGe layer doped with carbon (C) atoms, and each of the multiple active layers 106 may comprise a Si layer. In the vertical direction (Z direction), the thickness T1 of each of the multiple active layers 106 may be less than the thickness T2 of each of the multiple sacrificial layers 104. In one or more embodiments, the thickness T2 of each of the multiple sacrificial layers 104 may be at least three times the thickness T1 of each of the multiple active layers 106, but is not limited thereto.

[0073] refer to Figure 12 A silicon oxide film 108 and a silicon nitride film 109 can be sequentially formed on a stacked structure including multiple sacrificial layers 104 and multiple active layers 106, and a mask pattern MP1 can be formed on the silicon nitride film 109. The mask pattern MP1 may include multiple first openings OP1. In one or more embodiments, the mask pattern MP1 may include a photoresist pattern, but is not limited thereto. Subsequently, the silicon nitride film 109 and the silicon oxide film 108 can be sequentially etched through the multiple first openings OP1 using the mask pattern MP1 as an etching mask. Subsequently, the stacked structure including multiple sacrificial layers 104 and multiple active layers 106 can be etched, thus forming multiple holes H1 exposing the substrate 102 in the stacked structure.

[0074] Subsequently, portions of the multiple sacrificial layers 104 can be removed through the multiple first openings OP1 and the multiple holes H1. As a result, multiple active layers 106 can protrude along the first lateral direction (X direction) between the remaining portions of the multiple sacrificial layers 104.

[0075] refer to Figure 13 ,exist Figure 12 In the resulting structure, a first insulating pad 121 and a second insulating pad 122 can be formed to conformally cover the surfaces exposed through the plurality of holes H1. A buried insulating film 123 can be formed to fill the remaining space defined by the second insulating pad 122 in the plurality of holes H1. In one or more embodiments, the first insulating pad 121 may comprise silicon oxide, the second insulating pad 122 may comprise silicon nitride, and the buried insulating film 123 may comprise silicon oxide.

[0076] Next, the mask pattern MP1, silicon nitride film 109, and silicon oxide film 108 can be removed using a chemical mechanical polishing (CMP) process. This creates a flat top surface, exposing one of the active layers 106 located at the vertical level furthest from the substrate 102. Subsequently, silicon oxide film 108A and silicon nitride film 109A can be formed on the resulting structure.

[0077] refer to Figure 14 A mask pattern MP2 can be formed on the silicon nitride film 109A. The mask pattern MP2 may include a second opening OP2. The second opening OP2 may be located in the first lateral direction (X direction) from the mask pattern MP2. Figure 12 The mask pattern MP1 shown is located at a position offset from the position of the plurality of first openings OP1. In one or more embodiments, the mask pattern MP2 may include, but is not limited to, a photoresist pattern.

[0078] By using the mask pattern MP2 as an etching mask, a stacked structure including multiple sacrificial layers 104 and multiple active layers 106 can be etched through the second opening OP2. Therefore, a hole H2 exposing the substrate 102 can be formed in the stacked structure.

[0079] refer to Figure 15A and Figure 15B ,exist Figure 14In the resulting structure, multiple sacrificial layers 104 exposed through via H2 can be removed. During the removal of the multiple sacrificial layers 104, corresponding portions of the multiple active layers 106 may be consumed. Subsequently, a third insulating pad 125 and a fourth insulating pad 126 can be formed to conformally cover the surfaces of the multiple active layers 106 exposed through via H2. A buried insulating film 127 can be formed to fill the remaining space defined by the fourth insulating pad 126 in via H2. In one or more embodiments, the third insulating pad 125 may comprise silicon oxide, the fourth insulating pad 126 may comprise silicon nitride, and the buried insulating film 127 may comprise silicon oxide. Subsequently, a CMP process can be used to remove the mask pattern MP2 to expose the top surface of the silicon nitride film 109A.

[0080] refer to Figure 16A and Figure 16B It can be referenced after it has been executed. Figure 15A and Figure 15B The described process forms a mask pattern MP3 on the resulting structure. The mask pattern MP3 may include multiple third openings OP3. The mask pattern MP3 may include, but is not limited to, a photoresist pattern.

[0081] Subsequently, by using the mask pattern MP3 as an etching mask, the silicon nitride film 109A and the silicon oxide film 108A can be etched sequentially through multiple third openings OP3. Then, the buried insulating film 123, the second insulating pad 122 and the first insulating pad 121 can be removed sequentially to form multiple holes H3 exposing multiple active layers 106 and the substrate 102.

[0082] refer to Figure 17A and Figure 17B It can be seen from Figure 16A and Figure 16BThe resulting structure removes the mask pattern MP3 to expose the top surface of the silicon nitride film 109A. Next, a gate dielectric film 130 can be formed to conformally cover the surface exposed by the plurality of holes H3, a conductive layer can be formed to cover the surface of the gate dielectric film 130, and a protective pattern can be formed to cover desired portions of the conductive layer. Subsequently, the exposed portions of the conductive layer can be selectively removed by using the protective pattern as an etch mask, thus forming a plurality of conductive patterns WLM for forming multiple word lines. The remaining spaces of the plurality of holes H3 exposing the plurality of conductive patterns WLM can then be filled by an insulating structure 129. The insulating structure 129 may include a silicon oxide film, a silicon nitride film, or a combination thereof. In one or more embodiments, the insulating structure 129 may include silicon oxide pads, silicon nitride pads, and a silicon oxide film for filling, sequentially stacked on the surfaces of the gate dielectric film 130 and the plurality of conductive patterns WLM. After the insulating structure 129 is formed, the top surface of the silicon nitride film 109A may be exposed around the insulating structure 129.

[0083] refer to Figure 18 , after it has been implemented reference Figure 17A and Figure 17B In the structure obtained by the described process, multiple bit lines BL can be formed passing through a portion of the insulating structure 129 in the vertical direction (Z direction). Each of the multiple bit lines BL can be formed to contact a plurality of active layers 106 arranged in a row in the vertical direction (Z direction). To form the multiple bit lines BL, a plurality of vertical vias can be formed passing through a portion of the insulating structure 129 in the vertical direction (Z direction). The plurality of active layers 106 arranged in a row in the vertical direction (Z direction) can be exposed through the plurality of vertical vias. Dopant can be doped into each of the plurality of active layers 106 exposed through the plurality of vertical vias to form direct contact DC. Subsequently, a metal silicide film 152, a conductive pad 154, and a conductive plug 156 can be sequentially formed inside the plurality of vertical vias. The dopant can include p-type or n-type impurity ions. For example, the dopant can include boron (B), phosphorus (P), or arsenic (As), but is not limited thereto. Subsequently, the silicon nitride film 109A and the silicon oxide film 108A can be removed using a chemical mechanical polishing (CMP) process. A flat top surface can then be formed, on which the active layers 106 located at the vertical level furthest from the substrate 102 are exposed.

[0084] refer to Figure 19A and Figure 19B It can form a mask pattern 160 to cover the reference that has already been applied. Figure 18The structure obtained from the described process. Mask pattern 160 may include a fourth opening OP4. In the above figure, the position of the fourth opening OP4 may be related to... Figure 14 The second opening OP2 shown is in the same or similar position. Mask pattern 160 may include a silicon nitride film.

[0085] Buried insulating film 127, fourth insulating pad 126 and third insulating pad 125 (reference) Figure 18 The hole H4 can be formed by removing the fourth opening OP4. This exposes multiple active layers 106, multiple gate dielectric films 130, and the substrate 102. Subsequently, the exposed portions of the multiple gate dielectric films 130 can be partially removed through the hole H4 to expose multiple conductive patterns WLM. The corresponding portions of the exposed conductive patterns WLM can be etched, thus forming multiple word lines WL from the multiple conductive patterns WLM. As a result, as... Figure 19B As shown in the enlarged view, the insulating structure 129 can be exposed inside the hole H4 around the word line WL surrounding the active layer 106.

[0086] refer to Figure 20 An insulating pad 172 can be formed to conformally cover the surfaces of each of the multiple word lines WL, multiple gate dielectric films 130, and insulating structures 129 exposed inside the via H4. Subsequently, a buried insulating film 173 can be formed on the insulating pad 172 to partially fill the corresponding spaces between the multiple active layers 106. The buried insulating film 173 can be formed to surround a portion of each of the multiple active layers 106, with the insulating pad 172 therebetween. After the buried insulating film 173 is formed, portions of the multiple active layers 106 and portions of the insulating pad 172 covering the multiple active layers 106 can protrude beyond the sidewalls of the buried insulating film 173 in a first lateral direction (X direction) inside the via H4.

[0087] refer to Figure 21 ,exist Figure 20 In the resulting structure, the portion of the insulating pad 172 exposed inside the via H4 can be removed to expose a portion of each of the plurality of active layers 106, and a plurality of annular spaces LS can be formed, respectively, surrounding the plurality of active layers 106, between the plurality of active layers 106 and the buried insulating film 173. The plurality of annular spaces LS can be connected to the via H4. To form the plurality of annular spaces LS connected to the via H4, a portion of the insulating pad 172 can be etched using a wet etching process through the via H4 or an isotropic dry etching process.

[0088] refer to Figure 22 ,exist Figure 21In the resulting structure, a metal-containing amorphous STN film can be formed to fill multiple annular spaces LS. The metal-containing amorphous STN film can fill multiple annular spaces LS and conformally cover the surfaces of multiple active layers 106 exposed by the aperture H4 and the surface of the buried insulating film 173. In one or more embodiments, the metal-containing amorphous STN film can include, but is not limited to, an amorphous hafnium oxide film, an amorphous zirconium oxide film, an amorphous tantalum oxide film, an amorphous niobium oxide film, an amorphous titanium oxide film, an amorphous lanthanum oxide film, or combinations thereof.

[0089] refer to Figure 23 ,exist Figure 22 In the resulting structure, a portion of the metal-containing amorphous STN film can be etched using an atomic layer etching process to form multiple metal-containing insulating ring patterns STP. The multiple metal-containing insulating ring patterns STP can include portions of the metal-containing amorphous STN film filling multiple ring spaces LS. During the formation of the multiple metal-containing insulating ring patterns STP, exposed portions of the buried insulating film 173 may be consumed due to the etching atmosphere of the metal-containing amorphous STN film; therefore, a portion of the buried insulating film 173 can be removed. As a result, inside the aperture H4, the multiple metal-containing insulating ring patterns STP can protrude further than the exposed surface of the buried insulating film 173 towards the center of the aperture H4 in the first lateral direction (X direction).

[0090] refer to Figure 24 ,exist Figure 23 In the resulting structure, multiple metal-containing insulating ring patterns STP can be crystallized, thus forming multiple metal-containing insulating rings STL including crystalline metal oxides.

[0091] refer to Figure 25 Through Figure 24 A selective oxide film deposition process is performed on the resulting structure, whereby the oxide pad 174S can be selectively formed only on the exposed surfaces of the plurality of active layers 106 and the exposed surfaces of the buried insulating film 173 within the surfaces exposed by the aperture H4, without being deposited on the exposed surfaces of the plurality of metal-containing insulating rings STLs, which include crystalline metal oxides. Because the selective oxide film deposition process is performed without forming the oxide pad 174S on the surface of each of the plurality of metal-containing insulating rings STLs, the oxide pad 174S can be formed at locations adjacent to the plurality of metal-containing insulating rings STLs to have apertures exposing the plurality of metal-containing insulating rings STLs. The oxide pad 174S can be formed such that at least a portion of the surface of the oxide pad 174S facing the metal-containing insulating rings STLs is spaced apart from the metal-containing insulating rings STLs.

[0092] In one or more embodiments, the oxide pad 174S may comprise a silicon oxide film. In this case, the selective oxide film deposition process for forming the oxide pad 174S may include performing an atomic layer deposition process that sequentially supplies a deposition inhibitor, a silicon precursor, and a co-reactant at least once. For example, in the selective oxide film deposition process for forming the oxide pad 174S, the atomic layer deposition process that sequentially supplies the deposition inhibitor, the silicon precursor, and the co-reactant may be repeated a desired number of times, selected from the range of 1 to 20 times.

[0093] Deposition inhibitors may include materials that are selectively self-assembled or adsorbed onto portions thereon where oxide pads 174S are not desired to form (i.e., on the surface of each of the plurality of metal-insulating ring STLs). Deposition inhibitors may self-assemble or adsorb onto the surface of each of the plurality of metal-insulating ring STLs and prevent the adsorption of silicon precursors supplied in subsequent operations.

[0094] In one or more embodiments, the deposition inhibitor may include self-assembled monolayer (SAM) forming materials (such as octadecyltrichlorosilane (ODTS) and octadecylphosphonic acid (ODPA)) or materials derived from small molecule inhibitors (SMI) (such as dimethylaminotrimethylsilane (DMATMS) and acetylacetone).

[0095] Silicon precursors may include, but are not limited to, bis(diethylamino)silane (BDEAS).

[0096] Co-reactants may include O2, O3, H2O, O2 plasma, or combinations thereof, but are not limited thereto.

[0097] In one or more embodiments, to increase the selective deposition selectivity in the selective oxide film deposition process, the atomic layer deposition process and the atomic layer etching process described above may be repeated alternately multiple times.

[0098] refer to Figure 26 , after it has been implemented reference Figure 25 In the structure obtained by the described process, a first silicon nitride pad 175A can be formed to conformally cover the oxide pad 174S. The first silicon nitride pad 175A can be formed to cover the oxide pad 174S and a plurality of metal-containing insulating rings STL.

[0099] refer to Figure 27 ,exist Figure 26 In the resulting structure, a silicon oxide film can be formed to fill the pore H4, and then the silicon oxide film can be partially removed to form a silicon oxide pattern 176 that exposes a portion of the silicon nitride pad 175A.

[0100] refer to Figure 28 ,exist Figure 27 In the resulting structure, a silicon nitride plug 175P can be formed to fill the hole H4.

[0101] refer to Figure 29 It can be seen from Figure 28 The resulting structure removes a portion of the silicon nitride plug 175P. Therefore, a second silicon nitride liner 175B can be formed, including the remaining portion of the silicon nitride plug 175P. A portion of the first silicon nitride liner 175A can be exposed within the orifice H4 through the second silicon nitride liner 175B. The exposed first silicon nitride liner 175A can be removed. Subsequently, a portion of the oxide liner 174S can be exposed within the orifice H4 through the second silicon nitride liner 175B. The first silicon nitride liner 175A and the second silicon nitride liner 175B can constitute a silicon nitride liner structure 175 surrounding the silicon oxide pattern 176.

[0102] refer to Figure 30 ,exist Figure 29 In the resulting structure, the oxide pad 174S can be removed through the aperture H4, thus allowing the formation of spatial SPs around the multiple active layers 106. The oxide pad 174S can be removed using a wet etching process or an isotropic dry etching process. During the removal of the oxide pad 174S, multiple metal-containing insulating rings STLs can be used as etching stop films. Therefore, by removing the oxide pad 174S, the desired length of the spatial SPs formed around the multiple active layers 106 in the first lateral direction (X direction) can be consistently controlled.

[0103] refer to Figure 31 , after it has been implemented reference Figure 30 In the structure obtained by the described process, corresponding portions of the plurality of active layers 106 exposed through the aperture H4 can be removed to form a plurality of active regions AC. A plurality of electrode spaces EP can be formed at locations adjacent to the plurality of active regions AC, the dimensions of the plurality of electrode spaces EP in the vertical direction (Z direction) defined by the first silicon nitride pad structure 175. Subsequently, by doping the plurality of active layers 106 with dopant via the aperture H4 and the plurality of electrode spaces EP, buried contacts BC can be formed in each of the plurality of active layers 106, thus forming a plurality of active regions AC. In one or more embodiments, the dopant may include p-type or n-type impurity ions. For example, the dopant may include boron (B), phosphorus (P), or arsenic (As), but is not limited thereto.

[0104] refer to Figure 32A metal silicide film 184 can be formed on the surface of each of the multiple active regions AC exposed in multiple electrode spaces EP. In one or more embodiments, the formation of the metal silicide film 184 may include forming a metal-silicon composite layer by vapor deposition of metal and silicon on the surface of each of the multiple active regions AC and silicide formation of the metal-silicon composite layer by using a thermal annealing process or an annealing process.

[0105] refer to Figure 33 A conductive layer 186L can be formed to conformally cover the surface exposed by the hole H4 and the multiple electrode spaces EP. The constituent material of the conductive layer 186L can be the same as the constituent material of the first electrode 186 described above.

[0106] refer to Figure 34 The portion of the conductive layer 186L outside the multiple electrode spaces EP can be removed to form multiple first electrodes 186.

[0107] refer to Figure 35A and Figure 35B It can be referenced from what has already been executed. Figure 34 The described process results in a structure that removes the silicon nitride pad structure 175 and the silicon oxide pattern 176. Therefore, the outer surface of each of the plurality of first electrodes 186 can be exposed.

[0108] refer to Figure 36A and 36B ,exist Figure 35A and Figure 35B In the resulting structure, a dielectric film 187 can be formed to conformally cover the corresponding exposed surfaces of the plurality of first electrodes 186 and the exposed surfaces of the oxide pads 174S.

[0109] After that, as Figures 2 to 4 As shown, a second electrode 188 covering a dielectric film 187 and a plate electrode 190 can be formed sequentially, thus enabling the fabrication of... Figures 2 to 6B The semiconductor memory device 100 shown.

[0110] Figures 37 to 39B This is a diagram illustrating a method of manufacturing a semiconductor memory device according to one or more embodiments. More specifically, Figure 37 , Figure 38A and Figure 39A Each is based on the process sequence and Figure 7 An enlarged cross-sectional view of an example area corresponding to the region “EX2”. Figure 38B and Figure 39B Each is based on the process sequence and along Figure 4 A cross-sectional view of an example region corresponding to the section intercepted by line Y2-Y2'. (Reference) Figures 37 to 39B The manufacturing process has been described and referenced. Figures 7 to 9 An example of a method for describing a semiconductor memory device 200. Figures 37 to 39B In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 2 to 9 Since the same elements are used in the same way, their repeated descriptions can be omitted.

[0111] refer to Figure 37 Reference can be executed Figures 11 to 32 The described process. Subsequently, in Figure 32 In the resulting structure, a first electrode 286 can be formed to fill multiple electrode spaces EP.

[0112] refer to Figure 38A and 38B It can be referenced from what has already been executed. Figure 37 The described process results in a structure that removes the silicon nitride pad structure 175 and the silicon oxide pattern 176. Therefore, the outer surface of each of the plurality of first electrodes 286 can be exposed.

[0113] refer to Figure 39A and Figure 39B ,exist Figure 38A and Figure 38B In the resulting structure, a dielectric film 287 can be formed to conformally cover the exposed surfaces of each of the plurality of first electrodes 286 and the exposed surfaces of the oxide pad 174S.

[0114] After that, as Figure 7 and Figure 8 As shown, a second electrode 288 covering a dielectric film 287 and a plate electrode 190 can be formed sequentially, thus enabling the fabrication of... Figures 7 to 9 The semiconductor memory device 200 shown.

[0115] In order to manufacture Figure 10 The semiconductor memory device 300 shown can perform operations similar to those described above. Figures 11 to 36B The process described is similar to that described above. However, by controlling the selective oxide film deposition process used to form the oxide pad 174S (already referenced) Figure 25 The selective deposition selectivity described herein can form oxide pad 374S instead of oxide pad 174S. The formation of oxide pad 374S may include contacting the surface of oxide pad 374S facing the metal-containing insulating ring STL with the outer surface of the metal-containing insulating ring STL, such that no empty space is retained between oxide pad 374S and metal-containing insulating ring STL.

[0116] Subsequently, a reference operation can be performed on the obtained structure. Figures 26 to 36B The described process allows for the manufacture of... Figure 10 The semiconductor memory device 300 shown in the figure.

[0117] Although it has been referenced Figures 11 to 39B Description of manufacturing Figures 2 to 10 The methods for semiconductor memory devices 100, 200, and 300 are shown in the references, but it will be understood that within the scope of this disclosure, methods can be derived by referring to the references. Figures 11 to 39B The described process is modified and altered in various ways to manufacture it. Figures 2 to 10 Semiconductor memory devices 100, 200, and 300, as well as semiconductor memory devices with various modified structures, are shown.

[0118] In one or more embodiments, a semiconductor memory device is provided having a structure that maximizes the capacitance of a capacitor in a limited area by preventing the capacitor from tilting or collapsing, even when the area occupied by a plurality of memory cells arranged in three dimensions is reduced due to miniaturization and high integration of the plurality of memory cells.

[0119] It is not excluded that each of the embodiments described above is associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with this disclosure.

[0120] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0121] Cross-reference to related applications

[0122] This application is based on priority to Korean Patent Application No. 10-2024-0126176, filed on September 13, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: Substrate, having an upper surface; The active region is spaced apart from the substrate in a vertical direction perpendicular to the upper surface of the substrate, and extends in a first lateral direction parallel to the upper surface of the substrate. The word line at least partially surrounds the active region and extends in a second lateral direction parallel to the upper surface of the substrate and perpendicular to the first lateral direction; A capacitor, including a first electrode connected to the active region; as well as An insulating ring, protruding from the first electrode of the capacitor toward the word line in the first lateral direction, the insulating ring surrounding a portion of the active region and comprising a metallic element.

2. The semiconductor memory device of claim 1, wherein the insulating ring comprises a crystalline metal oxide.

3. The semiconductor memory device of claim 1, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode, and The dielectric film is in contact with the insulating ring.

4. The semiconductor memory device of claim 1, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode, and The dielectric film comprises a metal element of the same type as the metal element in the insulating ring.

5. The semiconductor memory device of claim 1, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. The active region includes a channel region at least partially surrounded by the word line and a buried contact between the first electrode of the capacitor and the channel region. The semiconductor memory device further includes: An insulating pad, at least partially surrounding the buried contact, the insulating pad contacting the surface of the insulating ring that is closest to the letter line in the first lateral direction; An insulating film is buried, at least partially surrounding the insulating pad and the insulating ring; as well as An oxide liner covers the surface of the buried insulating film facing the dielectric film and the second electrode. The oxide liner at least partially surrounds the insulating ring, and The dielectric film includes a protrusion that projects toward the letter line in the first lateral direction, the protrusion being between the oxide pad and the insulating ring.

6. The semiconductor memory device of claim 1, further comprising a metal silicide film between the first electrode of the capacitor and the active region, the metal silicide film contacting each of the first electrode and the active region. The metal silicide film is surrounded by the insulating ring.

7. The semiconductor memory device of claim 1, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. The first electrode of the capacitor has a cylindrical shape defining an internal space, the internal space being configured to accommodate a portion of the dielectric film and a portion of the second electrode. The dielectric film covers the inner and outer surfaces of the first electrode.

8. The semiconductor memory device of claim 1, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode and a second electrode spaced apart from the first electrode, the dielectric film being located between the first electrode and the second electrode. The first electrode of the capacitor has an internally filled column shape, and The dielectric film covers the outer surface of the first electrode.

9. The semiconductor memory device of claim 1, further comprising a bit line extending in the vertical direction from the upper surface of the substrate on the substrate, the bit line being connected to the active region. The bit line is spaced apart from the capacitor in the first lateral direction, and the word line is between the bit line and the capacitor.

10. The semiconductor memory device of claim 1, further comprising a gate dielectric film between the word line and the active region. The gate dielectric film is aligned with and collinear with the insulating ring in the first lateral direction.

11. A semiconductor memory device having a three-dimensional structure, the semiconductor memory device comprising: Substrate, having an upper surface; as well as A memory cell block on the substrate, the memory cell block comprising: Multiple active regions are arranged in a row in a direction perpendicular to the upper surface of the substrate; Multiple word lines, each of the multiple word lines at least partially surrounding a corresponding active region of the multiple active regions and extending in a second lateral direction parallel to the upper surface of the substrate; Bit lines extend on the substrate in the vertical direction and are connected to a first side of each of the plurality of active regions; A plurality of capacitors, each of the plurality of capacitors including a first electrode connected to a second side of a corresponding active region of the plurality of active regions, the second side being opposite to the first side; and A plurality of insulating rings are arranged in a row in the vertical direction. Each of the plurality of insulating rings protrudes from the first electrode of a corresponding capacitor in a first lateral direction parallel to the upper surface of the substrate and perpendicular to the second lateral direction toward a corresponding word line in the plurality of capacitors. Each of the plurality of insulating rings surrounds a portion of a corresponding active region in the plurality of active regions. Each of the plurality of insulating rings comprises a metallic element.

12. The semiconductor memory device of claim 11, wherein the plurality of insulating rings comprises crystalline metal oxide.

13. The semiconductor memory device of claim 11, wherein each of the plurality of capacitors further comprises a dielectric film covering the surface of the first electrode and contacting at least one of the plurality of insulating rings.

14. The semiconductor memory device of claim 11, wherein each of the plurality of capacitors further comprises a dielectric film covering the surface of the first electrode, and The dielectric film and each of the plurality of insulating rings comprise a metal oxide.

15. The semiconductor memory device of claim 11, further comprising a plurality of metal silicide films, the plurality of metal silicide films being respectively between and in contact with the first electrode of each of the plurality of capacitors and the corresponding active region of the plurality of active regions. Each of the plurality of metal silicide films is surrounded by an insulating ring of the plurality of insulating rings.

16. The semiconductor memory device of claim 11, further comprising a plurality of gate dielectric films respectively between the plurality of word lines and the plurality of active regions. The plurality of insulating rings are respectively aligned with and collinear with the plurality of gate dielectric films in the first lateral direction.

17. A semiconductor memory device, comprising: Substrate, having an upper surface; An active region extends in a first lateral direction parallel to the upper surface of the substrate and is spaced apart from the substrate in a vertical direction perpendicular to the upper surface of the substrate. The active region includes a channel region, a buried contact, and a direct contact, wherein the buried contact and the direct contact are spaced apart from each other in the first lateral direction and the channel region is between the buried contact and the direct contact. The word line at least partially surrounds the channel region of the active region and extends in a second lateral direction parallel to the upper surface of the substrate and perpendicular to the first lateral direction; A gate dielectric film is located between the channel region and the word line in the active region; Bit lines are connected to the direct contact of the active region; A capacitor, including a first electrode connected to the buried contact of the active region; A metal silicide film is placed between the first electrode of the capacitor and the buried contact of the active region. as well as An insulating ring includes a first portion that contacts the first electrode of the capacitor, a second portion that surrounds the metal silicide film, and a third portion that surrounds a portion of the buried contact. The insulating ring comprises a metallic element. The gate dielectric film is aligned with and collinear with the insulating ring in the first lateral direction.

18. The semiconductor memory device of claim 17, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode, and The dielectric film has a surface that contacts the insulating ring.

19. The semiconductor memory device of claim 17, wherein the capacitor further comprises a dielectric film covering the surface of the first electrode, and The dielectric film comprises a metal element of the same type as the metal element in the insulating ring.

20. The semiconductor memory device of claim 17, wherein the insulating ring comprises HfO2, ZrO2, Ta2O5, Nb2O5, TiO2, La2O3 or a combination thereof.

Images